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WO2006037560A2 - Transistor a canal n - Google Patents

Transistor a canal n Download PDF

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Publication number
WO2006037560A2
WO2006037560A2 PCT/EP2005/010546 EP2005010546W WO2006037560A2 WO 2006037560 A2 WO2006037560 A2 WO 2006037560A2 EP 2005010546 W EP2005010546 W EP 2005010546W WO 2006037560 A2 WO2006037560 A2 WO 2006037560A2
Authority
WO
WIPO (PCT)
Prior art keywords
region
well
type doped
nmos transistor
type
Prior art date
Application number
PCT/EP2005/010546
Other languages
German (de)
English (en)
Other versions
WO2006037560A3 (fr
Inventor
Martin Knaipp
Georg RÖHRER
Original Assignee
Austriamicrosystems Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Austriamicrosystems Ag filed Critical Austriamicrosystems Ag
Publication of WO2006037560A2 publication Critical patent/WO2006037560A2/fr
Publication of WO2006037560A3 publication Critical patent/WO2006037560A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/314—Channel regions of field-effect devices of FETs of IGFETs having vertical doping variations 

Definitions

  • the present invention relates to an electrically insulated NMOS transistor with optimized breakdown voltages.
  • a p-doped well which is in the form of a body and in which the transistor is arranged, is electrically conductively connected to the semiconductor substrate. Therefore, the source region n-doped in the body can not be set to an electric potential that is negative to the substrate. In contrast, a source-body breakdown occurs at high source potentials, typically at a source potential of 8 volts with respect to the substrate potential.
  • a similar arrangement is disclosed in the publication by R. Ramanathan et al. in ISPSD 2003, pages 257 to 260, be ⁇ written.
  • a p-epitaxial layer is grown on a p-substrate. Between the p-type portion of the substrate and the p-type epitaxial layer there is a buried n-type layer provided with a high n-type doped terminal region. In the p-epitaxial layer, a shallow and a deep p-well are formed. The deep p-well is provided with a high p-type doped connection area. In the shallow p-well, the n-type drain region is arranged. net; in the deep p-well, the n-type source region is arranged.
  • the object of the present invention is to specify an improved NMOS transistor which is completely isolated from the substrate so that current can be switched on both below the substrate potential and above the substrate potential.
  • the breakdown voltages between drain and source as well as between drain and body should be optimized.
  • an n-conductively doped well is located in the substrate with a p-type doped base region, a p-type doped inner well as body therein, and the regions of the source and drain of the transistor in this case. are doped conductive.
  • the drain region is preferably surrounded by a low n-doped LDD region (lightly doped drain).
  • LDD region lightly doped drain
  • the inner tub is provided with an electrical connection as a body connection.
  • the n-type doped well also has an electrical connection.
  • the n-type doped well is set to a positive potential with respect to the inner well.
  • the pn junctions formed between the n-type doped well, the inner well and the drain region or the LDD region are thus poled in the reverse direction. Depletion zones are formed around the pn junctions in which an increased potential drop occurs.
  • the thickness and the dopant concentration of the inner tub are selected such that, during operation of the NMOS transistor, the inner tub is at least completely cleared of charge carriers under the drain region. A suitable choice of the dopant concentration in the n-doped well makes it possible to set the breakdown voltages between the source and drain and between the drain and the body region in the desired manner.
  • a preferred embodiment is produced such that the implantation of the inner tub is shielded by the implantation mask in a strip-shaped area provided below the drain area and the vertical projection of the drain area into the inner tub in a frame-shaped or circular manner. This results after diffusion of the dopant in a locally reduced dopant concentration below the drain region. Thus, it is achieved that after the complete depletion of the inner well on charge carriers, the potential drop in the inner well is increased, but the potential drop at the pn junction to the drain in this region is reduced, resulting in a higher breakdown voltage between drain and body results.
  • FIG. 1 shows a cross section through a first embodiment.
  • FIG. 2 shows a cross section through a second embodiment.
  • a p-type doped base region 1 vor ⁇ present, which may be formed by a p-type base doping of the entire semiconductor body or substrate or by a formed therein p-type doped outer well.
  • the transistor structure is arranged on a main side of the semiconductor body or substrate.
  • the n-type doped well 2 is formed by a deep n-type diffusion, designated DN in FIG. 1, and the inner well 3 is formed by a deep p-type diffusion DP.
  • the inner well 3 represents the body region of the transistor and is provided with an electrical connection, designated as body connection B in FIG.
  • body connection B a high p-type doped bottom connection region is preferably provided in the inner trough 3.
  • SP a flat p-type diffusion
  • the source region 4 is also arranged, which is doped highly n-type.
  • the drain region 5 is also highly n-doped, and the channel region 8 at the upper side between the regions of source and drain in the p-type doped semiconductor material of the inner well 3 the semiconductor body or substrate.
  • the gate dielectric 9 and the gate electrode 10 arranged thereon control the channel.
  • the highly n-doped drain region 5 is preferably embedded in a weakly n-doped LDD region which is provided for a reduction in the difference in dopant concentration from the drain to the channel.
  • the n-type doped well 2 is likewise provided with an electrical connection T.
  • a highly n-doped connection region 12 can be provided on the main side within the n-type doped well 2.
  • An electrical connection with a connection region 13 doped with a high p conductivity can likewise be provided for the basic region 1.
  • the pn junctions are shown in the figures by solid lines, while the transitions between regions of the same sign of the conductivity are shown in dashed lines.
  • the highest intended electrical potential is applied to the n-type doped well 2.
  • the inner tub 3 and optionally the basic area 1 are set at a demge ⁇ genüber lower potential by a corresponding der ⁇ electrical voltage to the body port B and, if appropriate, is applied to the connection area 13.
  • the electrical voltage applied between the body region of the transistor formed by the inner well 3 and the electrical connection of the n-type doped well 2 and the intermediate between the inner well 3 and the drain region 5 are applied in the blocking direction Voltages cause depletion of charge carriers around the respective pn junctions.
  • the inner well 3 is depleted in the operation of the device at least below the drain region 5 completely on Ladsträ ⁇ like. As a result, the potential increases below the drain region 5 or the LDD region 7, and the breakdown voltage is increased.
  • the drain-body breakdown voltage can be increased in this way to values of at least 15 volts.
  • the implantation of dopant into the inner well 3 has been shielded in a preferably strip-shaped region 14 below the drain region 5.
  • This strip-shaped region 14 is located approximately below the lateral pn junction between the LDD region 7 and the inner well 3.
  • the dopant concentration for p-type conductivity which is thereupon established by diffusion is weaker than in the rest of FIG inner wall 3.
  • the implantation of the n-type dopant of the n-type doped well can still be done with the same mask during manufacture if the mask is provided in the region of the n-type doped well 2 with closely spaced strips.
  • the dopant concentration in the n-conducting well and therefore the drain-body breakdown voltage and the drain-source breakdown voltage are as intended optimized, wherein at the same time a possible wise before the complete clearing of the charge carriers under the drain region occurring punch-through is prevented.
  • the doping of the LDD region 7 can be suitably adjusted. A punch-through between the LDD region and the n-type doped well 2 is avoided up to high voltages.
  • the formation of the LDD region is particularly preferred with a dopant concentration which has been graded toward the channel, that is, which is gradually decreasing.
  • an implantation direction inclined by at least 7 ° to the upper side is selected during the implantation of the dopant provided for the LDD region.
  • the grading of the dopant concentration is increased by increasing the angle of inclination, for example to values of more than 7 ° to about 45 ° (LATID, large angle tilt implanted drain).
  • the graded dopant profile can also be achieved by incorporating an LDD implanter optimized for integrated low-voltage transistors. In this case, an LDD region corresponding to the low-voltage transistors is optimized by the additional inclined implantation for the NMOS transistor which is completely isolated according to the invention.
  • the inclined implantation produces the desired dopant profile that is variable in the horizontal direction. This measure also improves the breakdown voltage, typically over 15 volts.
  • this NMOS transistor can be adapted to the respective requirements, in particular to the size of the voltages and currents to be switched. This happens, for example, through model calculations that are familiar to the person skilled in the art. It is therefore within the scope of the invention to suitably adjust the thickness of the layers and their dopant concentrations and to provide a drive circuit which provides the respective required electrical potentials for the described mode of operation.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention concerne un transistor à canal N entièrement isolé comprenant une zone de base de conductivité de type p du substrat, une cuvette de conductivité n (2) et une cuvette intérieure de conductivité de type p (2) prévue comme corps, dans laquelle sont disposée une zone source (4) et une zone de drain (5) avec une zone de drain faiblement dopé (LDD) (7), entre lesquelles se situe la zone de canal (8), qui est régulée avec une électrode de grille (10) disposée côté supérieur au-dessus d'un diélectrique de grille (9). L'application d'un potentiel positif élevé à la cuvette de conductivité de type n et d'un potentiel par contraste négatif à la cuvette intérieure permet de créer dans chaque cas des couches d'appauvrissement entre le drain, le corps et la cuvette dopée de conductivité de type n. Ladite cuvette intérieure est entièrement vidée de porteurs de charge, au moins en dessous de la zone de drain et la tension de claquage est ainsi élevée.
PCT/EP2005/010546 2004-10-01 2005-09-29 Transistor a canal n WO2006037560A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004047956A DE102004047956A1 (de) 2004-10-01 2004-10-01 NMOS-Transistor
DE102004047956.9 2004-10-01

Publications (2)

Publication Number Publication Date
WO2006037560A2 true WO2006037560A2 (fr) 2006-04-13
WO2006037560A3 WO2006037560A3 (fr) 2006-09-14

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2005/010546 WO2006037560A2 (fr) 2004-10-01 2005-09-29 Transistor a canal n

Country Status (3)

Country Link
DE (1) DE102004047956A1 (fr)
TW (1) TW200618292A (fr)
WO (1) WO2006037560A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114121940A (zh) * 2021-11-25 2022-03-01 微龛(广州)半导体有限公司 触发电压可调的esd保护结构及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0758213A (ja) * 1993-08-13 1995-03-03 Oki Electric Ind Co Ltd 半導体装置におけるウェルの形成方法
US6033946A (en) * 1995-12-08 2000-03-07 Texas Instruments Incorporated Method for fabricating an isolated NMOS transistor on a digital BiCMOS process
US20020005550A1 (en) * 2000-04-07 2002-01-17 Shigeki Takahashi Semiconductor device and manufacturing method of the same
US20040046191A1 (en) * 2001-08-30 2004-03-11 Hideki Mori Semiconductor device and production method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6489653B2 (en) * 1999-12-27 2002-12-03 Kabushiki Kaisha Toshiba Lateral high-breakdown-voltage transistor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0758213A (ja) * 1993-08-13 1995-03-03 Oki Electric Ind Co Ltd 半導体装置におけるウェルの形成方法
US6033946A (en) * 1995-12-08 2000-03-07 Texas Instruments Incorporated Method for fabricating an isolated NMOS transistor on a digital BiCMOS process
US20020005550A1 (en) * 2000-04-07 2002-01-17 Shigeki Takahashi Semiconductor device and manufacturing method of the same
US20040046191A1 (en) * 2001-08-30 2004-03-11 Hideki Mori Semiconductor device and production method thereof

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
HARDIKAR S ET AL: "1200 V fully implanted JI technology" ELECTRONICS LETTERS, Bd. 36, Nr. 18, 31. August 2000 (2000-08-31), Seiten 1587-1589, XP006015657 IEE, STEVENAGE, UK ISSN: 0013-5194 *
HORI T ET AL: "DEEP-SUBMICROMETER LARGE-ANGLE-TILT IMPLANTED DRAIN (LATID) TECHNOLOGY" IEEE TRANSACTIONS ON ELECTRON DEVICES, Bd. 39, Nr. 10, Oktober 1992 (1992-10), Seiten 2312-2324, XP000322936 IEEE, NEW YORK, NY, USA ISSN: 0018-9383 *
KAWAGUCHI Y ET AL: "A low on-resistance 60 V MOSFET high side switch and a 30 V npn transistor based on 5 V BiCMOS process" PROCEEDINGS OF THE 1997 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING (BCTM), MINNEAPOLIS, MN, USA, 28. September 1997 (1997-09-28), Seiten 151-154, XP010261595 IEEE, NEW YORK, NY, USA ISBN: 0-7803-3916-9 *
PATENT ABSTRACTS OF JAPAN Bd. 1995, Nr. 06, 31. Juli 1995 (1995-07-31) & JP 07 058213 A (OKI ELECTRIC IND CO LTD), 3. März 1995 (1995-03-03) *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114121940A (zh) * 2021-11-25 2022-03-01 微龛(广州)半导体有限公司 触发电压可调的esd保护结构及其制作方法

Also Published As

Publication number Publication date
DE102004047956A1 (de) 2006-04-13
TW200618292A (en) 2006-06-01
WO2006037560A3 (fr) 2006-09-14

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