WO2006037560A2 - Nmos transistor - Google Patents
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- WO2006037560A2 WO2006037560A2 PCT/EP2005/010546 EP2005010546W WO2006037560A2 WO 2006037560 A2 WO2006037560 A2 WO 2006037560A2 EP 2005010546 W EP2005010546 W EP 2005010546W WO 2006037560 A2 WO2006037560 A2 WO 2006037560A2
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- type doped
- nmos transistor
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- 239000000758 substrate Substances 0.000 claims abstract description 17
- 230000015556 catabolic process Effects 0.000 claims abstract description 13
- 239000002800 charge carrier Substances 0.000 claims abstract description 8
- 239000002019 doping agent Substances 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 11
- 238000002513 implantation Methods 0.000 claims description 10
- 238000009792 diffusion process Methods 0.000 claims description 7
- 101100536354 Drosophila melanogaster tant gene Proteins 0.000 claims 1
- 239000007943 implant Substances 0.000 claims 1
- 210000000746 body region Anatomy 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012821 model calculation Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/351—Substrate regions of field-effect devices
- H10D62/357—Substrate regions of field-effect devices of FETs
- H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
- H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/213—Channel regions of field-effect devices
- H10D62/221—Channel regions of field-effect devices of FETs
- H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
- H10D62/314—Channel regions of field-effect devices of FETs of IGFETs having vertical doping variations
Definitions
- the present invention relates to an electrically insulated NMOS transistor with optimized breakdown voltages.
- a p-doped well which is in the form of a body and in which the transistor is arranged, is electrically conductively connected to the semiconductor substrate. Therefore, the source region n-doped in the body can not be set to an electric potential that is negative to the substrate. In contrast, a source-body breakdown occurs at high source potentials, typically at a source potential of 8 volts with respect to the substrate potential.
- a similar arrangement is disclosed in the publication by R. Ramanathan et al. in ISPSD 2003, pages 257 to 260, be ⁇ written.
- a p-epitaxial layer is grown on a p-substrate. Between the p-type portion of the substrate and the p-type epitaxial layer there is a buried n-type layer provided with a high n-type doped terminal region. In the p-epitaxial layer, a shallow and a deep p-well are formed. The deep p-well is provided with a high p-type doped connection area. In the shallow p-well, the n-type drain region is arranged. net; in the deep p-well, the n-type source region is arranged.
- the object of the present invention is to specify an improved NMOS transistor which is completely isolated from the substrate so that current can be switched on both below the substrate potential and above the substrate potential.
- the breakdown voltages between drain and source as well as between drain and body should be optimized.
- an n-conductively doped well is located in the substrate with a p-type doped base region, a p-type doped inner well as body therein, and the regions of the source and drain of the transistor in this case. are doped conductive.
- the drain region is preferably surrounded by a low n-doped LDD region (lightly doped drain).
- LDD region lightly doped drain
- the inner tub is provided with an electrical connection as a body connection.
- the n-type doped well also has an electrical connection.
- the n-type doped well is set to a positive potential with respect to the inner well.
- the pn junctions formed between the n-type doped well, the inner well and the drain region or the LDD region are thus poled in the reverse direction. Depletion zones are formed around the pn junctions in which an increased potential drop occurs.
- the thickness and the dopant concentration of the inner tub are selected such that, during operation of the NMOS transistor, the inner tub is at least completely cleared of charge carriers under the drain region. A suitable choice of the dopant concentration in the n-doped well makes it possible to set the breakdown voltages between the source and drain and between the drain and the body region in the desired manner.
- a preferred embodiment is produced such that the implantation of the inner tub is shielded by the implantation mask in a strip-shaped area provided below the drain area and the vertical projection of the drain area into the inner tub in a frame-shaped or circular manner. This results after diffusion of the dopant in a locally reduced dopant concentration below the drain region. Thus, it is achieved that after the complete depletion of the inner well on charge carriers, the potential drop in the inner well is increased, but the potential drop at the pn junction to the drain in this region is reduced, resulting in a higher breakdown voltage between drain and body results.
- FIG. 1 shows a cross section through a first embodiment.
- FIG. 2 shows a cross section through a second embodiment.
- a p-type doped base region 1 vor ⁇ present, which may be formed by a p-type base doping of the entire semiconductor body or substrate or by a formed therein p-type doped outer well.
- the transistor structure is arranged on a main side of the semiconductor body or substrate.
- the n-type doped well 2 is formed by a deep n-type diffusion, designated DN in FIG. 1, and the inner well 3 is formed by a deep p-type diffusion DP.
- the inner well 3 represents the body region of the transistor and is provided with an electrical connection, designated as body connection B in FIG.
- body connection B a high p-type doped bottom connection region is preferably provided in the inner trough 3.
- SP a flat p-type diffusion
- the source region 4 is also arranged, which is doped highly n-type.
- the drain region 5 is also highly n-doped, and the channel region 8 at the upper side between the regions of source and drain in the p-type doped semiconductor material of the inner well 3 the semiconductor body or substrate.
- the gate dielectric 9 and the gate electrode 10 arranged thereon control the channel.
- the highly n-doped drain region 5 is preferably embedded in a weakly n-doped LDD region which is provided for a reduction in the difference in dopant concentration from the drain to the channel.
- the n-type doped well 2 is likewise provided with an electrical connection T.
- a highly n-doped connection region 12 can be provided on the main side within the n-type doped well 2.
- An electrical connection with a connection region 13 doped with a high p conductivity can likewise be provided for the basic region 1.
- the pn junctions are shown in the figures by solid lines, while the transitions between regions of the same sign of the conductivity are shown in dashed lines.
- the highest intended electrical potential is applied to the n-type doped well 2.
- the inner tub 3 and optionally the basic area 1 are set at a demge ⁇ genüber lower potential by a corresponding der ⁇ electrical voltage to the body port B and, if appropriate, is applied to the connection area 13.
- the electrical voltage applied between the body region of the transistor formed by the inner well 3 and the electrical connection of the n-type doped well 2 and the intermediate between the inner well 3 and the drain region 5 are applied in the blocking direction Voltages cause depletion of charge carriers around the respective pn junctions.
- the inner well 3 is depleted in the operation of the device at least below the drain region 5 completely on Ladsträ ⁇ like. As a result, the potential increases below the drain region 5 or the LDD region 7, and the breakdown voltage is increased.
- the drain-body breakdown voltage can be increased in this way to values of at least 15 volts.
- the implantation of dopant into the inner well 3 has been shielded in a preferably strip-shaped region 14 below the drain region 5.
- This strip-shaped region 14 is located approximately below the lateral pn junction between the LDD region 7 and the inner well 3.
- the dopant concentration for p-type conductivity which is thereupon established by diffusion is weaker than in the rest of FIG inner wall 3.
- the implantation of the n-type dopant of the n-type doped well can still be done with the same mask during manufacture if the mask is provided in the region of the n-type doped well 2 with closely spaced strips.
- the dopant concentration in the n-conducting well and therefore the drain-body breakdown voltage and the drain-source breakdown voltage are as intended optimized, wherein at the same time a possible wise before the complete clearing of the charge carriers under the drain region occurring punch-through is prevented.
- the doping of the LDD region 7 can be suitably adjusted. A punch-through between the LDD region and the n-type doped well 2 is avoided up to high voltages.
- the formation of the LDD region is particularly preferred with a dopant concentration which has been graded toward the channel, that is, which is gradually decreasing.
- an implantation direction inclined by at least 7 ° to the upper side is selected during the implantation of the dopant provided for the LDD region.
- the grading of the dopant concentration is increased by increasing the angle of inclination, for example to values of more than 7 ° to about 45 ° (LATID, large angle tilt implanted drain).
- the graded dopant profile can also be achieved by incorporating an LDD implanter optimized for integrated low-voltage transistors. In this case, an LDD region corresponding to the low-voltage transistors is optimized by the additional inclined implantation for the NMOS transistor which is completely isolated according to the invention.
- the inclined implantation produces the desired dopant profile that is variable in the horizontal direction. This measure also improves the breakdown voltage, typically over 15 volts.
- this NMOS transistor can be adapted to the respective requirements, in particular to the size of the voltages and currents to be switched. This happens, for example, through model calculations that are familiar to the person skilled in the art. It is therefore within the scope of the invention to suitably adjust the thickness of the layers and their dopant concentrations and to provide a drive circuit which provides the respective required electrical potentials for the described mode of operation.
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
NMOS-Transistor NMOS transistor
ie vorliegende Erfindung betrifft einen elektrisch isolier¬ ten NMOS-Transistor mit optimierten Durchbruchspannungen.The present invention relates to an electrically insulated NMOS transistor with optimized breakdown voltages.
In einem gewöhnlichen NMOS-Transistor ist eine als Body be¬ zeichnete p-dotierte Wanne, in der der Transistor angeordnet ist, mit dem Halbleitersubstrat elektrisch leitend verbunden. Daher kann der in dem Body n-dotierte Source-Bereich nicht auf ein elektrisches Potential gelegt werden, das gegenüber dem Substrat negativ ist. Ein Source-Body-Durchbruch erfolgt dagegen bei hohen Source-Potentialen, typisch etwa bei einem Source-Potential von 8 Volt gegenüber dem Substratpotential.In an ordinary NMOS transistor, a p-doped well, which is in the form of a body and in which the transistor is arranged, is electrically conductively connected to the semiconductor substrate. Therefore, the source region n-doped in the body can not be set to an electric potential that is negative to the substrate. In contrast, a source-body breakdown occurs at high source potentials, typically at a source potential of 8 volts with respect to the substrate potential.
In der Veröffentlichung von S. Pendharkar et al . in ISPSD 2004, Seiten 419 bis 422, ist ein Bauelement mit einem iso¬ lierten Drain-Bereich beschrieben, bei dem eine vergrabene n- dotierte Schicht als n-Isolationsschicht verwendet wird und der hoch n-leitend dotierte Drain-Bereich in einer epitak¬ tisch aufgewachsenen p-Isolationsschicht angeordnet ist.In the publication by S. Pendharkar et al. ISPSD 2004, pages 419 to 422, describes a component with an insulated drain region, in which a buried n-doped layer is used as n-insulating layer and the highly n-doped drain region in an epitak¬ table grown p-insulating layer is arranged.
Eine ähnliche Anordnung ist in der Veröffentlichung von R. Ramanathan et al . in ISPSD 2003, Seiten 257 bis 260, be¬ schrieben. Auf einem p-Substrat ist eine p-Epitaxieschicht aufgewachsen. Zwischen dem p-leitenden Anteil des Substrates und der p-Epitaxieschicht befindet sich eine vergrabene n- Schicht, die mit einem hoch n-leitend dotierten Anschlussbe¬ reich versehen ist . In der p-Epitaxieschicht sind eine flache und eine tiefe p-Wanne ausgebildet. Die tiefe p-Wanne ist mit einem hoch p-leitend dotierten Anschlussbereich versehen. In der flachen p-Wanne ist der n-leitende Drain-Bereich angeord- net; in der tiefen p-Wanne ist der n-leitende Source-Bereich angeordnet.A similar arrangement is disclosed in the publication by R. Ramanathan et al. in ISPSD 2003, pages 257 to 260, be¬ written. A p-epitaxial layer is grown on a p-substrate. Between the p-type portion of the substrate and the p-type epitaxial layer there is a buried n-type layer provided with a high n-type doped terminal region. In the p-epitaxial layer, a shallow and a deep p-well are formed. The deep p-well is provided with a high p-type doped connection area. In the shallow p-well, the n-type drain region is arranged. net; in the deep p-well, the n-type source region is arranged.
Eine Isolation eines NMOS-Transistors mittels einer p-Epita- xieschicht und einer vergrabenen n-Schicht ist ebenfalls der US 6,033,946 zu entnehmen.An insulation of an NMOS transistor by means of a p-epitaxial layer and a buried n-layer can likewise be taken from US Pat. No. 6,033,946.
Aufgabe der vorliegenden Erfindung ist es, einen verbesserten NMOS-Transistor anzugeben, der gegenüber dem Substrat voll¬ ständig isoliert ist, so dass damit sowohl unter dem Sub¬ stratpotential als auch über dem Substratpotential Strom ge¬ schaltet werden kann. Die Durchbruchspannungen zwischen Drain und Source sowie zwischen Drain und Body sollen optimiert werden können.The object of the present invention is to specify an improved NMOS transistor which is completely isolated from the substrate so that current can be switched on both below the substrate potential and above the substrate potential. The breakdown voltages between drain and source as well as between drain and body should be optimized.
Diese Aufgabe wird mit dem NMOS-Transistor mit den Merkmalen des Anspruches 1 gelöst . Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen.This object is achieved with the NMOS transistor having the features of claim 1. Embodiments emerge from the dependent claims.
Bei dem NMOS-Transistor befindet sich in dem Substrat mit ei¬ nem p-leitend dotierten Grundbereich eine n-leitend dotierte Wanne, darin eine p-leitend dotierte innere Wanne als Body und darin die Bereiche von Source und Drain des Transistors, die n-leitend dotiert sind. Der Drain-Bereich ist vorzugswei¬ se mit einem niedriger n-leitend dotierten LDD-Bereich (lightly doped drain) umgeben. Zwischen Source und Drain be¬ findet sich an der Oberseite des Substrates der in p-leitend dotiertem Halbleitermaterial vorgesehene Kanalbereich, über dem eine Gate-Elektrode angeordnet ist, die von dem Halblei¬ termaterial durch ein übliches Gate-Dielektrikum getrennt ist. Die innere Wanne ist mit einem elektrischen Anschluss als Body-Anschluss versehen. Die n-leitend dotierte Wanne be¬ sitzt ebenfalls einen elektrischen Anschluss. Die n-leitend dotierte Wanne wird im Betrieb des Bauelementes auf ein gegenüber der inneren Wanne positives Potential ge¬ legt. Die zwischen der n-leitend dotierten Wanne, der inneren Wanne und dem Drain-Bereich beziehungsweise dem LDD-Bereich gebildeten pn-Übergänge werden so in Sperrrichtung gepolt. Es bilden sich um die pn-Übergänge Verarmungszonen aus, in denen ein erhöhter Potentialabfall auftritt. Die Dicke und die Do- tierstoffkonzentration der inneren Wanne sind so gewählt, dass im Betrieb des NMOS-Transistors die innere Wanne zumin¬ dest unter dem Drain-Bereich vollständig von Ladungsträgern ausgeräumt ist. Eine geeignete Wahl der Dotierstoffkonzentra¬ tion in der n-leitend dotierten Wanne ermöglicht es, die Durchbruchspannungen zwischen Source und Drain und zwischen Drain und dem Body-Bereich in der gewünschten Weise einzu¬ stellen.In the case of the NMOS transistor, an n-conductively doped well is located in the substrate with a p-type doped base region, a p-type doped inner well as body therein, and the regions of the source and drain of the transistor in this case. are doped conductive. The drain region is preferably surrounded by a low n-doped LDD region (lightly doped drain). Between the source and the drain, at the upper side of the substrate, there is the channel region provided in p-type doped semiconductor material, above which a gate electrode is arranged, which is separated from the semiconductor material by a conventional gate dielectric. The inner tub is provided with an electrical connection as a body connection. The n-type doped well also has an electrical connection. During operation of the component, the n-type doped well is set to a positive potential with respect to the inner well. The pn junctions formed between the n-type doped well, the inner well and the drain region or the LDD region are thus poled in the reverse direction. Depletion zones are formed around the pn junctions in which an increased potential drop occurs. The thickness and the dopant concentration of the inner tub are selected such that, during operation of the NMOS transistor, the inner tub is at least completely cleared of charge carriers under the drain region. A suitable choice of the dopant concentration in the n-doped well makes it possible to set the breakdown voltages between the source and drain and between the drain and the body region in the desired manner.
Eine bevorzugte Ausführungsform wird so hergestellt, dass die Implantation der inneren Wanne in einem unterhalb des Drain- Bereiches vorgesehenen und die vertikale Projektion des Drain-Bereiches in die innere Wanne rahmenförmig oder kreis¬ förmig umlaufenden streifenförmigen Bereich durch die Implan¬ tationsmaske abgeschirmt wird. Das resultiert nach der Diffu¬ sion des Dotierstoffes in einer lokal verminderten Dotier- stoffkonzentration unter dem Drain-Bereich. Damit wird er¬ reicht, dass nach der vollständigen Verarmung der inneren Wanne an Ladungsträgern der Potentialabfall in der inneren Wanne erhöht ist, aber der Potentialabfall an dem pn-Übergang zum Drain in diesem Bereich verringert ist, woraus sich eine höhere Durchbruchspannung zwischen Drain und Body ergibt.A preferred embodiment is produced such that the implantation of the inner tub is shielded by the implantation mask in a strip-shaped area provided below the drain area and the vertical projection of the drain area into the inner tub in a frame-shaped or circular manner. This results after diffusion of the dopant in a locally reduced dopant concentration below the drain region. Thus, it is achieved that after the complete depletion of the inner well on charge carriers, the potential drop in the inner well is increased, but the potential drop at the pn junction to the drain in this region is reduced, resulting in a higher breakdown voltage between drain and body results.
Es folgt eine genauere Beschreibung von Beispielen des NMOS- Transistors anhand der beigefügten Figuren. ie Figur 1 zeigt einen Querschnitt durch ein erstes Ausfüh¬ rungsbeispiel .The following is a more detailed description of examples of the NMOS transistor with reference to the attached figures. FIG. 1 shows a cross section through a first embodiment.
Die Figur 2 zeigt einen Querschnitt durch ein zweites Ausfüh¬ rungsbeispiel .FIG. 2 shows a cross section through a second embodiment.
Die Figur 1 zeigt einen Querschnitt durch ein erstes Ausfüh¬ rungsbeispiel des NMOS-Transistors. In einem Halbleiterkörper oder Substrat ist ein p-leitend dotierter Grundbereich 1 vor¬ handen, der durch eine p-leitende Grunddotierung des gesamten Halbleiterkörpers oder Substrates oder auch durch eine darin ausgebildete p-leitend dotierte äußere Wanne gebildet sein kann. Die Transistorstruktur ist an einer Hauptseite des Halbleiterkörpers oder Substrates angeordnet . Dort befindet sich eine n-leitend dotierte Wanne 2 in dem Grundbereich 1, in der wiederum eine p-leitend dotierte innere Wanne 3 ange¬ ordnet ist. Die n-leitend dotierte Wanne 2 ist durch eine tiefe n-Diffusion, in der Figur 1 mit DN bezeichnet, und die innere Wanne 3 durch eine tiefe p-Diffusion DP gebildet . Die innere Wanne 3 stellt den Body-Bereich des Transistors dar und ist mit einem elektrischen Anschluss, in der Figur 1 als Body-Anschluss B bezeichnet, versehen. Für diesen Body- Anschluss B ist vorzugsweise ein hoch p-leitend dotierter Bo- dy-Anschlussbereich in der inneren Wanne 3 vorgesehen. Es kann außerdem eine flache p-Diffusion, in der Figur 1 mit SP bezeichnet, vorhanden sein, in der auch der Source-Bereich 4 angeordnet ist, der hoch n-leitend dotiert ist. Im Abstand zu dem Source-Bereich 4 befindet sich der ebenfalls hoch n- leitend dotierte Drain-Bereich 5 und zwischen den Bereichen von Source und Drain in dem p-leitend dotierten Halbleiterma¬ terial der inneren Wanne 3 der Kanalbereich 8 an der Obersei¬ te des Halbleiterkörpers oder Substrates. Darauf befindet sich das Gate-Dielektrikum 9 sowie die darauf angeordnete Ga¬ te-Elektrode 10 zur Steuerung des Kanals. Der hoch n-leitend dotierte Drain-Bereich 5 ist vorzugsweise in einen schwach n- leitend dotierten LDD-Bereich eingebettet, der für eine Ver¬ minderung des Unterschieds in der Dotierstoffkonzentration vom Drain zum Kanal hin vorgesehen ist . Die n-leitend dotier¬ te Wanne 2 ist ebenfalls mit einem elektrischen Anschluss T versehen. Dafür kann an der Hauptseite innerhalb der n- leitend dotierten Wanne 2 ein hoch n-leitend dotierter An¬ schlussbereich 12 vorgesehen sein. Für den Grundbereich 1 kann ebenfalls ein elektrischer Anschluss mit einem hoch p- leitend dotierten Anschlussbereich 13 vorgesehen sein. Die pn-Übergänge sind in den Figuren mit durchgezogenen Linien eingezeichnet, während die Übergänge zwischen Bereichen des¬ selben Vorzeichens der Leitfähigkeit gestrichelt eingezeich¬ net sind. Vorzugsweise befinden sich an der Hauptseite zwi¬ schen den elektrisch leitend dotierten Bereichen jeweils O- xidbereiche, die durch ein Feldoxid, in der Figur 1 mit FOX bezeichnet, gebildet sein können.1 shows a cross section through a first Ausfüh¬ approximately embodiment of the NMOS transistor. In a semiconductor body or substrate, a p-type doped base region 1 vor¬ present, which may be formed by a p-type base doping of the entire semiconductor body or substrate or by a formed therein p-type doped outer well. The transistor structure is arranged on a main side of the semiconductor body or substrate. There is an n-type doped well 2 in the base region 1, in which in turn a p-type doped inner well 3 ange¬ is arranged. The n-type doped well 2 is formed by a deep n-type diffusion, designated DN in FIG. 1, and the inner well 3 is formed by a deep p-type diffusion DP. The inner well 3 represents the body region of the transistor and is provided with an electrical connection, designated as body connection B in FIG. For this body connection B, a high p-type doped bottom connection region is preferably provided in the inner trough 3. There may also be a flat p-type diffusion, denoted by SP in FIG. 1, in which the source region 4 is also arranged, which is doped highly n-type. At a distance from the source region 4, there is also the drain region 5, which is also highly n-doped, and the channel region 8 at the upper side between the regions of source and drain in the p-type doped semiconductor material of the inner well 3 the semiconductor body or substrate. Located on it the gate dielectric 9 and the gate electrode 10 arranged thereon control the channel. The highly n-doped drain region 5 is preferably embedded in a weakly n-doped LDD region which is provided for a reduction in the difference in dopant concentration from the drain to the channel. The n-type doped well 2 is likewise provided with an electrical connection T. For this purpose, a highly n-doped connection region 12 can be provided on the main side within the n-type doped well 2. An electrical connection with a connection region 13 doped with a high p conductivity can likewise be provided for the basic region 1. The pn junctions are shown in the figures by solid lines, while the transitions between regions of the same sign of the conductivity are shown in dashed lines. Preferably, on the main side, between the electrically conductive doped regions, there are respective oxide regions, which may be formed by a field oxide, designated FOX in FIG.
Im Betrieb des NMOS-Transistors wird das höchste vorgesehene elektrische Potential, typisch zum Beispiel etwa 20 Volt, an die n-leitend dotierte Wanne 2 angelegt. Die innere Wanne 3 und gegebenenfalls der Grundbereich 1 werden auf ein demge¬ genüber niedrigeres Potential gelegt, indem eine entsprechen¬ de elektrische Spannung an den Body-Anschluss B und gegebe¬ nenfalls an den Anschlussbereich 13 angelegt wird. Die zwi¬ schen den durch die innere Wanne 3 gebildeten Body-Bereich des Transistors und den elektrischen Anschluss der n-leitend dotierten Wanne 2 angelegte elektrische Spannung und die zwi¬ schen die innere Wanne 3 und den Drain-Bereich 5 in Sperr¬ richtung angelegten Spannungen verursachen eine Verarmung an Ladungsträgern im Bereich um die jeweiligen pn-Übergänge. Die innere Wanne 3 verarmt im Betrieb des Bauelementes zumindest unterhalb des Drain-Bereiches 5 vollständig an Ladungsträ¬ gern. Es resultiert eine Anhebung des Potentials in der inne¬ ren Wanne 3. Infolgedessen erhöht sich das Potential unter¬ halb des Drain-Bereiches 5 beziehungsweise des LDD-Bereiches 7, und die Durchbruchspannung ist erhöht. Die Drain-Body- Durchbruchspannung kann auf diese Weise auf Werte von mindes¬ tens 15 Volt erhöht werden.In operation of the NMOS transistor, the highest intended electrical potential, typically, for example, about 20 volts, is applied to the n-type doped well 2. The inner tub 3 and optionally the basic area 1 are set at a demge¬ genüber lower potential by a corresponding der¬ electrical voltage to the body port B and, if appropriate, is applied to the connection area 13. The electrical voltage applied between the body region of the transistor formed by the inner well 3 and the electrical connection of the n-type doped well 2 and the intermediate between the inner well 3 and the drain region 5 are applied in the blocking direction Voltages cause depletion of charge carriers around the respective pn junctions. The inner well 3 is depleted in the operation of the device at least below the drain region 5 completely on Ladsträ¬ like. As a result, the potential increases below the drain region 5 or the LDD region 7, and the breakdown voltage is increased. The drain-body breakdown voltage can be increased in this way to values of at least 15 volts.
Bei dem Ausführungsbeispiel gemäß der Figur 2 wurde die Im¬ plantierung von Dotierstoff in die innere Wanne 3 in einem vorzugsweise streifenförmigen Bereich 14 unterhalb des Drain- Bereiches 5 abgeschirmt . Dieser streifenförmige Bereich 14 befindet sich in etwa unter dem lateralen pn-Übergang zwi¬ schen dem LDD-Bereich 7 und der inneren Wanne 3. Die sich da¬ nach durch Diffusion dort einstellende Dotierstoffkonzentra¬ tion für p-Leitung ist schwächer als im Rest der inneren Wan¬ ne 3. Durch eine damit verbundene Anhebung des Bodypotentials unterhalb des Drain-Bereiches wird die Durchbruchspannung zwischen Drain und Body erhöht.In the exemplary embodiment according to FIG. 2, the implantation of dopant into the inner well 3 has been shielded in a preferably strip-shaped region 14 below the drain region 5. This strip-shaped region 14 is located approximately below the lateral pn junction between the LDD region 7 and the inner well 3. The dopant concentration for p-type conductivity which is thereupon established by diffusion is weaker than in the rest of FIG inner wall 3. By an associated increase in the Bodypotentials below the drain region, the breakdown voltage between the drain and body is increased.
Für den Fall, dass die Konzentration des Dotierstoffes in der n-leitend dotierten Wanne 2 durch andere integrierte Bauele¬ mente desselben Halbleiterchips zu hoch vorgegeben ist, kann bei der Herstellung die Implantation des n-Dotierstoffs der n-leitend dotierten Wanne trotzdem mit derselben Maske erfol¬ gen, wenn die Maske im Bereich der n-leitend dotierten Wanne 2 mit in dichtem Abstand zueinander verlaufenden Streifen versehen wird. Nach der auf diese Weise in parallelen Strei¬ fen modulierten Implantation und der anschließenden thermi¬ schen Diffusion der Dotierstoffe sind die Dotierstoffkonzent¬ ration in der n-leitenden Wanne und damit die Drain-Body- Durchbruchspannung und die Drain-Source-Durchbruchspannung wie vorgesehen optimiert, wobei gleichzeitig ein möglicher¬ weise vor dem vollständigen Ausräumen der Ladungsträger unter dem Drain-Bereich auftretender Punch-through verhindert ist. Zu diesem Zweck kann auch die Dotierung des LDD-Bereiches 7 geeignet eingestellt werden. Ein Punch-through zwischen dem LDD-Bereich und der n-leitend dotierten Wanne 2 wird bis zu hohen Spannungen vermieden.In the event that the concentration of the dopant in the n-type doped well 2 is set too high by other integrated components of the same semiconductor chip, the implantation of the n-type dopant of the n-type doped well can still be done with the same mask during manufacture if the mask is provided in the region of the n-type doped well 2 with closely spaced strips. After the implantation modulated in this way in parallel striations and the subsequent thermal diffusion of the dopants, the dopant concentration in the n-conducting well and therefore the drain-body breakdown voltage and the drain-source breakdown voltage are as intended optimized, wherein at the same time a possible wise before the complete clearing of the charge carriers under the drain region occurring punch-through is prevented. For this purpose, the doping of the LDD region 7 can be suitably adjusted. A punch-through between the LDD region and the n-type doped well 2 is avoided up to high voltages.
Besonders bevorzugt ist die Ausbildung des LDD-Bereiches mit einer zum Kanal hin gradierten, das heißt, allmählich abneh¬ menden Dotierstoffkonzentration. Zur Herstellung wird bei der Implantation des für den LDD-Bereich vorgesehenen Dotierstof¬ fes eine zur Oberseite um mindestens 7° geneigte Implantati¬ onsrichtung gewählt. Die Gradierung der Dotierstoffkonzentra- tion wird durch eine Vergrößerung des Neigungswinkels, zum Beispiel auf Werte von über 7° bis etwa 45°, erhöht (LATID, large angle tilt implanted drain) . Das gradierte Dotierstoff¬ profil kann auch unter Einbeziehung eines LDD-Implants, der für integrierte Niedervolttransistoren optimiert ist, er¬ reicht werden. In diesem Fall wird ein LDD-Bereich entspre¬ chend den Niedervolttransistoren durch die zusätzliche ge¬ neigte Implantation für den erfindungsgemäß vollständig iso¬ lierten NMOS-Transistor optimiert. Die geneigte Implantation erzeugt das gewünschte in der horizontalen Richtung veränder¬ liche Dotierstoffprofil . Diese Maßnahme verbessert ebenfalls die Durchbruchspannung, typisch auf über 15 Volt.The formation of the LDD region is particularly preferred with a dopant concentration which has been graded toward the channel, that is, which is gradually decreasing. For the production, an implantation direction inclined by at least 7 ° to the upper side is selected during the implantation of the dopant provided for the LDD region. The grading of the dopant concentration is increased by increasing the angle of inclination, for example to values of more than 7 ° to about 45 ° (LATID, large angle tilt implanted drain). The graded dopant profile can also be achieved by incorporating an LDD implanter optimized for integrated low-voltage transistors. In this case, an LDD region corresponding to the low-voltage transistors is optimized by the additional inclined implantation for the NMOS transistor which is completely isolated according to the invention. The inclined implantation produces the desired dopant profile that is variable in the horizontal direction. This measure also improves the breakdown voltage, typically over 15 volts.
Durch die beschriebenen Maßnahmen wird erreicht, dass nur ein geringer Anteil des Spannungsabfalls im Bereich unterhalb des Drain-Bereiches 5 auftritt und der hauptsächliche Potential- abfall zwischen Drain D und Body-Anschluss B in die Verar¬ mungszone längs des pn-Überganges zwischen der inneren Wanne 3 und dem LDD-Bereich 7 verlagert wird. Die in dieser Hin- sieht optimierte Betriebsweise des Bauelementes, bei der ins¬ besondere ein ausreichend hohes positives Potential an den Anschluss T der n-leitend dotierten Wanne angelegt wird, kann vorzugsweise durch eine integrierte elektronische Ansteuer¬ schaltung gewährleistet werden. Damit wird erreicht, dass das Bauelement in einem erweiterten Spannungsbereich betrieben wird, wobei der Body-Bereich unter dem Drain-Bereich voll¬ ständig an Ladungsträgern ausgeräumt ist.As a result of the measures described, only a small proportion of the voltage drop occurs in the region below the drain region 5, and the main potential drop between the drain D and the body junction B enters the treatment zone along the pn junction between the inner layer Tray 3 and the LDD area 7 is shifted. The in this If optimized operation of the component, in which, in particular, a sufficiently high positive potential is applied to the terminal T of the n-type doped well, can preferably be ensured by an integrated electronic control circuit. This ensures that the component is operated in an extended voltage range, wherein the body region under the drain region is completely cleared of charge carriers.
Die Ausgestaltung dieses NMOS-Transistors kann den jeweiligen Anforderungen, insbesondere an die Größe der zu schaltenden Spannungen und Ströme, angepasst werden. Das geschieht zum Beispiel durch ModelIrechnungen, die dem Fachmann an sich ge¬ läufig sind. Es liegt daher im Rahmen der Erfindung, die Di¬ cke der Schichten und deren Dotierstoffkonzentrationen geeig¬ net anzupassen und eine Ansteuerschaltung vorzusehen, die die für die beschriebene Betriebsweise jeweils benötigten elekt¬ rischen Potentiale bereitstellt. The design of this NMOS transistor can be adapted to the respective requirements, in particular to the size of the voltages and currents to be switched. This happens, for example, through model calculations that are familiar to the person skilled in the art. It is therefore within the scope of the invention to suitably adjust the thickness of the layers and their dopant concentrations and to provide a drive circuit which provides the respective required electrical potentials for the described mode of operation.
BezugszeichenlisteLIST OF REFERENCE NUMBERS
1 Grundbereich1 basic area
2 n-leitend dotierte Wanne2 n-type doped well
3 innere Wanne3 inner tub
4 Source-Bereich4 source area
5 Drain-Bereich5 drain area
6 weitere Wanne6 more tub
7 LDD-Bereich7 LDD range
8 Kanalbereich8 channel area
9 Gate-Dielektrikum9 gate dielectric
10 Gate-Elektrode10 gate electrode
11 Body-Anschlussbereich11 Body connection area
12 Anschlussbereich12 connection area
13 Anschlussbereich13 connection area
14 streifenförmiger Bereich B Body-Anschluss14 strip-shaped area B body connection
D Drain-BereichD drain area
G Gate-ElektrodeG gate electrode
S Source-BereichS source area
T elektrischer Anschluss der n-leitend dotierten Wanne T electrical connection of the n-type doped well
Claims
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102004047956A DE102004047956A1 (en) | 2004-10-01 | 2004-10-01 | NMOS transistor |
| DE102004047956.9 | 2004-10-01 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2006037560A2 true WO2006037560A2 (en) | 2006-04-13 |
| WO2006037560A3 WO2006037560A3 (en) | 2006-09-14 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/EP2005/010546 WO2006037560A2 (en) | 2004-10-01 | 2005-09-29 | Nmos transistor |
Country Status (3)
| Country | Link |
|---|---|
| DE (1) | DE102004047956A1 (en) |
| TW (1) | TW200618292A (en) |
| WO (1) | WO2006037560A2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114121940A (en) * | 2021-11-25 | 2022-03-01 | 微龛(广州)半导体有限公司 | ESD protection structure with adjustable trigger voltage and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0758213A (en) * | 1993-08-13 | 1995-03-03 | Oki Electric Ind Co Ltd | Well forming method in semiconductor device |
| US6033946A (en) * | 1995-12-08 | 2000-03-07 | Texas Instruments Incorporated | Method for fabricating an isolated NMOS transistor on a digital BiCMOS process |
| US20020005550A1 (en) * | 2000-04-07 | 2002-01-17 | Shigeki Takahashi | Semiconductor device and manufacturing method of the same |
| US20040046191A1 (en) * | 2001-08-30 | 2004-03-11 | Hideki Mori | Semiconductor device and production method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6489653B2 (en) * | 1999-12-27 | 2002-12-03 | Kabushiki Kaisha Toshiba | Lateral high-breakdown-voltage transistor |
-
2004
- 2004-10-01 DE DE102004047956A patent/DE102004047956A1/en not_active Withdrawn
-
2005
- 2005-09-29 WO PCT/EP2005/010546 patent/WO2006037560A2/en active Application Filing
- 2005-09-30 TW TW094134207A patent/TW200618292A/en unknown
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0758213A (en) * | 1993-08-13 | 1995-03-03 | Oki Electric Ind Co Ltd | Well forming method in semiconductor device |
| US6033946A (en) * | 1995-12-08 | 2000-03-07 | Texas Instruments Incorporated | Method for fabricating an isolated NMOS transistor on a digital BiCMOS process |
| US20020005550A1 (en) * | 2000-04-07 | 2002-01-17 | Shigeki Takahashi | Semiconductor device and manufacturing method of the same |
| US20040046191A1 (en) * | 2001-08-30 | 2004-03-11 | Hideki Mori | Semiconductor device and production method thereof |
Non-Patent Citations (4)
| Title |
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| HARDIKAR S ET AL: "1200 V fully implanted JI technology" ELECTRONICS LETTERS, Bd. 36, Nr. 18, 31. August 2000 (2000-08-31), Seiten 1587-1589, XP006015657 IEE, STEVENAGE, UK ISSN: 0013-5194 * |
| HORI T ET AL: "DEEP-SUBMICROMETER LARGE-ANGLE-TILT IMPLANTED DRAIN (LATID) TECHNOLOGY" IEEE TRANSACTIONS ON ELECTRON DEVICES, Bd. 39, Nr. 10, Oktober 1992 (1992-10), Seiten 2312-2324, XP000322936 IEEE, NEW YORK, NY, USA ISSN: 0018-9383 * |
| KAWAGUCHI Y ET AL: "A low on-resistance 60 V MOSFET high side switch and a 30 V npn transistor based on 5 V BiCMOS process" PROCEEDINGS OF THE 1997 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING (BCTM), MINNEAPOLIS, MN, USA, 28. September 1997 (1997-09-28), Seiten 151-154, XP010261595 IEEE, NEW YORK, NY, USA ISBN: 0-7803-3916-9 * |
| PATENT ABSTRACTS OF JAPAN Bd. 1995, Nr. 06, 31. Juli 1995 (1995-07-31) & JP 07 058213 A (OKI ELECTRIC IND CO LTD), 3. März 1995 (1995-03-03) * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114121940A (en) * | 2021-11-25 | 2022-03-01 | 微龛(广州)半导体有限公司 | ESD protection structure with adjustable trigger voltage and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| DE102004047956A1 (en) | 2006-04-13 |
| TW200618292A (en) | 2006-06-01 |
| WO2006037560A3 (en) | 2006-09-14 |
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