+

WO2006065160A8 - Procede de fabrication de couches epitaxiales inx alyga1-x-yn dopees, couche epitaxiale inxalyga1-x-yn dopee et structure multicouche a semi-conducteurs comprenant au moins une couche epitaxiale inxalyga1-x-y - Google Patents

Procede de fabrication de couches epitaxiales inx alyga1-x-yn dopees, couche epitaxiale inxalyga1-x-yn dopee et structure multicouche a semi-conducteurs comprenant au moins une couche epitaxiale inxalyga1-x-y

Info

Publication number
WO2006065160A8
WO2006065160A8 PCT/PL2005/000081 PL2005000081W WO2006065160A8 WO 2006065160 A8 WO2006065160 A8 WO 2006065160A8 PL 2005000081 W PL2005000081 W PL 2005000081W WO 2006065160 A8 WO2006065160 A8 WO 2006065160A8
Authority
WO
WIPO (PCT)
Prior art keywords
doped
inxalyga1
epitaxial
layer
epitaxial layer
Prior art date
Application number
PCT/PL2005/000081
Other languages
English (en)
Other versions
WO2006065160A1 (fr
Inventor
Czeslaw Skierbiszewski
Sylwester Porowski
Izabella Grzegory
Piotr Perlin
Michal Leszczynski
Marcin Siekacz
Anna Feduniewicz
Tadeusz Suski
Przemyslaw Wisniewski
Michal Bockowski
Original Assignee
Inst Wysokich Cisnien Polskiej
Czeslaw Skierbiszewski
Sylwester Porowski
Izabella Grzegory
Piotr Perlin
Michal Leszczynski
Marcin Siekacz
Anna Feduniewicz
Tadeusz Suski
Przemyslaw Wisniewski
Michal Bockowski
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inst Wysokich Cisnien Polskiej, Czeslaw Skierbiszewski, Sylwester Porowski, Izabella Grzegory, Piotr Perlin, Michal Leszczynski, Marcin Siekacz, Anna Feduniewicz, Tadeusz Suski, Przemyslaw Wisniewski, Michal Bockowski filed Critical Inst Wysokich Cisnien Polskiej
Priority to EP05817699A priority Critical patent/EP1829090A1/fr
Publication of WO2006065160A1 publication Critical patent/WO2006065160A1/fr
Publication of WO2006065160A8 publication Critical patent/WO2006065160A8/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02581—Transition metal or rare earth elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

Le procédé de l'invention est basé sur le dépôt épitaxial de couches avec donneur ou/et accepteur ou/et dopants izoélectroniques ou/et magnétiques sur des substrats cristallins avec une densité de dislocations traversantes inférieure à 105cm-2 et un angle de désorientation (α) de phases atomiques (1) par rapport aux plans cristallins compris entre 0,3' et 30°, la température de croissance épitaxiale étant inférieure à la température de métastabilité InN, par épitaxie en faisceau moléculaire avec des atomes et des molécules d'azote chimiquement actifs (épitaxie en faisceau moléculaire avec azote réactif - RN MBE). Selon cette invention, la concentration des dislocations traversantes dans la couche formée est inférieure à 105cm-2 et la concentrations des dopants substitutionnels (Si, Ge, Te, Mn, Mg, Be, Fe, Er, Ca, C, Cr, Zn) est supérieure à 1018cm-3.
PCT/PL2005/000081 2004-12-15 2005-12-14 Procede de fabrication de couches epitaxiales inx alyga1-x-yn dopees, couche epitaxiale inxalyga1-x-yn dopee et structure multicouche a semi-conducteurs comprenant au moins une couche epitaxiale inxalyga1-x-y WO2006065160A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP05817699A EP1829090A1 (fr) 2004-12-15 2005-12-14 Procede de fabrication de couches epitaxiales inx alyga1-x-yn dopees, couche epitaxiale inxalyga1-x-yn dopee et structure multicouche a semi-conducteurs comprenant au moins une couche epitaxiale inxalyga1-x-y

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PL371753A PL371753A1 (pl) 2004-12-15 2004-12-15 Sposób wytwarzania domieszkowanych warstw epitaksjalnych InxAlyGa1-x-yN, domieszkowana warstwa epitaksjalna InxAlyGa1-x-yN i półprzewodnikowa struktura wielowarstwowa zawierająca warstwę epitaksjalną InxAlyGa1-x-yN, dla której 1 ˛ x > 0.001 a 0.999 ˛ y > 0
PLP371753 2004-12-15

Publications (2)

Publication Number Publication Date
WO2006065160A1 WO2006065160A1 (fr) 2006-06-22
WO2006065160A8 true WO2006065160A8 (fr) 2006-11-02

Family

ID=36051512

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/PL2005/000081 WO2006065160A1 (fr) 2004-12-15 2005-12-14 Procede de fabrication de couches epitaxiales inx alyga1-x-yn dopees, couche epitaxiale inxalyga1-x-yn dopee et structure multicouche a semi-conducteurs comprenant au moins une couche epitaxiale inxalyga1-x-y

Country Status (3)

Country Link
EP (1) EP1829090A1 (fr)
PL (1) PL371753A1 (fr)
WO (1) WO2006065160A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
PL385048A1 (pl) * 2008-04-28 2009-11-09 Topgan Spółka Z Ograniczoną Odpowiedzialnością Sposób wytwarzania domieszkowanej magnezem warstwy epitaksjalnej InxAlyGa1-x-yN o przewodnictwie typu p, dla której )0 x 0,2 a 0 y 0,3 oraz półprzewodnikowych struktur wielowarstwowych zawierających taką warstwę epitaksjalną

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU7346396A (en) * 1995-10-13 1997-04-30 Centrum Badan Wysokocisnieniowych Method of manufacturing epitaxial layers of gan or ga(a1,in)n on single crystal gan and mixed ga(a1,in)n substrates
JP4432180B2 (ja) * 1999-12-24 2010-03-17 豊田合成株式会社 Ｉｉｉ族窒化物系化合物半導体の製造方法、ｉｉｉ族窒化物系化合物半導体素子及びｉｉｉ族窒化物系化合物半導体
US6447604B1 (en) * 2000-03-13 2002-09-10 Advanced Technology Materials, Inc. Method for achieving improved epitaxy quality (surface texture and defect density) on free-standing (aluminum, indium, gallium) nitride ((al,in,ga)n) substrates for opto-electronic and electronic devices
SG157960A1 (en) * 2001-10-22 2010-01-29 Univ Yale Methods of hyperdoping semiconductor materials and hyperdoped semiconductor materials and devices
KR101017657B1 (ko) * 2002-04-30 2011-02-25 크리 인코포레이티드 고 전압 스위칭 디바이스 및 이의 제조 방법

Also Published As

Publication number Publication date
PL371753A1 (pl) 2006-06-26
EP1829090A1 (fr) 2007-09-05
WO2006065160A1 (fr) 2006-06-22

Similar Documents

Publication Publication Date Title
Cantu et al. Si doping effect on strain reduction in compressively strained Al 0.49 Ga 0.51 N thin films
Lahreche et al. Buffer free direct growth of GaN on 6H–SiC by metalorganic vapor phase epitaxy
Heying et al. Optimization of the surface morphologies and electron mobilities in GaN grown by plasma-assisted molecular beam epitaxy
US6232138B1 (en) Relaxed InxGa(1-x)as buffers
US20070012943A1 (en) Group III nitride semiconductor substrate and manufacturing method thereof
Uesugi et al. Fabrication of AlN templates on SiC substrates by sputtering-deposition and high-temperature annealing
Morkoç III-Nitride semiconductor growth by MBE: Recent issues
Bulsara et al. Relaxed In x Ga 1− x As graded buffers grown with organometallic vapor phase epitaxy on GaAs
Horikawa et al. Heteroepitaxial growth of InP on a GaAs substrate by low‐pressure metalorganic vapor phase epitaxy
US6352884B1 (en) Method for growing crystals having impurities and crystals prepared thereby
Hiroki et al. Flat surfaces and interfaces in AlN/GaN heterostructures and superlattices grown by flow-rate modulation epitaxy
WO2006065160A8 (fr) Procede de fabrication de couches epitaxiales inx alyga1-x-yn dopees, couche epitaxiale inxalyga1-x-yn dopee et structure multicouche a semi-conducteurs comprenant au moins une couche epitaxiale inxalyga1-x-y
TW200639926A (en) Semiconductor substrate, semiconductor device and method of manufacturing a semiconductor substrate
Lee et al. Growth of semi-insulating GaN layer by controlling size of nucleation sites for SAW device applications
WO1999059195A1 (fr) Procede de croissance de cristaux pour nitrures du groupe iii et semiconducteurs mixtes associes
Tambo et al. Control of GaN nanorod diameter by changing growth temperature during molecular-beam epitaxy
Tamura et al. GaN growth on (111) Si with very thin amorphous SiN layer by ECR plasma-assisted MBE
WO2005041269A3 (fr) Croissance epitaxiale laterale sans masque de nitrure d'aluminium et de nitrure de gallium et d'aluminium a teneur elevee en aluminium
Jang et al. Characteristics of GaN/Si (1 1 1) epitaxy grown using Al0. 1Ga0. 9N/AlN composite nucleation layers having different thicknesses of AlN
Takano et al. Threading dislocations and phase separation in InGaAs layers on GaAs substrates grown by low-temperature metalorganic vapor phase epitaxy
Koshelev et al. Kinetic limitations of stress relaxation and generation in GaN/AlN and AlGaN: Si/AlN heterostructures grown on c-sapphire by plasma-assisted molecular beam epitaxy
Feuillet et al. Surface Reconstructions and III-V Stoichiometry: The Case of Cubic and Hexagonal GaN
EP1675166A2 (fr) Plaquettes heteroépitaxiales avec piégeage interne et procédé de fabrication
Ito et al. Trap states in n‐GaN grown on AlN/sapphire template by MOVPE
Akasaka et al. BGaN micro-islands as novel buffers for GaN hetero-epitaxy

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KN KP KR KZ LC LK LR LS LT LU LV LY MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU LV MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)
NENP Non-entry into the national phase in:

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2005817699

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 2005817699

Country of ref document: EP

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载