+

WO2005074035A1 - Transistor à effet de champ et procédé pour fabriquer celui-ci - Google Patents

Transistor à effet de champ et procédé pour fabriquer celui-ci Download PDF

Info

Publication number
WO2005074035A1
WO2005074035A1 PCT/JP2005/001064 JP2005001064W WO2005074035A1 WO 2005074035 A1 WO2005074035 A1 WO 2005074035A1 JP 2005001064 W JP2005001064 W JP 2005001064W WO 2005074035 A1 WO2005074035 A1 WO 2005074035A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor layer
region
gate electrode
layer
insulating film
Prior art date
Application number
PCT/JP2005/001064
Other languages
English (en)
Japanese (ja)
Inventor
Risho Koh
Kiyoshi Takeuchi
Katsuhiko Tanaka
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to JP2005517473A priority Critical patent/JP5170958B2/ja
Publication of WO2005074035A1 publication Critical patent/WO2005074035A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H10D30/0245—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6212—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies having non-rectangular cross-sections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6212—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies having non-rectangular cross-sections
    • H10D30/6213—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies having non-rectangular cross-sections having rounded corners

Definitions

  • the present invention relates to a field-effect transistor and a method for manufacturing the same.
  • a gate electrode is provided on both sides of a protruding semiconductor region, and a channel is formed on both sides of the semiconductor region. Proposed.
  • Typical structures are shown in Figs. 81 is a plan view, FIG. 82 (a) is a cross-sectional view taken along the line AA ′ of FIG. 81, and FIG. 82 (b) is a cross-sectional view taken along the line BB ′ of FIG.
  • a buried insulating film 2 is provided on a support substrate 1, and a semiconductor layer 3 is provided thereon.
  • a gate electrode 5 is provided on a side surface of the semiconductor layer 3 via a gate insulating film 4 (FIG. 82 (a)).
  • a high-concentration impurity of the first conductivity type is introduced to form a source / drain region 6.
  • the semiconductor layer 3 covered with the gate electrode 5 forms a channel forming region 7, and by applying an appropriate voltage to the gate electrode, carriers of the first conductivity type are induced on the surface to form a channel.
  • a low concentration impurity of the second conductivity type is introduced or not introduced into the channel forming region.
  • an AA 'cross section in FIG. 81 is a plane perpendicular to a direction connecting the two source Z drain regions (hereinafter, this direction is referred to as a channel length direction) at a position where the semiconductor layer is covered with the gate. 81, and a section taken along line BB ′ of FIG. 81 shows a section in the channel length direction.
  • a FinFET when the difference between the thickness of the insulating film provided on the semiconductor layer 3 and the thickness of the insulating film provided on the side surface of the semiconductor layer 3 is small, when the transistor is turned on, Channels are formed on both side surfaces of the semiconductor layer 3 forming the formation region 7 and on the upper surface of the semiconductor layer.
  • This structure is called a tri-gate structure.
  • the relationship between the thickness of the insulating film provided over the semiconductor layer 3 and the thickness of the insulating film provided on the side surface of the semiconductor layer 3 is typically that one of the thicknesses is the other.
  • FIG. 82 (a) and FIG. 82 (b) show a typical structure of a tri-gate transistor.
  • FIGS. 83 (a) and 83 (b) show typical cross-sectional shapes of a transistor having a double gate structure. These are drawn on the section A-A in FIG. 81 and the section BB 'in FIG. 81, respectively.
  • the concentration of the electric field in the upper corner portion 34 of the semiconductor layer 3 indicates the influence on the transistor characteristics.
  • a structure in which the upper corner portion of the semiconductor layer 3 is rounded has been proposed (Japanese Patent Application Laid-Open No. 2002-118255: FIG. 28 of Patent Document 1 and related description). This is shown in Figure 85.
  • Such a structure is formed, for example, by thermally oxidizing the upper corner of the semiconductor layer.
  • FIG. 85 shows a cross-sectional view at the same position as FIG. 82 (a).
  • the ratio between the thickness of the cap insulating layer 8 and the thickness of the gate insulating film 4 used in the description of the difference between the double gate structure and the tri-gate structure is such that both have the same dielectric constant. It is based on having. If the two have different dielectric constants, the respective film thicknesses are divided by the respective dielectric constants.
  • the above comparison may be made by using the product of the two ratios) as the converted film thickness.
  • Patent Document 2 Japanese Patent Application Laid-Open No. 2002-270850 aims at suppressing an increase in parasitic capacitance due to position mismatch and a decrease in operating performance due to a change in parasitic resistance.
  • a field effect transistor having an island-shaped semiconductor crystal layer having a drain region and a channel region, and a gate electrode provided on both sides of the channel region opposed to each other via a gate insulating film. Then, as one embodiment, a configuration in which the width of the island-shaped semiconductor crystal layer in the channel region portion (portion sandwiched between both gate electrodes) is reduced in order to further suppress the short channel effect is described.
  • the insulating film on the top of the island-shaped layer has a shape protruding from the side surface of the island-shaped layer.
  • n-channel transistor S for a p-channel transistor
  • the force described for the n-channel transistor S, for a p-channel transistor if the polarity is reversed (for example, a potential rise in an n-channel transistor can be read as a potential drop in a p-channel transistor.
  • a decrease in the threshold voltage of a transistor can be read as an increase in the threshold voltage of a p-channel transistor.
  • FIGS. 84 (a) and 84 (b) show the results of simulating the potential distribution at the upper end of the semiconductor layer 3 in the AA ′ section of FIG. 81.
  • FIG. 84 (a) shows the case of the tri-gate structure, corresponding to the cross section of FIG. 82 (a)
  • FIG. 84 (b) shows the case of the double gate structure, corresponding to the cross section of FIG. 83 (a). Is what you do.
  • the contour lines in the figure are equipotential lines based on intrinsic semiconductor silicon, and are -0.4 V, -0.2 V, 0.0 V, 0.2 V, 0.4 V from the center of the semiconductor layer to the outside. It is.
  • the impurity concentration in the channel region is 8 ⁇ 10 18 cm— 3
  • the gate voltage is zero volts
  • the gate oxide film thickness is 2 nm. Since the potential is based on intrinsic semiconductor silicon, the potential of zero-biased n + -type silicon is 0.56 V, and the potential of the zero-biased gate is 0.56 V.
  • the simulation results for each element structure shown in this specification were performed under the same conditions as described above, unless otherwise specified.
  • FIGS. 92 (a) and 92 (b) are cross-sectional views at positions corresponding to the upper portions of the semiconductor layers in the cross-sections of FIGS. 82 (a) and 83 (a), respectively.
  • the upper corner portion 34 of the semiconductor layer 3 is processed into a round shape by performing a rounding process such as thermal oxidation, so that the electric field at the corner portion is reduced, and the parasitic transistor is formed.
  • a rounding process such as thermal oxidation
  • the thickness, carrier mobility, and interface state density of the gate insulating film formed by thermal oxidation depend on the plane orientation.
  • the basic characteristics of a transistor, such as the threshold voltage and the drain current strongly depend on the thickness of the gate insulating film, carrier mobility, and interface state density. A new parasitic transistor with different characteristics will appear, and the characteristics of FinFET will change. In particular, if the radius of curvature of the corners is increased in order to strongly suppress the parasitic transistor described in the first problem, the second problem becomes more prominent.
  • An object of the present invention is to provide a FinFET with improved element characteristics by preventing a parasitic transistor from being formed at a corner of a semiconductor layer protruding from the base plane of the FinFET.
  • the following field-effect transistor and a method for manufacturing the same can be provided.
  • the cap insulating layer has an overhanging portion extending from the surface of the gate insulating film in a direction parallel to the plane of the base and perpendicular to a channel length direction connecting the pair of source / drain regions.
  • Field-effect transistor Field-effect transistor.
  • the overhang portion has an overhang width with respect to the surface of the gate insulating film of 5 nm or more,
  • the field effect transistor according to Invention 1 which has a thickness of 20 nm or less.
  • the overhang portion has the widest width in a direction parallel to the substrate plane of the semiconductor layer and perpendicular to the channel length direction, and overhangs the surface of the gate insulating film at the position.
  • Invention 7 The method for manufacturing a field-effect transistor according to Invention 7, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.
  • the invention having a low dielectric constant region having a lower dielectric constant than SiO below the semiconductor layer.
  • a low dielectric constant region having a lower dielectric constant than SiO is provided below the semiconductor layer, and a low dielectric constant region having a lower dielectric constant than SiO is not provided below the gate electrode.
  • the semiconductor layer is provided on the first insulating layer via a second insulating layer made of a material different from that of the first insulating layer,
  • a low dielectric constant region having a lower dielectric constant than SiO is provided below the semiconductor layer, and a low dielectric constant region having a lower dielectric constant than SiO is not provided below the gate electrode.
  • a method for manufacturing a transistor. (26) A step of forming a gate insulating film on the side surface of the protruding semiconductor layer, a step of depositing a gate electrode material, and a step of patterning the gate electrode material deposited film to form a gate electrode ,
  • Invention 25 The method for manufacturing a field-effect transistor according to Invention 25, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.
  • the invention further comprising a step of backfilling the cavity with a material having a lower dielectric constant than SiO.
  • a field-effect transistor having an end insulator region.
  • the semiconductor layer includes a semiconductor layer upper region in which a width W of the semiconductor layer in a direction perpendicular to a channel length direction connecting the pair of source / drain regions and parallel to the substrate plane is smaller than a width of a lower portion thereof.
  • a semiconductor layer lower region located below the layer upper region and having a width W of the semiconductor layer larger than the width of the semiconductor layer upper region;
  • a side surface of the semiconductor layer is recessed from a side surface of the semiconductor layer in the semiconductor layer lower region, and an end portion thicker than the gate insulating film is provided between the recessed side surface and the gate electrode.
  • a field-effect transistor having an insulator region.
  • the width W of the upper portion of the semiconductor layer gradually decreases with a constant gradient toward the upper end of the semiconductor layer, and accordingly, the thickness of the end insulator region is reduced.
  • Invention 32 The field-effect transistor of Invention 32, which gradually increases with the upward force.
  • the width W of the upper part of the semiconductor layer gradually decreases toward the upper end of the semiconductor layer so that the side surface of the semiconductor layer has a curvature, and accordingly, the end insulator region 32.
  • the field-effect transistor according to Invention 32 wherein the thickness of the semiconductor layer gradually increases with the directional force toward the upper end of the semiconductor layer.
  • the semiconductor layer includes a semiconductor layer upper region in which a width W of the semiconductor layer in a direction perpendicular to a channel length direction connecting the pair of source / drain regions and parallel to the base plane is smaller than a width of a lower portion thereof.
  • the width of the semiconductor layer is located below the upper region.
  • W has a semiconductor layer lower region larger than the width of the semiconductor layer upper region
  • the semiconductor layer upper region has a transition region in which the width w of the semiconductor layer continuously changes at a portion connected to the semiconductor layer lower region, and an upper end of the semiconductor layer from an end of the transition region.
  • the width W is constant over
  • a field effect transistor having an end insulator region thicker than the gate insulating film between the semiconductor layer upper region and the gate electrode.
  • Invention 45 The method for manufacturing a field-effect transistor according to Invention 45, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.
  • a method for manufacturing a field-effect transistor according to invention 32 comprising:
  • a method for manufacturing a field effect transistor comprising: a step of forming a gate insulating film on a side surface of a semiconductor layer exposed by the etching; and a step of forming an end insulator region including a cavity by removing the corner dummy layer.
  • a method for manufacturing a field-effect transistor comprising: a step of forming a gate insulating film on a side surface of a semiconductor layer exposed by the above-mentioned etching; and a step of forming an end insulator region comprising a cavity by removing a first corner dummy layer.
  • a method for manufacturing a field-effect transistor according to invention 35 comprising:
  • the side surfaces of the semiconductor layer are covered and exposed.
  • Invention 51 The method for manufacturing a field-effect transistor according to Invention 51, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.
  • a method of manufacturing a field effect transistor comprising: a step of forming an upper semiconductor layer region that gradually becomes smaller as the force increases, and a step of forming an edge insulating region that gradually increases in thickness accordingly.
  • Invention 54 The method for manufacturing a field-effect transistor according to Invention 54, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.
  • Invention 54 The method for manufacturing a field-effect transistor according to Invention 54, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.
  • a first end insulator region thicker than the gate insulating film is provided between the semiconductor layer and the gate electrode;
  • a field-effect transistor having a second end insulator region, which is thicker than the gate insulating film, between a gate electrode and a lower side surface of the semiconductor layer.
  • the semiconductor layer includes a semiconductor layer upper region in which a width W of the semiconductor layer in a direction perpendicular to a channel length direction connecting the pair of source / drain regions and parallel to the base plane is smaller than a width of a lower portion thereof.
  • a semiconductor layer main portion region located below the upper region and having a width W of the semiconductor layer larger than the width of the semiconductor layer upper region; and a semiconductor layer main portion region located below the semiconductor layer main portion region and having a width W of the semiconductor layer.
  • a semiconductor layer lower region smaller than a width of the semiconductor layer main portion region;
  • a side surface of the semiconductor layer is recessed from a side surface of the semiconductor layer in the semiconductor layer main portion region, and a portion of the semiconductor layer upper region which is thicker than the gate insulating film is provided between the recessed side surface and the gate electrode. Having one end insulator region,
  • a side surface of the semiconductor layer is recessed from a side surface of the semiconductor layer in the semiconductor layer main portion region, and a gap between the recessed side surface and the gate electrode is thicker than the gate insulating film.
  • a field-effect transistor having two end insulator regions.
  • a method for manufacturing a field-effect transistor according to invention 58 comprising:
  • the semiconductor layer is placed in an oxidizing atmosphere so that the side surface of the semiconductor layer recedes inward. Oxidize,
  • a field effect type having a step of forming a lower region of the semiconductor layer in which the width W of the semiconductor layer gradually decreases as it moves toward the lower end of the semiconductor layer, and a second end insulating region in which the thickness gradually increases accordingly.
  • Invention 60 The method for manufacturing a field-effect transistor according to Invention 60, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.
  • Inventions 1, 6, 9, 24, 31 wherein a supporting substrate is provided below the protruding semiconductor, and the semiconductor layer is provided on the supporting substrate via a buried insulating film. — Field effect transistor of any of 44, 57-59.
  • the overhang portion has an overhang width relative to the surface of the gate insulating film.
  • the semiconductor layer is formed on a first insulating layer and is made of a material different from that of the first insulating layer.
  • a field-effect transistor in which the gate electrode has a portion on the first insulating layer and directly in contact with the first insulating layer without through a second insulating layer.
  • the gate electrode is formed so as to extend over the semiconductor layer and to extend on both sides facing each other so as to straddle the semiconductor layer from the viewpoint of ease of manufacture, formation of a tri-gate structure, and the like. It is preferable to have
  • substrate surface means any plane parallel (horizontal) to the substrate.
  • an increase in potential at an upper corner of the semiconductor layer can be reduced, and the influence of a parasitic transistor can be reduced.
  • the present invention it is possible to suppress an increase in the potential of the corner portion and suppress the parasitic transistor without rounding the corner portion. Alternatively, according to the present invention, it is possible to reduce the amount of corner rounding required to suppress the rise in the potential of the corner.
  • the present invention it is possible to prevent the electric field from the drain region from invading the channel portion via the cap insulating layer or the buried insulating film, thereby preventing the characteristics of the short-channel transistor from deteriorating.
  • FIG. 1 A cross-sectional view illustrating a first embodiment.
  • FIG. 2 is a cross-sectional view illustrating a first embodiment.
  • FIG. 3 is a cross-sectional view and a plan view illustrating a first embodiment.
  • FIG. 4 is a cross-sectional view and a plan view illustrating a first embodiment.
  • FIG. 5 is a cross-sectional view and a plan view illustrating a first embodiment.
  • FIG. 6 is a cross-sectional view illustrating a first embodiment.
  • FIG. 7 is a cross-sectional view illustrating a first embodiment.
  • FIG. 8 is a plan view illustrating a first embodiment.
  • FIG. 9 is an explanatory view of the structure and effects of the first embodiment.
  • FIG. 10 is a sectional view illustrating a second embodiment.
  • FIG. 11 is a cross-sectional view illustrating a second embodiment.
  • FIG. 12 is a sectional view illustrating a second embodiment.
  • FIG. 13 is a sectional view illustrating a second embodiment.
  • FIG. 14 is a sectional view illustrating a second embodiment.
  • FIG. 15 is a sectional view illustrating a second embodiment.
  • FIG. 16 is a sectional view illustrating a second embodiment.
  • FIG. 17 is a sectional view illustrating a second embodiment.
  • FIG. 18 is a cross-sectional view and a plan view illustrating a second embodiment.
  • FIG. 19 is a cross-sectional view and a plan view illustrating a second embodiment.
  • FIG. 20 is a sectional view illustrating a second embodiment.
  • FIG. 21 is a plan view illustrating a second embodiment.
  • FIG. 22 is a cross-sectional view illustrating a second embodiment.
  • FIG. 23 is a cross-sectional view and a plan view illustrating a second embodiment.
  • FIG. 24 is a cross-sectional view and a plan view illustrating a second embodiment.
  • FIG. 25 is a cross-sectional view and a plan view illustrating a second embodiment.
  • FIG. 26 is a sectional view illustrating a second embodiment.
  • FIG. 27 is a plan view illustrating a second embodiment.
  • FIG. 28 is a sectional view illustrating a second embodiment.
  • FIG. 29 is a sectional view illustrating a second embodiment.
  • FIG. 30 is a cross-sectional view and a plan view illustrating a second embodiment.
  • FIG. 31 is a cross-sectional view and a plan view illustrating a second embodiment.
  • FIG. 32 is a cross-sectional view illustrating a second embodiment.
  • FIG. 33 is a sectional view illustrating a second embodiment.
  • FIG. 34 is a sectional view illustrating a second embodiment.
  • FIG. 35 is a cross-sectional view illustrating a second embodiment.
  • FIG. 36 is a plan view illustrating a second embodiment.
  • FIG. 37 is a cross-sectional view illustrating a second embodiment.
  • FIG. 38 is a plan view illustrating the effect of the second embodiment.
  • FIG. 39 An explanatory diagram of an effect of the second embodiment.
  • FIG. 40 is a cross-sectional view and a plan view illustrating a third embodiment.
  • FIG. 41 is a sectional view illustrating a third embodiment.
  • FIG. 42 is a sectional view illustrating a third embodiment.
  • FIG. 43 is a cross-sectional view illustrating a third embodiment.
  • FIG. 44 is a cross-sectional view illustrating a third embodiment.
  • FIG. 45 is a cross-sectional view illustrating a third embodiment.
  • FIG. 46 is a sectional view illustrating a third embodiment.
  • FIG. 47 is a cross-sectional view and a plan view illustrating a third embodiment.
  • FIG. 48 is a cross-sectional view and a plan view illustrating a third embodiment.
  • FIG. 49 is a cross-sectional view and a plan view illustrating a third embodiment.
  • FIG. 50 is a cross-sectional view and a plan view illustrating a third embodiment.
  • FIG. 51 is a cross-sectional view illustrating a third embodiment.
  • FIG. 52 is a sectional view illustrating a third embodiment.
  • FIG. 53 is an explanatory diagram of an effect of the third embodiment.
  • FIG. 54 is an explanatory diagram of effects of the second embodiment and the third embodiment
  • FIG. 55 is a cross-sectional view illustrating a third embodiment.
  • FIG. 56 is a cross-sectional view explaining a fourth embodiment.
  • FIG. 57 is a cross-sectional view illustrating a fourth embodiment.
  • FIG. 58 is a cross-sectional view illustrating a fourth embodiment.
  • FIG. 59 is a cross-sectional view explaining a fourth embodiment.
  • FIG. 60 is a sectional view illustrating a fourth embodiment.
  • FIG. 61 is a cross-sectional view and a plan view illustrating a fourth embodiment.
  • FIG. 62 is a cross-sectional view and a plan view illustrating a fourth embodiment.
  • FIG. 63 is a cross-sectional view and a plan view illustrating a fourth embodiment.
  • FIG. 64 is a cross-sectional view illustrating a fourth embodiment.
  • FIG. 65 is a plan view illustrating a fourth embodiment.
  • FIG. 66 is a sectional view illustrating a fourth embodiment.
  • FIG. 67 is a sectional view illustrating a fifth embodiment.
  • FIG. 68 is a sectional view illustrating a fifth embodiment.
  • FIG. 69 A cross-sectional view illustrating a fifth embodiment.
  • FIG. 71 is a cross-sectional view illustrating a sixth embodiment.
  • FIG. 72 A cross-sectional view illustrating a sixth embodiment.
  • FIG. 73 is a cross-sectional view illustrating a sixth embodiment.
  • FIG. 74 is a cross-sectional view illustrating a sixth embodiment.
  • FIG. 75 is a plan view illustrating another embodiment of the present invention.
  • FIG. 76 is a plan view illustrating another embodiment of the present invention.
  • FIG. 77 is a plan view illustrating another embodiment of the present invention.
  • FIG. 78 is a plan view illustrating another embodiment of the present invention.
  • FIG. 79 is a plan view illustrating another embodiment of the present invention.
  • FIG. 80 is a plan view illustrating an embodiment of the present invention.
  • FIG. 87 is a sectional view for explaining another embodiment of the present invention.
  • FIG. 88 is a sectional view illustrating another embodiment of the present invention.
  • FIG. 89 is a sectional view illustrating another embodiment of the present invention.
  • FIG. 90 is a cross-sectional view illustrating another embodiment of the present invention.
  • FIG. 91 is a sectional view illustrating another embodiment of the present invention.
  • FIG. 92 A cross-sectional view explaining a problem of a conventional technique.
  • FIG. 93 A cross-sectional view illustrating a problem of the conventional technique.
  • FIG. 94 is a sectional view illustrating another embodiment of the present invention.
  • FIG. 95 is a cross-sectional view illustrating another embodiment of the invention.
  • FIG. 96 is a cross-sectional view illustrating another embodiment of the present invention.
  • FIG. 97 is a cross-sectional view illustrating another embodiment of the present invention.
  • FIG. 98 is a cross-sectional view illustrating another embodiment of the present invention.
  • FIG. 99 is a cross-sectional view illustrating another embodiment of the present invention.
  • FIG. 100 An explanatory view of an effect of the first embodiment.
  • a cap insulating layer 8 is provided on the semiconductor layer 3 protruding upward from the substrate, and the cap insulating layer 8 is provided in the double-gate FinFET in which the gate electrode 5 is formed so as to cover the semiconductor layer 3 and the cap insulating layer 8.
  • the horizontal direction in the plane perpendicular to the direction in which the semiconductor layer 3 protrudes from the substrate, in the direction perpendicular to the channel length direction.
  • the extension of the surface where the cap insulating layer 8 contacts the semiconductor layer 3 Direction and projecting toward the gate electrode 5 so that the cap insulating layer 8 has a protruding portion protruding from the surface of the gate insulating film 4.
  • Figure 1 shows an example.
  • the symbol Wext indicates the width of the cap insulating layer 8 projecting from the surface of the gate insulating film 4 in the horizontal direction, that is, the overhang width.
  • the “channel length direction” refers to a direction connecting a pair of source / drain regions.
  • the gate electrode 5 is provided on the side surface of the semiconductor layer with the gate insulating film 4 interposed therebetween.
  • the source / drain region 6 into which the impurity of the first conductivity type is introduced at a high concentration is formed in the layer.
  • the channel forming region 7, which is a semiconductor layer covered by the gate electrode 5 a channel made of the first conductivity type carrier is formed by applying an appropriate voltage to the gate electrode 5. Wiring is connected to the gate electrode 5 and the source / drain region 6 via a contact region.
  • FIG. 1 (a) is a cross-sectional view taken along the line AA ′ of FIG. 1 (b), and is a cross-sectional view at a position corresponding to the cross section AA ′ of FIG. 81 showing a conventional example.
  • the source / drain region 6 is originally covered with the cap insulating layer 8, and the source / drain region 6 is not visible, but the structure is easily resolved. For this reason, the position of the source Z drain region 6 is shown transparently.
  • the conductivity type of the source Z drain region is referred to as a first conductivity type, and a conductivity type different from the source Z drain region is referred to as a second conductivity type.
  • FIGS. 3 (a), 4 (a), 5 (a), and 7 (a) are plan views of FIGS. 3 (c), 4 (c), 5 (c), and 5 (a), respectively.
  • FIG. 3 is a cross-sectional view taken along line A—A ′ in FIG. 8, and FIGS. 3 (b), 4 (b), 5 (b), and 7 (b) are plan views, respectively.
  • FIGS. 3 (c), 4 FIG. 9C is a cross-sectional view taken along the line BB ′ in FIG. 5C, FIG. 5C, and FIG. FIGS. 6 (a) and 6 (b) are cross-sectional views each showing a shape taken along the line DD ′ of FIG. 5 (c).
  • the position of the cross section AA ′ of each drawing explaining this embodiment is the position of the cross section AA ′ of FIG. 81 showing the conventional example, and the position of the cross section BB ′ of each drawing explaining this embodiment. 81 correspond to the positions of the cross section BB 'in FIG. 81 showing the conventional example.
  • the semiconductor layer 3 and the cap insulating layer 8 are appropriately formed.
  • the semiconductor layer 3 is etched to form a shape (FIG. 3), and the side of the semiconductor layer 3 is etched so that the side of the semiconductor layer 3 recedes inward from the end of the cap insulating layer 8 to make the semiconductor layer 3 thin ( ( Figure 4).
  • a gate insulating film 4 is formed on the side surface of the semiconductor layer, a gate electrode material is deposited, and the gate electrode material is patterned by RIE (reactive 'ion' etching) or the like.
  • a gate electrode 5 is formed, and a high concentration first conductivity type impurity is introduced into a region of the semiconductor layer 3 which is not covered with the gate electrode 5 to form a source / drain region 6 (FIG. 5).
  • an interlayer insulating film 16 is deposited, and a contact 17 and a wiring 18 are formed by a usual method (FIGS. 7 and 8).
  • the gate electrode is formed by processing using an etching process such as RIE, at least in the latter half of the etching process, highly isotropic etching is performed, and excess surplus remaining under the protruding cap insulating layer 8 is formed. It is desirable to remove the gate electrode material 26 (FIG. 6 (a)).
  • the element structure of the first embodiment can be formed.
  • a cap substrate is formed on an SOI substrate in which a supporting substrate 1 made of silicon, a filled insulating layer 2 made of an insulator such as Si ⁇ , and a semiconductor layer 3 made of single crystal silicon are further stacked thereon.
  • the cap insulating layer 8 is, for example, a Si ⁇ film deposited by a CVD method.
  • the cap insulating layer 8 and the semiconductor layer 3 are patterned and processed into an appropriate shape by a normal lithography process and a normal etching process such as RIE to form an element region.
  • Figure 3 shows the shape obtained at this stage.
  • both the cap insulating layer 8 and the semiconductor layer 3 may be patterned by etching using a photoresist as a mask, or only the cap insulating layer 8 may be etched using a photoresist as a mask, followed by cap insulating. Patterning may be performed by etching the semiconductor layer 3 using the layer 8 as a mask.
  • the side surface of the semiconductor layer 3 is etched by performing highly isotropic etching, and the side surface of the semiconductor layer 3 is processed into a shape recessed from the side surface of the cap insulating layer 8. As a result, the shape shown in FIG. 4 is obtained.
  • Strongly isotropic etching for example, CI, HC1, C
  • the etching is performed by an isotropic plasma etching apparatus using a gas such as CF.
  • polysilicon is deposited.
  • the gate electrode is formed by patterning by etching in the usual lithography process and RIE process to form a gate electrode, followed by high-concentration ion implantation using the gate electrode as a mask and heat treatment to cover the gate electrode.
  • the source / drain region 6 is provided in the semiconductor layer 3 at a position where there is not, and the shape shown in FIG. 5 is obtained.
  • the gate electrode is formed by etching polysilicon to form the gate electrode, as shown in FIG. 6A, the polysilicon is formed below the cap insulating layer 8 in the section taken along the line D-D 'in FIG. 5C.
  • the D-D 'cross section in Fig. 5 (c) can be obtained.
  • the gate insulating film is provided by, for example, thermally oxidizing the semiconductor layer 3.
  • the source Z drain region is formed by introducing an impurity through an impurity introduction step such as vertical ion implantation, oblique ion implantation, or plasma doping.
  • a gate sidewall 14 is provided by depositing an insulating film on the whole and etching it back.
  • the insulating film forming the gate side wall 14 is, for example, a single-layer film of Si ⁇ , a single-layer film of SiN,
  • An insulating film such as a multilayer film of 2 3 4 2 and SiN is used. Also, the insulating film forming the gate side wall 14
  • FIGS. 7 (a) shows the cross-sectional shape taken along the line AA ′ in FIG. 8, and FIG.
  • FIG. 7 (b) shows the cross-sectional shape taken along the line BB ′ in FIG.
  • the contact 17 is located at the lower part of the wiring 18. In FIG. 8, the position is shown in a transparent manner.
  • the element structure of the first embodiment can be formed.
  • FIG. 9 (b) shows the result of simulating the potential distribution in the section C_C ′ in FIG. 9 (a).
  • the vertical axis represents the potential and the horizontal axis represents the position, and indicates the depth from the upper end of the semiconductor layer.
  • the impurity concentration in the semiconductor layer was 4 ⁇ 10 18 cm 3 .
  • the reference of the potential is the source potential, and the potential of the source electrode is zero V.
  • the left end of FIG. 9B corresponds to the surface of the semiconductor layer.
  • the dashed line shown as the double gate structure in the figure is the calculation result for the structure in FIG. 83, and the dashed line shown as the tri-gate structure in the figure is the calculation result for the structure in FIG.
  • FIG. 100 shows a plot of the simulation results with the horizontal axis representing Wext and the vertical axis representing the maximum potential at the upper corner of the semiconductor layer.
  • the data in Fig. 100 (a) and Fig. 100 (b) are the same, and Fig. 100 (a) shows the explanation for the lower limit of Wext, and Fig. 100 (b) shows the explanation for the upper limit of Wext. Things.
  • the impurity concentration in the semiconductor layer is 4 ⁇ 10 18 cm ⁇ 3
  • the gate voltage is 0 V (in FIG. 100, the gate potential at this time is 0.556 V, and the level is Wfm). Is 30 nm
  • the gate insulating film thickness is 2 nm.
  • Wext when Wext exceeds lOnm, the change in potential becomes gradual, and when 15 nm or more, the change in potential tends to be saturated. Even if Wext is increased in the region where the potential change is saturated, Since the potential cannot be reduced simply by increasing the load on the process, Wext is preferably 15 nm or less. Also, considering the variation of Wext due to process causes, if a margin of 5 nm is provided for 15 nm, Wext is preferably 20 nm or less.
  • Wext is preferably 20 nm or less, and more preferably 15 nm or less.
  • the thickness of the gate insulating film was set to 2 nm. Therefore, in order to obtain a certain effect of the present invention, Wext is required to have an effect of the present invention in which the gate insulating film is preferably at least one time the gate insulating film thickness. Wext should be at least 2.5 times the thickness of the gate insulating film to obtain a large value, and 5 times or more is preferable to obtain the maximum effect. In addition, the same Wext is preferred to be 10 times or less of the gate insulating film thickness, and if the judgment is made purely from the viewpoint of effect ignoring process variations, Wext is 7.5 times or less of the gate insulating film thickness. Is considered to be more preferable.
  • FIGS. 10 to 16 and FIG. 26 are cross-sectional views at positions corresponding to the cross section taken along the line AA ′ of FIG. 81, which is a drawing showing a conventional example.
  • one of the upper and lower portions of the semiconductor layer 3 projecting upward from the substrate, or both the upper and lower portions of the semiconductor layer 3 projecting upward from the substrate have a dielectric constant higher than that of SiO.
  • a low dielectric constant region 10 which is a low region is provided.
  • a gate electrode 5 is provided on a side surface of the semiconductor layer via a gate insulating film 4. The gate electrode 5 is patterned to an appropriate size, and a source / drain region 6 in which impurities of the first conductivity type are introduced at a high concentration is formed in a portion of the semiconductor layer which is not covered with the gate electrode.
  • a channel made of carriers of the first conductivity type is formed by applying an appropriate voltage to the gate electrode 5. Wiring is connected to the gate electrode 5 and the source Z drain region 6 via a contact region.
  • the low dielectric constant region 10 provided above the semiconductor layer 3 and the low dielectric constant region 10 provided below the semiconductor layer 3 are formed in the upper corner portion 34 and the lower corner portion 35 of the semiconductor layer, respectively. Has the effect of suppressing parasitic transistors.
  • the whole or a part of the cap insulating layer 8 formed on the semiconductor layer 3 is constituted by a low dielectric constant region 10 having a dielectric constant lower than that of Si ⁇ . ( Figure 10 (a)). Further, a low dielectric constant region 10 is provided both above and below the semiconductor layer 3 (FIG. 10 (b), FIG. 11 (a)). Alternatively, a low dielectric constant region is provided only below the semiconductor layer 3 (FIG. 11 (b), FIG. 11 (c), symbol 36 is a cap insulating layer made of SiO). In addition, these low dielectric regions 10
  • the low dielectric constant material forming the low dielectric constant region 10 has a relative dielectric constant lower than the relative dielectric constant of SiO of 3.9. It is strongly desirable that the relative dielectric constant of the low dielectric constant material be 3.0 or less.
  • the low dielectric constant region 10 is partially or entirely provided at a position lower than the upper end of the gate electrode (FIG. 94).
  • the low dielectric constant region 10 is provided below the gate electrode (FIG. 10).
  • a low dielectric constant region is also provided below the gate electrode 5 in a region where the semiconductor layer 3 does not exist. 11).
  • This structure has an advantage that the capacitance between the lower part of the gate electrode 5 and the supporting substrate can be reduced.
  • a structure in which a low dielectric constant region is not provided below the gate electrode 5 (FIG. 10B) is acceptable.
  • This structure has an advantage that the potential distribution inside the semiconductor layer 3 is vertically symmetrical, so that the element design becomes easy.
  • This structure also has the advantage that low dielectric constant materials, which are generally mechanically more fragile than SiO films, can reduce the surface area exposed during the manufacturing process.
  • a gate sidewall (for example, FIG. 20, FIG. 26, or FIG. 28) which is a sidewall provided on the side surface of the gate electrode 5 only by providing a region made of a material having a lower dielectric constant than Si ⁇ on the semiconductor layer , Part or all of symbol 14 in FIG. 35) is made of a material having a lower dielectric constant than SiO. It may be formed.
  • a thin protective insulating film 13 formed by thermally oxidizing the semiconductor layer between the semiconductor layer 3 and the low dielectric constant region 10 may be formed.
  • the protective insulating film 13 has an effect of reducing defects such as interface states at the interface between the low dielectric region and the semiconductor layer.
  • the protective insulating film 13 has the same strength as Si ⁇ or has a higher dielectric constant than Si ⁇ .
  • the protective insulating film 13 may have a lower dielectric constant than SiO.
  • the thickness of the protective insulating film is the thickness of the low dielectric constant region (however, the thickness refers to the width in the direction perpendicular to the substrate plane, for example, in the cross section of FIG. 13).
  • FIG. 13 shows a structure in a case where the low dielectric region 10 is a cavity 12 and a protective insulating film 13 is interposed between the semiconductor layer 3 and the low dielectric region 10.
  • FIG. 13A shows the case where the low dielectric constant region is provided above the semiconductor layer
  • FIG. 13B shows the case where the low dielectric constant region is provided above and below the semiconductor layer.
  • the protective insulating film 13 may be formed on the surface of the gate electrode in contact with the cavity (FIG. 26).
  • a protective insulating film 13 may be provided between the semiconductor layer 3 and the low dielectric constant region below the semiconductor layer.
  • FIG. 12 shows the protective insulating film 39 provided under the semiconductor layer as a protective insulating film 39.
  • the purpose of providing the buried protective insulating film 39 is the same as the purpose of providing the protective insulating film 13 provided above the semiconductor, and is to reduce defects such as interface states at the interface between the low dielectric constant region and the semiconductor layer.
  • the buried protective insulating film 39 is the same as Si ⁇ , or has a higher dielectric constant than SiO, and may have a lower dielectric constant than SiO, similarly to the protective insulating film 13 provided above the semiconductor layer. is there.
  • the second embodiment may be implemented in combination with the first embodiment.
  • the entire or a part of the cap insulating layer 8 on the semiconductor layer may be constituted by the low dielectric constant region 10 which is a region made of a low dielectric constant material or a cavity.
  • the low dielectric constant region 10 which is a region made of a low dielectric constant material or a cavity.
  • part or all of the insulator below the semiconductor layer may be formed of a low dielectric constant region made of a low dielectric constant material or a cavity.
  • various configurations of the first embodiment may be applied to the upper portion of the semiconductor layer
  • various configurations of the second embodiment may be applied to the lower portion of the semiconductor layer. This suppresses the parasitic transistor at the upper corner portion of the semiconductor layer according to the first embodiment, and the parasitic transistor at the lower corner portion 35 of the semiconductor layer according to the second embodiment.
  • FIGS. 15 and 16 show examples. These are all cross-sectional views in the same cross section as FIG. 1 (a).
  • FIG. 15 (a) shows a case where the cap insulating layer is formed of the low dielectric constant region 10 in the structure of FIG. 1, and
  • FIG. 15 (b) shows the structure of FIG. This is a case where it is configured by a structure including the dielectric constant region 10 and the protective insulating film 13.
  • the protective insulating film 13 is provided to protect the interface between the semiconductor layer 3 and the cavity 12.
  • FIG. 16 (a) shows a case where a low dielectric constant region 10 is provided below the semiconductor layer 3 in the structure of FIG. 1, and
  • FIG. 16 (b) shows a low dielectric constant region having a cavity 12 below the semiconductor layer 3 in the structure of FIG.
  • the protective region 13 is provided at the interface between the cavity 12 and the semiconductor layer 3 and at the interface between the cavity 12 and the gate electrode 5.
  • first embodiment and the second embodiment may be combined in a different form from those shown in Figs.
  • FIGS. 18 (a), 19 (a) and 20 (a) are cross-sectional views taken along the line AA ′ in FIG. 21 which is a plan view, respectively.
  • 20) and FIG. 20 (b) are cross-sectional views taken along the line BB ′ in FIG. 21 which is a plan view.
  • a low-dielectric-constant film made of a material having a lower dielectric constant than that of Si 30 (Fig. 17)
  • semiconductor layer 3 and low dielectric constant Putter the membrane 10 into a suitable shape (Fig. 18).
  • a gate insulating film 4 is formed on the side surface of the semiconductor, a gate electrode material is deposited, and then the gate electrode material is patterned by RIE or the like to form a gate electrode 5, which is covered with the gate electrode 5 of the semiconductor layer 3.
  • a high-concentration impurity of the first conductivity type is introduced into the unreacted region to form the source Z drain region 6 (FIG. 19).
  • an interlayer insulating film is deposited, and the contact 17 and the wiring 18 are formed by a usual method (FIGS. 20 and 21).
  • the low dielectric constant region 10 On a SOI substrate in which a support substrate 1 made of silicon, a buried insulating layer 2 made of Si ⁇ , and a semiconductor layer 3 made of single crystal silicon are further stacked thereon, the low dielectric constant region 10 A low dielectric constant insulating film 30 made of a material having a lower dielectric constant than SiO is deposited.
  • the low dielectric constant insulating film 30 is, for example, a SiOF film deposited by a CVD method. As a result, the configuration shown in FIG. 17 is obtained.
  • the low-dielectric-constant film 30 and the semiconductor layer 3 are patterned by a normal lithography process and a normal etching process such as RIE to obtain the shape shown in FIG.
  • the low dielectric constant film 30 and the semiconductor layer 3 may be patterned by etching both using a photoresist as a mask, or only the low dielectric constant film 30 may be etched using a photoresist as a mask, followed by low dielectric constant. Patterning may be performed by etching the semiconductor layer 3 using the film 30 as a mask.
  • a gate insulating film 4 is provided on the side surface of the semiconductor layer 3, polysilicon is deposited, and this is etched by a usual lithography process and RIE process to form a gate electrode by patterning. Then, high-concentration ion implantation is performed using the gate electrode as a mask, and heat treatment is performed to provide the source / drain regions 6 in the semiconductor layer 3 at positions not covered by the gate electrode, thereby obtaining the shape shown in FIG. .
  • the insulating film forming the gate side wall 14 is, for example, a Si ⁇ or SiN multilayer film,
  • the gate side wall 14 is composed of a multilayer film composed of 2 3 4 2 and SiN.
  • the insulating film forming the gate side wall 14 is formed by CVD or the like.
  • a metal is deposited on the source / drain region 6 and the gate electrode 5 and heat-treated to form a silicide layer 15 on the source Z drain region 6 and on the gate electrode 5.
  • an interlayer insulating film 16 is deposited and flattened. After that, contact holes are opened in the upper portions of the source / drain regions 6 and the gate electrodes 5, and the contacts 17 are formed by embedding metal.
  • a wiring 18 made of metal is connected to the contact 17 to obtain the shapes shown in FIGS. It is acceptable to carry out metal loading in the contact area and deposition of metal to be wiring at the same time.
  • the contact 17 is located at the lower part of the wiring 18 and its position is shown in FIG.
  • the low dielectric constant film 30 forms the low dielectric constant region 10.
  • the low dielectric constant region 10 is provided below the semiconductor layer 3, the following changes are made in the first manufacturing method of the second embodiment or the second manufacturing method of the second embodiment. All or part of the embedded insulating layer is formed by the low dielectric constant film 30. Further, the cap insulating layer 8 may be a low dielectric constant film or a non-low dielectric constant film. Also, without forming the cap insulating layer 8, a gate insulating film is formed on the side and top surfaces of the semiconductor, a gate electrode material is deposited, and then the gate electrode material is patterned by RIE or the like, as shown in FIG. 11 (b). A tri-gate structure may be formed.
  • Fig. 10 (b) uses an S ⁇ I substrate in which the upper region of the buried insulating film is formed of a low dielectric constant film, and the low dielectric constant film below the semiconductor layer 3 is not covered by the semiconductor layer 3. This is the shape obtained by etching the area and the area.
  • FIG. 23 (a), FIG. 24 (a), FIG. 25 (a), FIG. 26 (a), and FIG. 28 (a) are plan views of FIG. 23 (c) and FIG. 28 is a cross-sectional view taken along the line A--A 'in FIGS. 23 (c), 25 (c) and 27, and FIGS. 23 (b), 24 (b), 25 (b), 26 (b), and 28 ( b) is a cross-sectional view taken along the line BB 'in FIGS. 23 (c), 24 (c), 25 (c), and 27 which are plan views.
  • a dummy layer 11 is deposited on the semiconductor layer 3 (Fig. 22), and the semiconductor layer 3 and the dummy layer 11 are patterned into an appropriate shape (Fig. 23).
  • the gate electrode material is patterned by RIE or the like to form a gate electrode 5 so as to cover the semiconductor layer 3, the gate insulating film 4, and the dummy layer 11, and the gate of the semiconductor layer 3 is formed.
  • a source / drain region 6 is formed by introducing high-concentration first conductivity type impurities into a region not covered by the electrode 5 (FIGS. 24 and 14 (a)).
  • the dummy layer 11 is removed by etching to form a cavity 12 in a region on the semiconductor layer 3 covered with the gate electrode 5 (FIGS. 25 and 14 (b)).
  • an interlayer insulating film is deposited, and contacts and wirings are formed by a usual method (FIGS. 26 and 27).
  • the low-dielectric-constant region 10 may be formed by back-filling the low-dielectric-constant material in the cavity 12 on the semiconductor layer 3 covered with the gate electrode 5.
  • the dummy layer 11 for example, a SiN film deposited by CVD is used, and in order to form a cavity, the SiN film of the dummy layer 11 is removed by an etching step such as wet etching using phosphoric acid. .
  • the manufacturing method for providing the low dielectric constant region 10 will be described in more detail with reference to FIGS.
  • a dummy layer 11 is deposited on an S ⁇ I substrate in which a support substrate 1 made of silicon, a buried insulating layer 2 made of Si ⁇ , and a semiconductor layer 3 made of single crystal silicon are further stacked thereon.
  • the dummy layer 11 is, for example, a SiN film deposited by a CVD method.
  • a pad insulating film made of an insulating film different from the dummy layer 11, for example, a pad insulating film made of a Si film formed by thermal oxidation may be formed between the dummy layer 11 and the semiconductor layer 3.
  • a dummy layer is formed by a normal lithography process and a normal etching process such as RIE.
  • the shape of FIG. 23 is obtained by patterning 11 and the semiconductor layer 3.
  • the dummy layer 11 and the semiconductor layer 3 may be patterned by etching using a photoresist as a mask, or only the dummy layer 11 may be etched using a photoresist as a mask, and then the dummy layer 11 may be masked.
  • the semiconductor layer 3 may be patterned by etching the semiconductor layer 3 first. When a pad insulating film is provided between the dummy layer 11 and the semiconductor layer 3, the pad insulating film is also patterned at the same time.
  • the gate insulating film 4 is deposited, and this is etched by a usual lithography process and RIE process to form a gate electrode.
  • high-concentration ion implantation is performed using the gate electrode as a mask, and heat treatment is performed to provide the source / drain region 6 in the semiconductor layer 3 at a position not covered by the gate electrode, thereby obtaining the shape shown in FIG.
  • the gate insulating film is provided, for example, by thermally oxidizing the semiconductor layer 3.
  • the source / drain regions are formed by introducing impurities through an impurity introduction step such as vertical ion implantation, oblique ion implantation, and plasma doping.
  • the dummy layer 11 is replaced with the cavity 12 by selectively etching and removing the dummy layer 11.
  • the dummy layer 11 below the gate electrode is removed by the lateral penetration of the etching solution or etching gas as shown by the arrow in FIG.
  • phosphoric acid may be used as an etchant.
  • a protective insulating film may be provided at the interface adjacent to the cavity 12 of the semiconductor layer 3 or at the interface adjacent to the cavity 12 of the gate electrode 5 for the purpose of preventing the generation of interface states at the interface adjacent to the cavity. .
  • FIG. 25 shows a structure in which a protective insulating film 13 is provided by thermally oxidizing the interface adjacent to the cavity 12 of the semiconductor layer 3 or the interface adjacent to the cavity 12 of the gate electrode 5.
  • the protective insulating film 13 is omitted, and the drawing is omitted. (The entire structure is covered with the protective insulating film 13, so that the structure is not To be clear).
  • a gate sidewall 14 is provided by depositing an insulating film on the whole and etching it back.
  • the insulating film forming the gate side wall 14 is, for example, a Si ⁇ or SiN multilayer film,
  • the gate side wall 14 is composed of a multilayer film composed of 2 3 4 2 and SiN.
  • the insulating film forming the gate side wall 14 is formed by CVD or the like.
  • FIG. 26 (a) shows the cross-sectional shape taken along the line AA in FIG. 27, and FIG.
  • FIG. 26 (b) shows the cross-sectional shape taken along the line ⁇ _ ⁇ ′ in FIG. Note that the filling of the metal into the contact region and the deposition of the metal to be the wiring may be performed simultaneously.
  • the contact 17 is located at the lower part of the wiring 18 and its position is shown in Fig. 27.
  • the cavities may be back filled with a low dielectric constant material.
  • the low dielectric constant material to be filled in the cavity may be a continuous film such as SiOF or a porous material.
  • a low dielectric constant material is buried in the cavity by a CVD method or a spin coating method to form a low dielectric constant material. Etch back the low-k material only in the area covered by the gate electrode. This structure is shown in FIG.
  • a step of refilling the cavity with a low dielectric constant material is performed, or After completing these high temperature heat treatment steps, the formation of cavities and the cavities are made of low dielectric constant material. Performing the reconstitution step can prevent high-temperature heat treatment from causing a chemical or physical change to the low dielectric constant material.
  • the element structure of the second embodiment can be formed.
  • a manufacturing method in which a low dielectric constant region 10 including a cavity 12 is provided below the semiconductor layer 3, and a low dielectric constant material is returned to the cavity 12 provided below the semiconductor layer 3 so that a low dielectric constant A manufacturing method for providing the dielectric constant region 10 will be described with reference to FIGS. 29 to 37.
  • FIGS. 30 (a), 31 (a), and 34 are plan views of FIGS. 30 (c), 31 (c), and 36, respectively.
  • (b), FIG. 31 (b), and FIG. 35 are cross-sectional views taken along line BB ′ of FIG. 30 (c), FIG. 31 (c), and
  • FIGS. 32 (a) and 33 (a) are cross-sectional views of the cross-section of FIG. 30 (a) in which the process has been advanced, and FIGS. 32 (b), 33 (b), and FIG. It is sectional drawing in the state where the process advanced in the cross section of b).
  • the source / drain region 6 is formed by introducing the first conductivity type impurity (FIG. 32).
  • the dummy layer 11 is removed by etching to form a cavity 12 in a region below the semiconductor layer 3 (FIG. 33).
  • an interlayer insulating film is deposited, and contacts and wirings are formed by a usual method (FIGS. 34, 35, and 36).
  • a structure having a cavity below the semiconductor can be obtained by providing a dummy layer below the semiconductor layer and removing the dummy layer below the semiconductor layer.
  • a structure having cavities above and below the semiconductor can be obtained by providing dummy layers above and below the semiconductor layer 3 and removing the dummy layers above and below the semiconductor layer.
  • the semiconductor layer when a cavity is provided below the semiconductor layer, the semiconductor layer may be separated from the substrate. In order to prevent this, it is not necessary to provide a cavity below the semiconductor layer, such as in the source / drain region, the region may not be etched, and the side surfaces of the dummy layer may not be etched by the dummy layer removing step. (For example, when phosphoric acid is used for removing the dummy layer, it is preferable to cover with Si ⁇ ).
  • the low dielectric constant region 10 may be formed under the semiconductor layer 3 by burying the dummy layer provided under the semiconductor layer 3 with a low dielectric constant material having a lower dielectric constant than SiO. .
  • the element structure of the second embodiment can be formed.
  • the supporting insulating film 21 is provided on the side surface of the patterned semiconductor layer 3 as shown in FIG. 30, and the side surface of the semiconductor layer 3 once covered with the supporting insulating film 21 is formed as a channel forming region as shown in FIG.
  • the second etching may be performed on the semiconductor layer 3 so that the semiconductor layer 3 is exposed.
  • FIGS. 30 (a), 31 (a), and 34 are plan views of FIGS. 30 (c), 31 (c) and 36, respectively, and are sectional views taken along line A--A 'of FIG. (b), FIG. 31 (b), and FIG. 34 (b) are cross-sectional views taken along line BB ′ of FIG. 30 (c), FIG. 31 (c), and FIG. FIGS. 32 (a) and 33 (a) are cross-sectional views of the cross-section of FIG. 30 (a) in a state where the process has been advanced, and FIGS. 32 (b), 33 (b) and 37 are FIGS. It is sectional drawing in the state where the process advanced in the cross section of b).
  • An S ⁇ I-based substrate having a support substrate 1 made of silicon, a buried insulating layer 2 made of Si ⁇ , a lower dummy layer 20 thereon, and a semiconductor layer 3 made of single-crystal silicon stacked thereon
  • An upper dummy layer 19 is deposited on the plate.
  • the upper dummy layer 19 and the lower dummy layer 20 are, for example, SiN films.
  • the configuration shown in FIG. 29 is obtained.
  • the dummy layer 11 is simply referred to, it refers to both the upper dummy layer 19 and the lower dummy layer 20.
  • the upper dummy layer 19, the semiconductor layer 3, and the lower dummy layer 20 are patterned by a normal lithography process and a normal etching process such as RIE.
  • RIE normal etching process
  • support insulation throughout A film 21 is deposited and etched back to obtain the shape shown in FIG.
  • the laminated structure of the upper dummy layer 19, the semiconductor layer 3, and the lower dummy layer 20 is formed around the region where the channel is formed so that the side surface of the semiconductor layer 3 is exposed in the region where the channel is formed.
  • the portion adjacent to 21 is etched away.
  • FIG. 31 shows the shape obtained by this step.
  • FIG. 32 corresponds to FIG. 24
  • FIG. 33 corresponds to FIG. 25
  • FIGS. 34, 35 and 36 correspond to FIGS. 26 (a), 26 (b) and 27, respectively. It shows the shape formed by performing the step of forming the shape.
  • each step is as follows. After forming a gate insulating film on the side surface of the semiconductor layer 3, a gate electrode material is deposited, and the gate electrode material is processed to form a gate electrode. In the step of introducing impurities into 6, an upper dummy layer 19 is formed above the semiconductor layer, and a lower dummy layer 20 is formed below the semiconductor layer (FIG. 32). Further, the cavity 12 is formed above and below the semiconductor layer by the step of forming the cavity 12 by removing the dummy layer. When the protective insulating film 13 is provided in the cavity, the protective insulating film 13 is formed above and below the semiconductor layer (FIGS. 33, 34, 35, and 37). FIGS.
  • a cavity may be formed over the entire semiconductor layer below the semiconductor layer 3 (FIGS. 33 and 35), and a cavity may be formed below the semiconductor layer 3 only in a part of the region below the gate electrode. It may be formed (Fig. 37).
  • the lower dummy layer may be entirely removed, or the lower dummy layer may be removed only in a part of the region located below the gate electrode.
  • the purpose of providing the supporting insulating film 21 is to support the semiconductor layer in a state where the lower dummy layer 20 below the semiconductor layer is removed to form a cavity. Therefore, when a cavity is formed below the semiconductor layer 3 only in a part of the region below the gate electrode (FIG. 37), the semiconductor layer is supported by the connection at the contact surface between the gate electrode 5 and the buried insulating film 2. Therefore, when sufficient mechanical strength is obtained, the supporting insulating film 21 may be omitted.
  • the element structure of the second embodiment is formed. It becomes possible.
  • a portion located above the semiconductor layer, a portion located below the semiconductor layer, or a portion located above and below the semiconductor layer has a lower dielectric constant than SiO.
  • the low dielectric constant region has a function of relaxing the electric field between the gate electrode and the semiconductor layer, if a portion located above the semiconductor layer is replaced by the low dielectric constant region, the upper corner portion of the semiconductor layer 34 (FIG. 82, The rise in potential in FIG. 83) is suppressed, the occurrence of parasitic transistors is suppressed, and transistor characteristics are improved. Parasitic transistors also occur in the lower corners 35 (Figs. 82 and 83), but if the lower part of the semiconductor layer is replaced by a low dielectric constant region, the potential rise in the lower corners of the semiconductor layer will increase. Is suppressed, the occurrence of a parasitic transistor is suppressed, and the characteristics of the transistor are improved.
  • Fig. 39 shows a potential distribution in the case where a cavity is formed above the semiconductor layer of FinFET.
  • FIG. 54 shows a plot of the potential distribution on the side surface of the semiconductor layer as in FIG. 9B.
  • FIG. 54 (a) shows the double gate structure in FIG. 83
  • FIG. 54 (b) shows the tri-gate structure in FIG. 82
  • FIG. 54 (c) shows the structure in FIG. 10 (a).
  • the number in the figure is the amount of potential rise at the upper end of the semiconductor layer, which is 63.4 mV in the structure of FIG. This value is smaller in the case of the normal double gate structure (186 mV) than in the case of the normal tri-gate structure (358 mV), and the parasitic transistor suppressing effect according to the present embodiment is remarkable.
  • the cap insulating layer is formed using a low dielectric constant region or part of the cap insulating layer is formed using a low dielectric constant material, an action of suppressing an electric field from a drain to a channel through the cap insulating layer and the cap insulating layer. Is also obtained. Also, by replacing the buried insulating film in the low dielectric constant region or by replacing part of the buried insulating film with a low dielectric constant material, the electric field from the drain through the buried insulating film to the channel is suppressed. The effect of this is obtained.
  • the electric field from the drain to the channel through the cap insulating layer or the filled insulating film causes a threshold voltage fluctuation called DIBL (drain-induced barrier lowering, drain 'induced' barrier 'lowering) to occur in short-channel transistors.
  • DIBL drain-induced barrier lowering, drain 'induced' barrier 'lowering
  • the present embodiment also has the effect of improving the characteristics of the short-channel transistor, such as suppressing threshold value fluctuation due to DIBL, because it causes various characteristics degradation.
  • the threshold variation due to DIBL can be improved. And the effect of improving the characteristics of the short-channel transistor, such as suppression of the noise, can be enhanced.
  • planar-type field-effect transistors have conventionally been proposed to have a structure in which a cavity is provided below the semiconductor layer to reduce parasitic capacitance and suppress the short-channel effect.
  • the feature is that the gate electrode adjacent to the vertical channel reaches the buried insulating layer below the cavity. This has the advantage that heat generated in the channel region can easily escape to the support substrate side via the gate electrode.
  • FIG. 38 (a) shows a planar type In the case of the conventional structure, FIGS. 38 (b) and 38 (c) show the case of the structure of the present invention.
  • FIG. 38 (c) shows a case where a plurality of semiconductor layers are arranged as shown in FIG.
  • FIG. 38 (b) is a cross-sectional view at a position corresponding to the AA ′ cross section in FIG. 36, and FIG.
  • 38 (b) is a cross-sectional view at a position corresponding to the AA ′ cross section in FIG. 75.
  • 38 (a) is a cross section in the channel width direction of a channel region covered with a gate electrode of a planar transistor.
  • the arrow (symbol 33) in FIG. 38 indicates the flow of heat, and the symbol 32 indicates a field insulating film.
  • FIGS. 41, 55, 56, 57, 59, 60, 66, 67, 68, and 68 show a conventional structure at a position corresponding to a section taken along the line AA ′ of FIG. 81.
  • FIG. 82 is a cross-sectional view, corresponding to the cross-section shown in FIGS. 82 (a) and 83 (a), illustrating the conventional structure.
  • the semiconductor layer 3 of the FinFET of the third, fourth, and fifth embodiments has a form protruding from the substrate surface, and the gate insulating film 4 is provided on both sides of the semiconductor layer 3 via the gate insulating film 4. A gate electrode is provided.
  • the semiconductor layer includes a semiconductor layer main portion region 43 and a semiconductor layer end region 44 provided on at least one of an upper portion and a lower portion of the semiconductor layer main portion region 43.
  • the semiconductor layer main portion region 43 is a region in which the width Wfin of the semiconductor layer in a plane perpendicular to the direction connecting the two source / drain regions is larger than the semiconductor layer end region 44.
  • the semiconductor layer end region 44 is a region in which the width Wfin of the semiconductor layer in a plane perpendicular to the direction connecting the two source / drain regions is smaller than the width of the semiconductor layer main region 43, or the two source / drain regions.
  • the width Wfin of the semiconductor layer in a plane perpendicular to the direction connecting the drain regions becomes smaller than the width of the semiconductor layer main region 43 as the distance from the semiconductor layer main region 43 increases, and one or both of the two regions of the transition region transition.
  • This is a region in which an end insulator region 27 is provided between the semiconductor layer 3 and the gate electrode 5.
  • the end insulator 27 is provided between the semiconductor layer 3 and the gate electrode 5, and has a maximum width of the insulator.
  • We ⁇ is an insulator larger than the thickness of the gate insulating film 4.
  • the gate electrode 5 is patterned into an appropriate size, and a source / drain region 6 in which impurities of the first conductivity type are introduced at a high concentration is formed in the semiconductor layer at a position not covered by the gate electrode. Is done.
  • a channel made of carriers of the first conductivity type is formed by applying an appropriate voltage to the gate electrode 5. Wiring is connected to the gate electrode 5 and the source / drain region 6 via a contact region.
  • the third, fourth, and fifth embodiments may be applied to a transistor having a double gate structure in which the upper interface of the semiconductor layer 3 hardly contributes as a channel (see FIG. 41), which can be applied to a transistor having a tri-gate structure (FIG. 42 (a)) in which a channel is formed at the upper interface of the semiconductor layer 3.
  • FIG. 42 (a) the side surface of the semiconductor layer 3 corresponds to the end insulator region 27.
  • the portion in contact is the semiconductor layer end region 44, and the side of the semiconductor layer 3 is not in contact with the end insulator region 27, and the portion in contact with the gate insulating film is the semiconductor layer main region 43.
  • the end insulator region 27 may be a normal insulator such as Si ⁇ , a low dielectric constant material, or a cavity.
  • FIG. 42 (b) shows a case where a cavity is provided as the end insulator region 27. It is more preferable to use a material having a lower dielectric constant than SiO or a cavity for all or a part of the end insulator region because the effect of alleviating electric field concentration is increased.
  • the end insulator region 27 and the cap insulating layer may be the same material or different materials. When the end insulator region 27 and the cap insulating layer are made of the same material, both may be formed integrally.
  • FIG. 42 (c) shows an example in which the end insulator region 27 and the cap insulating layer are integrally formed.
  • the end insulator region 27 is made of a different material from the cap insulator 8 on the semiconductor layer 3 or is not formed integrally with the same material, the end insulator region 27 becomes semiconductive. A structure that penetrates into a part of the cap insulator 8 on the body layer 3 is acceptable. If the end insulator region 27 is made of a different material from the gate insulating film 4 on the semiconductor layer 3 or is not formed integrally with the same material, the end insulator region 27 is formed on the semiconductor layer 3. Get Even if the structure penetrates into a part of the heat insulator 4, it is acceptable.
  • FIG. 43A shows a structure in which the end insulator region 27 penetrates a part of the cap insulator 8 on the semiconductor layer 3.
  • the gate insulating film 4 may be formed so as to cover the semiconductor layer 3 and the end insulator region 27.
  • This is a structure obtained when, for example, a gate insulating film is formed by a film deposition technique such as a CVD method after forming an end insulator region. An example is shown in Figure 43 (b).
  • FIG. 42 (a), FIG. 42 (b) and FIG. 42 (c), FIG. 43 (a) and FIG. 43 (b) are cross-sectional views taken along the line AA ′ of FIG.
  • FIG. 83 is a cross-sectional view at a corresponding position, which is a cross-sectional view corresponding to the cross-section shown in FIGS. 82 (a) and 83 (a) for explaining the conventional structure.
  • the width of the semiconductor layer main portion region 43 changes due to a factor due to processing accuracy (etching accuracy), particularly in a partial region such as the upper end or the lower end in the semiconductor layer main portion region 43. There may be an area to do. Further, in the semiconductor region 29, the width Wfin of the semiconductor layer may be changed within a certain limit (for example, within ⁇ 20%, more preferably within 10%) due to factors such as processing accuracy. .
  • the interface between the end insulator 27 and the gate electrode 5, and the interface between the gate insulating film 4 and the gate electrode 5 are in the same plane (the same straight line in the cross-sectional view). This is most preferable for controlling the gate electrode.
  • the effects of the present invention can be obtained even if the interface between the end insulator 27 and the gate electrode 5 is not in the same plane as the interface between the gate insulating film 4 and the gate electrode 5.
  • the end insulating film which is an insulator thicker than the gate insulating film is provided between the semiconductor layer and the gate electrode. Since the body region 27 is provided, a part of the corner of the semiconductor layer is formed by the end insulator region 27 (the upper corner portion and the end insulator region when the end insulator region 27 is provided above the semiconductor layer). In the case where 27 is provided below the semiconductor layer, the potential rise in the lower corner portion is suppressed, and the parasitic transistor is suppressed, so that the first problem is solved and the characteristics of the transistor are improved.
  • the plane orientation of the upper surface of the semiconductor layer and the plane orientation of the side surface of the semiconductor layer in the corner portion If a plane orientation significantly different from any of the above is not formed, or if it is formed, the surface is covered with the end insulator, so that both the plane orientation of the top surface of the semiconductor layer and the plane orientation of the side surface of the semiconductor layer Since the second problem does not occur unless a new parasitic transistor having a greatly different plane orientation is formed, good transistor characteristics can be obtained.
  • the field-effect transistor according to the third embodiment has, in addition to the features common to the third, fourth, and fifth embodiments, a part of the semiconductor layer end region 44 (preferably, The width Wtop of the semiconductor layer is almost constant over the entirety of the semiconductor layer end region 44 or more than 50% of the height of the semiconductor layer end region 44 (preferably, the fluctuation amount of the semiconductor width is ⁇ 20% or less, more preferably Has a characteristic that the fluctuation amount of the semiconductor width is ⁇ 10% or less).
  • FIG. 40 (a) is a plan view, which is a cross-sectional view taken along the line AA ′ of FIG. 40 (c).
  • FIG. 40 (b) is a plan view, which is a cross-sectional view taken along the line BB ′ 41 is a cross-sectional view of FIG. 40 (a) enlarged.
  • the semiconductor layer of the FinFET according to the third embodiment includes a semiconductor layer upper region 28 in which the width of the semiconductor layer is small in a plane perpendicular to the direction connecting the two source Z drain regions, and a semiconductor layer upper region.
  • the side surface of the semiconductor layer is recessed from the side surface of the semiconductor layer in the lower semiconductor layer region 29.
  • the symbol Wtop is the width of the semiconductor layer upper region 28 in a plane perpendicular to the direction connecting the two source / drain regions
  • the symbol Wfin is the width in a plane perpendicular to the direction connecting the two source / drain regions.
  • the width of the lower region 29 of the semiconductor layer is shown.
  • An end insulator region 27 is provided between the semiconductor layer upper region 28 and the gate electrode 5.
  • the gate insulating film 4 is provided between the semiconductor layer upper region 29 and the gate electrode 5.
  • the width Wei of the end insulator region 27 is larger than the thickness of the gate insulating film.
  • the gate electrode 5 is patterned to an appropriate size, and a source Z drain region 6 in which impurities of the first conductivity type are introduced at a high concentration is formed in the semiconductor layer at a position not covered by the gate electrode. Is done.
  • a channel made of carriers of the first conductivity type is formed by applying an appropriate voltage to the gate electrode 5. Wiring is connected to the gate electrode 5 and the source / drain region 6 via a contact region.
  • connection between the semiconductor layer upper region 28 and the semiconductor layer lower region 29 is as steep as possible. That is, it is most desirable that the width of each of the semiconductor layer upper region 28 and the semiconductor layer lower region 29 be discontinuously changed at the connection portion between them.
  • the semiconductor layer upper region 28 and the semiconductor lower region 29 there are regions in which the widths are different from Wtop and Wfin, respectively, in some of the regions due to factors such as processing accuracy. Is also good. For example, there may be a region where the width of the semiconductor layer changes at the upper end or lower end of the semiconductor layer upper region 28 and the upper end or lower end of the semiconductor lower region 29.
  • the transition region 40 may be provided in a region of the semiconductor layer upper region 28 that is in contact with the semiconductor layer lower region 29. This example is shown in FIG.
  • the minimum gradient 41 of the transition region in the transition region 40 is desirably 45 degrees or less, and particularly desirably 25 degrees or less.
  • FIG. 55 shows a cross-sectional view of the same cross section as FIG. Note that the minimum gradient 41 of the transition region refers to the angle between the semiconductor layer interface in the transition region 40 and the substrate surface at the position where the angle between the semiconductor layer interface and the substrate surface in the transition region 40 is minimum.
  • the semiconductor layer has a constant width, or in the semiconductor lower region 29, the width of the semiconductor layer is within a certain limit due to factors such as processing accuracy (or the top of Wtop). (Less than minus 10%, plus or minus 10% of Wfin).
  • FIG. 42 (a) shows an embodiment in which the third embodiment is applied to a tri-gate transistor.
  • FIG. 42 (b) shows a case where a cavity is provided as the end insulator region 27 in the third embodiment.
  • FIG. 42 (c) shows an example in which the end insulator region 27 and the cap insulating layer are integrally formed.
  • FIG. 43A shows a structure in which the end insulator region 27 penetrates a part of the cap insulator 8 on the semiconductor layer 3.
  • Figure 43 (b) shows an example of the structure obtained when the gate insulating film is formed by a film deposition technique such as the CVD method.
  • FIG. 83 is a cross-sectional view at a position, corresponding to the cross-section shown in FIGS. 82 (a) and 83 (a) for explaining the conventional structure.
  • the thickness of the force end insulator 27 mainly described in the case where the thickness of the end insulator 27 at the position where the width of the semiconductor layer is constant in the semiconductor layer upper region 28 is constant is described. May not be constant as long as its maximum value is thicker than the gate insulating film.
  • the thickness of the end insulator 27 is 5 nm or more and 3 times or more the gate insulating film thickness. More preferably, the thickness of the end insulator 27 is 5 nm or more, and more preferably 5 times or more the thickness of the gate insulating film.
  • the thickness of the gate insulating film 4 or the thickness of the end insulator 27 refers to the thickness in the vertical direction from the interface between the gate electrode 5 and each insulating film, which is the origin of the electric field. Point. Therefore, FIG. 80 (a), which is an enlarged view of the upper right corner of the semiconductor layer 3 in FIG. 85, indicates the thickness tl instead of the thickness t2, and shows the enlarged upper right corner of FIG. 66. In Fig. 80 (b), this indicates the thickness t3 instead of the thickness t4.
  • the width Wei of the end insulator region 27 and the term Thickness of the insulator region 27 are synonymous.
  • FIG. 44 shows the shape at a position corresponding to the cross section taken along the line AA ′ of FIG. 81 for explaining the conventional example, following the steps.
  • a cap insulating layer 8 (an insulating film layer such as SiO) is deposited on the semiconductor layer 3, and the upper portions of the cap insulating layer 8 and the semiconductor layer 3 are processed into a desired width by a normal lithography and RIE process ( Figure 44 (a)).
  • an insulator film such as a SiO film is deposited and etched back, and an end insulator region 27 is formed on the side surface of the cap insulating layer and the side surface of the semiconductor layer 3 (FIG. 44 (b)).
  • the semiconductor layer 3 is etched using the cap insulating layer 8 and the end insulator region 27 as a mask (FIG. 44 (c)).
  • a gate insulating film 4 is provided on the side surface of the semiconductor layer exposed by this step, and subsequently, a gate electrode material is deposited. Then, the gate electrode material is processed by a usual lithography and RIE step to form a gate electrode 5.
  • a source / drain region 6 is formed by introducing a high-concentration first conductivity type impurity into a region of the semiconductor layer 3 that is not covered by the gate electrode 5. Thereafter, an interlayer insulating film is deposited, and a contact 17 and a wiring 18 are formed by an ordinary method.
  • a cap insulating layer 8 (an insulating film layer such as SiO) is deposited on the semiconductor layer 3, and the upper portions of the cap insulating layer 8 and the semiconductor layer 3 are formed to have a desired width by a normal lithography and RIE process. If the top surface of the semiconductor layer exposed by etching is not horizontal in the process of FIG. 44 (a), a form having a cross section as shown in FIG. 55 is formed, but the effect of the invention is obtained. It doesn't change.
  • FIG. 45 shows a process at a position corresponding to a section taken along line AA ′ of FIG. 81 for explaining a conventional example. It is shown later.
  • a cap insulating layer 8 (an insulating film layer such as SiO) is deposited on the semiconductor layer 3, and the upper portions of the cap insulating layer 8 and the semiconductor layer 3 are processed into a desired width by a normal lithography and RIE process ( Figure 45 (a)). Next, corner dummy layer material such as SiN film is deposited and etched back
  • the corner dummy layer 22 composed of the N side wall 37 is provided on the side surface of the cap insulating layer and the side surface of the semiconductor layer 3. Subsequently, a second sidewall material such as a Si ⁇ film is deposited and etched back, and an SiO sidewall 38 is formed on the side surface of the corner dummy layer 22 (FIG. 45B). Subsequently, the semiconductor layer 3 is etched using the cap insulating layer, the corner dummy layer composed of the SiN side wall 37, and the second side wall composed of the SiO side wall 38 as a mask (FIG. 45 (c)). A gate insulating film 4 is provided on the side surface of the semiconductor layer exposed by this step, and subsequently, a gate electrode material is deposited.
  • the gate electrode material is processed by a usual lithography and RIE step to form a gate electrode 5.
  • a corner dummy layer 22 composed of the SiN side wall 37 is removed, an end insulator region 27 composed of the cavity 12 is formed in a region where the semiconductor layer has receded from the gate electrode.
  • a high concentration first conductivity type impurity is introduced into a region of the semiconductor layer 3 which is not covered with the gate electrode 5 to form a source / drain region 6.
  • an interlayer insulating film is deposited, and a contact 17 and a wiring 18 are formed by an ordinary method.
  • the deposition and etchback of SiN followed by the deposition and etchback of SiN and the formation of the second sidewall are performed by removing the sacrificial oxide film and cleaning the semiconductor layer. Is formed of an SiO film to prevent the side surface of the semiconductor layer from entering the inner side of the SiN side wall and to prevent the upper SiN side wall from protruding horizontally to form an overhang shape. If the second side wall is provided, in the step of removing the sacrificial oxide film, the second side wall also retreats at the same time, so that it does not have an overhang shape. If the overhanging shape is allowed by adding isotropic etching to the step of forming the gate electrode, the step of forming the second side wall may be omitted.
  • the cavity may be backfilled with a low dielectric constant material to form an end insulator region 27 made of a low dielectric constant material.
  • the low dielectric constant material carried in the cavities may be a continuous film such as SiOF, or may be a porous material.
  • a high-temperature heat treatment such as a heat treatment for activating impurities implanted into the source Z drain region.
  • a process of refilling the cavity with a low-k material or after completing these high-temperature heat treatment processes, form the cavity and fill the cavity with a low-k material.
  • Performing the reversion step can prevent high-temperature heat treatment from causing a chemical or physical change in the low-k material.
  • the element structure of the third embodiment can be formed.
  • FIGS. Fig. 47 (a), Fig. 48 (a), Fig. 49 (a), Fig. 50 (a) are plan views Fig. 47 (c), 048 (c), Fig. 49 (c), Fig. 50 (c) A—A ′ cross section of FIG. 47 (b), FIG. 48 (b), FIG. 49 (b), and FIG. 50 (b) are plan views, and FIG. 47 (c) and FIG. 48 (c).
  • FIG. 49 (c) and FIG. 50 (c) are cross-sectional views taken along line BB of FIG.
  • FIGS. 51 (a) and 52 are cross-sectional views in the same cross section as FIG. 20 (a)
  • FIG. 51 (b) is a cross-sectional view in the same cross section as FIG. 20 (b).
  • a cap insulating layer 8 is deposited on an SOI substrate in which a supporting substrate 1 made of silicon, a buried insulating layer 2 made of Si ⁇ , and a semiconductor layer 3 made of single crystal silicon are further stacked thereon.
  • FIG. 46 shows a cross section in this state.
  • the upper portion of the cap insulating layer 8 and the semiconductor layer 3 is patterned by a normal lithography process and a normal etching process such as RIE to obtain the shape shown in FIG.
  • the cap insulating layer 8 and the semiconductor layer 3 may be patterned by etching using a photoresist as a mask, or only the cap insulating layer 8 may be etched using a photoresist as a mask.
  • the patterning may be performed by etching the semiconductor layer 3 using the mask as a mask.
  • the cap insulating layer 8 is patterned so that its width is substantially the same as the width Wtop of the semiconductor layer upper region 28 (see FIG. 41) and is smaller than the width Wfin of the semiconductor layer lower region 29. You.
  • the etching depth of the semiconductor layer 3 is substantially equal to the height Htop of the semiconductor layer upper region 28. This state is shown in FIG.
  • a material to be a corner dummy layer is deposited and etched back to provide a corner dummy layer 22 on the side surface of the cap insulating layer and the exposed side surface of the semiconductor layer.
  • the material of the corner dummy layer 22 is, for example, SiN. In this process The resulting form is shown in FIG.
  • the semiconductor layer 3 is patterned by an etching process such as RIE to form an element region.
  • an etching process such as RIE to form an element region.
  • FIG. 4 a gate insulating film 4 is provided on the side surface of the semiconductor layer exposed by this step, and then a gate electrode material is deposited.
  • the gate electrode material is processed by a normal lithography and RIE step to form a gate electrode 5. . This state is shown in FIG.
  • a source / drain region 6 is formed by introducing a high-concentration first conductivity type impurity into a region of the semiconductor layer 3 which is not covered by the gate electrode 5.
  • corner dummy layer 22 is removed by etching to provide a cavity 24 to be an end insulator region 23.
  • a gate sidewall 14 is provided on the side surface of the gate electrode by depositing and etching back an insulating film, and thereafter, an interlayer insulating film is deposited, and a contact 17 and a wiring 18 are formed by an ordinary method. This state is shown in FIG.
  • a material to be an end insulator region 23 is deposited and etched back.
  • the end insulator region 23 may be provided on the side surface of the cap insulating layer and the side surface of the semiconductor layer which is exposed by etching.
  • the material of the end insulator region 23 is, for example, Si.
  • the material of the end insulator region 23 is a low dielectric constant material such as SiOF.
  • the semiconductor layer 3 is patterned by an etching process such as RIE using the cap insulating layer 8 and the end insulator region 23 as a mask to form an element region.
  • FIG. 52 is a cross-sectional view of the same cross section as FIG. 51 (a), and an end SiO 2 region 25 is formed instead of the cavity 24 in FIG.
  • FIG. 53 shows a potential distribution in the structure of FIG. 42 (b) in which a cavity is formed in a region where the semiconductor layer is recessed from the gate electrode. Note that the upper end of the semiconductor layer serving as a channel is a portion adjacent to the lower end of the cavity.
  • the curvature of equipotential lines at the corners below the cavity is significantly reduced, and the potential rise at the corners is suppressed. This indicates that the parasitic transistor at the corner is suppressed.
  • FIG. 54 (d) shows a plot of the potential distribution on the side surface of the semiconductor layer as in FIG. 9 (b).
  • the left end of the figure is the upper end of the semiconductor layer below the cavity.
  • the potential rise is reduced to 30.8 mV, and this embodiment suppresses the potential rise at the corner and the effect of the parasitic transistor at the corner is remarkable.
  • the surface of the end insulator region and the surface of the gate insulating film 4 (the interface on the gate electrode side is referred to as surface) be aligned because the gate electrode can be easily processed.
  • the effect of suppressing the potential rise at the upper corner portion of the semiconductor layer and suppressing the parasitic transistor can be obtained.
  • the side surface of the semiconductor layer 3 recedes from the gate electrode side with respect to the corner dummy layer 22 due to the sacrificial oxidation step and the wet etching step for the sacrificial oxide film.
  • the surface of the gate insulating film 4 recedes as compared with the surface of the end insulator region 23.
  • Fig. 89 shows an example of the structure. This structure is the same as that of the first embodiment shown in FIG. 4A after the formation of the structure shown in FIG. As described above, this is obtained when the semiconductor layer 3 is selectively narrowed with respect to the cap insulating layer 8 and the end insulator region 27 by an isotropic etching process.
  • FIG. 44 (a), Fig. 90 (b), Fig. 90 (c), and Fig. 91 (b) show Fig. 44 (a), Fig. 44 ( b), corresponding to the steps in FIG. 44 (c) and FIG. 44 (d).
  • the field effect transistor according to the fourth embodiment has a feature common to the third embodiment, the fourth embodiment, and the fifth embodiment. It has the feature that it does not have a constant width area.
  • the semiconductor layer end region 44 of the field effect transistor according to the fourth embodiment has a form in which the width of the semiconductor layer becomes narrower as the distance from the connection portion with the semiconductor layer main region 43 increases.
  • the end insulator region 27 provided between the semiconductor layer end region 44 and the gate electrode 5 forms a connection portion force between the semiconductor layer end region 44 and the semiconductor layer main region 43 as the force increases. It becomes thicker.
  • the maximum value of the thickness of the end insulator region 27 is larger than the thickness of the gate insulating film.
  • FIGS. 56, 57, 59, and 60 show the structure of the field-effect transistor according to the fourth embodiment, taking the case as an example.
  • FIG. 56, FIG. 57, FIG. 59 and FIG. 60 are cross-sectional views taken along the line AA ′ of FIG. 81 illustrating the conventional structure
  • FIG. 82 (a) and FIG. FIG. 2 is a cross-sectional view of a cross section corresponding to the cross section shown in FIG.
  • the symbol Wtop is the minimum width of the semiconductor layer edge region
  • the symbol Wei is the maximum width of the edge insulator region
  • the symbol Wfin is the width of the semiconductor layer main region.
  • FIGS. 56 and 59 show FIGS. 57 and 60 when the fourth embodiment is applied to a double-gate transistor having a cap insulating layer 8. The case where the fourth embodiment is applied to a transistor having a tri-gate structure having the gate insulating film 4 at the upper interface of the semiconductor layer without the cap insulating layer 8 is shown. In any of FIG. 56, FIG. 57, FIG. 59 or FIG.
  • an end insulator region 27 is provided between the semiconductor upper region 28 and the gate electrode 5, and at least a part of the end insulator region 27 is provided. At the position, the width of the end insulator region 27 is thicker than the gate insulating film 4.
  • FIG. 58 shows the shape at a position corresponding to the AA ′ cross section of FIG. 81 for explaining the conventional example, step by step.
  • a cap insulating layer 8 (an insulating film layer of SiO or the like) is deposited on the semiconductor layer 3, the cap insulating layer 8 is removed by a usual lithography and RIE process, and the upper portion of the semiconductor layer 3 is tapered. Etching is performed by RIE so that it has (Fig. 58 (a)).
  • an insulator film such as a SiO film is deposited and etched back to form an end insulator region 27 on the side surface of the cap insulating layer and the side surface of the semiconductor layer 3 (FIG. 58 (b)).
  • the semiconductor layer is etched using the cap insulating layer 8 and the end insulator region 27 as a mask (FIG. 58 (c)).
  • a gate insulating film 4 is provided on the side surface of the semiconductor layer exposed by this step, and after a gate electrode material is deposited, the gate electrode material is processed by a usual lithography and RIE step to form a gate electrode 5.
  • a taper etching technique of mixing a gas containing carbon when performing RIE is used. For example, by mixing CH with C1, a carbon compound is gradually deposited during etching, and a tapered shape is formed by utilizing the fact that etching does not proceed at the position where the carbon compound is deposited.
  • a high-concentration first conductivity type impurity is introduced into a region of the semiconductor layer 3 that is not covered with the gate electrode 5, to form a source / drain region 6.
  • an interlayer insulating film is deposited, and a contact 17 and a wiring 18 are formed by an ordinary method.
  • the cap insulating layer 8 is removed by an etching step such as RIE, and then the gate insulating film 4 is formed, and the subsequent steps are performed.
  • a tri-gate structure as shown in FIG. 57 is obtained.
  • Fig. 57 shows the cap insulating layer 8 by RIE. Is removed, the upper portion of the end insulating film is also etched at the same time.
  • the cap insulating layer 8 is removed by an etching process such as RIE, if the thickness of the buried insulating layer 2 is larger than that of the cap insulating layer 8, the etching of the buried insulating layer is performed simultaneously with the etching of the cap insulating layer.
  • the etching progresses or the cap insulating layer is removed Even if the etching progresses or the cap insulating layer is removed, a part of the embedded insulating film remains and a form in which the supporting substrate is not exposed is obtained, which is preferable.
  • a material that is resistant to etching with respect to the cap insulating layer for example, SiN, is used for the whole, the surface, or the layer at a certain depth of the filled insulating layer, even if the cap insulating layer is removed, the carrier is not removed.
  • FIGS. 61 (a), 62 (a), 63 (a) and 64 (a) are plan views of FIGS. 61 (c), 62 (c), 63 (c) and FIG. 61 (b), FIG. 62 (b), FIG. 63 (b), and FIG. 64 (b) are plan views of FIG. 61 (c).
  • FIG. 66 is a cross-sectional view taken along the line ⁇ _ ⁇ ′ of FIGS. 62 (c), 63 (c), and 65.
  • the position of the ⁇ -A ′ cross section of each drawing explaining the present embodiment is the same as the position of the BB cross section of FIG. 81 correspond to the positions of the cross section BB ′ in FIG. 81 showing the conventional example.
  • a cap insulating layer 8 made of, for example, Si ⁇ is formed on the semiconductor layer 3 on the buried insulating layer 2 (at this time,
  • the semiconductor layer 3 and the cap insulating layer 8 are patterned into an appropriate shape (the shape at this point is the same as in FIG. 3). Subsequently, at the interface between the semiconductor layer 3 and the cap insulating layer and at the interface between the semiconductor layer 3 and the buried insulating layer 2, the side surface of the semiconductor layer 3 recedes inward from the position of the end of the cap insulating layer 8, The semiconductor layer 3 is thermally oxidized. At this time, the oxide film thickly formed at the upper and lower corners of the semiconductor layer is This becomes insulator region 27 ( Figure 61).
  • a sacrificial oxide film layer 44 is formed on the side surface of the semiconductor layer 3.
  • the sacrificial oxide film layer 44 is removed from the side surfaces of the semiconductor layer 3 by an etching process such as wet etching to obtain the configuration shown in FIG.
  • a gate insulating film 4 is provided on the side surface of the semiconductor layer (FIG.
  • a gate electrode material is formed by a usual lithography and RIE process to form a gate electrode 5. I do. Subsequently, a high-concentration first conductivity type impurity is introduced into a region of the semiconductor layer 3 that is not covered with the gate electrode 5 to form a source / drain region. Thereafter, an interlayer insulating film is deposited, and contacts and wirings are formed by a usual method (FIGS. 64 and 65).
  • the cap insulating layer 8 is removed by an etching process such as RIE at a certain stage before the formation of the gate insulating film, and a subsequent process is performed. Then, a tri-gate structure as shown in FIG. 60 is obtained.
  • an etching process such as RIE
  • the cap insulating layer is etched simultaneously with the etching of the cap insulating layer. This is preferable because a form in which a part of the buried insulating film remains even when the cap insulating layer is removed and the supporting substrate is not exposed can be obtained.
  • the embedded insulating film may be removed.
  • the end insulator when the filled insulating layer easily diffuses an oxidizing agent, specifically when the buried insulating layer is SiO, the end insulator is also provided below the semiconductor layer. Region 27 is formed.
  • the filled insulating layer does not easily diffuse the oxidant, specifically, when the filled insulating layer is SiN, or when the filled insulating layer is SiO, but the film thickness is extremely thin If it is (for example, 10 nm or less), the end insulator region 27 is not formed below the semiconductor layer.
  • the fourth embodiment has an advantage that the height of the semiconductor layer end region 44 can be reduced as compared with the third embodiment.
  • the semiconductor layer upper region 28 of FIG. 55 this corresponds to a mode in which the semiconductor layer above the transition region 40 is removed, and the structure is simplified, so that the height of the semiconductor layer is reduced.
  • the manufacturing method is easy, for example, the end insulator region 27 can be formed only by thermally oxidizing the semiconductor layer 3 in the region in contact with the cap insulating layer 8.
  • the fourth embodiment has a structure in which the transition between the semiconductor layer upper region and the semiconductor layer lower region does not change sharply in the modes shown in Figs.
  • a gate is provided between the semiconductor layer and the gate electrode above the semiconductor layer. Since the end insulator 27 thicker than the insulating film 4 is provided and the channel is hardly formed on the side surface of the upper region of the semiconductor layer, the second problem can be sufficiently solved, and sufficient element performance can be obtained. it can. Further, since an end insulator 27 thicker than the gate insulating film 4 is provided between the semiconductor layer and the gate electrode above the semiconductor layer, the ability to solve the first problem is achieved similarly to the third embodiment. Excellent.
  • the field effect transistor according to the fifth embodiment has a feature common to the third embodiment, the fourth embodiment, and the fifth embodiment.
  • the semiconductor provided below 43 and the semiconductor layer provided below the main part 43
  • An end insulator region 27 which is an insulating film thicker than the gate insulating film 4 is provided between the layer end region 44 (semiconductor layer lower end region 42) and the gate electrode 5.
  • the field-effect transistor according to the fifth embodiment has a feature common to the third embodiment, the fourth embodiment, and the fifth embodiment. It is provided on both the upper portion of the main layer portion 43 and the lower portion of the main portion 43 of the semiconductor layer. Between the semiconductor layer end region 44 provided below 43 and the gate electrode 5, an end insulator region 27 which is thicker than the gate insulating film 4 and is an insulating film is provided.
  • the structure of the fifth embodiment is manufactured by, for example, the second manufacturing method of the fourth embodiment.
  • the buried insulating layer 2 is made of Si which easily diffuses an oxidizing agent such as oxygen in order to form the end insulator region 27 below the semiconductor layer.
  • cap insulating layer 8 is removed after the end insulating film 27 is formed, the configuration shown in FIG. 68 is formed, and if the cap insulating layer 8 is not removed, the configuration shown in FIG. 66 is formed.
  • the fifth embodiment suppresses a rise in potential at a lower corner portion of the semiconductor layer (a lower corner portion of the semiconductor layer) and suppresses a parasitic transistor at a lower corner portion of the semiconductor layer, thereby improving the characteristics of the transistor. It has the effect of improving.
  • the upper corner portion and the lower corner portion of the semiconductor layer are formed. Since the potential rise in both of them can be suppressed and the parasitic transistor can be suppressed in both the upper corner part and the lower corner part of the semiconductor layer, the effect of improving the characteristics of the transistor is remarkable.
  • the first to fourth embodiments of the present invention are not limited to FinFET, in which a semiconductor layer is formed on an insulator, and have no embedded insulating layer, and may be applied to FinFET.
  • This example is shown in FIGS. 71 (a), 71 (b), 72 (a), 72 (b), and 73.
  • FIGS. 1 (a), 10 (a), 13 (a), FIGS. 41 and 60 does not use the embedded insulating layer 2.
  • the sixth embodiment is different from the manufacturing method of the first embodiment to the fourth embodiment in that, instead of the SOI substrate which is a substrate having a buried insulating layer, a normal semiconductor substrate, typically Is formed when a silicon substrate is used. The shape during the manufacturing process is shown in FIG. FIG.
  • FIG. 74 (a) is a drawing corresponding to FIG. 18 (a) when a substrate having no embedded insulating layer is used.
  • FIGS. 74 (b) and 74 (c) show the state where the source Z drain region is formed and the transistor structure is formed, and correspond to FIGS. 19 (a) and 19 (b), respectively. I do.
  • the gate electrode 5 is provided under the semiconductor layer. It is desirable to provide an insulating film 31 under the gate electrode.
  • the insulating film 31 below the gate electrode is formed, for example, by processing a semiconductor substrate by etching to form a convex semiconductor layer 3, and then depositing an insulator such as Si ⁇ on the entire surface by a film forming technique such as a CVD method. C deposited insulator
  • the gate electrode lower insulating film 31 After flattening by a flattening technique such as the MP method, it can be formed by etching back the deposited insulator until the thickness of the insulator at the foot of the semiconductor layer 3 becomes an appropriate thickness.
  • the gate electrode lower insulating film 31 After the gate electrode lower insulating film 31 is formed, it is manufactured by applying the same manufacturing method as in the embodiment in which the embedded insulating layer is provided. It is desirable that the insulating film 31 below the gate electrode be formed of a material having a lower dielectric constant than SiO, in terms of suppressing parasitic capacitance between the gate electrode and the supporting substrate. In addition, when the insulating film 31 below the gate electrode is formed of a material having a lower dielectric constant than SiO, it is effective in suppressing the electric field concentration at the lower corner 35 of the semiconductor layer 3.
  • the side surface of the semiconductor layer 3 corresponds to the end insulator region 27.
  • the portion in contact with the semiconductor layer is the semiconductor layer end region 44.
  • the side surface of the semiconductor layer 3 is not in contact with the end insulator region 27, and the side surface of the semiconductor layer 3 faces the gate electrode via the gate insulating film, and a portion corresponding to the semiconductor layer main region 43. .
  • Embodiments of the present invention are not limited to FinFETs formed on a single semiconductor region, and a semiconductor layer forming a channel formation region is not limited to a FinFET formed on a single semiconductor region. May be applied. That is, as shown in FIG. 75 (a), the present invention may be applied to a transistor composed of a plurality of semiconductor layers each having a channel formed thereon, and each channel may be formed as shown in FIG. 75 (b). It may be applied to a transistor in which a plurality of semiconductor layers are connected to each other at a position away from the gate.
  • the positions indicated by AA in FIGS. 75A and 75B correspond to the positions of the cross section AA 'in each embodiment.
  • one of the upper corner portion and the lower corner portion of the semiconductor layer 3, or both the upper corner portion and the lower corner portion of the semiconductor layer 3 may have a rounded shape. good.
  • the lower corner portion of the semiconductor layer 3, the corner portion located near the upper end of the end insulator region in the semiconductor layer 3, the vicinity of the lower end of the end insulator region in the semiconductor layer 3 At least one of the corners may have a rounded shape.
  • FIG. 76 shows a form in which the upper corner is rounded in the form of Fig. 1 (a), and Fig. 77 (a) shows a form in which the upper corner is rounded in the form of Fig. 10 (a).
  • FIG. 77 (b) shows the form in which the upper corner and the lower corner are rounded in the form of FIG. 10 (b), and
  • FIG. 13 (a) shows the form in which the upper corner is rounded.
  • FIG. 78 (a) shows the configuration of FIG. 78
  • FIG. 78 (b) shows the configuration in which the upper corner portion and the lower corner portion are rounded in the configuration of FIG. 13 (b)
  • FIG. FIG. 79 shows a form in which both the corner located near the upper end of the insulator region and the corner portion located near the lower end of the end insulator region in the semiconductor layer 3 are both rounded.
  • These forms are formed by thermally oxidizing the semiconductor layer.
  • the upper corner of the semiconductor layer may be rounded, and the cap insulating layer 8 may be rounded (FIGS. 87 and 88).
  • Such a configuration is formed by performing sacrificial oxidation and wet etching of the semiconductor layer before forming the gate oxide film.
  • the corner of the semiconductor layer is rounded by the sacrificial oxidation, and the corner of the cap insulating layer is removed in the wet etching process.
  • the corner of the semiconductor layer is rounded by the sacrificial oxidation, and the corner of the cap insulating layer is removed in the wet etching process. Are formed when they are rounded by etching.
  • the surface of the gate insulating film is located at the same height as the upper end of the semiconductor layer and at a position lower than the upper end of the semiconductor layer. If at least a part of the cap insulating layer extends to the gate electrode side with respect to the surface of the gate insulating film at the position most receded from the electrode side (the interface on the gate electrode side) (the extension width is Wext in the figure) ), An electric field relaxation effect at the upper corner portion is obtained as in the first embodiment. Also, the size of the overhang width Wext may be set in the same manner as in the first embodiment. Other operations and principles are the same as those of the first embodiment.
  • the manufacturing method is the same as that of the first embodiment except for the features in the sacrificial oxidation and the subsequent wet etching step as described above.
  • the projection of the cap insulating layer on the side of the gate electrode beyond the surface of the gate insulating film at the position where the width of the semiconductor layer is the widest provides an electric field relaxation effect at the upper corner portion.
  • the cap insulating layer is recessed from the gate electrode side of the gate insulating film at the position where the width of the semiconductor layer is the widest as shown in FIG. In this case, the electric field relaxation effect can be obtained to some extent.
  • the overhang width Wext is horizontal (in the plane perpendicular to the direction in which the semiconductor layer 3 protrudes from the substrate and perpendicular to the channel length direction) as shown in FIG. Is defined in
  • the combination of each embodiment of the present invention with the process of rounding the corner portion does not combine with each embodiment of the present invention.
  • the amount of rounding required to obtain the electric field relaxation effect that can solve the first problem can be reduced, and the radius of curvature of the corner can be reduced. Therefore, when each embodiment of the present invention is combined with a process of rounding a part of a corner, a region having a curved surface is reduced, so that even if the second problem cannot be completely solved, the second problem can be solved. It can be greatly reduced.
  • the support substrate 1 is usually a single-crystal silicon wafer, but a substrate other than a silicon substrate such as quartz, glass, sapphire, or a semiconductor other than silicon may be used.
  • the buried insulating layer 2 is usually made of Si, but may be another insulator or a multilayer film made of a plurality of materials. Also, the insulating layer to be filled is porous SiO, Si ⁇ F, etc.
  • a low dielectric constant material having a lower dielectric constant than SiO may be used.
  • the support substrate is an insulator such as quartz, glass, or sapphire
  • the support substrate 1 may also serve as the insulating film 2 to be buried.
  • the thickness of the buried insulating layer 2 is generally about 50 nm to 2 ⁇ m, more typically 50 nm to 200 nm. The thickness may be 50 nm or less or 2 ⁇ m or more as needed.
  • a structure having no buried insulating layer 2 is used.
  • the semiconductor layer 3 is a single crystal from the viewpoint of improving the on-current and suppressing the off-current, but when the required on-current specification is low or the required off-current specification is large, It may be a material other than a single crystal, such as amorphous, polycrystalline, or the like.
  • the semiconductor layer 3 it is acceptable to replace the semiconductor layer 3 with a semiconductor layer other than silicon. Also, it can be replaced by a combination of two or more semiconductors.
  • the semiconductor layer has a shape protruding from the substrate surface.
  • the substrate surface is generally the upper surface of the support substrate 1, but in the case of a structure in which the embedded insulating layer 2 and the support substrate are integrated, the substrate surface is the upper surface of the embedded insulating layer 2.
  • the under-gate insulating film 31 is provided, it is the upper surface of the under-gate insulating film 31.
  • the height Hfm of the semiconductor layer 3 is typically 20 nm, 150 nm, and more typical.
  • the width of the semiconductor layer Wfm is typically 5 nm to 100 nm, which is more typical. Is between 15 nm and 50 nm. However, even if Hfm and Wfin use values outside this range, Good les ,.
  • the semiconductor layer in the channel formation region is depleted when a threshold voltage is applied to the gate electrode, which is a characteristic of FinFET (represented by a reduction in S factor, sharpening of ON-OFF characteristics, etc.). It is desirable from the viewpoint of utilizing In order to achieve a fully depleted state where the depletion layers extending from both sides of the semiconductor layer are in contact with each other with a threshold voltage applied to the gate electrode, Wfin is usually 50 nm or less, more typically 30 nm. It is preferable to set the following.
  • the gate insulating film 4 may be formed by thermal oxidation of silicon or may be a SiO film formed by another method. For example, an SiO film formed by radical oxidation may be used. Also, the gate insulating film should be replaced with an insulating material other than SiO. Also
  • the gate insulating film may be replaced with a high dielectric constant material such as Hf ⁇ or HfSiO.
  • the equivalent oxide film thickness of the gate insulating film is typically 1.2 nm to 3 nm. However, the oxide equivalent film thickness is obtained by multiplying the quotient obtained by dividing the thickness of the insulating film constituting the gate insulating film by the dielectric constant of the gate insulating film by the dielectric constant of Si ⁇ . When the gate insulating film is a multilayer film, the oxide film equivalent thickness is obtained for each layer by the above-described method, and these are added.
  • the gate electrode 5 may be a polycrystalline semiconductor such as polysilicon or a conductor other than a polycrystalline semiconductor such as a metal or a metal compound.
  • the gate electrode 5 is made of a polycrystalline semiconductor such as polysilicon, typically, the first conductivity type impurity having the same conductivity type as the channel is introduced into the polysilicon of the gate electrode 5 at a high concentration.
  • the gate electrode may be formed by a replacement gate (also called a replacement 'gate) process. That is, the shape of the gate electrode is formed with a dummy material, the first conductivity type impurity is introduced into the source Z drain region at a high concentration, the dummy material is covered with an insulating film, and then the dummy material is removed.
  • a gate electrode or a gate insulating film and a gate electrode may be buried in the cavity thus obtained.
  • the gate electrode material is formed of a semiconductor such as polysilicon or polycrystalline silicon-germanium mixed crystal
  • the introduction of impurities into the gate may be performed at the same time as the introduction of impurities into the source / drain. Further, it may be performed simultaneously with the deposition of the gate electrode material. Alternatively, it may be performed before a gate electrode material is deposited and processed into the shape of the gate electrode.
  • the gate electrode usually has a structure straddling the semiconductor layer.
  • the present invention provides a transistor in which a gate electrode is disposed above a semiconductor layer and on a side surface of a semiconductor layer, and an electric field from the gate above the semiconductor layer and an electric field from a gate on the side surface of the semiconductor layer cause electric field concentration. It is particularly effective for alleviating.
  • FIG. 94 shows the case where the second embodiment is applied to the FinFET where the gate electrode is not arranged above the semiconductor layer
  • FIG. 95 shows the case where the third embodiment is applied.
  • FIG. 94 is a sectional view corresponding to FIG. 10, and
  • FIG. 95 is a sectional view corresponding to FIG.
  • the source / drain region 6 is doped with a first conductivity type impurity at a high concentration.
  • the source / drain regions include all regions called shallow source / drain regions (also called extension regions) and regions called deep / source / drain regions in a Balta transistor.
  • the definition of the extension region and the deep source / drain region is not generally clarified, but, for example, the source / drain region formed in the strip-shaped region adjacent to the gate in FIG. It is assumed that the strip-shaped area at a position away from the gate includes both areas connected to each other.
  • a semiconductor such as silicon is epitaxially grown on a part of the source Z drain region, thereby increasing the size of the semiconductor layer forming the source / drain region. It is also possible to combine techniques for expanding in the plane.
  • a source / drain region is provided in a portion of the semiconductor layer 3 that is not covered by the gate electrode.
  • the source Z drain region provided in the part not covered by the gate electrode
  • a source / drain region that penetrates a region of the semiconductor layer 3 that is covered with the gate electrode may be provided.
  • a source / drain region may be provided with a certain width of an offset region from a semiconductor layer covered with a gate electrode.
  • the electric field strength at the end of the source / drain region decreases, so that the leakage current decreases.
  • This structure is desirably applied to DRAM (dynamic-random access memory) cell transistors, in which the reduction of leakage current is prioritized over the magnitude of drain current.
  • a low concentration of ceptor or donor impurity is introduced into the channel forming region 7.
  • the gate electrode is polysilicon of the first conductivity type
  • a low concentration of the second conductivity type impurity is typically introduced into the channel formation region because the threshold voltage needs to be set to an appropriate value.
  • the threshold voltage is set low, or if the gate electrode is made of metal or metal
  • no impurity is introduced into the channel formation region 7 or a low concentration of the first conductivity type impurity is introduced. May be.
  • a region adjacent to the source / drain region covered with the gate electrode is closer to the source / drain region covered by the gate electrode, and the second conductivity type is A halo region into which impurities are introduced slightly higher may be provided.
  • FIG. 96 shows a case where the method of increasing the concentration of the second conductivity type impurity in the upper part of the semiconductor layer 3 forming the channel formation region is applied to the first embodiment, and is applied to the second embodiment.
  • FIG. 97 shows the case, and FIGS. 98 and 99 show the case where the third embodiment is applied.
  • 96 corresponds to FIG. 1
  • FIG. 97 corresponds to FIG. 10
  • FIGS. 98 and 99 correspond to FIG. 41.
  • Symbol 47 in the figure is a region where the concentration of the second conductivity type impurity is high.
  • a technique of providing a high-concentration portion above a semiconductor layer of a FinFET to suppress a parasitic transistor is described in Japanese Patent Application Laid-Open No. 6-302817.
  • the impurity concentration above the semiconductor layer which is necessary for suppressing the parasitic transistor, can be set lower. If the impurity concentration in the upper part of the semiconductor layer is set lower, the electric field strength between the source / drain region end and the high concentration part in the upper part of the semiconductor layer becomes smaller, so that the height of the source / drain region end and the upper part of the semiconductor layer become higher. Leakage current between the impurity and the concentration portion is reduced.
  • the cap insulating layer 8 is provided on the semiconductor layer 3.
  • the cap insulating layer 8 is provided below the gate electrode.
  • the cap insulating layer 8 is arranged such that at least a part of the cap insulating layer 8 is located at a position lower than the upper end of the gate electrode. (The case where the gate electrode 5 does not straddle the semiconductor layer 3 is shown in FIGS. 94 and 95.)
  • the cap insulating layer 8 may be a single-layer insulating film such as a Si ⁇ film or a SiN film.
  • It may be a multilayer film made of an insulating film such as a SiO film or a SiN film. Also, cap insulating layer
  • Part or all of 8 may be made of a material having a lower dielectric constant than Si ⁇ . It is also acceptable that part or all of the cap insulating layer 8 is formed of a cavity.
  • the cap insulating layer 8 may be formed of a cavity and a protective insulating film made of an insulator such as SiO provided around the cavity.
  • the thickness of the cap insulating layer 8 is at least twice the thickness of the gate insulating film, more typically at least five times the thickness of the gate insulating film.
  • the thickness of the cap insulating layer 8 is typically 10 nm force, 100 nm or more, more typically 10 nm to 50 nm. If the gate insulating film is thin, the thickness may be 10 nm or less. Note that the thickness of the cap insulating layer 8 is a thickness as viewed in a direction perpendicular to the upper surface of the semiconductor layer, and is usually a thickness in the vertical direction.
  • the ratio of the thickness to the gate insulating film is calculated as the converted film thickness (the physical film thickness is divided by the dielectric constant. Quotient multiplied by a constant (usually the relative dielectric constant of SiO).
  • the thickness of the low dielectric constant region 10 provided above or below the semiconductor layer is typically 10 nm, typically 100 nm, more typically 20 to 50 nm. It is desirable to have a thickness of 10 nm or more to obtain a large effect.
  • the material in the low dielectric constant region is SiOF, porous Si ⁇ , porous siloxane, or Si.
  • materials in the low dielectric constant region include C, such as black diamond, amorphous carbon, and a low dielectric constant material made of an organic material.
  • the low dielectric constant region may be a cavity. Further, the low dielectric constant region may be formed of a porous material, and the low dielectric constant region may include many cavities.
  • the corner dummy layer 22 may be made of any material that can be selectively removed in the manufacturing process. For example, when SiN is used for the corner dummy layer 22,
  • Layer 22 is selectively etched.
  • the gate insulating film and the filled insulating layer are selectively etched.
  • the corner dummy layer 22 is selectively etched with hydrofluoric acid.
  • the inside of the cavity is filled with vacuum or a suitable gas.
  • the cavity 12 is not filled with the solid material.
  • the gate sidewall 14 may be a single-layer insulating film such as a SiO film or a SiN film.
  • a multilayer film made of an insulating film such as an O film or a SiN film is acceptable.
  • the thickness of the gate sidewall 14 is If it is necessary to miniaturize the force element, which is usually from 20 nm to 150 nm, it may be set to 20 nm or less.
  • the step of depositing the insulating film to be the gate side wall 14 uses a deposition technique with poor coverage. It is desirable that the cavity is not filled. For example, CVD is performed under relatively high gas partial pressure conditions.
  • CVD is performed under relatively high gas partial pressure conditions.
  • the gate side wall 14 is a multilayer film, only the insulating film to be deposited first may be formed by using a deposition technique having poor coverage.
  • the silicide layer 15 is typically made of a material such as titanium silicide, cobalt silicide, nickel silicide, or platinum silicide.
  • the silicide layer 15 is formed, for example, by depositing a metal such as titanium, cobalt, nickel, or platinum on the source / drain region by a deposition technique such as a sputtering method and performing a heat treatment to form a silicide between the metal and the silicon layer. It is formed by causing a reaction.
  • the contact 17 and the wiring 18 are formed by a normal contact forming step and a normal wiring step.
  • the contact 17 and the wiring 18 are usually formed of a metal such as aluminum or copper, and are appropriately combined with other conductive materials such as TiN.
  • the supporting insulating film 21 is usually an insulating film such as SiO deposited by a film forming technique such as CVD, but may be a film formed by another method as long as insulating properties can be obtained. Films other than ⁇ may be used.
  • the corner dummy layer 22 may be any material that can be selectively removed in the manufacturing process.
  • the corner dummy layer 22 is selectively etched with phosphoric acid. If the gate insulating film and the filled insulating layer are made of a material that cannot be etched with hydrofluoric acid, such as SiN, a corner dummy layer
  • the corner dummy layer 22 is selectively etched with hydrofluoric acid.
  • End insulator regions 23, 27 The end insulator regions (23, 27) can be made of any insulating material, for example, Si ⁇ , Si N
  • the regions 23 and 27 are formed of the same low dielectric constant material as the low dielectric constant region 10.
  • the low dielectric constant region 10 For example, SiOF, a porous material, fluorinated carbon, a cavity, and the like can be given.
  • the width Wei of the end insulator region (23, 27) should be thicker than the gate oxide film, which is smaller than half the width Wfin of the entire semiconductor.
  • a typical upper limit is on the order of 15nm, more typically 5nm to 10nm.
  • the height Htop of the end insulator region is not particularly limited, but is generally less than half of the total height of the semiconductor layer including the upper region 28, more typically from 5 nm. 25 nm.
  • the width Wei of the end insulator may be not constant, but the first problem is solved by being larger than the thickness of the gate oxide film at least at a position in contact with the upper end of the semiconductor layer 3. For this reason, if the width of the desired and end insulator Wei is not constant, a typical upper limit for the maximum value of Wei is on the order of 15 nm, more typically 5 nm to 10 nm.
  • Ion implantation typically introduces 5 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 21 cm 3 of donor or acceptor impurities into high concentration regions, such as source / drain regions and gate electrodes. More typically, 3 ⁇ 10 19 cm ⁇ 3 to 1 ⁇ 10 2 Q cm 3 of donor or acceptor impurities are introduced.
  • the impurity is introduced by, for example, ion implantation or vapor phase diffusion. Typical doses during ion implantation are 1 ⁇ 10 14 cm 2 to 3 ⁇ 10 15 cm— 2 , more typically 3 ⁇ 10 14 cm— 2 to 1 ⁇ 10 15 cm— 2 .
  • Net impurity concentration in the low concentration region such as the channel formation region is typically 1 X 10 17 cm- 3 From 1 ⁇ 10 19 cm— 3 , more typically 5 ⁇ 10 17 cm— 3 force 5 ⁇ 10 18 cm— 3 .
  • the transistor may locally exceed the typical value depending on ion implantation conditions.
  • the influence of the parasitic transistor is particularly remarkable, since the net impurity concentration of the second conductivity type Keru Contact to the channel formation region region is the case of 1 X 10 18 cm- 3 or more, the present invention
  • the concentration of the net impurity of the second conductivity type in the channel forming region is 1 ⁇ 10 18 cm— 3 It is particularly effective when applied to the above-described field-effect transistor.
  • electric field concentration occurs for reasons other than the suppression of parasitic transistors (for example, improvement of the reliability of the gate insulation film, improvement of the yield of the gate insulation film, and suppression of the short channel effect as described in the description of the second embodiment).
  • each embodiment of the present invention may be applied to a field-effect transistor in which a channel formation region is a first conductivity type.
  • the first conductivity type impurity introduced into the source Z drain region and the first conductivity type impurity introduced into the source / drain region are a donor impurity having an n type conductivity in the case of an n-channel transistor.
  • an impurity having a p-type conductivity may be selected.
  • the impurity of the second conductivity type introduced into the halo region is an acceptor impurity having a p-type conductivity in the case of an n-channel transistor, and a donor impurity having an n-type conductivity in the case of a p-channel transistor. Good choice ,.
  • Typical examples of the n-type impurity are arsenic, phosphorus, and antimony.
  • Typical examples of the p-type impurity are boron and indium.
  • Activation of the ion-implanted impurities is performed by a heat treatment such as annealing or lamp annealing in a normal electric furnace after the ion implantation.
  • a heat treatment such as annealing or lamp annealing in a normal electric furnace after the ion implantation.
  • the heat treatment for activating the ions implanted into the channel region may be performed immediately after the ion implantation, or may be combined with the heat treatment for activating the impurities introduced into the source / drain regions.
  • Impurity introduction into the source / drain regions may be performed by introducing the impurity into the region not covered by the gate electrode after the formation of the gate electrode.
  • a method in which an impurity is previously introduced into a region where a drain region is to be formed may be used.
  • each part constituting the semiconductor device such as the source Z drain region 6, the interlayer insulating film 16, the contact 17, the wiring 18 and the like
  • the arrangement is the same as that shown in FIGS. 8 and 9 for explaining the first embodiment.
  • the polarity is reversed in the power S and p channel transistors described mainly for the n channel transistor (for example, the potential rise in the n channel transistor and the potential in the p channel transistor are reversed).
  • a decrease in the threshold voltage of an n-channel transistor can be interpreted as a rise in the threshold voltage of a p-channel transistor, and an increase in the voltage or potential can be interpreted as a decrease in the voltage-to-potential.
  • the sign of the applied voltage such as the drain voltage is reversed.

Landscapes

  • Thin Film Transistor (AREA)

Abstract

Un transistor à effet de champ, comprenant une couche de semiconducteur dépassant au dessus d'une surface plate d'une base, une électrode de grille agencée de façon à chevaucher la couche de semiconducteur s'étendant depuis la partie supérieure de la couche de semiconducteur le long des deux surfaces latérales opposées de celle-ci, une couche d'isolation de grille étant interposée entre l'électrode de grille et chaque surface latérale de la couche de semiconducteur, une couche d'isolation de coiffe étant formée sur la surface supérieure de la couche de semiconducteur sous l'électrode de grille et des régions source / drain étant formées dans une région de la couche de semiconducteur qui n'est pas recouverte par l'électrode de grille, est caractérisé en ce que la couche d'isolation de coiffe comporte une partie faisant saillie, s'étendant au-delà de la surface de la couche d'isolation de grille dans la direction parallèle à la surface plate de la base et perpendiculaire à la direction de la longueur du canal reliant une paire de régions source / drain.
PCT/JP2005/001064 2004-01-30 2005-01-27 Transistor à effet de champ et procédé pour fabriquer celui-ci WO2005074035A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005517473A JP5170958B2 (ja) 2004-01-30 2005-01-27 電界効果型トランジスタおよびその製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004023887 2004-01-30
JP2004-023887 2004-01-30

Publications (1)

Publication Number Publication Date
WO2005074035A1 true WO2005074035A1 (fr) 2005-08-11

Family

ID=34823892

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2005/001064 WO2005074035A1 (fr) 2004-01-30 2005-01-27 Transistor à effet de champ et procédé pour fabriquer celui-ci

Country Status (2)

Country Link
JP (1) JP5170958B2 (fr)
WO (1) WO2005074035A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7465998B2 (en) 2004-09-21 2008-12-16 Kabushiki Kaisha Toshiba Semiconductor device
JP2011097058A (ja) * 2009-10-28 2011-05-12 Taiwan Semiconductor Manufacturing Co Ltd 異なる誘電材料を用いたインター装置ｓｔｉ領域とイントラ装置ｓｔｉ領域の形成
TWI556322B (zh) * 2014-03-28 2016-11-01 英特爾股份有限公司 使用選擇性再生的頂部接點的半導體裝置及其製造方法
CN113972279A (zh) * 2014-04-18 2022-01-25 索尼公司 场效应晶体管
WO2022234691A1 (fr) * 2021-05-06 2022-11-10 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie à semi-conducteur

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1093093A (ja) * 1996-09-18 1998-04-10 Toshiba Corp 半導体装置およびその製造方法
JP2002009289A (ja) * 2000-06-20 2002-01-11 Nec Corp 電界効果型トランジスタ及びその製造方法
JP2002270850A (ja) * 2001-03-13 2002-09-20 National Institute Of Advanced Industrial & Technology 二重ゲート電界効果トランジスタ

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3175691B2 (ja) * 1998-05-08 2001-06-11 日本電気株式会社 多層配線半導体装置の製造方法
KR100304713B1 (ko) * 1999-10-12 2001-11-02 윤종용 부분적인 ｓｏｉ 구조를 갖는 반도체소자 및 그 제조방법
JP2002050767A (ja) * 2000-08-04 2002-02-15 Mitsubishi Electric Corp 半導体装置及びその製造方法
US7029958B2 (en) * 2003-11-04 2006-04-18 Advanced Micro Devices, Inc. Self aligned damascene gate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1093093A (ja) * 1996-09-18 1998-04-10 Toshiba Corp 半導体装置およびその製造方法
JP2002009289A (ja) * 2000-06-20 2002-01-11 Nec Corp 電界効果型トランジスタ及びその製造方法
JP2002270850A (ja) * 2001-03-13 2002-09-20 National Institute Of Advanced Industrial & Technology 二重ゲート電界効果トランジスタ

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7465998B2 (en) 2004-09-21 2008-12-16 Kabushiki Kaisha Toshiba Semiconductor device
US7816242B2 (en) 2004-09-21 2010-10-19 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
JP2011097058A (ja) * 2009-10-28 2011-05-12 Taiwan Semiconductor Manufacturing Co Ltd 異なる誘電材料を用いたインター装置ｓｔｉ領域とイントラ装置ｓｔｉ領域の形成
KR101229709B1 (ko) * 2009-10-28 2013-02-05 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 인터디바이스 ｓｔｉ 영역의 제조 및 상이한 유전체 물질을 이용한 인트라디바이스 ｓｔｉ 영역
US8592918B2 (en) 2009-10-28 2013-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Forming inter-device STI regions and intra-device STI regions using different dielectric materials
US8846466B2 (en) 2009-10-28 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Forming inter-device STI regions and intra-device STI regions using different dielectric materials
TWI556322B (zh) * 2014-03-28 2016-11-01 英特爾股份有限公司 使用選擇性再生的頂部接點的半導體裝置及其製造方法
US10727339B2 (en) 2014-03-28 2020-07-28 Intel Corporation Selectively regrown top contact for vertical semiconductor devices
CN113972279A (zh) * 2014-04-18 2022-01-25 索尼公司 场效应晶体管
WO2022234691A1 (fr) * 2021-05-06 2022-11-10 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie à semi-conducteur

Also Published As

Publication number Publication date
JPWO2005074035A1 (ja) 2007-09-13
JP5170958B2 (ja) 2013-03-27

Similar Documents

Publication Publication Date Title
US7326634B2 (en) Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
CN100541797C (zh) 有部分或全包围栅电极的非平面半导体器件及其制造方法
US7560755B2 (en) Self aligned gate JFET structure and method
KR100748261B1 (ko) 낮은 누설전류를 갖는 ｆｉｎ 전계효과트랜지스터 및 그제조 방법
TWI509736B (zh) 半導體結構及其形成方法
CN102122645B (zh) 集成电路结构、其制造方法和使用方法
CN101604691B (zh) 半导体器件和半导体器件的制造方法
TWI485854B (zh) 於三維電晶體中基於應變隔離材料之應變工程
US7790548B2 (en) Methods of fabricating field effect transistors including recessed forked gate structures
CN100378965C (zh) 形成差别应变主动区的方法及其应变主动区
JP2005229107A (ja) 電界効果トランジスタ及びその製造方法
KR20050119424A (ko) 접합 영역의 어브럽트니스를 개선시킬 수 있는 전계 효과트랜지스터 및 그 제조방법
KR20050094576A (ko) 3차원 시모스 전계효과 트랜지스터 및 그것을 제조하는 방법
JP2007299951A (ja) 半導体装置およびその製造方法
JP2012004473A (ja) 半導体装置及び半導体装置の製造方法
US7550330B2 (en) Deep junction SOI MOSFET with enhanced edge body contacts
CN109801960B (zh) 半导体器件及其制造方法及包括该器件的电子设备
CN111370306B (zh) 晶体管的制作方法及全包围栅极器件结构
CN104347508B (zh) 半导体结构及其形成方法
WO2005074035A1 (fr) Transistor à effet de champ et procédé pour fabriquer celui-ci
JP4178296B2 (ja) 半導体装置及びその製造方法
JP2016058726A (ja) 半導体装置およびその製造方法
US20250040196A1 (en) Fin field-effect transistor device with hybrid conduction mechanism
JP2007123519A (ja) 半導体装置の製造方法及び半導体装置
KR20060077546A (ko) 반도체 소자의 제조 방법

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2005517473

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

WWW Wipo information: withdrawn in national office

Country of ref document: DE

122 Ep: pct application non-entry in european phase
点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载