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WO2005074035A1 - Field effect transistor and method for manufacturing same - Google Patents

Field effect transistor and method for manufacturing same Download PDF

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Publication number
WO2005074035A1
WO2005074035A1 PCT/JP2005/001064 JP2005001064W WO2005074035A1 WO 2005074035 A1 WO2005074035 A1 WO 2005074035A1 JP 2005001064 W JP2005001064 W JP 2005001064W WO 2005074035 A1 WO2005074035 A1 WO 2005074035A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor layer
region
gate electrode
layer
insulating film
Prior art date
Application number
PCT/JP2005/001064
Other languages
French (fr)
Japanese (ja)
Inventor
Risho Koh
Kiyoshi Takeuchi
Katsuhiko Tanaka
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to JP2005517473A priority Critical patent/JP5170958B2/en
Publication of WO2005074035A1 publication Critical patent/WO2005074035A1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H10D30/0245—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6212—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies having non-rectangular cross-sections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6212—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies having non-rectangular cross-sections
    • H10D30/6213—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies having non-rectangular cross-sections having rounded corners

Definitions

  • the present invention relates to a field-effect transistor and a method for manufacturing the same.
  • a gate electrode is provided on both sides of a protruding semiconductor region, and a channel is formed on both sides of the semiconductor region. Proposed.
  • Typical structures are shown in Figs. 81 is a plan view, FIG. 82 (a) is a cross-sectional view taken along the line AA ′ of FIG. 81, and FIG. 82 (b) is a cross-sectional view taken along the line BB ′ of FIG.
  • a buried insulating film 2 is provided on a support substrate 1, and a semiconductor layer 3 is provided thereon.
  • a gate electrode 5 is provided on a side surface of the semiconductor layer 3 via a gate insulating film 4 (FIG. 82 (a)).
  • a high-concentration impurity of the first conductivity type is introduced to form a source / drain region 6.
  • the semiconductor layer 3 covered with the gate electrode 5 forms a channel forming region 7, and by applying an appropriate voltage to the gate electrode, carriers of the first conductivity type are induced on the surface to form a channel.
  • a low concentration impurity of the second conductivity type is introduced or not introduced into the channel forming region.
  • an AA 'cross section in FIG. 81 is a plane perpendicular to a direction connecting the two source Z drain regions (hereinafter, this direction is referred to as a channel length direction) at a position where the semiconductor layer is covered with the gate. 81, and a section taken along line BB ′ of FIG. 81 shows a section in the channel length direction.
  • a FinFET when the difference between the thickness of the insulating film provided on the semiconductor layer 3 and the thickness of the insulating film provided on the side surface of the semiconductor layer 3 is small, when the transistor is turned on, Channels are formed on both side surfaces of the semiconductor layer 3 forming the formation region 7 and on the upper surface of the semiconductor layer.
  • This structure is called a tri-gate structure.
  • the relationship between the thickness of the insulating film provided over the semiconductor layer 3 and the thickness of the insulating film provided on the side surface of the semiconductor layer 3 is typically that one of the thicknesses is the other.
  • FIG. 82 (a) and FIG. 82 (b) show a typical structure of a tri-gate transistor.
  • FIGS. 83 (a) and 83 (b) show typical cross-sectional shapes of a transistor having a double gate structure. These are drawn on the section A-A in FIG. 81 and the section BB 'in FIG. 81, respectively.
  • the concentration of the electric field in the upper corner portion 34 of the semiconductor layer 3 indicates the influence on the transistor characteristics.
  • a structure in which the upper corner portion of the semiconductor layer 3 is rounded has been proposed (Japanese Patent Application Laid-Open No. 2002-118255: FIG. 28 of Patent Document 1 and related description). This is shown in Figure 85.
  • Such a structure is formed, for example, by thermally oxidizing the upper corner of the semiconductor layer.
  • FIG. 85 shows a cross-sectional view at the same position as FIG. 82 (a).
  • the ratio between the thickness of the cap insulating layer 8 and the thickness of the gate insulating film 4 used in the description of the difference between the double gate structure and the tri-gate structure is such that both have the same dielectric constant. It is based on having. If the two have different dielectric constants, the respective film thicknesses are divided by the respective dielectric constants.
  • the above comparison may be made by using the product of the two ratios) as the converted film thickness.
  • Patent Document 2 Japanese Patent Application Laid-Open No. 2002-270850 aims at suppressing an increase in parasitic capacitance due to position mismatch and a decrease in operating performance due to a change in parasitic resistance.
  • a field effect transistor having an island-shaped semiconductor crystal layer having a drain region and a channel region, and a gate electrode provided on both sides of the channel region opposed to each other via a gate insulating film. Then, as one embodiment, a configuration in which the width of the island-shaped semiconductor crystal layer in the channel region portion (portion sandwiched between both gate electrodes) is reduced in order to further suppress the short channel effect is described.
  • the insulating film on the top of the island-shaped layer has a shape protruding from the side surface of the island-shaped layer.
  • n-channel transistor S for a p-channel transistor
  • the force described for the n-channel transistor S, for a p-channel transistor if the polarity is reversed (for example, a potential rise in an n-channel transistor can be read as a potential drop in a p-channel transistor.
  • a decrease in the threshold voltage of a transistor can be read as an increase in the threshold voltage of a p-channel transistor.
  • FIGS. 84 (a) and 84 (b) show the results of simulating the potential distribution at the upper end of the semiconductor layer 3 in the AA ′ section of FIG. 81.
  • FIG. 84 (a) shows the case of the tri-gate structure, corresponding to the cross section of FIG. 82 (a)
  • FIG. 84 (b) shows the case of the double gate structure, corresponding to the cross section of FIG. 83 (a). Is what you do.
  • the contour lines in the figure are equipotential lines based on intrinsic semiconductor silicon, and are -0.4 V, -0.2 V, 0.0 V, 0.2 V, 0.4 V from the center of the semiconductor layer to the outside. It is.
  • the impurity concentration in the channel region is 8 ⁇ 10 18 cm— 3
  • the gate voltage is zero volts
  • the gate oxide film thickness is 2 nm. Since the potential is based on intrinsic semiconductor silicon, the potential of zero-biased n + -type silicon is 0.56 V, and the potential of the zero-biased gate is 0.56 V.
  • the simulation results for each element structure shown in this specification were performed under the same conditions as described above, unless otherwise specified.
  • FIGS. 92 (a) and 92 (b) are cross-sectional views at positions corresponding to the upper portions of the semiconductor layers in the cross-sections of FIGS. 82 (a) and 83 (a), respectively.
  • the upper corner portion 34 of the semiconductor layer 3 is processed into a round shape by performing a rounding process such as thermal oxidation, so that the electric field at the corner portion is reduced, and the parasitic transistor is formed.
  • a rounding process such as thermal oxidation
  • the thickness, carrier mobility, and interface state density of the gate insulating film formed by thermal oxidation depend on the plane orientation.
  • the basic characteristics of a transistor, such as the threshold voltage and the drain current strongly depend on the thickness of the gate insulating film, carrier mobility, and interface state density. A new parasitic transistor with different characteristics will appear, and the characteristics of FinFET will change. In particular, if the radius of curvature of the corners is increased in order to strongly suppress the parasitic transistor described in the first problem, the second problem becomes more prominent.
  • An object of the present invention is to provide a FinFET with improved element characteristics by preventing a parasitic transistor from being formed at a corner of a semiconductor layer protruding from the base plane of the FinFET.
  • the following field-effect transistor and a method for manufacturing the same can be provided.
  • the cap insulating layer has an overhanging portion extending from the surface of the gate insulating film in a direction parallel to the plane of the base and perpendicular to a channel length direction connecting the pair of source / drain regions.
  • Field-effect transistor Field-effect transistor.
  • the overhang portion has an overhang width with respect to the surface of the gate insulating film of 5 nm or more,
  • the field effect transistor according to Invention 1 which has a thickness of 20 nm or less.
  • the overhang portion has the widest width in a direction parallel to the substrate plane of the semiconductor layer and perpendicular to the channel length direction, and overhangs the surface of the gate insulating film at the position.
  • Invention 7 The method for manufacturing a field-effect transistor according to Invention 7, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.
  • the invention having a low dielectric constant region having a lower dielectric constant than SiO below the semiconductor layer.
  • a low dielectric constant region having a lower dielectric constant than SiO is provided below the semiconductor layer, and a low dielectric constant region having a lower dielectric constant than SiO is not provided below the gate electrode.
  • the semiconductor layer is provided on the first insulating layer via a second insulating layer made of a material different from that of the first insulating layer,
  • a low dielectric constant region having a lower dielectric constant than SiO is provided below the semiconductor layer, and a low dielectric constant region having a lower dielectric constant than SiO is not provided below the gate electrode.
  • a method for manufacturing a transistor. (26) A step of forming a gate insulating film on the side surface of the protruding semiconductor layer, a step of depositing a gate electrode material, and a step of patterning the gate electrode material deposited film to form a gate electrode ,
  • Invention 25 The method for manufacturing a field-effect transistor according to Invention 25, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.
  • the invention further comprising a step of backfilling the cavity with a material having a lower dielectric constant than SiO.
  • a field-effect transistor having an end insulator region.
  • the semiconductor layer includes a semiconductor layer upper region in which a width W of the semiconductor layer in a direction perpendicular to a channel length direction connecting the pair of source / drain regions and parallel to the substrate plane is smaller than a width of a lower portion thereof.
  • a semiconductor layer lower region located below the layer upper region and having a width W of the semiconductor layer larger than the width of the semiconductor layer upper region;
  • a side surface of the semiconductor layer is recessed from a side surface of the semiconductor layer in the semiconductor layer lower region, and an end portion thicker than the gate insulating film is provided between the recessed side surface and the gate electrode.
  • a field-effect transistor having an insulator region.
  • the width W of the upper portion of the semiconductor layer gradually decreases with a constant gradient toward the upper end of the semiconductor layer, and accordingly, the thickness of the end insulator region is reduced.
  • Invention 32 The field-effect transistor of Invention 32, which gradually increases with the upward force.
  • the width W of the upper part of the semiconductor layer gradually decreases toward the upper end of the semiconductor layer so that the side surface of the semiconductor layer has a curvature, and accordingly, the end insulator region 32.
  • the field-effect transistor according to Invention 32 wherein the thickness of the semiconductor layer gradually increases with the directional force toward the upper end of the semiconductor layer.
  • the semiconductor layer includes a semiconductor layer upper region in which a width W of the semiconductor layer in a direction perpendicular to a channel length direction connecting the pair of source / drain regions and parallel to the base plane is smaller than a width of a lower portion thereof.
  • the width of the semiconductor layer is located below the upper region.
  • W has a semiconductor layer lower region larger than the width of the semiconductor layer upper region
  • the semiconductor layer upper region has a transition region in which the width w of the semiconductor layer continuously changes at a portion connected to the semiconductor layer lower region, and an upper end of the semiconductor layer from an end of the transition region.
  • the width W is constant over
  • a field effect transistor having an end insulator region thicker than the gate insulating film between the semiconductor layer upper region and the gate electrode.
  • Invention 45 The method for manufacturing a field-effect transistor according to Invention 45, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.
  • a method for manufacturing a field-effect transistor according to invention 32 comprising:
  • a method for manufacturing a field effect transistor comprising: a step of forming a gate insulating film on a side surface of a semiconductor layer exposed by the etching; and a step of forming an end insulator region including a cavity by removing the corner dummy layer.
  • a method for manufacturing a field-effect transistor comprising: a step of forming a gate insulating film on a side surface of a semiconductor layer exposed by the above-mentioned etching; and a step of forming an end insulator region comprising a cavity by removing a first corner dummy layer.
  • a method for manufacturing a field-effect transistor according to invention 35 comprising:
  • the side surfaces of the semiconductor layer are covered and exposed.
  • Invention 51 The method for manufacturing a field-effect transistor according to Invention 51, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.
  • a method of manufacturing a field effect transistor comprising: a step of forming an upper semiconductor layer region that gradually becomes smaller as the force increases, and a step of forming an edge insulating region that gradually increases in thickness accordingly.
  • Invention 54 The method for manufacturing a field-effect transistor according to Invention 54, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.
  • Invention 54 The method for manufacturing a field-effect transistor according to Invention 54, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.
  • a first end insulator region thicker than the gate insulating film is provided between the semiconductor layer and the gate electrode;
  • a field-effect transistor having a second end insulator region, which is thicker than the gate insulating film, between a gate electrode and a lower side surface of the semiconductor layer.
  • the semiconductor layer includes a semiconductor layer upper region in which a width W of the semiconductor layer in a direction perpendicular to a channel length direction connecting the pair of source / drain regions and parallel to the base plane is smaller than a width of a lower portion thereof.
  • a semiconductor layer main portion region located below the upper region and having a width W of the semiconductor layer larger than the width of the semiconductor layer upper region; and a semiconductor layer main portion region located below the semiconductor layer main portion region and having a width W of the semiconductor layer.
  • a semiconductor layer lower region smaller than a width of the semiconductor layer main portion region;
  • a side surface of the semiconductor layer is recessed from a side surface of the semiconductor layer in the semiconductor layer main portion region, and a portion of the semiconductor layer upper region which is thicker than the gate insulating film is provided between the recessed side surface and the gate electrode. Having one end insulator region,
  • a side surface of the semiconductor layer is recessed from a side surface of the semiconductor layer in the semiconductor layer main portion region, and a gap between the recessed side surface and the gate electrode is thicker than the gate insulating film.
  • a field-effect transistor having two end insulator regions.
  • a method for manufacturing a field-effect transistor according to invention 58 comprising:
  • the semiconductor layer is placed in an oxidizing atmosphere so that the side surface of the semiconductor layer recedes inward. Oxidize,
  • a field effect type having a step of forming a lower region of the semiconductor layer in which the width W of the semiconductor layer gradually decreases as it moves toward the lower end of the semiconductor layer, and a second end insulating region in which the thickness gradually increases accordingly.
  • Invention 60 The method for manufacturing a field-effect transistor according to Invention 60, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.
  • Inventions 1, 6, 9, 24, 31 wherein a supporting substrate is provided below the protruding semiconductor, and the semiconductor layer is provided on the supporting substrate via a buried insulating film. — Field effect transistor of any of 44, 57-59.
  • the overhang portion has an overhang width relative to the surface of the gate insulating film.
  • the semiconductor layer is formed on a first insulating layer and is made of a material different from that of the first insulating layer.
  • a field-effect transistor in which the gate electrode has a portion on the first insulating layer and directly in contact with the first insulating layer without through a second insulating layer.
  • the gate electrode is formed so as to extend over the semiconductor layer and to extend on both sides facing each other so as to straddle the semiconductor layer from the viewpoint of ease of manufacture, formation of a tri-gate structure, and the like. It is preferable to have
  • substrate surface means any plane parallel (horizontal) to the substrate.
  • an increase in potential at an upper corner of the semiconductor layer can be reduced, and the influence of a parasitic transistor can be reduced.
  • the present invention it is possible to suppress an increase in the potential of the corner portion and suppress the parasitic transistor without rounding the corner portion. Alternatively, according to the present invention, it is possible to reduce the amount of corner rounding required to suppress the rise in the potential of the corner.
  • the present invention it is possible to prevent the electric field from the drain region from invading the channel portion via the cap insulating layer or the buried insulating film, thereby preventing the characteristics of the short-channel transistor from deteriorating.
  • FIG. 1 A cross-sectional view illustrating a first embodiment.
  • FIG. 2 is a cross-sectional view illustrating a first embodiment.
  • FIG. 3 is a cross-sectional view and a plan view illustrating a first embodiment.
  • FIG. 4 is a cross-sectional view and a plan view illustrating a first embodiment.
  • FIG. 5 is a cross-sectional view and a plan view illustrating a first embodiment.
  • FIG. 6 is a cross-sectional view illustrating a first embodiment.
  • FIG. 7 is a cross-sectional view illustrating a first embodiment.
  • FIG. 8 is a plan view illustrating a first embodiment.
  • FIG. 9 is an explanatory view of the structure and effects of the first embodiment.
  • FIG. 10 is a sectional view illustrating a second embodiment.
  • FIG. 11 is a cross-sectional view illustrating a second embodiment.
  • FIG. 12 is a sectional view illustrating a second embodiment.
  • FIG. 13 is a sectional view illustrating a second embodiment.
  • FIG. 14 is a sectional view illustrating a second embodiment.
  • FIG. 15 is a sectional view illustrating a second embodiment.
  • FIG. 16 is a sectional view illustrating a second embodiment.
  • FIG. 17 is a sectional view illustrating a second embodiment.
  • FIG. 18 is a cross-sectional view and a plan view illustrating a second embodiment.
  • FIG. 19 is a cross-sectional view and a plan view illustrating a second embodiment.
  • FIG. 20 is a sectional view illustrating a second embodiment.
  • FIG. 21 is a plan view illustrating a second embodiment.
  • FIG. 22 is a cross-sectional view illustrating a second embodiment.
  • FIG. 23 is a cross-sectional view and a plan view illustrating a second embodiment.
  • FIG. 24 is a cross-sectional view and a plan view illustrating a second embodiment.
  • FIG. 25 is a cross-sectional view and a plan view illustrating a second embodiment.
  • FIG. 26 is a sectional view illustrating a second embodiment.
  • FIG. 27 is a plan view illustrating a second embodiment.
  • FIG. 28 is a sectional view illustrating a second embodiment.
  • FIG. 29 is a sectional view illustrating a second embodiment.
  • FIG. 30 is a cross-sectional view and a plan view illustrating a second embodiment.
  • FIG. 31 is a cross-sectional view and a plan view illustrating a second embodiment.
  • FIG. 32 is a cross-sectional view illustrating a second embodiment.
  • FIG. 33 is a sectional view illustrating a second embodiment.
  • FIG. 34 is a sectional view illustrating a second embodiment.
  • FIG. 35 is a cross-sectional view illustrating a second embodiment.
  • FIG. 36 is a plan view illustrating a second embodiment.
  • FIG. 37 is a cross-sectional view illustrating a second embodiment.
  • FIG. 38 is a plan view illustrating the effect of the second embodiment.
  • FIG. 39 An explanatory diagram of an effect of the second embodiment.
  • FIG. 40 is a cross-sectional view and a plan view illustrating a third embodiment.
  • FIG. 41 is a sectional view illustrating a third embodiment.
  • FIG. 42 is a sectional view illustrating a third embodiment.
  • FIG. 43 is a cross-sectional view illustrating a third embodiment.
  • FIG. 44 is a cross-sectional view illustrating a third embodiment.
  • FIG. 45 is a cross-sectional view illustrating a third embodiment.
  • FIG. 46 is a sectional view illustrating a third embodiment.
  • FIG. 47 is a cross-sectional view and a plan view illustrating a third embodiment.
  • FIG. 48 is a cross-sectional view and a plan view illustrating a third embodiment.
  • FIG. 49 is a cross-sectional view and a plan view illustrating a third embodiment.
  • FIG. 50 is a cross-sectional view and a plan view illustrating a third embodiment.
  • FIG. 51 is a cross-sectional view illustrating a third embodiment.
  • FIG. 52 is a sectional view illustrating a third embodiment.
  • FIG. 53 is an explanatory diagram of an effect of the third embodiment.
  • FIG. 54 is an explanatory diagram of effects of the second embodiment and the third embodiment
  • FIG. 55 is a cross-sectional view illustrating a third embodiment.
  • FIG. 56 is a cross-sectional view explaining a fourth embodiment.
  • FIG. 57 is a cross-sectional view illustrating a fourth embodiment.
  • FIG. 58 is a cross-sectional view illustrating a fourth embodiment.
  • FIG. 59 is a cross-sectional view explaining a fourth embodiment.
  • FIG. 60 is a sectional view illustrating a fourth embodiment.
  • FIG. 61 is a cross-sectional view and a plan view illustrating a fourth embodiment.
  • FIG. 62 is a cross-sectional view and a plan view illustrating a fourth embodiment.
  • FIG. 63 is a cross-sectional view and a plan view illustrating a fourth embodiment.
  • FIG. 64 is a cross-sectional view illustrating a fourth embodiment.
  • FIG. 65 is a plan view illustrating a fourth embodiment.
  • FIG. 66 is a sectional view illustrating a fourth embodiment.
  • FIG. 67 is a sectional view illustrating a fifth embodiment.
  • FIG. 68 is a sectional view illustrating a fifth embodiment.
  • FIG. 69 A cross-sectional view illustrating a fifth embodiment.
  • FIG. 71 is a cross-sectional view illustrating a sixth embodiment.
  • FIG. 72 A cross-sectional view illustrating a sixth embodiment.
  • FIG. 73 is a cross-sectional view illustrating a sixth embodiment.
  • FIG. 74 is a cross-sectional view illustrating a sixth embodiment.
  • FIG. 75 is a plan view illustrating another embodiment of the present invention.
  • FIG. 76 is a plan view illustrating another embodiment of the present invention.
  • FIG. 77 is a plan view illustrating another embodiment of the present invention.
  • FIG. 78 is a plan view illustrating another embodiment of the present invention.
  • FIG. 79 is a plan view illustrating another embodiment of the present invention.
  • FIG. 80 is a plan view illustrating an embodiment of the present invention.
  • FIG. 87 is a sectional view for explaining another embodiment of the present invention.
  • FIG. 88 is a sectional view illustrating another embodiment of the present invention.
  • FIG. 89 is a sectional view illustrating another embodiment of the present invention.
  • FIG. 90 is a cross-sectional view illustrating another embodiment of the present invention.
  • FIG. 91 is a sectional view illustrating another embodiment of the present invention.
  • FIG. 92 A cross-sectional view explaining a problem of a conventional technique.
  • FIG. 93 A cross-sectional view illustrating a problem of the conventional technique.
  • FIG. 94 is a sectional view illustrating another embodiment of the present invention.
  • FIG. 95 is a cross-sectional view illustrating another embodiment of the invention.
  • FIG. 96 is a cross-sectional view illustrating another embodiment of the present invention.
  • FIG. 97 is a cross-sectional view illustrating another embodiment of the present invention.
  • FIG. 98 is a cross-sectional view illustrating another embodiment of the present invention.
  • FIG. 99 is a cross-sectional view illustrating another embodiment of the present invention.
  • FIG. 100 An explanatory view of an effect of the first embodiment.
  • a cap insulating layer 8 is provided on the semiconductor layer 3 protruding upward from the substrate, and the cap insulating layer 8 is provided in the double-gate FinFET in which the gate electrode 5 is formed so as to cover the semiconductor layer 3 and the cap insulating layer 8.
  • the horizontal direction in the plane perpendicular to the direction in which the semiconductor layer 3 protrudes from the substrate, in the direction perpendicular to the channel length direction.
  • the extension of the surface where the cap insulating layer 8 contacts the semiconductor layer 3 Direction and projecting toward the gate electrode 5 so that the cap insulating layer 8 has a protruding portion protruding from the surface of the gate insulating film 4.
  • Figure 1 shows an example.
  • the symbol Wext indicates the width of the cap insulating layer 8 projecting from the surface of the gate insulating film 4 in the horizontal direction, that is, the overhang width.
  • the “channel length direction” refers to a direction connecting a pair of source / drain regions.
  • the gate electrode 5 is provided on the side surface of the semiconductor layer with the gate insulating film 4 interposed therebetween.
  • the source / drain region 6 into which the impurity of the first conductivity type is introduced at a high concentration is formed in the layer.
  • the channel forming region 7, which is a semiconductor layer covered by the gate electrode 5 a channel made of the first conductivity type carrier is formed by applying an appropriate voltage to the gate electrode 5. Wiring is connected to the gate electrode 5 and the source / drain region 6 via a contact region.
  • FIG. 1 (a) is a cross-sectional view taken along the line AA ′ of FIG. 1 (b), and is a cross-sectional view at a position corresponding to the cross section AA ′ of FIG. 81 showing a conventional example.
  • the source / drain region 6 is originally covered with the cap insulating layer 8, and the source / drain region 6 is not visible, but the structure is easily resolved. For this reason, the position of the source Z drain region 6 is shown transparently.
  • the conductivity type of the source Z drain region is referred to as a first conductivity type, and a conductivity type different from the source Z drain region is referred to as a second conductivity type.
  • FIGS. 3 (a), 4 (a), 5 (a), and 7 (a) are plan views of FIGS. 3 (c), 4 (c), 5 (c), and 5 (a), respectively.
  • FIG. 3 is a cross-sectional view taken along line A—A ′ in FIG. 8, and FIGS. 3 (b), 4 (b), 5 (b), and 7 (b) are plan views, respectively.
  • FIGS. 3 (c), 4 FIG. 9C is a cross-sectional view taken along the line BB ′ in FIG. 5C, FIG. 5C, and FIG. FIGS. 6 (a) and 6 (b) are cross-sectional views each showing a shape taken along the line DD ′ of FIG. 5 (c).
  • the position of the cross section AA ′ of each drawing explaining this embodiment is the position of the cross section AA ′ of FIG. 81 showing the conventional example, and the position of the cross section BB ′ of each drawing explaining this embodiment. 81 correspond to the positions of the cross section BB 'in FIG. 81 showing the conventional example.
  • the semiconductor layer 3 and the cap insulating layer 8 are appropriately formed.
  • the semiconductor layer 3 is etched to form a shape (FIG. 3), and the side of the semiconductor layer 3 is etched so that the side of the semiconductor layer 3 recedes inward from the end of the cap insulating layer 8 to make the semiconductor layer 3 thin ( ( Figure 4).
  • a gate insulating film 4 is formed on the side surface of the semiconductor layer, a gate electrode material is deposited, and the gate electrode material is patterned by RIE (reactive 'ion' etching) or the like.
  • a gate electrode 5 is formed, and a high concentration first conductivity type impurity is introduced into a region of the semiconductor layer 3 which is not covered with the gate electrode 5 to form a source / drain region 6 (FIG. 5).
  • an interlayer insulating film 16 is deposited, and a contact 17 and a wiring 18 are formed by a usual method (FIGS. 7 and 8).
  • the gate electrode is formed by processing using an etching process such as RIE, at least in the latter half of the etching process, highly isotropic etching is performed, and excess surplus remaining under the protruding cap insulating layer 8 is formed. It is desirable to remove the gate electrode material 26 (FIG. 6 (a)).
  • the element structure of the first embodiment can be formed.
  • a cap substrate is formed on an SOI substrate in which a supporting substrate 1 made of silicon, a filled insulating layer 2 made of an insulator such as Si ⁇ , and a semiconductor layer 3 made of single crystal silicon are further stacked thereon.
  • the cap insulating layer 8 is, for example, a Si ⁇ film deposited by a CVD method.
  • the cap insulating layer 8 and the semiconductor layer 3 are patterned and processed into an appropriate shape by a normal lithography process and a normal etching process such as RIE to form an element region.
  • Figure 3 shows the shape obtained at this stage.
  • both the cap insulating layer 8 and the semiconductor layer 3 may be patterned by etching using a photoresist as a mask, or only the cap insulating layer 8 may be etched using a photoresist as a mask, followed by cap insulating. Patterning may be performed by etching the semiconductor layer 3 using the layer 8 as a mask.
  • the side surface of the semiconductor layer 3 is etched by performing highly isotropic etching, and the side surface of the semiconductor layer 3 is processed into a shape recessed from the side surface of the cap insulating layer 8. As a result, the shape shown in FIG. 4 is obtained.
  • Strongly isotropic etching for example, CI, HC1, C
  • the etching is performed by an isotropic plasma etching apparatus using a gas such as CF.
  • polysilicon is deposited.
  • the gate electrode is formed by patterning by etching in the usual lithography process and RIE process to form a gate electrode, followed by high-concentration ion implantation using the gate electrode as a mask and heat treatment to cover the gate electrode.
  • the source / drain region 6 is provided in the semiconductor layer 3 at a position where there is not, and the shape shown in FIG. 5 is obtained.
  • the gate electrode is formed by etching polysilicon to form the gate electrode, as shown in FIG. 6A, the polysilicon is formed below the cap insulating layer 8 in the section taken along the line D-D 'in FIG. 5C.
  • the D-D 'cross section in Fig. 5 (c) can be obtained.
  • the gate insulating film is provided by, for example, thermally oxidizing the semiconductor layer 3.
  • the source Z drain region is formed by introducing an impurity through an impurity introduction step such as vertical ion implantation, oblique ion implantation, or plasma doping.
  • a gate sidewall 14 is provided by depositing an insulating film on the whole and etching it back.
  • the insulating film forming the gate side wall 14 is, for example, a single-layer film of Si ⁇ , a single-layer film of SiN,
  • An insulating film such as a multilayer film of 2 3 4 2 and SiN is used. Also, the insulating film forming the gate side wall 14
  • FIGS. 7 (a) shows the cross-sectional shape taken along the line AA ′ in FIG. 8, and FIG.
  • FIG. 7 (b) shows the cross-sectional shape taken along the line BB ′ in FIG.
  • the contact 17 is located at the lower part of the wiring 18. In FIG. 8, the position is shown in a transparent manner.
  • the element structure of the first embodiment can be formed.
  • FIG. 9 (b) shows the result of simulating the potential distribution in the section C_C ′ in FIG. 9 (a).
  • the vertical axis represents the potential and the horizontal axis represents the position, and indicates the depth from the upper end of the semiconductor layer.
  • the impurity concentration in the semiconductor layer was 4 ⁇ 10 18 cm 3 .
  • the reference of the potential is the source potential, and the potential of the source electrode is zero V.
  • the left end of FIG. 9B corresponds to the surface of the semiconductor layer.
  • the dashed line shown as the double gate structure in the figure is the calculation result for the structure in FIG. 83, and the dashed line shown as the tri-gate structure in the figure is the calculation result for the structure in FIG.
  • FIG. 100 shows a plot of the simulation results with the horizontal axis representing Wext and the vertical axis representing the maximum potential at the upper corner of the semiconductor layer.
  • the data in Fig. 100 (a) and Fig. 100 (b) are the same, and Fig. 100 (a) shows the explanation for the lower limit of Wext, and Fig. 100 (b) shows the explanation for the upper limit of Wext. Things.
  • the impurity concentration in the semiconductor layer is 4 ⁇ 10 18 cm ⁇ 3
  • the gate voltage is 0 V (in FIG. 100, the gate potential at this time is 0.556 V, and the level is Wfm). Is 30 nm
  • the gate insulating film thickness is 2 nm.
  • Wext when Wext exceeds lOnm, the change in potential becomes gradual, and when 15 nm or more, the change in potential tends to be saturated. Even if Wext is increased in the region where the potential change is saturated, Since the potential cannot be reduced simply by increasing the load on the process, Wext is preferably 15 nm or less. Also, considering the variation of Wext due to process causes, if a margin of 5 nm is provided for 15 nm, Wext is preferably 20 nm or less.
  • Wext is preferably 20 nm or less, and more preferably 15 nm or less.
  • the thickness of the gate insulating film was set to 2 nm. Therefore, in order to obtain a certain effect of the present invention, Wext is required to have an effect of the present invention in which the gate insulating film is preferably at least one time the gate insulating film thickness. Wext should be at least 2.5 times the thickness of the gate insulating film to obtain a large value, and 5 times or more is preferable to obtain the maximum effect. In addition, the same Wext is preferred to be 10 times or less of the gate insulating film thickness, and if the judgment is made purely from the viewpoint of effect ignoring process variations, Wext is 7.5 times or less of the gate insulating film thickness. Is considered to be more preferable.
  • FIGS. 10 to 16 and FIG. 26 are cross-sectional views at positions corresponding to the cross section taken along the line AA ′ of FIG. 81, which is a drawing showing a conventional example.
  • one of the upper and lower portions of the semiconductor layer 3 projecting upward from the substrate, or both the upper and lower portions of the semiconductor layer 3 projecting upward from the substrate have a dielectric constant higher than that of SiO.
  • a low dielectric constant region 10 which is a low region is provided.
  • a gate electrode 5 is provided on a side surface of the semiconductor layer via a gate insulating film 4. The gate electrode 5 is patterned to an appropriate size, and a source / drain region 6 in which impurities of the first conductivity type are introduced at a high concentration is formed in a portion of the semiconductor layer which is not covered with the gate electrode.
  • a channel made of carriers of the first conductivity type is formed by applying an appropriate voltage to the gate electrode 5. Wiring is connected to the gate electrode 5 and the source Z drain region 6 via a contact region.
  • the low dielectric constant region 10 provided above the semiconductor layer 3 and the low dielectric constant region 10 provided below the semiconductor layer 3 are formed in the upper corner portion 34 and the lower corner portion 35 of the semiconductor layer, respectively. Has the effect of suppressing parasitic transistors.
  • the whole or a part of the cap insulating layer 8 formed on the semiconductor layer 3 is constituted by a low dielectric constant region 10 having a dielectric constant lower than that of Si ⁇ . ( Figure 10 (a)). Further, a low dielectric constant region 10 is provided both above and below the semiconductor layer 3 (FIG. 10 (b), FIG. 11 (a)). Alternatively, a low dielectric constant region is provided only below the semiconductor layer 3 (FIG. 11 (b), FIG. 11 (c), symbol 36 is a cap insulating layer made of SiO). In addition, these low dielectric regions 10
  • the low dielectric constant material forming the low dielectric constant region 10 has a relative dielectric constant lower than the relative dielectric constant of SiO of 3.9. It is strongly desirable that the relative dielectric constant of the low dielectric constant material be 3.0 or less.
  • the low dielectric constant region 10 is partially or entirely provided at a position lower than the upper end of the gate electrode (FIG. 94).
  • the low dielectric constant region 10 is provided below the gate electrode (FIG. 10).
  • a low dielectric constant region is also provided below the gate electrode 5 in a region where the semiconductor layer 3 does not exist. 11).
  • This structure has an advantage that the capacitance between the lower part of the gate electrode 5 and the supporting substrate can be reduced.
  • a structure in which a low dielectric constant region is not provided below the gate electrode 5 (FIG. 10B) is acceptable.
  • This structure has an advantage that the potential distribution inside the semiconductor layer 3 is vertically symmetrical, so that the element design becomes easy.
  • This structure also has the advantage that low dielectric constant materials, which are generally mechanically more fragile than SiO films, can reduce the surface area exposed during the manufacturing process.
  • a gate sidewall (for example, FIG. 20, FIG. 26, or FIG. 28) which is a sidewall provided on the side surface of the gate electrode 5 only by providing a region made of a material having a lower dielectric constant than Si ⁇ on the semiconductor layer , Part or all of symbol 14 in FIG. 35) is made of a material having a lower dielectric constant than SiO. It may be formed.
  • a thin protective insulating film 13 formed by thermally oxidizing the semiconductor layer between the semiconductor layer 3 and the low dielectric constant region 10 may be formed.
  • the protective insulating film 13 has an effect of reducing defects such as interface states at the interface between the low dielectric region and the semiconductor layer.
  • the protective insulating film 13 has the same strength as Si ⁇ or has a higher dielectric constant than Si ⁇ .
  • the protective insulating film 13 may have a lower dielectric constant than SiO.
  • the thickness of the protective insulating film is the thickness of the low dielectric constant region (however, the thickness refers to the width in the direction perpendicular to the substrate plane, for example, in the cross section of FIG. 13).
  • FIG. 13 shows a structure in a case where the low dielectric region 10 is a cavity 12 and a protective insulating film 13 is interposed between the semiconductor layer 3 and the low dielectric region 10.
  • FIG. 13A shows the case where the low dielectric constant region is provided above the semiconductor layer
  • FIG. 13B shows the case where the low dielectric constant region is provided above and below the semiconductor layer.
  • the protective insulating film 13 may be formed on the surface of the gate electrode in contact with the cavity (FIG. 26).
  • a protective insulating film 13 may be provided between the semiconductor layer 3 and the low dielectric constant region below the semiconductor layer.
  • FIG. 12 shows the protective insulating film 39 provided under the semiconductor layer as a protective insulating film 39.
  • the purpose of providing the buried protective insulating film 39 is the same as the purpose of providing the protective insulating film 13 provided above the semiconductor, and is to reduce defects such as interface states at the interface between the low dielectric constant region and the semiconductor layer.
  • the buried protective insulating film 39 is the same as Si ⁇ , or has a higher dielectric constant than SiO, and may have a lower dielectric constant than SiO, similarly to the protective insulating film 13 provided above the semiconductor layer. is there.
  • the second embodiment may be implemented in combination with the first embodiment.
  • the entire or a part of the cap insulating layer 8 on the semiconductor layer may be constituted by the low dielectric constant region 10 which is a region made of a low dielectric constant material or a cavity.
  • the low dielectric constant region 10 which is a region made of a low dielectric constant material or a cavity.
  • part or all of the insulator below the semiconductor layer may be formed of a low dielectric constant region made of a low dielectric constant material or a cavity.
  • various configurations of the first embodiment may be applied to the upper portion of the semiconductor layer
  • various configurations of the second embodiment may be applied to the lower portion of the semiconductor layer. This suppresses the parasitic transistor at the upper corner portion of the semiconductor layer according to the first embodiment, and the parasitic transistor at the lower corner portion 35 of the semiconductor layer according to the second embodiment.
  • FIGS. 15 and 16 show examples. These are all cross-sectional views in the same cross section as FIG. 1 (a).
  • FIG. 15 (a) shows a case where the cap insulating layer is formed of the low dielectric constant region 10 in the structure of FIG. 1, and
  • FIG. 15 (b) shows the structure of FIG. This is a case where it is configured by a structure including the dielectric constant region 10 and the protective insulating film 13.
  • the protective insulating film 13 is provided to protect the interface between the semiconductor layer 3 and the cavity 12.
  • FIG. 16 (a) shows a case where a low dielectric constant region 10 is provided below the semiconductor layer 3 in the structure of FIG. 1, and
  • FIG. 16 (b) shows a low dielectric constant region having a cavity 12 below the semiconductor layer 3 in the structure of FIG.
  • the protective region 13 is provided at the interface between the cavity 12 and the semiconductor layer 3 and at the interface between the cavity 12 and the gate electrode 5.
  • first embodiment and the second embodiment may be combined in a different form from those shown in Figs.
  • FIGS. 18 (a), 19 (a) and 20 (a) are cross-sectional views taken along the line AA ′ in FIG. 21 which is a plan view, respectively.
  • 20) and FIG. 20 (b) are cross-sectional views taken along the line BB ′ in FIG. 21 which is a plan view.
  • a low-dielectric-constant film made of a material having a lower dielectric constant than that of Si 30 (Fig. 17)
  • semiconductor layer 3 and low dielectric constant Putter the membrane 10 into a suitable shape (Fig. 18).
  • a gate insulating film 4 is formed on the side surface of the semiconductor, a gate electrode material is deposited, and then the gate electrode material is patterned by RIE or the like to form a gate electrode 5, which is covered with the gate electrode 5 of the semiconductor layer 3.
  • a high-concentration impurity of the first conductivity type is introduced into the unreacted region to form the source Z drain region 6 (FIG. 19).
  • an interlayer insulating film is deposited, and the contact 17 and the wiring 18 are formed by a usual method (FIGS. 20 and 21).
  • the low dielectric constant region 10 On a SOI substrate in which a support substrate 1 made of silicon, a buried insulating layer 2 made of Si ⁇ , and a semiconductor layer 3 made of single crystal silicon are further stacked thereon, the low dielectric constant region 10 A low dielectric constant insulating film 30 made of a material having a lower dielectric constant than SiO is deposited.
  • the low dielectric constant insulating film 30 is, for example, a SiOF film deposited by a CVD method. As a result, the configuration shown in FIG. 17 is obtained.
  • the low-dielectric-constant film 30 and the semiconductor layer 3 are patterned by a normal lithography process and a normal etching process such as RIE to obtain the shape shown in FIG.
  • the low dielectric constant film 30 and the semiconductor layer 3 may be patterned by etching both using a photoresist as a mask, or only the low dielectric constant film 30 may be etched using a photoresist as a mask, followed by low dielectric constant. Patterning may be performed by etching the semiconductor layer 3 using the film 30 as a mask.
  • a gate insulating film 4 is provided on the side surface of the semiconductor layer 3, polysilicon is deposited, and this is etched by a usual lithography process and RIE process to form a gate electrode by patterning. Then, high-concentration ion implantation is performed using the gate electrode as a mask, and heat treatment is performed to provide the source / drain regions 6 in the semiconductor layer 3 at positions not covered by the gate electrode, thereby obtaining the shape shown in FIG. .
  • the insulating film forming the gate side wall 14 is, for example, a Si ⁇ or SiN multilayer film,
  • the gate side wall 14 is composed of a multilayer film composed of 2 3 4 2 and SiN.
  • the insulating film forming the gate side wall 14 is formed by CVD or the like.
  • a metal is deposited on the source / drain region 6 and the gate electrode 5 and heat-treated to form a silicide layer 15 on the source Z drain region 6 and on the gate electrode 5.
  • an interlayer insulating film 16 is deposited and flattened. After that, contact holes are opened in the upper portions of the source / drain regions 6 and the gate electrodes 5, and the contacts 17 are formed by embedding metal.
  • a wiring 18 made of metal is connected to the contact 17 to obtain the shapes shown in FIGS. It is acceptable to carry out metal loading in the contact area and deposition of metal to be wiring at the same time.
  • the contact 17 is located at the lower part of the wiring 18 and its position is shown in FIG.
  • the low dielectric constant film 30 forms the low dielectric constant region 10.
  • the low dielectric constant region 10 is provided below the semiconductor layer 3, the following changes are made in the first manufacturing method of the second embodiment or the second manufacturing method of the second embodiment. All or part of the embedded insulating layer is formed by the low dielectric constant film 30. Further, the cap insulating layer 8 may be a low dielectric constant film or a non-low dielectric constant film. Also, without forming the cap insulating layer 8, a gate insulating film is formed on the side and top surfaces of the semiconductor, a gate electrode material is deposited, and then the gate electrode material is patterned by RIE or the like, as shown in FIG. 11 (b). A tri-gate structure may be formed.
  • Fig. 10 (b) uses an S ⁇ I substrate in which the upper region of the buried insulating film is formed of a low dielectric constant film, and the low dielectric constant film below the semiconductor layer 3 is not covered by the semiconductor layer 3. This is the shape obtained by etching the area and the area.
  • FIG. 23 (a), FIG. 24 (a), FIG. 25 (a), FIG. 26 (a), and FIG. 28 (a) are plan views of FIG. 23 (c) and FIG. 28 is a cross-sectional view taken along the line A--A 'in FIGS. 23 (c), 25 (c) and 27, and FIGS. 23 (b), 24 (b), 25 (b), 26 (b), and 28 ( b) is a cross-sectional view taken along the line BB 'in FIGS. 23 (c), 24 (c), 25 (c), and 27 which are plan views.
  • a dummy layer 11 is deposited on the semiconductor layer 3 (Fig. 22), and the semiconductor layer 3 and the dummy layer 11 are patterned into an appropriate shape (Fig. 23).
  • the gate electrode material is patterned by RIE or the like to form a gate electrode 5 so as to cover the semiconductor layer 3, the gate insulating film 4, and the dummy layer 11, and the gate of the semiconductor layer 3 is formed.
  • a source / drain region 6 is formed by introducing high-concentration first conductivity type impurities into a region not covered by the electrode 5 (FIGS. 24 and 14 (a)).
  • the dummy layer 11 is removed by etching to form a cavity 12 in a region on the semiconductor layer 3 covered with the gate electrode 5 (FIGS. 25 and 14 (b)).
  • an interlayer insulating film is deposited, and contacts and wirings are formed by a usual method (FIGS. 26 and 27).
  • the low-dielectric-constant region 10 may be formed by back-filling the low-dielectric-constant material in the cavity 12 on the semiconductor layer 3 covered with the gate electrode 5.
  • the dummy layer 11 for example, a SiN film deposited by CVD is used, and in order to form a cavity, the SiN film of the dummy layer 11 is removed by an etching step such as wet etching using phosphoric acid. .
  • the manufacturing method for providing the low dielectric constant region 10 will be described in more detail with reference to FIGS.
  • a dummy layer 11 is deposited on an S ⁇ I substrate in which a support substrate 1 made of silicon, a buried insulating layer 2 made of Si ⁇ , and a semiconductor layer 3 made of single crystal silicon are further stacked thereon.
  • the dummy layer 11 is, for example, a SiN film deposited by a CVD method.
  • a pad insulating film made of an insulating film different from the dummy layer 11, for example, a pad insulating film made of a Si film formed by thermal oxidation may be formed between the dummy layer 11 and the semiconductor layer 3.
  • a dummy layer is formed by a normal lithography process and a normal etching process such as RIE.
  • the shape of FIG. 23 is obtained by patterning 11 and the semiconductor layer 3.
  • the dummy layer 11 and the semiconductor layer 3 may be patterned by etching using a photoresist as a mask, or only the dummy layer 11 may be etched using a photoresist as a mask, and then the dummy layer 11 may be masked.
  • the semiconductor layer 3 may be patterned by etching the semiconductor layer 3 first. When a pad insulating film is provided between the dummy layer 11 and the semiconductor layer 3, the pad insulating film is also patterned at the same time.
  • the gate insulating film 4 is deposited, and this is etched by a usual lithography process and RIE process to form a gate electrode.
  • high-concentration ion implantation is performed using the gate electrode as a mask, and heat treatment is performed to provide the source / drain region 6 in the semiconductor layer 3 at a position not covered by the gate electrode, thereby obtaining the shape shown in FIG.
  • the gate insulating film is provided, for example, by thermally oxidizing the semiconductor layer 3.
  • the source / drain regions are formed by introducing impurities through an impurity introduction step such as vertical ion implantation, oblique ion implantation, and plasma doping.
  • the dummy layer 11 is replaced with the cavity 12 by selectively etching and removing the dummy layer 11.
  • the dummy layer 11 below the gate electrode is removed by the lateral penetration of the etching solution or etching gas as shown by the arrow in FIG.
  • phosphoric acid may be used as an etchant.
  • a protective insulating film may be provided at the interface adjacent to the cavity 12 of the semiconductor layer 3 or at the interface adjacent to the cavity 12 of the gate electrode 5 for the purpose of preventing the generation of interface states at the interface adjacent to the cavity. .
  • FIG. 25 shows a structure in which a protective insulating film 13 is provided by thermally oxidizing the interface adjacent to the cavity 12 of the semiconductor layer 3 or the interface adjacent to the cavity 12 of the gate electrode 5.
  • the protective insulating film 13 is omitted, and the drawing is omitted. (The entire structure is covered with the protective insulating film 13, so that the structure is not To be clear).
  • a gate sidewall 14 is provided by depositing an insulating film on the whole and etching it back.
  • the insulating film forming the gate side wall 14 is, for example, a Si ⁇ or SiN multilayer film,
  • the gate side wall 14 is composed of a multilayer film composed of 2 3 4 2 and SiN.
  • the insulating film forming the gate side wall 14 is formed by CVD or the like.
  • FIG. 26 (a) shows the cross-sectional shape taken along the line AA in FIG. 27, and FIG.
  • FIG. 26 (b) shows the cross-sectional shape taken along the line ⁇ _ ⁇ ′ in FIG. Note that the filling of the metal into the contact region and the deposition of the metal to be the wiring may be performed simultaneously.
  • the contact 17 is located at the lower part of the wiring 18 and its position is shown in Fig. 27.
  • the cavities may be back filled with a low dielectric constant material.
  • the low dielectric constant material to be filled in the cavity may be a continuous film such as SiOF or a porous material.
  • a low dielectric constant material is buried in the cavity by a CVD method or a spin coating method to form a low dielectric constant material. Etch back the low-k material only in the area covered by the gate electrode. This structure is shown in FIG.
  • a step of refilling the cavity with a low dielectric constant material is performed, or After completing these high temperature heat treatment steps, the formation of cavities and the cavities are made of low dielectric constant material. Performing the reconstitution step can prevent high-temperature heat treatment from causing a chemical or physical change to the low dielectric constant material.
  • the element structure of the second embodiment can be formed.
  • a manufacturing method in which a low dielectric constant region 10 including a cavity 12 is provided below the semiconductor layer 3, and a low dielectric constant material is returned to the cavity 12 provided below the semiconductor layer 3 so that a low dielectric constant A manufacturing method for providing the dielectric constant region 10 will be described with reference to FIGS. 29 to 37.
  • FIGS. 30 (a), 31 (a), and 34 are plan views of FIGS. 30 (c), 31 (c), and 36, respectively.
  • (b), FIG. 31 (b), and FIG. 35 are cross-sectional views taken along line BB ′ of FIG. 30 (c), FIG. 31 (c), and
  • FIGS. 32 (a) and 33 (a) are cross-sectional views of the cross-section of FIG. 30 (a) in which the process has been advanced, and FIGS. 32 (b), 33 (b), and FIG. It is sectional drawing in the state where the process advanced in the cross section of b).
  • the source / drain region 6 is formed by introducing the first conductivity type impurity (FIG. 32).
  • the dummy layer 11 is removed by etching to form a cavity 12 in a region below the semiconductor layer 3 (FIG. 33).
  • an interlayer insulating film is deposited, and contacts and wirings are formed by a usual method (FIGS. 34, 35, and 36).
  • a structure having a cavity below the semiconductor can be obtained by providing a dummy layer below the semiconductor layer and removing the dummy layer below the semiconductor layer.
  • a structure having cavities above and below the semiconductor can be obtained by providing dummy layers above and below the semiconductor layer 3 and removing the dummy layers above and below the semiconductor layer.
  • the semiconductor layer when a cavity is provided below the semiconductor layer, the semiconductor layer may be separated from the substrate. In order to prevent this, it is not necessary to provide a cavity below the semiconductor layer, such as in the source / drain region, the region may not be etched, and the side surfaces of the dummy layer may not be etched by the dummy layer removing step. (For example, when phosphoric acid is used for removing the dummy layer, it is preferable to cover with Si ⁇ ).
  • the low dielectric constant region 10 may be formed under the semiconductor layer 3 by burying the dummy layer provided under the semiconductor layer 3 with a low dielectric constant material having a lower dielectric constant than SiO. .
  • the element structure of the second embodiment can be formed.
  • the supporting insulating film 21 is provided on the side surface of the patterned semiconductor layer 3 as shown in FIG. 30, and the side surface of the semiconductor layer 3 once covered with the supporting insulating film 21 is formed as a channel forming region as shown in FIG.
  • the second etching may be performed on the semiconductor layer 3 so that the semiconductor layer 3 is exposed.
  • FIGS. 30 (a), 31 (a), and 34 are plan views of FIGS. 30 (c), 31 (c) and 36, respectively, and are sectional views taken along line A--A 'of FIG. (b), FIG. 31 (b), and FIG. 34 (b) are cross-sectional views taken along line BB ′ of FIG. 30 (c), FIG. 31 (c), and FIG. FIGS. 32 (a) and 33 (a) are cross-sectional views of the cross-section of FIG. 30 (a) in a state where the process has been advanced, and FIGS. 32 (b), 33 (b) and 37 are FIGS. It is sectional drawing in the state where the process advanced in the cross section of b).
  • An S ⁇ I-based substrate having a support substrate 1 made of silicon, a buried insulating layer 2 made of Si ⁇ , a lower dummy layer 20 thereon, and a semiconductor layer 3 made of single-crystal silicon stacked thereon
  • An upper dummy layer 19 is deposited on the plate.
  • the upper dummy layer 19 and the lower dummy layer 20 are, for example, SiN films.
  • the configuration shown in FIG. 29 is obtained.
  • the dummy layer 11 is simply referred to, it refers to both the upper dummy layer 19 and the lower dummy layer 20.
  • the upper dummy layer 19, the semiconductor layer 3, and the lower dummy layer 20 are patterned by a normal lithography process and a normal etching process such as RIE.
  • RIE normal etching process
  • support insulation throughout A film 21 is deposited and etched back to obtain the shape shown in FIG.
  • the laminated structure of the upper dummy layer 19, the semiconductor layer 3, and the lower dummy layer 20 is formed around the region where the channel is formed so that the side surface of the semiconductor layer 3 is exposed in the region where the channel is formed.
  • the portion adjacent to 21 is etched away.
  • FIG. 31 shows the shape obtained by this step.
  • FIG. 32 corresponds to FIG. 24
  • FIG. 33 corresponds to FIG. 25
  • FIGS. 34, 35 and 36 correspond to FIGS. 26 (a), 26 (b) and 27, respectively. It shows the shape formed by performing the step of forming the shape.
  • each step is as follows. After forming a gate insulating film on the side surface of the semiconductor layer 3, a gate electrode material is deposited, and the gate electrode material is processed to form a gate electrode. In the step of introducing impurities into 6, an upper dummy layer 19 is formed above the semiconductor layer, and a lower dummy layer 20 is formed below the semiconductor layer (FIG. 32). Further, the cavity 12 is formed above and below the semiconductor layer by the step of forming the cavity 12 by removing the dummy layer. When the protective insulating film 13 is provided in the cavity, the protective insulating film 13 is formed above and below the semiconductor layer (FIGS. 33, 34, 35, and 37). FIGS.
  • a cavity may be formed over the entire semiconductor layer below the semiconductor layer 3 (FIGS. 33 and 35), and a cavity may be formed below the semiconductor layer 3 only in a part of the region below the gate electrode. It may be formed (Fig. 37).
  • the lower dummy layer may be entirely removed, or the lower dummy layer may be removed only in a part of the region located below the gate electrode.
  • the purpose of providing the supporting insulating film 21 is to support the semiconductor layer in a state where the lower dummy layer 20 below the semiconductor layer is removed to form a cavity. Therefore, when a cavity is formed below the semiconductor layer 3 only in a part of the region below the gate electrode (FIG. 37), the semiconductor layer is supported by the connection at the contact surface between the gate electrode 5 and the buried insulating film 2. Therefore, when sufficient mechanical strength is obtained, the supporting insulating film 21 may be omitted.
  • the element structure of the second embodiment is formed. It becomes possible.
  • a portion located above the semiconductor layer, a portion located below the semiconductor layer, or a portion located above and below the semiconductor layer has a lower dielectric constant than SiO.
  • the low dielectric constant region has a function of relaxing the electric field between the gate electrode and the semiconductor layer, if a portion located above the semiconductor layer is replaced by the low dielectric constant region, the upper corner portion of the semiconductor layer 34 (FIG. 82, The rise in potential in FIG. 83) is suppressed, the occurrence of parasitic transistors is suppressed, and transistor characteristics are improved. Parasitic transistors also occur in the lower corners 35 (Figs. 82 and 83), but if the lower part of the semiconductor layer is replaced by a low dielectric constant region, the potential rise in the lower corners of the semiconductor layer will increase. Is suppressed, the occurrence of a parasitic transistor is suppressed, and the characteristics of the transistor are improved.
  • Fig. 39 shows a potential distribution in the case where a cavity is formed above the semiconductor layer of FinFET.
  • FIG. 54 shows a plot of the potential distribution on the side surface of the semiconductor layer as in FIG. 9B.
  • FIG. 54 (a) shows the double gate structure in FIG. 83
  • FIG. 54 (b) shows the tri-gate structure in FIG. 82
  • FIG. 54 (c) shows the structure in FIG. 10 (a).
  • the number in the figure is the amount of potential rise at the upper end of the semiconductor layer, which is 63.4 mV in the structure of FIG. This value is smaller in the case of the normal double gate structure (186 mV) than in the case of the normal tri-gate structure (358 mV), and the parasitic transistor suppressing effect according to the present embodiment is remarkable.
  • the cap insulating layer is formed using a low dielectric constant region or part of the cap insulating layer is formed using a low dielectric constant material, an action of suppressing an electric field from a drain to a channel through the cap insulating layer and the cap insulating layer. Is also obtained. Also, by replacing the buried insulating film in the low dielectric constant region or by replacing part of the buried insulating film with a low dielectric constant material, the electric field from the drain through the buried insulating film to the channel is suppressed. The effect of this is obtained.
  • the electric field from the drain to the channel through the cap insulating layer or the filled insulating film causes a threshold voltage fluctuation called DIBL (drain-induced barrier lowering, drain 'induced' barrier 'lowering) to occur in short-channel transistors.
  • DIBL drain-induced barrier lowering, drain 'induced' barrier 'lowering
  • the present embodiment also has the effect of improving the characteristics of the short-channel transistor, such as suppressing threshold value fluctuation due to DIBL, because it causes various characteristics degradation.
  • the threshold variation due to DIBL can be improved. And the effect of improving the characteristics of the short-channel transistor, such as suppression of the noise, can be enhanced.
  • planar-type field-effect transistors have conventionally been proposed to have a structure in which a cavity is provided below the semiconductor layer to reduce parasitic capacitance and suppress the short-channel effect.
  • the feature is that the gate electrode adjacent to the vertical channel reaches the buried insulating layer below the cavity. This has the advantage that heat generated in the channel region can easily escape to the support substrate side via the gate electrode.
  • FIG. 38 (a) shows a planar type In the case of the conventional structure, FIGS. 38 (b) and 38 (c) show the case of the structure of the present invention.
  • FIG. 38 (c) shows a case where a plurality of semiconductor layers are arranged as shown in FIG.
  • FIG. 38 (b) is a cross-sectional view at a position corresponding to the AA ′ cross section in FIG. 36, and FIG.
  • 38 (b) is a cross-sectional view at a position corresponding to the AA ′ cross section in FIG. 75.
  • 38 (a) is a cross section in the channel width direction of a channel region covered with a gate electrode of a planar transistor.
  • the arrow (symbol 33) in FIG. 38 indicates the flow of heat, and the symbol 32 indicates a field insulating film.
  • FIGS. 41, 55, 56, 57, 59, 60, 66, 67, 68, and 68 show a conventional structure at a position corresponding to a section taken along the line AA ′ of FIG. 81.
  • FIG. 82 is a cross-sectional view, corresponding to the cross-section shown in FIGS. 82 (a) and 83 (a), illustrating the conventional structure.
  • the semiconductor layer 3 of the FinFET of the third, fourth, and fifth embodiments has a form protruding from the substrate surface, and the gate insulating film 4 is provided on both sides of the semiconductor layer 3 via the gate insulating film 4. A gate electrode is provided.
  • the semiconductor layer includes a semiconductor layer main portion region 43 and a semiconductor layer end region 44 provided on at least one of an upper portion and a lower portion of the semiconductor layer main portion region 43.
  • the semiconductor layer main portion region 43 is a region in which the width Wfin of the semiconductor layer in a plane perpendicular to the direction connecting the two source / drain regions is larger than the semiconductor layer end region 44.
  • the semiconductor layer end region 44 is a region in which the width Wfin of the semiconductor layer in a plane perpendicular to the direction connecting the two source / drain regions is smaller than the width of the semiconductor layer main region 43, or the two source / drain regions.
  • the width Wfin of the semiconductor layer in a plane perpendicular to the direction connecting the drain regions becomes smaller than the width of the semiconductor layer main region 43 as the distance from the semiconductor layer main region 43 increases, and one or both of the two regions of the transition region transition.
  • This is a region in which an end insulator region 27 is provided between the semiconductor layer 3 and the gate electrode 5.
  • the end insulator 27 is provided between the semiconductor layer 3 and the gate electrode 5, and has a maximum width of the insulator.
  • We ⁇ is an insulator larger than the thickness of the gate insulating film 4.
  • the gate electrode 5 is patterned into an appropriate size, and a source / drain region 6 in which impurities of the first conductivity type are introduced at a high concentration is formed in the semiconductor layer at a position not covered by the gate electrode. Is done.
  • a channel made of carriers of the first conductivity type is formed by applying an appropriate voltage to the gate electrode 5. Wiring is connected to the gate electrode 5 and the source / drain region 6 via a contact region.
  • the third, fourth, and fifth embodiments may be applied to a transistor having a double gate structure in which the upper interface of the semiconductor layer 3 hardly contributes as a channel (see FIG. 41), which can be applied to a transistor having a tri-gate structure (FIG. 42 (a)) in which a channel is formed at the upper interface of the semiconductor layer 3.
  • FIG. 42 (a) the side surface of the semiconductor layer 3 corresponds to the end insulator region 27.
  • the portion in contact is the semiconductor layer end region 44, and the side of the semiconductor layer 3 is not in contact with the end insulator region 27, and the portion in contact with the gate insulating film is the semiconductor layer main region 43.
  • the end insulator region 27 may be a normal insulator such as Si ⁇ , a low dielectric constant material, or a cavity.
  • FIG. 42 (b) shows a case where a cavity is provided as the end insulator region 27. It is more preferable to use a material having a lower dielectric constant than SiO or a cavity for all or a part of the end insulator region because the effect of alleviating electric field concentration is increased.
  • the end insulator region 27 and the cap insulating layer may be the same material or different materials. When the end insulator region 27 and the cap insulating layer are made of the same material, both may be formed integrally.
  • FIG. 42 (c) shows an example in which the end insulator region 27 and the cap insulating layer are integrally formed.
  • the end insulator region 27 is made of a different material from the cap insulator 8 on the semiconductor layer 3 or is not formed integrally with the same material, the end insulator region 27 becomes semiconductive. A structure that penetrates into a part of the cap insulator 8 on the body layer 3 is acceptable. If the end insulator region 27 is made of a different material from the gate insulating film 4 on the semiconductor layer 3 or is not formed integrally with the same material, the end insulator region 27 is formed on the semiconductor layer 3. Get Even if the structure penetrates into a part of the heat insulator 4, it is acceptable.
  • FIG. 43A shows a structure in which the end insulator region 27 penetrates a part of the cap insulator 8 on the semiconductor layer 3.
  • the gate insulating film 4 may be formed so as to cover the semiconductor layer 3 and the end insulator region 27.
  • This is a structure obtained when, for example, a gate insulating film is formed by a film deposition technique such as a CVD method after forming an end insulator region. An example is shown in Figure 43 (b).
  • FIG. 42 (a), FIG. 42 (b) and FIG. 42 (c), FIG. 43 (a) and FIG. 43 (b) are cross-sectional views taken along the line AA ′ of FIG.
  • FIG. 83 is a cross-sectional view at a corresponding position, which is a cross-sectional view corresponding to the cross-section shown in FIGS. 82 (a) and 83 (a) for explaining the conventional structure.
  • the width of the semiconductor layer main portion region 43 changes due to a factor due to processing accuracy (etching accuracy), particularly in a partial region such as the upper end or the lower end in the semiconductor layer main portion region 43. There may be an area to do. Further, in the semiconductor region 29, the width Wfin of the semiconductor layer may be changed within a certain limit (for example, within ⁇ 20%, more preferably within 10%) due to factors such as processing accuracy. .
  • the interface between the end insulator 27 and the gate electrode 5, and the interface between the gate insulating film 4 and the gate electrode 5 are in the same plane (the same straight line in the cross-sectional view). This is most preferable for controlling the gate electrode.
  • the effects of the present invention can be obtained even if the interface between the end insulator 27 and the gate electrode 5 is not in the same plane as the interface between the gate insulating film 4 and the gate electrode 5.
  • the end insulating film which is an insulator thicker than the gate insulating film is provided between the semiconductor layer and the gate electrode. Since the body region 27 is provided, a part of the corner of the semiconductor layer is formed by the end insulator region 27 (the upper corner portion and the end insulator region when the end insulator region 27 is provided above the semiconductor layer). In the case where 27 is provided below the semiconductor layer, the potential rise in the lower corner portion is suppressed, and the parasitic transistor is suppressed, so that the first problem is solved and the characteristics of the transistor are improved.
  • the plane orientation of the upper surface of the semiconductor layer and the plane orientation of the side surface of the semiconductor layer in the corner portion If a plane orientation significantly different from any of the above is not formed, or if it is formed, the surface is covered with the end insulator, so that both the plane orientation of the top surface of the semiconductor layer and the plane orientation of the side surface of the semiconductor layer Since the second problem does not occur unless a new parasitic transistor having a greatly different plane orientation is formed, good transistor characteristics can be obtained.
  • the field-effect transistor according to the third embodiment has, in addition to the features common to the third, fourth, and fifth embodiments, a part of the semiconductor layer end region 44 (preferably, The width Wtop of the semiconductor layer is almost constant over the entirety of the semiconductor layer end region 44 or more than 50% of the height of the semiconductor layer end region 44 (preferably, the fluctuation amount of the semiconductor width is ⁇ 20% or less, more preferably Has a characteristic that the fluctuation amount of the semiconductor width is ⁇ 10% or less).
  • FIG. 40 (a) is a plan view, which is a cross-sectional view taken along the line AA ′ of FIG. 40 (c).
  • FIG. 40 (b) is a plan view, which is a cross-sectional view taken along the line BB ′ 41 is a cross-sectional view of FIG. 40 (a) enlarged.
  • the semiconductor layer of the FinFET according to the third embodiment includes a semiconductor layer upper region 28 in which the width of the semiconductor layer is small in a plane perpendicular to the direction connecting the two source Z drain regions, and a semiconductor layer upper region.
  • the side surface of the semiconductor layer is recessed from the side surface of the semiconductor layer in the lower semiconductor layer region 29.
  • the symbol Wtop is the width of the semiconductor layer upper region 28 in a plane perpendicular to the direction connecting the two source / drain regions
  • the symbol Wfin is the width in a plane perpendicular to the direction connecting the two source / drain regions.
  • the width of the lower region 29 of the semiconductor layer is shown.
  • An end insulator region 27 is provided between the semiconductor layer upper region 28 and the gate electrode 5.
  • the gate insulating film 4 is provided between the semiconductor layer upper region 29 and the gate electrode 5.
  • the width Wei of the end insulator region 27 is larger than the thickness of the gate insulating film.
  • the gate electrode 5 is patterned to an appropriate size, and a source Z drain region 6 in which impurities of the first conductivity type are introduced at a high concentration is formed in the semiconductor layer at a position not covered by the gate electrode. Is done.
  • a channel made of carriers of the first conductivity type is formed by applying an appropriate voltage to the gate electrode 5. Wiring is connected to the gate electrode 5 and the source / drain region 6 via a contact region.
  • connection between the semiconductor layer upper region 28 and the semiconductor layer lower region 29 is as steep as possible. That is, it is most desirable that the width of each of the semiconductor layer upper region 28 and the semiconductor layer lower region 29 be discontinuously changed at the connection portion between them.
  • the semiconductor layer upper region 28 and the semiconductor lower region 29 there are regions in which the widths are different from Wtop and Wfin, respectively, in some of the regions due to factors such as processing accuracy. Is also good. For example, there may be a region where the width of the semiconductor layer changes at the upper end or lower end of the semiconductor layer upper region 28 and the upper end or lower end of the semiconductor lower region 29.
  • the transition region 40 may be provided in a region of the semiconductor layer upper region 28 that is in contact with the semiconductor layer lower region 29. This example is shown in FIG.
  • the minimum gradient 41 of the transition region in the transition region 40 is desirably 45 degrees or less, and particularly desirably 25 degrees or less.
  • FIG. 55 shows a cross-sectional view of the same cross section as FIG. Note that the minimum gradient 41 of the transition region refers to the angle between the semiconductor layer interface in the transition region 40 and the substrate surface at the position where the angle between the semiconductor layer interface and the substrate surface in the transition region 40 is minimum.
  • the semiconductor layer has a constant width, or in the semiconductor lower region 29, the width of the semiconductor layer is within a certain limit due to factors such as processing accuracy (or the top of Wtop). (Less than minus 10%, plus or minus 10% of Wfin).
  • FIG. 42 (a) shows an embodiment in which the third embodiment is applied to a tri-gate transistor.
  • FIG. 42 (b) shows a case where a cavity is provided as the end insulator region 27 in the third embodiment.
  • FIG. 42 (c) shows an example in which the end insulator region 27 and the cap insulating layer are integrally formed.
  • FIG. 43A shows a structure in which the end insulator region 27 penetrates a part of the cap insulator 8 on the semiconductor layer 3.
  • Figure 43 (b) shows an example of the structure obtained when the gate insulating film is formed by a film deposition technique such as the CVD method.
  • FIG. 83 is a cross-sectional view at a position, corresponding to the cross-section shown in FIGS. 82 (a) and 83 (a) for explaining the conventional structure.
  • the thickness of the force end insulator 27 mainly described in the case where the thickness of the end insulator 27 at the position where the width of the semiconductor layer is constant in the semiconductor layer upper region 28 is constant is described. May not be constant as long as its maximum value is thicker than the gate insulating film.
  • the thickness of the end insulator 27 is 5 nm or more and 3 times or more the gate insulating film thickness. More preferably, the thickness of the end insulator 27 is 5 nm or more, and more preferably 5 times or more the thickness of the gate insulating film.
  • the thickness of the gate insulating film 4 or the thickness of the end insulator 27 refers to the thickness in the vertical direction from the interface between the gate electrode 5 and each insulating film, which is the origin of the electric field. Point. Therefore, FIG. 80 (a), which is an enlarged view of the upper right corner of the semiconductor layer 3 in FIG. 85, indicates the thickness tl instead of the thickness t2, and shows the enlarged upper right corner of FIG. 66. In Fig. 80 (b), this indicates the thickness t3 instead of the thickness t4.
  • the width Wei of the end insulator region 27 and the term Thickness of the insulator region 27 are synonymous.
  • FIG. 44 shows the shape at a position corresponding to the cross section taken along the line AA ′ of FIG. 81 for explaining the conventional example, following the steps.
  • a cap insulating layer 8 (an insulating film layer such as SiO) is deposited on the semiconductor layer 3, and the upper portions of the cap insulating layer 8 and the semiconductor layer 3 are processed into a desired width by a normal lithography and RIE process ( Figure 44 (a)).
  • an insulator film such as a SiO film is deposited and etched back, and an end insulator region 27 is formed on the side surface of the cap insulating layer and the side surface of the semiconductor layer 3 (FIG. 44 (b)).
  • the semiconductor layer 3 is etched using the cap insulating layer 8 and the end insulator region 27 as a mask (FIG. 44 (c)).
  • a gate insulating film 4 is provided on the side surface of the semiconductor layer exposed by this step, and subsequently, a gate electrode material is deposited. Then, the gate electrode material is processed by a usual lithography and RIE step to form a gate electrode 5.
  • a source / drain region 6 is formed by introducing a high-concentration first conductivity type impurity into a region of the semiconductor layer 3 that is not covered by the gate electrode 5. Thereafter, an interlayer insulating film is deposited, and a contact 17 and a wiring 18 are formed by an ordinary method.
  • a cap insulating layer 8 (an insulating film layer such as SiO) is deposited on the semiconductor layer 3, and the upper portions of the cap insulating layer 8 and the semiconductor layer 3 are formed to have a desired width by a normal lithography and RIE process. If the top surface of the semiconductor layer exposed by etching is not horizontal in the process of FIG. 44 (a), a form having a cross section as shown in FIG. 55 is formed, but the effect of the invention is obtained. It doesn't change.
  • FIG. 45 shows a process at a position corresponding to a section taken along line AA ′ of FIG. 81 for explaining a conventional example. It is shown later.
  • a cap insulating layer 8 (an insulating film layer such as SiO) is deposited on the semiconductor layer 3, and the upper portions of the cap insulating layer 8 and the semiconductor layer 3 are processed into a desired width by a normal lithography and RIE process ( Figure 45 (a)). Next, corner dummy layer material such as SiN film is deposited and etched back
  • the corner dummy layer 22 composed of the N side wall 37 is provided on the side surface of the cap insulating layer and the side surface of the semiconductor layer 3. Subsequently, a second sidewall material such as a Si ⁇ film is deposited and etched back, and an SiO sidewall 38 is formed on the side surface of the corner dummy layer 22 (FIG. 45B). Subsequently, the semiconductor layer 3 is etched using the cap insulating layer, the corner dummy layer composed of the SiN side wall 37, and the second side wall composed of the SiO side wall 38 as a mask (FIG. 45 (c)). A gate insulating film 4 is provided on the side surface of the semiconductor layer exposed by this step, and subsequently, a gate electrode material is deposited.
  • the gate electrode material is processed by a usual lithography and RIE step to form a gate electrode 5.
  • a corner dummy layer 22 composed of the SiN side wall 37 is removed, an end insulator region 27 composed of the cavity 12 is formed in a region where the semiconductor layer has receded from the gate electrode.
  • a high concentration first conductivity type impurity is introduced into a region of the semiconductor layer 3 which is not covered with the gate electrode 5 to form a source / drain region 6.
  • an interlayer insulating film is deposited, and a contact 17 and a wiring 18 are formed by an ordinary method.
  • the deposition and etchback of SiN followed by the deposition and etchback of SiN and the formation of the second sidewall are performed by removing the sacrificial oxide film and cleaning the semiconductor layer. Is formed of an SiO film to prevent the side surface of the semiconductor layer from entering the inner side of the SiN side wall and to prevent the upper SiN side wall from protruding horizontally to form an overhang shape. If the second side wall is provided, in the step of removing the sacrificial oxide film, the second side wall also retreats at the same time, so that it does not have an overhang shape. If the overhanging shape is allowed by adding isotropic etching to the step of forming the gate electrode, the step of forming the second side wall may be omitted.
  • the cavity may be backfilled with a low dielectric constant material to form an end insulator region 27 made of a low dielectric constant material.
  • the low dielectric constant material carried in the cavities may be a continuous film such as SiOF, or may be a porous material.
  • a high-temperature heat treatment such as a heat treatment for activating impurities implanted into the source Z drain region.
  • a process of refilling the cavity with a low-k material or after completing these high-temperature heat treatment processes, form the cavity and fill the cavity with a low-k material.
  • Performing the reversion step can prevent high-temperature heat treatment from causing a chemical or physical change in the low-k material.
  • the element structure of the third embodiment can be formed.
  • FIGS. Fig. 47 (a), Fig. 48 (a), Fig. 49 (a), Fig. 50 (a) are plan views Fig. 47 (c), 048 (c), Fig. 49 (c), Fig. 50 (c) A—A ′ cross section of FIG. 47 (b), FIG. 48 (b), FIG. 49 (b), and FIG. 50 (b) are plan views, and FIG. 47 (c) and FIG. 48 (c).
  • FIG. 49 (c) and FIG. 50 (c) are cross-sectional views taken along line BB of FIG.
  • FIGS. 51 (a) and 52 are cross-sectional views in the same cross section as FIG. 20 (a)
  • FIG. 51 (b) is a cross-sectional view in the same cross section as FIG. 20 (b).
  • a cap insulating layer 8 is deposited on an SOI substrate in which a supporting substrate 1 made of silicon, a buried insulating layer 2 made of Si ⁇ , and a semiconductor layer 3 made of single crystal silicon are further stacked thereon.
  • FIG. 46 shows a cross section in this state.
  • the upper portion of the cap insulating layer 8 and the semiconductor layer 3 is patterned by a normal lithography process and a normal etching process such as RIE to obtain the shape shown in FIG.
  • the cap insulating layer 8 and the semiconductor layer 3 may be patterned by etching using a photoresist as a mask, or only the cap insulating layer 8 may be etched using a photoresist as a mask.
  • the patterning may be performed by etching the semiconductor layer 3 using the mask as a mask.
  • the cap insulating layer 8 is patterned so that its width is substantially the same as the width Wtop of the semiconductor layer upper region 28 (see FIG. 41) and is smaller than the width Wfin of the semiconductor layer lower region 29. You.
  • the etching depth of the semiconductor layer 3 is substantially equal to the height Htop of the semiconductor layer upper region 28. This state is shown in FIG.
  • a material to be a corner dummy layer is deposited and etched back to provide a corner dummy layer 22 on the side surface of the cap insulating layer and the exposed side surface of the semiconductor layer.
  • the material of the corner dummy layer 22 is, for example, SiN. In this process The resulting form is shown in FIG.
  • the semiconductor layer 3 is patterned by an etching process such as RIE to form an element region.
  • an etching process such as RIE to form an element region.
  • FIG. 4 a gate insulating film 4 is provided on the side surface of the semiconductor layer exposed by this step, and then a gate electrode material is deposited.
  • the gate electrode material is processed by a normal lithography and RIE step to form a gate electrode 5. . This state is shown in FIG.
  • a source / drain region 6 is formed by introducing a high-concentration first conductivity type impurity into a region of the semiconductor layer 3 which is not covered by the gate electrode 5.
  • corner dummy layer 22 is removed by etching to provide a cavity 24 to be an end insulator region 23.
  • a gate sidewall 14 is provided on the side surface of the gate electrode by depositing and etching back an insulating film, and thereafter, an interlayer insulating film is deposited, and a contact 17 and a wiring 18 are formed by an ordinary method. This state is shown in FIG.
  • a material to be an end insulator region 23 is deposited and etched back.
  • the end insulator region 23 may be provided on the side surface of the cap insulating layer and the side surface of the semiconductor layer which is exposed by etching.
  • the material of the end insulator region 23 is, for example, Si.
  • the material of the end insulator region 23 is a low dielectric constant material such as SiOF.
  • the semiconductor layer 3 is patterned by an etching process such as RIE using the cap insulating layer 8 and the end insulator region 23 as a mask to form an element region.
  • FIG. 52 is a cross-sectional view of the same cross section as FIG. 51 (a), and an end SiO 2 region 25 is formed instead of the cavity 24 in FIG.
  • FIG. 53 shows a potential distribution in the structure of FIG. 42 (b) in which a cavity is formed in a region where the semiconductor layer is recessed from the gate electrode. Note that the upper end of the semiconductor layer serving as a channel is a portion adjacent to the lower end of the cavity.
  • the curvature of equipotential lines at the corners below the cavity is significantly reduced, and the potential rise at the corners is suppressed. This indicates that the parasitic transistor at the corner is suppressed.
  • FIG. 54 (d) shows a plot of the potential distribution on the side surface of the semiconductor layer as in FIG. 9 (b).
  • the left end of the figure is the upper end of the semiconductor layer below the cavity.
  • the potential rise is reduced to 30.8 mV, and this embodiment suppresses the potential rise at the corner and the effect of the parasitic transistor at the corner is remarkable.
  • the surface of the end insulator region and the surface of the gate insulating film 4 (the interface on the gate electrode side is referred to as surface) be aligned because the gate electrode can be easily processed.
  • the effect of suppressing the potential rise at the upper corner portion of the semiconductor layer and suppressing the parasitic transistor can be obtained.
  • the side surface of the semiconductor layer 3 recedes from the gate electrode side with respect to the corner dummy layer 22 due to the sacrificial oxidation step and the wet etching step for the sacrificial oxide film.
  • the surface of the gate insulating film 4 recedes as compared with the surface of the end insulator region 23.
  • Fig. 89 shows an example of the structure. This structure is the same as that of the first embodiment shown in FIG. 4A after the formation of the structure shown in FIG. As described above, this is obtained when the semiconductor layer 3 is selectively narrowed with respect to the cap insulating layer 8 and the end insulator region 27 by an isotropic etching process.
  • FIG. 44 (a), Fig. 90 (b), Fig. 90 (c), and Fig. 91 (b) show Fig. 44 (a), Fig. 44 ( b), corresponding to the steps in FIG. 44 (c) and FIG. 44 (d).
  • the field effect transistor according to the fourth embodiment has a feature common to the third embodiment, the fourth embodiment, and the fifth embodiment. It has the feature that it does not have a constant width area.
  • the semiconductor layer end region 44 of the field effect transistor according to the fourth embodiment has a form in which the width of the semiconductor layer becomes narrower as the distance from the connection portion with the semiconductor layer main region 43 increases.
  • the end insulator region 27 provided between the semiconductor layer end region 44 and the gate electrode 5 forms a connection portion force between the semiconductor layer end region 44 and the semiconductor layer main region 43 as the force increases. It becomes thicker.
  • the maximum value of the thickness of the end insulator region 27 is larger than the thickness of the gate insulating film.
  • FIGS. 56, 57, 59, and 60 show the structure of the field-effect transistor according to the fourth embodiment, taking the case as an example.
  • FIG. 56, FIG. 57, FIG. 59 and FIG. 60 are cross-sectional views taken along the line AA ′ of FIG. 81 illustrating the conventional structure
  • FIG. 82 (a) and FIG. FIG. 2 is a cross-sectional view of a cross section corresponding to the cross section shown in FIG.
  • the symbol Wtop is the minimum width of the semiconductor layer edge region
  • the symbol Wei is the maximum width of the edge insulator region
  • the symbol Wfin is the width of the semiconductor layer main region.
  • FIGS. 56 and 59 show FIGS. 57 and 60 when the fourth embodiment is applied to a double-gate transistor having a cap insulating layer 8. The case where the fourth embodiment is applied to a transistor having a tri-gate structure having the gate insulating film 4 at the upper interface of the semiconductor layer without the cap insulating layer 8 is shown. In any of FIG. 56, FIG. 57, FIG. 59 or FIG.
  • an end insulator region 27 is provided between the semiconductor upper region 28 and the gate electrode 5, and at least a part of the end insulator region 27 is provided. At the position, the width of the end insulator region 27 is thicker than the gate insulating film 4.
  • FIG. 58 shows the shape at a position corresponding to the AA ′ cross section of FIG. 81 for explaining the conventional example, step by step.
  • a cap insulating layer 8 (an insulating film layer of SiO or the like) is deposited on the semiconductor layer 3, the cap insulating layer 8 is removed by a usual lithography and RIE process, and the upper portion of the semiconductor layer 3 is tapered. Etching is performed by RIE so that it has (Fig. 58 (a)).
  • an insulator film such as a SiO film is deposited and etched back to form an end insulator region 27 on the side surface of the cap insulating layer and the side surface of the semiconductor layer 3 (FIG. 58 (b)).
  • the semiconductor layer is etched using the cap insulating layer 8 and the end insulator region 27 as a mask (FIG. 58 (c)).
  • a gate insulating film 4 is provided on the side surface of the semiconductor layer exposed by this step, and after a gate electrode material is deposited, the gate electrode material is processed by a usual lithography and RIE step to form a gate electrode 5.
  • a taper etching technique of mixing a gas containing carbon when performing RIE is used. For example, by mixing CH with C1, a carbon compound is gradually deposited during etching, and a tapered shape is formed by utilizing the fact that etching does not proceed at the position where the carbon compound is deposited.
  • a high-concentration first conductivity type impurity is introduced into a region of the semiconductor layer 3 that is not covered with the gate electrode 5, to form a source / drain region 6.
  • an interlayer insulating film is deposited, and a contact 17 and a wiring 18 are formed by an ordinary method.
  • the cap insulating layer 8 is removed by an etching step such as RIE, and then the gate insulating film 4 is formed, and the subsequent steps are performed.
  • a tri-gate structure as shown in FIG. 57 is obtained.
  • Fig. 57 shows the cap insulating layer 8 by RIE. Is removed, the upper portion of the end insulating film is also etched at the same time.
  • the cap insulating layer 8 is removed by an etching process such as RIE, if the thickness of the buried insulating layer 2 is larger than that of the cap insulating layer 8, the etching of the buried insulating layer is performed simultaneously with the etching of the cap insulating layer.
  • the etching progresses or the cap insulating layer is removed Even if the etching progresses or the cap insulating layer is removed, a part of the embedded insulating film remains and a form in which the supporting substrate is not exposed is obtained, which is preferable.
  • a material that is resistant to etching with respect to the cap insulating layer for example, SiN, is used for the whole, the surface, or the layer at a certain depth of the filled insulating layer, even if the cap insulating layer is removed, the carrier is not removed.
  • FIGS. 61 (a), 62 (a), 63 (a) and 64 (a) are plan views of FIGS. 61 (c), 62 (c), 63 (c) and FIG. 61 (b), FIG. 62 (b), FIG. 63 (b), and FIG. 64 (b) are plan views of FIG. 61 (c).
  • FIG. 66 is a cross-sectional view taken along the line ⁇ _ ⁇ ′ of FIGS. 62 (c), 63 (c), and 65.
  • the position of the ⁇ -A ′ cross section of each drawing explaining the present embodiment is the same as the position of the BB cross section of FIG. 81 correspond to the positions of the cross section BB ′ in FIG. 81 showing the conventional example.
  • a cap insulating layer 8 made of, for example, Si ⁇ is formed on the semiconductor layer 3 on the buried insulating layer 2 (at this time,
  • the semiconductor layer 3 and the cap insulating layer 8 are patterned into an appropriate shape (the shape at this point is the same as in FIG. 3). Subsequently, at the interface between the semiconductor layer 3 and the cap insulating layer and at the interface between the semiconductor layer 3 and the buried insulating layer 2, the side surface of the semiconductor layer 3 recedes inward from the position of the end of the cap insulating layer 8, The semiconductor layer 3 is thermally oxidized. At this time, the oxide film thickly formed at the upper and lower corners of the semiconductor layer is This becomes insulator region 27 ( Figure 61).
  • a sacrificial oxide film layer 44 is formed on the side surface of the semiconductor layer 3.
  • the sacrificial oxide film layer 44 is removed from the side surfaces of the semiconductor layer 3 by an etching process such as wet etching to obtain the configuration shown in FIG.
  • a gate insulating film 4 is provided on the side surface of the semiconductor layer (FIG.
  • a gate electrode material is formed by a usual lithography and RIE process to form a gate electrode 5. I do. Subsequently, a high-concentration first conductivity type impurity is introduced into a region of the semiconductor layer 3 that is not covered with the gate electrode 5 to form a source / drain region. Thereafter, an interlayer insulating film is deposited, and contacts and wirings are formed by a usual method (FIGS. 64 and 65).
  • the cap insulating layer 8 is removed by an etching process such as RIE at a certain stage before the formation of the gate insulating film, and a subsequent process is performed. Then, a tri-gate structure as shown in FIG. 60 is obtained.
  • an etching process such as RIE
  • the cap insulating layer is etched simultaneously with the etching of the cap insulating layer. This is preferable because a form in which a part of the buried insulating film remains even when the cap insulating layer is removed and the supporting substrate is not exposed can be obtained.
  • the embedded insulating film may be removed.
  • the end insulator when the filled insulating layer easily diffuses an oxidizing agent, specifically when the buried insulating layer is SiO, the end insulator is also provided below the semiconductor layer. Region 27 is formed.
  • the filled insulating layer does not easily diffuse the oxidant, specifically, when the filled insulating layer is SiN, or when the filled insulating layer is SiO, but the film thickness is extremely thin If it is (for example, 10 nm or less), the end insulator region 27 is not formed below the semiconductor layer.
  • the fourth embodiment has an advantage that the height of the semiconductor layer end region 44 can be reduced as compared with the third embodiment.
  • the semiconductor layer upper region 28 of FIG. 55 this corresponds to a mode in which the semiconductor layer above the transition region 40 is removed, and the structure is simplified, so that the height of the semiconductor layer is reduced.
  • the manufacturing method is easy, for example, the end insulator region 27 can be formed only by thermally oxidizing the semiconductor layer 3 in the region in contact with the cap insulating layer 8.
  • the fourth embodiment has a structure in which the transition between the semiconductor layer upper region and the semiconductor layer lower region does not change sharply in the modes shown in Figs.
  • a gate is provided between the semiconductor layer and the gate electrode above the semiconductor layer. Since the end insulator 27 thicker than the insulating film 4 is provided and the channel is hardly formed on the side surface of the upper region of the semiconductor layer, the second problem can be sufficiently solved, and sufficient element performance can be obtained. it can. Further, since an end insulator 27 thicker than the gate insulating film 4 is provided between the semiconductor layer and the gate electrode above the semiconductor layer, the ability to solve the first problem is achieved similarly to the third embodiment. Excellent.
  • the field effect transistor according to the fifth embodiment has a feature common to the third embodiment, the fourth embodiment, and the fifth embodiment.
  • the semiconductor provided below 43 and the semiconductor layer provided below the main part 43
  • An end insulator region 27 which is an insulating film thicker than the gate insulating film 4 is provided between the layer end region 44 (semiconductor layer lower end region 42) and the gate electrode 5.
  • the field-effect transistor according to the fifth embodiment has a feature common to the third embodiment, the fourth embodiment, and the fifth embodiment. It is provided on both the upper portion of the main layer portion 43 and the lower portion of the main portion 43 of the semiconductor layer. Between the semiconductor layer end region 44 provided below 43 and the gate electrode 5, an end insulator region 27 which is thicker than the gate insulating film 4 and is an insulating film is provided.
  • the structure of the fifth embodiment is manufactured by, for example, the second manufacturing method of the fourth embodiment.
  • the buried insulating layer 2 is made of Si which easily diffuses an oxidizing agent such as oxygen in order to form the end insulator region 27 below the semiconductor layer.
  • cap insulating layer 8 is removed after the end insulating film 27 is formed, the configuration shown in FIG. 68 is formed, and if the cap insulating layer 8 is not removed, the configuration shown in FIG. 66 is formed.
  • the fifth embodiment suppresses a rise in potential at a lower corner portion of the semiconductor layer (a lower corner portion of the semiconductor layer) and suppresses a parasitic transistor at a lower corner portion of the semiconductor layer, thereby improving the characteristics of the transistor. It has the effect of improving.
  • the upper corner portion and the lower corner portion of the semiconductor layer are formed. Since the potential rise in both of them can be suppressed and the parasitic transistor can be suppressed in both the upper corner part and the lower corner part of the semiconductor layer, the effect of improving the characteristics of the transistor is remarkable.
  • the first to fourth embodiments of the present invention are not limited to FinFET, in which a semiconductor layer is formed on an insulator, and have no embedded insulating layer, and may be applied to FinFET.
  • This example is shown in FIGS. 71 (a), 71 (b), 72 (a), 72 (b), and 73.
  • FIGS. 1 (a), 10 (a), 13 (a), FIGS. 41 and 60 does not use the embedded insulating layer 2.
  • the sixth embodiment is different from the manufacturing method of the first embodiment to the fourth embodiment in that, instead of the SOI substrate which is a substrate having a buried insulating layer, a normal semiconductor substrate, typically Is formed when a silicon substrate is used. The shape during the manufacturing process is shown in FIG. FIG.
  • FIG. 74 (a) is a drawing corresponding to FIG. 18 (a) when a substrate having no embedded insulating layer is used.
  • FIGS. 74 (b) and 74 (c) show the state where the source Z drain region is formed and the transistor structure is formed, and correspond to FIGS. 19 (a) and 19 (b), respectively. I do.
  • the gate electrode 5 is provided under the semiconductor layer. It is desirable to provide an insulating film 31 under the gate electrode.
  • the insulating film 31 below the gate electrode is formed, for example, by processing a semiconductor substrate by etching to form a convex semiconductor layer 3, and then depositing an insulator such as Si ⁇ on the entire surface by a film forming technique such as a CVD method. C deposited insulator
  • the gate electrode lower insulating film 31 After flattening by a flattening technique such as the MP method, it can be formed by etching back the deposited insulator until the thickness of the insulator at the foot of the semiconductor layer 3 becomes an appropriate thickness.
  • the gate electrode lower insulating film 31 After the gate electrode lower insulating film 31 is formed, it is manufactured by applying the same manufacturing method as in the embodiment in which the embedded insulating layer is provided. It is desirable that the insulating film 31 below the gate electrode be formed of a material having a lower dielectric constant than SiO, in terms of suppressing parasitic capacitance between the gate electrode and the supporting substrate. In addition, when the insulating film 31 below the gate electrode is formed of a material having a lower dielectric constant than SiO, it is effective in suppressing the electric field concentration at the lower corner 35 of the semiconductor layer 3.
  • the side surface of the semiconductor layer 3 corresponds to the end insulator region 27.
  • the portion in contact with the semiconductor layer is the semiconductor layer end region 44.
  • the side surface of the semiconductor layer 3 is not in contact with the end insulator region 27, and the side surface of the semiconductor layer 3 faces the gate electrode via the gate insulating film, and a portion corresponding to the semiconductor layer main region 43. .
  • Embodiments of the present invention are not limited to FinFETs formed on a single semiconductor region, and a semiconductor layer forming a channel formation region is not limited to a FinFET formed on a single semiconductor region. May be applied. That is, as shown in FIG. 75 (a), the present invention may be applied to a transistor composed of a plurality of semiconductor layers each having a channel formed thereon, and each channel may be formed as shown in FIG. 75 (b). It may be applied to a transistor in which a plurality of semiconductor layers are connected to each other at a position away from the gate.
  • the positions indicated by AA in FIGS. 75A and 75B correspond to the positions of the cross section AA 'in each embodiment.
  • one of the upper corner portion and the lower corner portion of the semiconductor layer 3, or both the upper corner portion and the lower corner portion of the semiconductor layer 3 may have a rounded shape. good.
  • the lower corner portion of the semiconductor layer 3, the corner portion located near the upper end of the end insulator region in the semiconductor layer 3, the vicinity of the lower end of the end insulator region in the semiconductor layer 3 At least one of the corners may have a rounded shape.
  • FIG. 76 shows a form in which the upper corner is rounded in the form of Fig. 1 (a), and Fig. 77 (a) shows a form in which the upper corner is rounded in the form of Fig. 10 (a).
  • FIG. 77 (b) shows the form in which the upper corner and the lower corner are rounded in the form of FIG. 10 (b), and
  • FIG. 13 (a) shows the form in which the upper corner is rounded.
  • FIG. 78 (a) shows the configuration of FIG. 78
  • FIG. 78 (b) shows the configuration in which the upper corner portion and the lower corner portion are rounded in the configuration of FIG. 13 (b)
  • FIG. FIG. 79 shows a form in which both the corner located near the upper end of the insulator region and the corner portion located near the lower end of the end insulator region in the semiconductor layer 3 are both rounded.
  • These forms are formed by thermally oxidizing the semiconductor layer.
  • the upper corner of the semiconductor layer may be rounded, and the cap insulating layer 8 may be rounded (FIGS. 87 and 88).
  • Such a configuration is formed by performing sacrificial oxidation and wet etching of the semiconductor layer before forming the gate oxide film.
  • the corner of the semiconductor layer is rounded by the sacrificial oxidation, and the corner of the cap insulating layer is removed in the wet etching process.
  • the corner of the semiconductor layer is rounded by the sacrificial oxidation, and the corner of the cap insulating layer is removed in the wet etching process. Are formed when they are rounded by etching.
  • the surface of the gate insulating film is located at the same height as the upper end of the semiconductor layer and at a position lower than the upper end of the semiconductor layer. If at least a part of the cap insulating layer extends to the gate electrode side with respect to the surface of the gate insulating film at the position most receded from the electrode side (the interface on the gate electrode side) (the extension width is Wext in the figure) ), An electric field relaxation effect at the upper corner portion is obtained as in the first embodiment. Also, the size of the overhang width Wext may be set in the same manner as in the first embodiment. Other operations and principles are the same as those of the first embodiment.
  • the manufacturing method is the same as that of the first embodiment except for the features in the sacrificial oxidation and the subsequent wet etching step as described above.
  • the projection of the cap insulating layer on the side of the gate electrode beyond the surface of the gate insulating film at the position where the width of the semiconductor layer is the widest provides an electric field relaxation effect at the upper corner portion.
  • the cap insulating layer is recessed from the gate electrode side of the gate insulating film at the position where the width of the semiconductor layer is the widest as shown in FIG. In this case, the electric field relaxation effect can be obtained to some extent.
  • the overhang width Wext is horizontal (in the plane perpendicular to the direction in which the semiconductor layer 3 protrudes from the substrate and perpendicular to the channel length direction) as shown in FIG. Is defined in
  • the combination of each embodiment of the present invention with the process of rounding the corner portion does not combine with each embodiment of the present invention.
  • the amount of rounding required to obtain the electric field relaxation effect that can solve the first problem can be reduced, and the radius of curvature of the corner can be reduced. Therefore, when each embodiment of the present invention is combined with a process of rounding a part of a corner, a region having a curved surface is reduced, so that even if the second problem cannot be completely solved, the second problem can be solved. It can be greatly reduced.
  • the support substrate 1 is usually a single-crystal silicon wafer, but a substrate other than a silicon substrate such as quartz, glass, sapphire, or a semiconductor other than silicon may be used.
  • the buried insulating layer 2 is usually made of Si, but may be another insulator or a multilayer film made of a plurality of materials. Also, the insulating layer to be filled is porous SiO, Si ⁇ F, etc.
  • a low dielectric constant material having a lower dielectric constant than SiO may be used.
  • the support substrate is an insulator such as quartz, glass, or sapphire
  • the support substrate 1 may also serve as the insulating film 2 to be buried.
  • the thickness of the buried insulating layer 2 is generally about 50 nm to 2 ⁇ m, more typically 50 nm to 200 nm. The thickness may be 50 nm or less or 2 ⁇ m or more as needed.
  • a structure having no buried insulating layer 2 is used.
  • the semiconductor layer 3 is a single crystal from the viewpoint of improving the on-current and suppressing the off-current, but when the required on-current specification is low or the required off-current specification is large, It may be a material other than a single crystal, such as amorphous, polycrystalline, or the like.
  • the semiconductor layer 3 it is acceptable to replace the semiconductor layer 3 with a semiconductor layer other than silicon. Also, it can be replaced by a combination of two or more semiconductors.
  • the semiconductor layer has a shape protruding from the substrate surface.
  • the substrate surface is generally the upper surface of the support substrate 1, but in the case of a structure in which the embedded insulating layer 2 and the support substrate are integrated, the substrate surface is the upper surface of the embedded insulating layer 2.
  • the under-gate insulating film 31 is provided, it is the upper surface of the under-gate insulating film 31.
  • the height Hfm of the semiconductor layer 3 is typically 20 nm, 150 nm, and more typical.
  • the width of the semiconductor layer Wfm is typically 5 nm to 100 nm, which is more typical. Is between 15 nm and 50 nm. However, even if Hfm and Wfin use values outside this range, Good les ,.
  • the semiconductor layer in the channel formation region is depleted when a threshold voltage is applied to the gate electrode, which is a characteristic of FinFET (represented by a reduction in S factor, sharpening of ON-OFF characteristics, etc.). It is desirable from the viewpoint of utilizing In order to achieve a fully depleted state where the depletion layers extending from both sides of the semiconductor layer are in contact with each other with a threshold voltage applied to the gate electrode, Wfin is usually 50 nm or less, more typically 30 nm. It is preferable to set the following.
  • the gate insulating film 4 may be formed by thermal oxidation of silicon or may be a SiO film formed by another method. For example, an SiO film formed by radical oxidation may be used. Also, the gate insulating film should be replaced with an insulating material other than SiO. Also
  • the gate insulating film may be replaced with a high dielectric constant material such as Hf ⁇ or HfSiO.
  • the equivalent oxide film thickness of the gate insulating film is typically 1.2 nm to 3 nm. However, the oxide equivalent film thickness is obtained by multiplying the quotient obtained by dividing the thickness of the insulating film constituting the gate insulating film by the dielectric constant of the gate insulating film by the dielectric constant of Si ⁇ . When the gate insulating film is a multilayer film, the oxide film equivalent thickness is obtained for each layer by the above-described method, and these are added.
  • the gate electrode 5 may be a polycrystalline semiconductor such as polysilicon or a conductor other than a polycrystalline semiconductor such as a metal or a metal compound.
  • the gate electrode 5 is made of a polycrystalline semiconductor such as polysilicon, typically, the first conductivity type impurity having the same conductivity type as the channel is introduced into the polysilicon of the gate electrode 5 at a high concentration.
  • the gate electrode may be formed by a replacement gate (also called a replacement 'gate) process. That is, the shape of the gate electrode is formed with a dummy material, the first conductivity type impurity is introduced into the source Z drain region at a high concentration, the dummy material is covered with an insulating film, and then the dummy material is removed.
  • a gate electrode or a gate insulating film and a gate electrode may be buried in the cavity thus obtained.
  • the gate electrode material is formed of a semiconductor such as polysilicon or polycrystalline silicon-germanium mixed crystal
  • the introduction of impurities into the gate may be performed at the same time as the introduction of impurities into the source / drain. Further, it may be performed simultaneously with the deposition of the gate electrode material. Alternatively, it may be performed before a gate electrode material is deposited and processed into the shape of the gate electrode.
  • the gate electrode usually has a structure straddling the semiconductor layer.
  • the present invention provides a transistor in which a gate electrode is disposed above a semiconductor layer and on a side surface of a semiconductor layer, and an electric field from the gate above the semiconductor layer and an electric field from a gate on the side surface of the semiconductor layer cause electric field concentration. It is particularly effective for alleviating.
  • FIG. 94 shows the case where the second embodiment is applied to the FinFET where the gate electrode is not arranged above the semiconductor layer
  • FIG. 95 shows the case where the third embodiment is applied.
  • FIG. 94 is a sectional view corresponding to FIG. 10, and
  • FIG. 95 is a sectional view corresponding to FIG.
  • the source / drain region 6 is doped with a first conductivity type impurity at a high concentration.
  • the source / drain regions include all regions called shallow source / drain regions (also called extension regions) and regions called deep / source / drain regions in a Balta transistor.
  • the definition of the extension region and the deep source / drain region is not generally clarified, but, for example, the source / drain region formed in the strip-shaped region adjacent to the gate in FIG. It is assumed that the strip-shaped area at a position away from the gate includes both areas connected to each other.
  • a semiconductor such as silicon is epitaxially grown on a part of the source Z drain region, thereby increasing the size of the semiconductor layer forming the source / drain region. It is also possible to combine techniques for expanding in the plane.
  • a source / drain region is provided in a portion of the semiconductor layer 3 that is not covered by the gate electrode.
  • the source Z drain region provided in the part not covered by the gate electrode
  • a source / drain region that penetrates a region of the semiconductor layer 3 that is covered with the gate electrode may be provided.
  • a source / drain region may be provided with a certain width of an offset region from a semiconductor layer covered with a gate electrode.
  • the electric field strength at the end of the source / drain region decreases, so that the leakage current decreases.
  • This structure is desirably applied to DRAM (dynamic-random access memory) cell transistors, in which the reduction of leakage current is prioritized over the magnitude of drain current.
  • a low concentration of ceptor or donor impurity is introduced into the channel forming region 7.
  • the gate electrode is polysilicon of the first conductivity type
  • a low concentration of the second conductivity type impurity is typically introduced into the channel formation region because the threshold voltage needs to be set to an appropriate value.
  • the threshold voltage is set low, or if the gate electrode is made of metal or metal
  • no impurity is introduced into the channel formation region 7 or a low concentration of the first conductivity type impurity is introduced. May be.
  • a region adjacent to the source / drain region covered with the gate electrode is closer to the source / drain region covered by the gate electrode, and the second conductivity type is A halo region into which impurities are introduced slightly higher may be provided.
  • FIG. 96 shows a case where the method of increasing the concentration of the second conductivity type impurity in the upper part of the semiconductor layer 3 forming the channel formation region is applied to the first embodiment, and is applied to the second embodiment.
  • FIG. 97 shows the case, and FIGS. 98 and 99 show the case where the third embodiment is applied.
  • 96 corresponds to FIG. 1
  • FIG. 97 corresponds to FIG. 10
  • FIGS. 98 and 99 correspond to FIG. 41.
  • Symbol 47 in the figure is a region where the concentration of the second conductivity type impurity is high.
  • a technique of providing a high-concentration portion above a semiconductor layer of a FinFET to suppress a parasitic transistor is described in Japanese Patent Application Laid-Open No. 6-302817.
  • the impurity concentration above the semiconductor layer which is necessary for suppressing the parasitic transistor, can be set lower. If the impurity concentration in the upper part of the semiconductor layer is set lower, the electric field strength between the source / drain region end and the high concentration part in the upper part of the semiconductor layer becomes smaller, so that the height of the source / drain region end and the upper part of the semiconductor layer become higher. Leakage current between the impurity and the concentration portion is reduced.
  • the cap insulating layer 8 is provided on the semiconductor layer 3.
  • the cap insulating layer 8 is provided below the gate electrode.
  • the cap insulating layer 8 is arranged such that at least a part of the cap insulating layer 8 is located at a position lower than the upper end of the gate electrode. (The case where the gate electrode 5 does not straddle the semiconductor layer 3 is shown in FIGS. 94 and 95.)
  • the cap insulating layer 8 may be a single-layer insulating film such as a Si ⁇ film or a SiN film.
  • It may be a multilayer film made of an insulating film such as a SiO film or a SiN film. Also, cap insulating layer
  • Part or all of 8 may be made of a material having a lower dielectric constant than Si ⁇ . It is also acceptable that part or all of the cap insulating layer 8 is formed of a cavity.
  • the cap insulating layer 8 may be formed of a cavity and a protective insulating film made of an insulator such as SiO provided around the cavity.
  • the thickness of the cap insulating layer 8 is at least twice the thickness of the gate insulating film, more typically at least five times the thickness of the gate insulating film.
  • the thickness of the cap insulating layer 8 is typically 10 nm force, 100 nm or more, more typically 10 nm to 50 nm. If the gate insulating film is thin, the thickness may be 10 nm or less. Note that the thickness of the cap insulating layer 8 is a thickness as viewed in a direction perpendicular to the upper surface of the semiconductor layer, and is usually a thickness in the vertical direction.
  • the ratio of the thickness to the gate insulating film is calculated as the converted film thickness (the physical film thickness is divided by the dielectric constant. Quotient multiplied by a constant (usually the relative dielectric constant of SiO).
  • the thickness of the low dielectric constant region 10 provided above or below the semiconductor layer is typically 10 nm, typically 100 nm, more typically 20 to 50 nm. It is desirable to have a thickness of 10 nm or more to obtain a large effect.
  • the material in the low dielectric constant region is SiOF, porous Si ⁇ , porous siloxane, or Si.
  • materials in the low dielectric constant region include C, such as black diamond, amorphous carbon, and a low dielectric constant material made of an organic material.
  • the low dielectric constant region may be a cavity. Further, the low dielectric constant region may be formed of a porous material, and the low dielectric constant region may include many cavities.
  • the corner dummy layer 22 may be made of any material that can be selectively removed in the manufacturing process. For example, when SiN is used for the corner dummy layer 22,
  • Layer 22 is selectively etched.
  • the gate insulating film and the filled insulating layer are selectively etched.
  • the corner dummy layer 22 is selectively etched with hydrofluoric acid.
  • the inside of the cavity is filled with vacuum or a suitable gas.
  • the cavity 12 is not filled with the solid material.
  • the gate sidewall 14 may be a single-layer insulating film such as a SiO film or a SiN film.
  • a multilayer film made of an insulating film such as an O film or a SiN film is acceptable.
  • the thickness of the gate sidewall 14 is If it is necessary to miniaturize the force element, which is usually from 20 nm to 150 nm, it may be set to 20 nm or less.
  • the step of depositing the insulating film to be the gate side wall 14 uses a deposition technique with poor coverage. It is desirable that the cavity is not filled. For example, CVD is performed under relatively high gas partial pressure conditions.
  • CVD is performed under relatively high gas partial pressure conditions.
  • the gate side wall 14 is a multilayer film, only the insulating film to be deposited first may be formed by using a deposition technique having poor coverage.
  • the silicide layer 15 is typically made of a material such as titanium silicide, cobalt silicide, nickel silicide, or platinum silicide.
  • the silicide layer 15 is formed, for example, by depositing a metal such as titanium, cobalt, nickel, or platinum on the source / drain region by a deposition technique such as a sputtering method and performing a heat treatment to form a silicide between the metal and the silicon layer. It is formed by causing a reaction.
  • the contact 17 and the wiring 18 are formed by a normal contact forming step and a normal wiring step.
  • the contact 17 and the wiring 18 are usually formed of a metal such as aluminum or copper, and are appropriately combined with other conductive materials such as TiN.
  • the supporting insulating film 21 is usually an insulating film such as SiO deposited by a film forming technique such as CVD, but may be a film formed by another method as long as insulating properties can be obtained. Films other than ⁇ may be used.
  • the corner dummy layer 22 may be any material that can be selectively removed in the manufacturing process.
  • the corner dummy layer 22 is selectively etched with phosphoric acid. If the gate insulating film and the filled insulating layer are made of a material that cannot be etched with hydrofluoric acid, such as SiN, a corner dummy layer
  • the corner dummy layer 22 is selectively etched with hydrofluoric acid.
  • End insulator regions 23, 27 The end insulator regions (23, 27) can be made of any insulating material, for example, Si ⁇ , Si N
  • the regions 23 and 27 are formed of the same low dielectric constant material as the low dielectric constant region 10.
  • the low dielectric constant region 10 For example, SiOF, a porous material, fluorinated carbon, a cavity, and the like can be given.
  • the width Wei of the end insulator region (23, 27) should be thicker than the gate oxide film, which is smaller than half the width Wfin of the entire semiconductor.
  • a typical upper limit is on the order of 15nm, more typically 5nm to 10nm.
  • the height Htop of the end insulator region is not particularly limited, but is generally less than half of the total height of the semiconductor layer including the upper region 28, more typically from 5 nm. 25 nm.
  • the width Wei of the end insulator may be not constant, but the first problem is solved by being larger than the thickness of the gate oxide film at least at a position in contact with the upper end of the semiconductor layer 3. For this reason, if the width of the desired and end insulator Wei is not constant, a typical upper limit for the maximum value of Wei is on the order of 15 nm, more typically 5 nm to 10 nm.
  • Ion implantation typically introduces 5 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 21 cm 3 of donor or acceptor impurities into high concentration regions, such as source / drain regions and gate electrodes. More typically, 3 ⁇ 10 19 cm ⁇ 3 to 1 ⁇ 10 2 Q cm 3 of donor or acceptor impurities are introduced.
  • the impurity is introduced by, for example, ion implantation or vapor phase diffusion. Typical doses during ion implantation are 1 ⁇ 10 14 cm 2 to 3 ⁇ 10 15 cm— 2 , more typically 3 ⁇ 10 14 cm— 2 to 1 ⁇ 10 15 cm— 2 .
  • Net impurity concentration in the low concentration region such as the channel formation region is typically 1 X 10 17 cm- 3 From 1 ⁇ 10 19 cm— 3 , more typically 5 ⁇ 10 17 cm— 3 force 5 ⁇ 10 18 cm— 3 .
  • the transistor may locally exceed the typical value depending on ion implantation conditions.
  • the influence of the parasitic transistor is particularly remarkable, since the net impurity concentration of the second conductivity type Keru Contact to the channel formation region region is the case of 1 X 10 18 cm- 3 or more, the present invention
  • the concentration of the net impurity of the second conductivity type in the channel forming region is 1 ⁇ 10 18 cm— 3 It is particularly effective when applied to the above-described field-effect transistor.
  • electric field concentration occurs for reasons other than the suppression of parasitic transistors (for example, improvement of the reliability of the gate insulation film, improvement of the yield of the gate insulation film, and suppression of the short channel effect as described in the description of the second embodiment).
  • each embodiment of the present invention may be applied to a field-effect transistor in which a channel formation region is a first conductivity type.
  • the first conductivity type impurity introduced into the source Z drain region and the first conductivity type impurity introduced into the source / drain region are a donor impurity having an n type conductivity in the case of an n-channel transistor.
  • an impurity having a p-type conductivity may be selected.
  • the impurity of the second conductivity type introduced into the halo region is an acceptor impurity having a p-type conductivity in the case of an n-channel transistor, and a donor impurity having an n-type conductivity in the case of a p-channel transistor. Good choice ,.
  • Typical examples of the n-type impurity are arsenic, phosphorus, and antimony.
  • Typical examples of the p-type impurity are boron and indium.
  • Activation of the ion-implanted impurities is performed by a heat treatment such as annealing or lamp annealing in a normal electric furnace after the ion implantation.
  • a heat treatment such as annealing or lamp annealing in a normal electric furnace after the ion implantation.
  • the heat treatment for activating the ions implanted into the channel region may be performed immediately after the ion implantation, or may be combined with the heat treatment for activating the impurities introduced into the source / drain regions.
  • Impurity introduction into the source / drain regions may be performed by introducing the impurity into the region not covered by the gate electrode after the formation of the gate electrode.
  • a method in which an impurity is previously introduced into a region where a drain region is to be formed may be used.
  • each part constituting the semiconductor device such as the source Z drain region 6, the interlayer insulating film 16, the contact 17, the wiring 18 and the like
  • the arrangement is the same as that shown in FIGS. 8 and 9 for explaining the first embodiment.
  • the polarity is reversed in the power S and p channel transistors described mainly for the n channel transistor (for example, the potential rise in the n channel transistor and the potential in the p channel transistor are reversed).
  • a decrease in the threshold voltage of an n-channel transistor can be interpreted as a rise in the threshold voltage of a p-channel transistor, and an increase in the voltage or potential can be interpreted as a decrease in the voltage-to-potential.
  • the sign of the applied voltage such as the drain voltage is reversed.

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  • Thin Film Transistor (AREA)

Abstract

A field effect transistor comprising a semiconductor layer projecting upward from a flat surface of a base, a gate electrode so arranged as to straddle the semiconductor layer extending from the top portion of the semiconductor layer along both opposite lateral surfaces thereof, a gate insulating film interposed between the gate electrode and each lateral surface of the semiconductor layer, a cap insulating layer formed on the top surface of the semiconductor layer under the gate electrode, and source/drain regions formed in a region of the semiconductor layer which is not covered with the gate electrode is characterized in that the cap insulating layer has a jut-out portion extending beyond the surface of the gate insulating film in the direction parallel to the flat surface of the base and perpendicular to the channel length direction connecting a pair of source/drain regions.

Description

明 細 書  Specification

電界効果型トランジスタおよびその製造方法  Field effect transistor and method of manufacturing the same

技術分野  Technical field

[0001] 本発明は、電界効果型トランジスタおよびその製造方法に関するものである。  The present invention relates to a field-effect transistor and a method for manufacturing the same.

背景技術  Background art

[0002] [構造]  [0002] [Structure]

電界効果型トランジスタの性能向上を目的に、突起した半導体領域の両側面にゲ ート電極を設け、半導体領域の両側面にチャネルを形成することを特徴とする FinF ETと呼ばれる電界効果型トランジスタが提案されている。その典型的構造を図 81、 図 82に示す。図 81は平面図、図 82(a)は図 81の A— A'断面における断面図、図 82 (b)は図 81の B-B'断面における断面図である。支持基板 1上に埋め込み絶縁膜 2 が設けられ、その上部に半導体層 3が設けられる。半導体層 3の側面にはゲート絶縁 膜 4を介してゲート電極 5が設けられる（図 82 (a) )。半導体層 3のうち、ゲート電極に 覆われなレ、部分は高濃度の第一導電型の不純物が導入され、ソース/ドレイン領域 6をなす。ゲート電極 5に覆われた半導体層 3はチャネル形成領域 7をなし、ゲート電 極に適当な電圧を印加することにより、その表面に第一導電型のキャリアが誘起され てチャネルが形成される。チャネル形成領域には一般には低濃度の第二導電型不 純物が導入されるか、あるいは導入されない。  For the purpose of improving the performance of a field effect transistor, a gate electrode is provided on both sides of a protruding semiconductor region, and a channel is formed on both sides of the semiconductor region. Proposed. Typical structures are shown in Figs. 81 is a plan view, FIG. 82 (a) is a cross-sectional view taken along the line AA ′ of FIG. 81, and FIG. 82 (b) is a cross-sectional view taken along the line BB ′ of FIG. A buried insulating film 2 is provided on a support substrate 1, and a semiconductor layer 3 is provided thereon. A gate electrode 5 is provided on a side surface of the semiconductor layer 3 via a gate insulating film 4 (FIG. 82 (a)). In the portion of the semiconductor layer 3 that is not covered with the gate electrode, a high-concentration impurity of the first conductivity type is introduced to form a source / drain region 6. The semiconductor layer 3 covered with the gate electrode 5 forms a channel forming region 7, and by applying an appropriate voltage to the gate electrode, carriers of the first conductivity type are induced on the surface to form a channel. Generally, a low concentration impurity of the second conductivity type is introduced or not introduced into the channel forming region.

[0003] なお、図 81の A— A'断面は、半導体層がゲートに覆われた位置において、二つの ソース Zドレイン領域を結ぶ方向（以下この方向をチャネル長方向と記す）に垂直な 面における断面を示し、図 81の B—B'断面はチャネル長方向の断面を示す。  [0003] Note that an AA 'cross section in FIG. 81 is a plane perpendicular to a direction connecting the two source Z drain regions (hereinafter, this direction is referred to as a channel length direction) at a position where the semiconductor layer is covered with the gate. 81, and a section taken along line BB ′ of FIG. 81 shows a section in the channel length direction.

[0004] FinFETにおいて、半導体層 3の上部に設けられた絶縁膜の厚さと半導体層 3の側 面に設けられた絶縁膜の厚さの差が小さい場合、トランジスタがオン状態になると、チ ャネル形成領域 7をなす半導体層 3の両側面と半導体層の上面にチャネルが形成さ れる。この構造はトライゲート構造と呼ばれる。トライゲート構造のトランジスタでは、半 導体層 3の上部に設けられた絶縁膜の厚さと半導体層 3の側面に設けられた絶縁膜 の厚さの関係が、典型的には一方の膜厚が他方の膜厚の 1一 5倍であり、より典型的 には一方の膜厚が他方の膜厚の 1一 2倍であり、最も理想的には両者の膜厚がほぼ 等しレ、。図 82 (a)及び図 82 (b)はトライゲート構造のトランジスタの典型的な構造であ る。 In a FinFET, when the difference between the thickness of the insulating film provided on the semiconductor layer 3 and the thickness of the insulating film provided on the side surface of the semiconductor layer 3 is small, when the transistor is turned on, Channels are formed on both side surfaces of the semiconductor layer 3 forming the formation region 7 and on the upper surface of the semiconductor layer. This structure is called a tri-gate structure. In a transistor having a tri-gate structure, the relationship between the thickness of the insulating film provided over the semiconductor layer 3 and the thickness of the insulating film provided on the side surface of the semiconductor layer 3 is typically that one of the thicknesses is the other. 1-5 times the film thickness of In this case, the thickness of one film is 112 times the thickness of the other film, and most ideally, the film thicknesses of both films are almost equal. FIG. 82 (a) and FIG. 82 (b) show a typical structure of a tri-gate transistor.

[0005] また、半導体層 3の上部にゲート絶縁膜よりも充分厚いキャップ絶縁層 8が設けられ る場合、典型的にはキャップ絶縁層 8の厚さがゲート絶縁膜の厚さの 5倍以上、より典 型的には 10倍以上の場合、半導体層 3の上部にはほとんどチャネルが形成されず、 トランジスタがオンした状態では、半導体層 3の両側面に形成されるチャネルが主に 電気伝導を担う。この構造はダブルゲート構造と呼ばれる。図 83 (a)及び図 83 (b)は ダブルゲート構造のトランジスタの典型的な断面形状を示す。それぞれ図 81の A— A ，断面、及び図 81の B—B'断面において描いたものである。  When a cap insulating layer 8 that is sufficiently thicker than the gate insulating film is provided on the semiconductor layer 3, typically, the thickness of the cap insulating layer 8 is at least five times the thickness of the gate insulating film. When the transistor is turned on, the channel formed on both sides of the semiconductor layer 3 is mainly electrically conductive when the transistor is on. Carry. This structure is called a double gate structure. FIGS. 83 (a) and 83 (b) show typical cross-sectional shapes of a transistor having a double gate structure. These are drawn on the section A-A in FIG. 81 and the section BB 'in FIG. 81, respectively.

[0006] また、半導体層 3の上部コーナー部 34 (図 82 (a)及び図 83 (a)に、上部コーナー 部 34の一方を破線で囲んで示す。）における電界の集中によるトランジスタ特性への 悪影響を防ぐ目的から、半導体層 3の上部コーナー部を丸めた構造も提案されてい る（特開 2002-118255号公報：特許文献 1の図 28及び関連記載)。これを図 85に 示す。このような構造は、例えば半導体層の上部コーナーを熱酸化することによって 形成する。なお、図 85は図 82 (a)と同じ位置における断面図を示す。  [0006] Further, the concentration of the electric field in the upper corner portion 34 of the semiconductor layer 3 (one of the upper corner portions 34 is surrounded by a broken line in FIGS. 82 (a) and 83 (a)) indicates the influence on the transistor characteristics. For the purpose of preventing adverse effects, a structure in which the upper corner portion of the semiconductor layer 3 is rounded has been proposed (Japanese Patent Application Laid-Open No. 2002-118255: FIG. 28 of Patent Document 1 and related description). This is shown in Figure 85. Such a structure is formed, for example, by thermally oxidizing the upper corner of the semiconductor layer. FIG. 85 shows a cross-sectional view at the same position as FIG. 82 (a).

[0007] なお、ダブルゲート構造とトライゲート構造との相違についての説明で用いた、キヤ ップ絶縁層 8の厚さと、ゲート絶縁膜 4の厚さとの比は、両者が同一の誘電率を持つ 場合を基準としている。両者の誘電率が異なる場合は、それぞれの膜厚をそれぞれ の誘電率で割り、得られたそれぞれの商に両者共通の定数 (例えば SiO膜の誘電  [0007] The ratio between the thickness of the cap insulating layer 8 and the thickness of the gate insulating film 4 used in the description of the difference between the double gate structure and the tri-gate structure is such that both have the same dielectric constant. It is based on having. If the two have different dielectric constants, the respective film thicknesses are divided by the respective dielectric constants.

2 率）をかけた積を換算膜厚として、上記比較を行えば良い。  The above comparison may be made by using the product of the two ratios) as the converted film thickness.

[0008] 一方、特開 2002—270850号公報（特許文献 2)には、位置不整合による寄生容量 の増大や寄生抵抗の変動に起因する動作性能の低下を抑えることを目的とし、ソー ス/ドレイン領域及びチャネル領域を持つ島状半導体結晶層と、そのチャネル領域 部の対向する両側面部にそれぞれゲート絶縁膜を介して設けられたゲート電極を有 する電界効果トランジスタが開示されている。そして、その一実施形態として短チヤネ ル効果をより一層抑制することを目的としてチャネル領域部分（両ゲート電極に挟ま れた部分）の島状半導体結晶層の幅を薄くした構成が記載され、結果として、その島 状層上部の絶縁膜が当該島状層側面に対して突起した形状となっている（特許文献[0008] On the other hand, Japanese Patent Application Laid-Open No. 2002-270850 (Patent Document 2) aims at suppressing an increase in parasitic capacitance due to position mismatch and a decrease in operating performance due to a change in parasitic resistance. There is disclosed a field effect transistor having an island-shaped semiconductor crystal layer having a drain region and a channel region, and a gate electrode provided on both sides of the channel region opposed to each other via a gate insulating film. Then, as one embodiment, a configuration in which the width of the island-shaped semiconductor crystal layer in the channel region portion (portion sandwiched between both gate electrodes) is reduced in order to further suppress the short channel effect is described. As the island The insulating film on the top of the island-shaped layer has a shape protruding from the side surface of the island-shaped layer (Patent Document

2の図 19及び関連記載）。し力しながら、この電界効果トランジスタにおいて、ゲート 電極はその島状層の両側に分離 ·絶縁して設けられてレ、る。 (Figure 19 in 2 and related descriptions). However, in this field effect transistor, the gate electrodes are provided separately and insulated on both sides of the island layer.

[0009] [従来技術の課題]  [0009] [Problems of the prior art]

nチャネルトランジスタを例に、従来の FinFETにおける課題を説明する。ここでは n チャネルトランジスタについて説明する力 S、 pチャネルトランジスタにおいては、極性を 逆にすれば（例えば、 nチャネルトランジスタにおける電位上昇を、 pチャネルトランジ スタにおいては電位低下と読みかえる。また、 nチャネルトランジスタにおけるしきい値 電圧の低下を、 pチャネルトランジスタにおいてはしきい値電圧の上昇と読みかえる。 )同様の議論が成り立つ。  The problems in the conventional FinFET will be described using an n-channel transistor as an example. Here, the force described for the n-channel transistor S, for a p-channel transistor, if the polarity is reversed (for example, a potential rise in an n-channel transistor can be read as a potential drop in a p-channel transistor. A decrease in the threshold voltage of a transistor can be read as an increase in the threshold voltage of a p-channel transistor.) The same argument holds.

[0010] (第一の課題）  [0010] (First issue)

図 81の A— A'断面において、半導体層 3の上端部の電位分布をシミュレーションし た結果を図 84 (a)、図 84 (b)に示す。図 84 (a)はトライゲート構造の場合であり、図 8 2 (a)の断面に対応するもの、図 84 (b)はダブルゲート構造の場合であり、図 83 (a) の断面に対応するものである。図中の等高線は真性半導体シリコンを基準にした等 電位線であり、半導体層の中央から外側に向って、—0. 4V、 -0. 2V、 0. 0V、 0. 2 V、 0. 4Vである。チャネル領域の不純物濃度は 8 X 1018cm— 3、ゲート電圧はゼロボ ルト、ゲート酸化膜厚は 2nmである。なお、電位は真性半導体シリコンを基準にして いるため、ゼロバイアスされている n+型シリコンの電位は 0· 56Vであり、ゼロバイアス されているゲートの電位は 0. 56Vである。なお、本明細書中に示す各素子構造につ いてのシミュレーション結果は、特筆しないかぎり上記と同一の条件で実施したもの である。 FIGS. 84 (a) and 84 (b) show the results of simulating the potential distribution at the upper end of the semiconductor layer 3 in the AA ′ section of FIG. 81. FIG. 84 (a) shows the case of the tri-gate structure, corresponding to the cross section of FIG. 82 (a), and FIG. 84 (b) shows the case of the double gate structure, corresponding to the cross section of FIG. 83 (a). Is what you do. The contour lines in the figure are equipotential lines based on intrinsic semiconductor silicon, and are -0.4 V, -0.2 V, 0.0 V, 0.2 V, 0.4 V from the center of the semiconductor layer to the outside. It is. The impurity concentration in the channel region is 8 × 10 18 cm— 3 , the gate voltage is zero volts, and the gate oxide film thickness is 2 nm. Since the potential is based on intrinsic semiconductor silicon, the potential of zero-biased n + -type silicon is 0.56 V, and the potential of the zero-biased gate is 0.56 V. The simulation results for each element structure shown in this specification were performed under the same conditions as described above, unless otherwise specified.

[0011] ダブルゲート構造、トライゲート構造のいずれにおいても、半導体層の上部コーナ 一部において等電位線が湾曲している。これは上部コーナー部では、ゲート電極か ら不純物イオンに向う電界が集中するために、半導体層の他の部分よりも電位が上 昇していることを示している。上部コーナー部の電位が上昇すると、上部コーナー部 にしきレ、値電圧が低レ、寄生トランジスタが形成される。寄生トランジスタが形成される と、図 86のようにサブスレツショルド電流が増加し、オフ電流が増加するという問題が 生じる。 [0011] In both the double gate structure and the tri-gate structure, equipotential lines are curved at a part of the upper corner of the semiconductor layer. This indicates that the electric potential is higher at the upper corner than at other portions of the semiconductor layer because the electric field from the gate electrode to the impurity ions is concentrated. When the potential at the upper corner rises, a threshold voltage, a low value voltage, and a parasitic transistor are formed at the upper corner. When a parasitic transistor is formed, the problem that the subthreshold current increases and the off current increases as shown in Figure 86 Occurs.

[0012] このような電界集中は、ゲート電極から不純物イオンに向う電界が原因であるので、 チャネル領域の不純物濃度が高い場合、典型的には 5 X 1017cm 3以上の場合に顕 著になる。 [0012] Such electric field concentration, the electric field toward the gate electrode to the impurity ions have caused, when there is a high impurity concentration of the channel region, typically remarkable in the case of 5 X 10 17 cm 3 or more Become.

[0013] またこのような電界集中は、半導体層の側面に位置するゲートからの電界、半導体 層上方のゲート電極からの電界、半導体層の上端よりも上方へ延在したゲート電極 側面からの電界が、半導体層上部コーナー部に集中することによって発生する（図 9 2 (a)、図 92 (b) )。なお、図 92 (a)、図 92 (b)はそれぞれ図 82 (a)、図 83 (a)の断面 において半導体層の上部に相当する位置における断面図である。なお、矢印（記号 [0013] Further, such electric field concentration is caused by an electric field from the gate located on the side surface of the semiconductor layer, an electric field from the gate electrode above the semiconductor layer, and an electric field from the side surface of the gate electrode extending above the upper end of the semiconductor layer. Are generated by concentrating at the upper corner of the semiconductor layer (FIGS. 92 (a) and 92 (b)). FIGS. 92 (a) and 92 (b) are cross-sectional views at positions corresponding to the upper portions of the semiconductor layers in the cross-sections of FIGS. 82 (a) and 83 (a), respectively. The arrow (symbol

46)は電界集中をひき起こすゲート電界を示す。 46) indicates a gate electric field that causes electric field concentration.

[0014] したがって、半導体層上部コーナー部における電位上昇を抑制し、寄生トランジス タの影響を縮小する技術が望まれる。 [0014] Therefore, there is a need for a technique that suppresses a rise in potential at the upper corner portion of the semiconductor layer and reduces the influence of a parasitic transistor.

[0015] (第二の課題）  [0015] (Second task)

また、図 85に示すように、半導体層 3の上部コーナー部 34を熱酸化等の丸め工程 を実施することによって丸みを帯びた形状に加工し、コーナー部の電界を緩和し、寄 生トランジスタを抑制する方法が知られている。  In addition, as shown in FIG. 85, the upper corner portion 34 of the semiconductor layer 3 is processed into a round shape by performing a rounding process such as thermal oxidation, so that the electric field at the corner portion is reduced, and the parasitic transistor is formed. Methods of suppression are known.

[0016] し力しこの場合、丸めたコーナー部 9では、本来チャネルが形成される半導体側面 または半導体上面のいずれとも面方位が異なる結晶面が露出する。一方、熱酸化に より形成されるゲート絶縁膜の厚さ、キャリア移動度及び界面準位密度は面方位に依 存する。しきい値電圧やドレイン電流などトランジスタの基本的な特性は、ゲート絶縁 膜の厚さ、キャリア移動度及び界面準位密度に強く依存するので、丸めたコーナー 部 9では半導体側面および半導体上面とは異なる特性を持った新たな寄生トランジ スタが出現し、 FinFETの特性が変化してしまう。特に、第一の課題で述べた寄生トラ ンジスタを強く抑制しょうとしてコーナー部の曲率半径を大きくすると、第二の課題は より顕著になる。 In this case, in the rounded corner portion 9, a crystal plane having a different plane orientation from the semiconductor side surface or the semiconductor upper surface where the channel is originally formed is exposed. On the other hand, the thickness, carrier mobility, and interface state density of the gate insulating film formed by thermal oxidation depend on the plane orientation. The basic characteristics of a transistor, such as the threshold voltage and the drain current, strongly depend on the thickness of the gate insulating film, carrier mobility, and interface state density. A new parasitic transistor with different characteristics will appear, and the characteristics of FinFET will change. In particular, if the radius of curvature of the corners is increased in order to strongly suppress the parasitic transistor described in the first problem, the second problem becomes more prominent.

[0017] したがって、コーナー部を丸めなくとも、あるいはコーナー部を丸めたとしてもコーナ 一部の曲率半径が小さい状態において、コーナー部の電位上昇を抑制し、寄生トラ ンジスタを抑制できる技術が望まれる。 発明の開示 [0017] Therefore, there is a need for a technique capable of suppressing a rise in the potential of the corner portion and a parasitic transistor in a state where the radius of curvature of the corner is small without rounding the corner portion or even when the corner portion is rounded. . Disclosure of the invention

[0018] 本発明の目的は、 FinFETの基体平面から突起した半導体層のコーナー部におい て寄生トランジスタが形成されることを防止して、素子特性が改善された FinFETを提 供することにある。  An object of the present invention is to provide a FinFET with improved element characteristics by preventing a parasitic transistor from being formed at a corner of a semiconductor layer protruding from the base plane of the FinFET.

[0019] 本発明によれば、下記の電界効果型トランジスタ及びその製造方法を提供すること ができる。  According to the present invention, the following field-effect transistor and a method for manufacturing the same can be provided.

[0020] (1)基体平面から上方に突起した半導体層と、この半導体層を跨ぐようにその上部 から相対する両側面上に延在するゲート電極と、このゲート電極と前記半導体層の 側面の間に介在するゲート絶縁膜と、前記半導体層上に設けられ前記ゲート電極下 に位置するキャップ絶縁層と、前記半導体層の前記ゲート電極に覆われない領域に 形成されたソース/ドレイン領域とを有し、  (1) A semiconductor layer protruding upward from the substrate plane, a gate electrode extending from the upper portion to oppose both sides so as to straddle the semiconductor layer, and a gate electrode and side surfaces of the semiconductor layer. A gate insulating film interposed therebetween, a cap insulating layer provided on the semiconductor layer and positioned below the gate electrode, and a source / drain region formed in a region of the semiconductor layer not covered by the gate electrode. Have

前記キャップ絶縁層は、前記基体平面に平行方向であって一対のソース/ドレイン 領域を結ぶチャネル長方向に垂直な方向へ、前記ゲート絶縁膜の表面から張り出し た張り出し部を有することを特徴とする電界効果型トランジスタ。  The cap insulating layer has an overhanging portion extending from the surface of the gate insulating film in a direction parallel to the plane of the base and perpendicular to a channel length direction connecting the pair of source / drain regions. Field-effect transistor.

[0021] (2)前記張り出し部は、前記ゲート絶縁膜の表面に対する張り出し幅が 5nm以上 である発明 1の電界効果型トランジスタ。  (2) The field-effect transistor according to Invention 1, wherein the overhang portion has an overhang width of 5 nm or more with respect to the surface of the gate insulating film.

[0022] (3)前記張り出し部は、前記ゲート絶縁膜の表面に対する張り出し幅が 5nm以上、  (3) The overhang portion has an overhang width with respect to the surface of the gate insulating film of 5 nm or more,

20nm以下である発明 1の電界効果型トランジスタ。  The field effect transistor according to Invention 1, which has a thickness of 20 nm or less.

[0023] (4)前記張り出し部は、前記ゲート絶縁膜の表面に対する張り出し幅が当該ゲート 絶縁膜の厚さの 2. 5倍以上である発明 1、 2又は 3の電界効果型トランジスタ。  (4) The field-effect transistor according to Invention 1, 2 or 3, wherein the overhang portion has an overhang width with respect to the surface of the gate insulating film that is at least 2.5 times the thickness of the gate insulating film.

[0024] (5)前記張り出し部は、前記ゲート絶縁膜の表面に対する張り出し幅が当該ゲート 絶縁膜の厚さの 2. 5倍以上、 10倍以下である発明 1、 2又は 3の電界効果型トランジ スタ。  (5) The field effect type of the invention 1, 2 or 3, wherein the overhang portion has an overhang width with respect to the surface of the gate insulating film of not less than 2.5 times and not more than 10 times the thickness of the gate insulating film. Transistor.

[0025] (6)前記張り出し部は、前記半導体層の基体平面に平行且つチャネル長方向に垂 直な方向の幅が最も広レ、位置におけるゲート絶縁膜表面に対して張り出してレ、る発 明 1一 5のいずれかの電界効果型トランジスタ。  (6) The overhang portion has the widest width in a direction parallel to the substrate plane of the semiconductor layer and perpendicular to the channel length direction, and overhangs the surface of the gate insulating film at the position. 1-15 Field-effect transistor according to any one of 5.

[0026] (7)発明 1一 6のいずれかの電界効果型トランジスタの製造方法であって、  (7) Invention A method for manufacturing a field-effect transistor according to any one of 1 to 6,

半導体層上にキャップ絶縁層を形成し、前記半導体層および前記キャップ絶縁層 をパターユングして基体平面から上方に突起した半導体層とその上にパターユング されたキャップ絶縁層を形成する工程と、 Forming a cap insulating layer on a semiconductor layer, the semiconductor layer and the cap insulating layer Patterning to form a semiconductor layer protruding upward from the plane of the base and a cap insulating layer patterned thereon.

前記キャップ絶縁層下の半導体層の側面が当該キャップ絶縁層の端部よりも内側 に後退するように、前記半導体層の側面をエッチングして当該半導体層を細らせる 工程と、  Etching the side surface of the semiconductor layer so as to narrow the semiconductor layer so that the side surface of the semiconductor layer below the cap insulating layer recedes inward from the end of the cap insulating layer;

前記半導体層の側面にゲート絶縁膜を形成する工程とを有する電界効果型トラン ジスタの製造方法。  Forming a gate insulating film on a side surface of the semiconductor layer.

[0027] (8)ゲート電極材料を堆積し、このゲート電極材料堆積膜をパターニングしてゲート 電極を形成する工程と、  (8) depositing a gate electrode material and patterning the gate electrode material deposited film to form a gate electrode;

前記半導体層に不純物を導入してソース/ドレイン領域を形成する工程をさらに有 する発明 7の電界効果型トランジスタの製造方法。  Invention 7. The method for manufacturing a field-effect transistor according to Invention 7, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.

[0028] (9)基体平面から上方に突起した半導体層と、この半導体層の両側面上に設けら れたゲート電極と、このゲート電極と前記半導体層の側面の間に介在するゲート絶縁 膜と、前記ゲート電極に覆われない領域に形成されたソース/ドレイン領域とを有し さらに、前記半導体層の上部でゲート電極の上端よりも低い位置に、 SiOよりも誘 電率が低い低誘電率領域を有することを特徴とする電界効果型トランジスタ。 (9) A semiconductor layer protruding upward from the plane of the base, a gate electrode provided on both side surfaces of the semiconductor layer, and a gate insulating film interposed between the gate electrode and a side surface of the semiconductor layer And a source / drain region formed in a region not covered by the gate electrode. Further, a low dielectric constant having a lower dielectric constant than SiO is provided at a position lower than the upper end of the gate electrode above the semiconductor layer. A field-effect transistor having a rate region.

[0029] (10)前記半導体層の上部に接して、 SiOよりも誘電率が低い低誘電率領域を有 する発明 9の電界効果型トランジスタ。 (10) The field-effect transistor according to Invention 9, which has a low dielectric constant region having a lower dielectric constant than SiO in contact with the upper part of the semiconductor layer.

[0030] (11)前記半導体層の上部に接して、 SiOまたは SiOよりも誘電率が高い保護絶 縁膜が設けられ、この保護絶縁膜の上に SiOよりも誘電率が低い低誘電率領域を有 する発明 9の電界効果型トランジスタ。 (11) In contact with the upper part of the semiconductor layer, SiO or a protective insulating film having a higher dielectric constant than SiO is provided, and a low dielectric constant region having a lower dielectric constant than SiO is provided on the protective insulating film. The field-effect transistor according to Invention 9, having the following.

[0031] (12)前記低誘電率領域が空洞よりなる発明 9一 11のいずれかの電界効果型トラン ジスタ。 (12) The field-effect transistor according to any one of the inventions 911, wherein the low dielectric constant region is a cavity.

[0032] (13)前記半導体層の下部に SiOよりも誘電率が低い低誘電率領域を有する発明  (13) The invention having a low dielectric constant region having a lower dielectric constant than SiO below the semiconductor layer.

9一 12のいずれかの電界効果型トランジスタ。  9-1 A field-effect transistor according to any one of 12.

[0033] (14)前記半導体層の下部に、 SiOよりも誘電率が低い低誘電率領域を有し、前記 ゲート電極の下部には、 SiOよりも誘電率が低い低誘電率領域を有しない発明 9一 12のレ、ずれかの電界効果型トランジスタ。 (14) A low dielectric constant region having a lower dielectric constant than SiO is provided below the semiconductor layer, and a low dielectric constant region having a lower dielectric constant than SiO is not provided below the gate electrode. Invention 91 Twelve field-effect transistors.

[0034] (15)前記半導体層の下部に設けられる前記低誘電率領域が空洞よりなる発明 13 又は 14の電界効果型トランジスタ。 (15) The field effect transistor according to Invention 13 or 14, wherein the low dielectric constant region provided below the semiconductor layer comprises a cavity.

[0035] (16)前記半導体層は、第 1の絶縁層上に、この第 1の絶縁層とは異なる材料から なる第 2の絶縁層を介して設けられ、 (16) The semiconductor layer is provided on the first insulating layer via a second insulating layer made of a material different from that of the first insulating layer,

前記ゲート電極は、第 1の絶縁層上に第 2の絶縁層を介さずに直接第 1の絶縁層 に接する部分を有する発明 9一 12のいずれかの電界効果型トランジスタ。  The field effect transistor according to any one of Inventions 9 to 12, wherein the gate electrode has a portion on the first insulating layer which is in direct contact with the first insulating layer without interposing the second insulating layer.

[0036] (17)第 2の絶縁層が SiOよりも誘電率が低い材料からなる発明 16の電界効果型ト ランジスタ。 (17) The field-effect transistor according to invention 16, wherein the second insulating layer is made of a material having a lower dielectric constant than SiO.

[0037] (18)第 2の絶縁層が空洞よりなる発明 16の電界効果型トランジスタ。  (18) The field-effect transistor according to Invention 16, wherein the second insulating layer comprises a cavity.

[0038] (19)前記キャップ絶縁層の少なくとも一部が SiOよりも誘電率が低い低誘電率材 料よりなる発明 1一 6のいずれかの電界効果型トランジスタ。  (19) The field effect transistor according to any one of Inventions 16 to 16, wherein at least a part of the cap insulating layer is made of a low dielectric constant material having a dielectric constant lower than that of SiO.

[0039] (20)前記キャップ絶縁層の少なくとも一部に空洞を有する発明 1一 6のいずれかの 電界効果型トランジスタ。 (20) The field-effect transistor according to any one of the inventions 16 to 16, wherein at least a part of the cap insulating layer has a cavity.

[0040] (21)前記半導体層と前記空洞の間に、 SiOまたは SiOよりも誘電率が高い保護 絶縁膜を有する発明 20の電界効果型トランジスタ。 (21) The field-effect transistor according to Invention 20, comprising a protective insulating film having a higher dielectric constant than SiO between the semiconductor layer and the cavity.

[0041] (22)前記半導体層の下部に、 SiOよりも誘電率が低い低誘電率領域を有する発 明 1一 6のいずれかの電界効果型トランジスタ。 (22) The field-effect transistor according to any one of the inventions 1 to 16, wherein a lower dielectric constant region having a lower dielectric constant than SiO is provided below the semiconductor layer.

[0042] (23)前記半導体層の下部に、 SiOよりも誘電率が低い低誘電率領域を有し、前記 ゲート電極の下部には、 SiOよりも誘電率が低い低誘電率領域を有しない発明 1一(23) A low dielectric constant region having a lower dielectric constant than SiO is provided below the semiconductor layer, and a low dielectric constant region having a lower dielectric constant than SiO is not provided below the gate electrode. Invention 11

6のレ、ずれかの電界効果型トランジスタ。 6, the field-effect transistor.

[0043] (24)前記低誘電率領域が空洞よりなる発明 22又は 23の電界効果型トランジスタ。 (24) The field effect transistor according to Invention 22 or 23, wherein the low dielectric constant region is formed of a cavity.

[0044] (25)発明 9の電界効果型トランジスタの製造方法であって、 (25) A method for manufacturing a field-effect transistor according to Invention 9, comprising:

半導体層上に Si〇よりも誘電率が低い材料を堆積して低誘電率膜を形成するェ 程と、  Depositing a material having a lower dielectric constant than Si〇 on the semiconductor layer to form a low dielectric constant film;

前記半導体層および前記低誘電率膜をパターニングして、基体平面から突起した 半導体層とその上にパターニングされた前記低誘電率膜からなる低誘電率領域を形 成する工程とを有する電界効果型トランジスタの製造方法。 [0045] (26)前記の突起した半導体層の側面にゲート絶縁膜を形成する工程と、 ゲート電極材料を堆積し、このゲート電極材料堆積膜をパターユングしてゲート電 極を形成する工程と、 Patterning the semiconductor layer and the low dielectric constant film to form a semiconductor layer protruding from a substrate plane and a low dielectric constant region composed of the low dielectric constant film patterned thereon. A method for manufacturing a transistor. (26) A step of forming a gate insulating film on the side surface of the protruding semiconductor layer, a step of depositing a gate electrode material, and a step of patterning the gate electrode material deposited film to form a gate electrode ,

前記半導体層に不純物を導入してソース/ドレイン領域を形成する工程をさらに有 する発明 25の電界効果型トランジスタの製造方法。  Invention 25. The method for manufacturing a field-effect transistor according to Invention 25, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.

[0046] (27)発明 9の電界効果型トランジスタの製造方法であって、 (27) A method for manufacturing a field-effect transistor according to Invention 9, comprising:

半導体層上にダミー層を形成する工程と、  Forming a dummy layer on the semiconductor layer;

前記半導体層および前記ダミー層をパターニングして、基体平面から突起した半 導体層とその上にパターユングされたダミー層を形成する工程と、  Patterning the semiconductor layer and the dummy layer to form a semiconductor layer protruding from the plane of the base and a dummy layer patterned on the semiconductor layer;

前記ダミー層を除去して前記半導体層上部に前記低誘電率領域として空洞を形成 する工程とを有する電界効果型トランジスタの製造方法。  Removing the dummy layer to form a cavity above the semiconductor layer as the low dielectric constant region.

[0047] (28)前記の突起した半導体層の側面にゲート絶縁膜を形成する工程と、 (28) forming a gate insulating film on the side surface of the protruding semiconductor layer;

ゲート電極材料を堆積し、このゲート電極材料堆積膜をパターユングしてゲート電 極を形成する工程と、  Depositing a gate electrode material and patterning the gate electrode material deposited film to form a gate electrode;

前記半導体層に不純物を導入してソース/ドレイン領域を形成する工程をさらに有 し、  Forming a source / drain region by introducing an impurity into the semiconductor layer;

ゲート電極の形成後に前記ダミー層を除去することにより前記空洞よりなる低誘電 率領域を形成することを特徴とする発明 27の電界効果型トランジスタの製造方法。  A method for manufacturing a field-effect transistor according to Invention 27, wherein the low-dielectric region formed of the cavity is formed by removing the dummy layer after the formation of the gate electrode.

[0048] (29)前記空洞を SiOよりも誘電率が低い材料で埋め戻す工程をさらに有する発明 (29) The invention further comprising a step of backfilling the cavity with a material having a lower dielectric constant than SiO.

2  2

27又は 28の電界効果型トランジスタの製造方法。  27. The method for manufacturing a field-effect transistor according to 27 or 28.

[0049] (30)前記空洞を多孔質の材料で埋め戻す工程をさらに有する発明 27又は 28の 電界効果型トランジスタの製造方法。 (30) The method for manufacturing a field effect transistor according to invention 27 or 28, further comprising a step of backfilling the cavity with a porous material.

[0050] (31)基体平面から上方に突起した半導体層と、この半導体層の両側面上に設けら れたゲート電極と、このゲート電極と前記半導体層の側面の間に介在するゲート絶縁 膜と、 (31) A semiconductor layer protruding upward from the substrate plane, a gate electrode provided on both side surfaces of the semiconductor layer, and a gate insulating film interposed between the gate electrode and a side surface of the semiconductor layer When,

前記半導体層の前記ゲート電極に覆われない領域に形成されたソース zドレイン領 域とを有し、  A source / drain region formed in a region of the semiconductor layer that is not covered by the gate electrode,

前記半導体層の上部の側面には、ゲート電極との間に、前記ゲート絶縁膜よりも厚 い端部絶縁体領域を有することを特徴とする電界効果型トランジスタ。 On the upper side surface of the semiconductor layer, between the gate electrode and the gate insulating film, A field-effect transistor having an end insulator region.

[0051] (32)基体平面から上方に突起した半導体層と、この半導体層の両側面上に設けら れたゲート電極と、このゲート電極と前記半導体層の側面の間に介在するゲート絶縁 膜と、前記半導体層の前記ゲート電極に覆われない領域に形成されたソース/ドレ イン領域とを有し、  (32) A semiconductor layer protruding upward from the base plane, a gate electrode provided on both side surfaces of the semiconductor layer, and a gate insulating film interposed between the gate electrode and a side surface of the semiconductor layer And a source / drain region formed in a region of the semiconductor layer that is not covered by the gate electrode,

前記半導体層は、一対のソース/ドレイン領域を結ぶチャネル長方向と垂直な面 内における基体平面に平行方向の半導体層の幅 Wがその下方部分の幅より小さレヽ 半導体層上部領域と、この半導体層上部領域の下方に位置し、当該半導体層の幅 Wが前記半導体層上部領域の幅より大きい半導体層下部領域とを有し、  The semiconductor layer includes a semiconductor layer upper region in which a width W of the semiconductor layer in a direction perpendicular to a channel length direction connecting the pair of source / drain regions and parallel to the substrate plane is smaller than a width of a lower portion thereof. A semiconductor layer lower region located below the layer upper region and having a width W of the semiconductor layer larger than the width of the semiconductor layer upper region;

前記半導体層上部領域は、当該半導体層の側面が前記半導体層下部領域にお ける半導体層の側面よりも後退し、この後退した側面と前記ゲート電極の間に、前記 ゲート絶縁膜より厚い端部絶縁体領域を有することを特徴とする電界効果型トランジ スタ。  In the semiconductor layer upper region, a side surface of the semiconductor layer is recessed from a side surface of the semiconductor layer in the semiconductor layer lower region, and an end portion thicker than the gate insulating film is provided between the recessed side surface and the gate electrode. A field-effect transistor having an insulator region.

[0052] (33)前記半導体層上部の幅 Wが一定である発明 32の電界効果型トランジスタ。  (33) The field effect transistor according to Invention 32, wherein the width W of the upper part of the semiconductor layer is constant.

[0053] (34)前記半導体層上部の幅 Wが連続的に変化し、これに応じて前記端部絶縁体 領域の厚みも連続的に変化している発明 32の電界効果型トランジスタ。  (34) The field-effect transistor according to Invention 32, wherein the width W of the upper portion of the semiconductor layer continuously changes, and accordingly, the thickness of the end insulator region also changes continuously.

[0054] (35)前記半導体層上部の幅 Wは、当該半導体層の上端へ向かうに従って一定の 勾配をもって徐々に小さくなり、これに応じて前記端部絶縁体領域の厚みが当該半 導体層の上端へ向力 に従って徐々に大きくなる発明 32の電界効果型トランジスタ。  (35) The width W of the upper portion of the semiconductor layer gradually decreases with a constant gradient toward the upper end of the semiconductor layer, and accordingly, the thickness of the end insulator region is reduced. Invention 32. The field-effect transistor of Invention 32, which gradually increases with the upward force.

[0055] (36)前記半導体層上部の幅 Wは、当該半導体層の上端へ向かうに従って、当該 半導体層の側面が曲率をもつように徐々に小さくなり、これに応じて前記端部絶縁体 領域の厚みが当該半導体層の上端に向力 に従って徐々に大きくなる発明 32の電 界効果型トランジスタ。  (36) The width W of the upper part of the semiconductor layer gradually decreases toward the upper end of the semiconductor layer so that the side surface of the semiconductor layer has a curvature, and accordingly, the end insulator region 32. The field-effect transistor according to Invention 32, wherein the thickness of the semiconductor layer gradually increases with the directional force toward the upper end of the semiconductor layer.

[0056] (37)前記半導体層の幅 Wが、当該半導体層の下端部から上端部にかけて一定で ある発明 31の電界効果型トランジスタ。  (37) The field-effect transistor according to Invention 31, wherein the width W of the semiconductor layer is constant from the lower end to the upper end of the semiconductor layer.

[0057] (38)基体平面から上方に突起した半導体層と、この半導体層の両側面上に設けら れたゲート電極と、このゲート電極と前記半導体層の側面の間に介在するゲート絶縁 膜と、前記半導体層の前記ゲート電極に覆われない領域に形成されたソース/ドレ イン領域とを有し、 (38) A semiconductor layer protruding upward from the plane of the base, a gate electrode provided on both side surfaces of the semiconductor layer, and a gate insulating film interposed between the gate electrode and a side surface of the semiconductor layer And a source / drain formed in a region of the semiconductor layer not covered by the gate electrode. And an in area,

前記半導体層は、一対のソース/ドレイン領域を結ぶチャネル長方向と垂直な面 内における基体平面に平行方向の半導体層の幅 Wがその下方部分の幅より小さい 半導体層上部領域と、この半導体層上部領域の下方に位置し、当該半導体層の幅 The semiconductor layer includes a semiconductor layer upper region in which a width W of the semiconductor layer in a direction perpendicular to a channel length direction connecting the pair of source / drain regions and parallel to the base plane is smaller than a width of a lower portion thereof. The width of the semiconductor layer is located below the upper region.

Wが前記半導体層上部領域の幅より大きい半導体層下部領域とを有し、 W has a semiconductor layer lower region larger than the width of the semiconductor layer upper region,

前記半導体層上部領域は、前記半導体層下部領域に接続する部分に当該半導 体層の幅 wが連続的に変化する遷移領域を有し、この遷移領域端部から当該半導 体層の上端にかけて幅 Wが一定であり、  The semiconductor layer upper region has a transition region in which the width w of the semiconductor layer continuously changes at a portion connected to the semiconductor layer lower region, and an upper end of the semiconductor layer from an end of the transition region. The width W is constant over

当該半導体層上部領域と前記ゲート電極の間には、前記ゲート絶縁膜より厚い端 部絶縁体領域を有することを特徴とする電界効果型トランジスタ。  A field effect transistor having an end insulator region thicker than the gate insulating film between the semiconductor layer upper region and the gate electrode.

[0058] (39)前記半導体層の上部にゲート絶縁膜よりも厚いキャップ絶縁層が設けられて レ、る発明 31— 38のいずれかの電界効果型トランジスタ。  (39) The field effect transistor according to any one of Inventions 31 to 38, wherein a cap insulating layer thicker than a gate insulating film is provided on the semiconductor layer.

[0059] (40)前記端部絶縁体領域が前記キャップ絶縁層とは異なる材料からなる発明 39 の電界効果型トランジスタ。 (40) The field effect transistor according to invention 39, wherein the end insulator region is made of a material different from that of the cap insulating layer.

[0060] (41)前記端部絶縁体領域が Si〇により構成される発明 31— 39のいずれかの電 界効果型トランジスタ。 (41) The field effect transistor according to any one of Inventions 31 to 39, wherein the end insulator region is made of Si.

[0061] (42)前記端部絶縁体領域の少なくとも一部が Si〇よりも誘電率が低い材料により 構成される発明 31— 39のいずれかの電界効果型トランジスタ。  (42) The field effect transistor according to any one of Inventions 31 to 39, wherein at least a part of the end insulator region is made of a material having a lower dielectric constant than Si.

[0062] (43)前記端部絶縁体領域の少なくとも一部が多孔質の材料により構成される発明 (43) The invention in which at least a part of the end insulator region is made of a porous material

31— 39のいずれかの電界効果型トランジスタ。  31-39 Any one of the field effect transistors.

[0063] (44)前記端部絶縁体領域の少なくとも一部が空洞により構成される発明 31— 39 のレ、ずれかの電界効果型トランジスタ。 (44) The field effect transistor according to invention 31-39, wherein at least a part of the end insulator region is formed by a cavity.

[0064] (45)発明 32の電界効果型トランジスタの製造方法であって、 (45) A method for manufacturing a field-effect transistor according to invention 32, comprising:

半導体層上に第 1絶縁膜を堆積し、この第 1絶縁膜および前記半導体層の上部を 所定の幅にパターユングする工程と、  Depositing a first insulating film on the semiconductor layer, and patterning the upper portion of the first insulating film and the semiconductor layer to a predetermined width;

第 2絶縁膜の堆積とエッチバックを行レ、、パターユングされた第 1絶縁膜の側面及 び半導体層の側面に、第 2絶縁膜からなる端部絶縁体領域を形成する工程と、 この端部絶縁体領域およびパターニングされた第 1絶縁膜をマスクに前記半導体 層をエッチングする工程と、 Depositing and etching back the second insulating film, and forming an end insulator region made of the second insulating film on the side surface of the patterned first insulating film and the side surface of the semiconductor layer; The semiconductor using the end insulator region and the patterned first insulating film as a mask; Etching the layer;

前記のエッチングにより露出した半導体層の側面にゲート絶縁膜を形成する工程と を有する電界効果型トランジスタの製造方法。  Forming a gate insulating film on the side surface of the semiconductor layer exposed by the etching.

[0065] (46)ゲート電極材料を堆積し、このゲート電極材料堆積膜をパターニングしてグー ト電極を形成する工程と、  (46) depositing a gate electrode material and patterning the gate electrode material deposited film to form a gate electrode;

前記半導体層に不純物を導入してソース/ドレイン領域を形成する工程をさらに有 する発明 45の電界効果型トランジスタの製造方法。  Invention 45. The method for manufacturing a field-effect transistor according to Invention 45, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.

[0066] (47)発明 32の電界効果型トランジスタの製造方法であって、 (47) A method for manufacturing a field-effect transistor according to invention 32, comprising:

半導体層上にキャップ絶縁層を堆積し、このキャップ絶縁層および前記半導体層 の上部を所定の幅にパターユングする工程と、  Depositing a cap insulating layer on the semiconductor layer, and patterning the cap insulating layer and the upper portion of the semiconductor layer to a predetermined width;

ダミー層の堆積とエッチバックを行レ、、パターユングされたキャップ絶縁層の側面及 び半導体層の側面に、前記ダミー層からなるコーナーダミー層を形成する工程と、 このコーナーダミー層およびパターニングされた前記キャップ絶縁層をマスクに前 記半導体層をエッチングする工程と、  Depositing and etching back a dummy layer, forming a corner dummy layer composed of the dummy layer on the side surface of the patterned cap insulating layer and the side surface of the semiconductor layer; Etching the semiconductor layer using the cap insulating layer as a mask,

前記のエッチングにより露出した半導体層の側面にゲート絶縁膜を形成する工程と 前記コーナーダミー層を除去して空洞よりなる端部絶縁体領域を形成する工程とを 有する電界効果型トランジスタの製造方法。  A method for manufacturing a field effect transistor, comprising: a step of forming a gate insulating film on a side surface of a semiconductor layer exposed by the etching; and a step of forming an end insulator region including a cavity by removing the corner dummy layer.

[0067] (48)発明 32の電界効果型トランジスタの製造方法であって、 (48) A method for manufacturing a field-effect transistor according to invention 32, comprising:

半導体層上にキャップ絶縁層を堆積し、このキャップ絶縁層および前記半導体層 の上部を所定の幅にパターニングする工程と、  Depositing a cap insulating layer on the semiconductor layer, and patterning the cap insulating layer and the upper portion of the semiconductor layer to a predetermined width;

第 1ダミー層の堆積とエッチバックを行レ、、パターユングされたキャップ絶縁層の側 面及び半導体層の側面に、第 1ダミー層からなる第 1コーナーダミー層を形成するェ 程と、  Depositing and etching back the first dummy layer, and forming a first corner dummy layer comprising the first dummy layer on the side surface of the patterned cap insulating layer and the side surface of the semiconductor layer;

第 2ダミー層の堆積とエッチバックを行い、第 1コーナダミー層の側面に、第 2ダミー 層からなる第 2コーナーダミー層を形成する工程と、  Depositing and etching back a second dummy layer to form a second corner dummy layer comprising a second dummy layer on a side surface of the first corner dummy layer;

第 1及び第 2コーナーダミー層並びにパターユングされた前記キャップ絶縁層をマ スクに前記半導体層をエッチングする工程と、 前記のエッチングにより露出した半導体層の側面にゲート絶縁膜を形成する工程と 第 1コーナーダミー層を除去して空洞よりなる端部絶縁体領域を形成する工程とを 有する電界効果型トランジスタの製造方法。 Etching the semiconductor layer using the first and second corner dummy layers and the patterned cap insulating layer as a mask; A method for manufacturing a field-effect transistor, comprising: a step of forming a gate insulating film on a side surface of a semiconductor layer exposed by the above-mentioned etching; and a step of forming an end insulator region comprising a cavity by removing a first corner dummy layer. .

[0068] (49)ゲート電極材料を堆積し、このゲート電極材料堆積膜をパターニングしてグー ト電極を形成する工程と、  (49) a step of depositing a gate electrode material and patterning the gate electrode material deposited film to form a gate electrode;

前記半導体層に不純物を導入してソース/ドレイン領域を形成する工程をさらに有 し、  Forming a source / drain region by introducing an impurity into the semiconductor layer;

ゲート電極の形成後に前記空洞よりなる端部絶縁体領域を形成することを特徴とす る発明 47又は 48の電界効果型トランジスタの製造方法。  The method for manufacturing a field-effect transistor according to invention 47 or 48, wherein an end insulator region comprising the cavity is formed after forming the gate electrode.

[0069] (50)前記コーナーダミー層を除去して空洞を形成した後、この空洞に Si〇よりも誘 電率が低レ、低誘電率材料を埋め戻し、この低誘電率材料よりなる端部絶縁体領域を 形成する工程をさらに有する発明 47又は 48の電界効果型トランジスタの製造方法。 (50) After removing the corner dummy layer to form a cavity, the cavity is filled with a low dielectric constant material having a lower dielectric constant than that of Si〇, and an end made of the low dielectric constant material is formed. 48. The method for manufacturing a field effect transistor according to invention 47 or 48, further comprising a step of forming a partial insulator region.

[0070] (51)発明 35の電界効果型トランジスタの製造方法であって、 (51) A method for manufacturing a field-effect transistor according to invention 35, comprising:

半導体層上に第 1絶縁膜を形成し、この第 1絶縁膜をパターニングする工程と、 パターニングされた第 1絶縁膜をマスクに、前記半導体層の上部を、その幅 Wが上 端に向力うに従って徐々に小さくなるテーパー形状を有するようにエッチングするェ 程と、  Forming a first insulating film on the semiconductor layer, and patterning the first insulating film; using the patterned first insulating film as a mask, the upper portion of the semiconductor layer has a width W directed toward the upper end; Etching so as to have a tapered shape that gradually becomes smaller as

第 2絶縁膜の堆積とエッチバックを行い、パターニングされた第 1絶縁膜の側面およ び半導体層のテーパー形状の側面に、第 2絶縁膜からなる端部絶縁体領域を形成 する工程と、  Depositing and etching back the second insulating film to form an end insulator region made of the second insulating film on the side surface of the patterned first insulating film and the tapered side surface of the semiconductor layer;

この端部絶縁体領域およびパターニングされた第 1絶縁膜をマスクに前記半導体 層をエッチングする工程と、  Etching the semiconductor layer using the end insulator region and the patterned first insulating film as a mask;

前記のエッチングにより露出した半導体層の側面にゲート絶縁膜を形成する工程と を有する電界効果型トランジスタの製造方法。  Forming a gate insulating film on the side surface of the semiconductor layer exposed by the etching.

[0071] (52)前記のパターニングされた第 1絶縁膜及びその側面部分の第 2絶縁膜を除去 して前記半導体層の上面を露出する工程をさらに有し、 (52) a step of exposing the upper surface of the semiconductor layer by removing the patterned first insulating film and the second insulating film on the side surface thereof,

前記のゲート酸化膜の形成工程においては、前記半導体層の側面にカ卩えて、露出 した上面にもゲート酸化膜を形成する発明 51の電界効果型トランジスタの製造方法 In the step of forming the gate oxide film, the side surfaces of the semiconductor layer are covered and exposed. Invention in which a gate oxide film is also formed on a patterned upper surface.

[0072] (53)ゲート電極材料を堆積し、このゲート電極材料堆積膜をパターニングしてゲー ト電極を形成する工程と、 (53) depositing a gate electrode material and patterning the gate electrode material deposited film to form a gate electrode;

前記半導体層に不純物を導入してソース/ドレイン領域を形成する工程をさらに有 する発明 51の電界効果型トランジスタの製造方法。  Invention 51. The method for manufacturing a field-effect transistor according to Invention 51, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.

[0073] (54)発明 36の電界効果型トランジスタの製造方法であって、 (54) A method for manufacturing a field-effect transistor according to Invention 36,

半導体層上に酸化剤透過性のキャップ絶縁層を形成する工程と、  Forming an oxidant-permeable cap insulating layer on the semiconductor layer;

前記キャップ絶縁層および前記半導体層をパターニングして、基体平面から突起し た半導体層とその上にパターユングされたキャップ絶縁層を形成する工程と、 前記半導体層と前記キャップ絶縁層との界面において、当該半導体層の側面が当 該キャップ絶縁層の端部よりも内側に後退するように酸化剤雰囲気中で当該半導体 層を酸化して、当該半導体層上部の幅 Wが当該半導体層上端に向力うに従って徐 々に小さくなる半導体層上部領域と、これに応じて厚みが徐々に大きくなる端部絶縁 領域を形成する工程とを有する電界効果型トランジスタの製造方法。  Patterning the cap insulating layer and the semiconductor layer to form a semiconductor layer protruding from the substrate plane and a cap insulating layer patterned thereon; and, at an interface between the semiconductor layer and the cap insulating layer. Then, the semiconductor layer is oxidized in an oxidant atmosphere such that the side surface of the semiconductor layer recedes inside the end of the cap insulating layer, and the width W of the upper portion of the semiconductor layer is directed toward the upper end of the semiconductor layer. A method of manufacturing a field effect transistor, comprising: a step of forming an upper semiconductor layer region that gradually becomes smaller as the force increases, and a step of forming an edge insulating region that gradually increases in thickness accordingly.

[0074] (55)前記半導体層の側面にゲート絶縁膜を形成する工程と、 (55) forming a gate insulating film on the side surface of the semiconductor layer;

ゲート電極材料を堆積し、このゲート電極材料堆積膜をパターユングしてゲート電 極を形成する工程と、  Depositing a gate electrode material and patterning the gate electrode material deposited film to form a gate electrode;

前記半導体層に不純物を導入してソース/ドレイン領域を形成する工程をさらに有 する発明 54の電界効果型トランジスタの製造方法。  Invention 54. The method for manufacturing a field-effect transistor according to Invention 54, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.

[0075] (56)前記キャップ絶縁層を除去して前記半導体層の上面を露出する工程と、 前記半導体層の上面および側面にゲート絶縁膜を形成する工程と、 (56) removing the cap insulating layer to expose an upper surface of the semiconductor layer; and forming a gate insulating film on the upper surface and side surfaces of the semiconductor layer;

ゲート電極材料を堆積し、このゲート電極材料堆積膜をパターニングしてゲート電 極を形成する工程と、  Depositing a gate electrode material and patterning the gate electrode material deposited film to form a gate electrode;

前記半導体層に不純物を導入してソース/ドレイン領域を形成する工程をさらに有 する発明 54の電界効果型トランジスタの製造方法。  Invention 54. The method for manufacturing a field-effect transistor according to Invention 54, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.

[0076] (57)基体平面から上方に突起した半導体層と、この半導体層の両側面上に設けら れたゲート電極と、このゲート電極と前記半導体層の側面の間に介在するゲート絶縁 膜と、前記半導体層の前記ゲート電極に覆われない領域に形成されたソース/ドレ イン領域とを有し、 (57) A semiconductor layer projecting upward from the plane of the base, a gate electrode provided on both side surfaces of the semiconductor layer, and a gate insulating layer interposed between the gate electrode and a side surface of the semiconductor layer. A film, and a source / drain region formed in a region of the semiconductor layer that is not covered by the gate electrode,

前記半導体層の上部の側面には、ゲート電極との間に、前記ゲート絶縁膜よりも厚 い第 1の端部絶縁体領域を有し、  On the upper side surface of the semiconductor layer, a first end insulator region thicker than the gate insulating film is provided between the semiconductor layer and the gate electrode;

前記半導体層の下部の側面には、ゲート電極との間に、前記ゲート絶縁膜よりも厚 い第 2の端部絶縁体領域を有することを特徴とする電界効果型トランジスタ。  A field-effect transistor having a second end insulator region, which is thicker than the gate insulating film, between a gate electrode and a lower side surface of the semiconductor layer.

[0077] (58)基体平面から上方に突起した半導体層と、この半導体層の両側面上に設けら れたゲート電極と、このゲート電極と前記半導体層の側面の間に介在するゲート絶縁 膜と、 (58) A semiconductor layer projecting upward from the plane of the base, a gate electrode provided on both side surfaces of the semiconductor layer, and a gate insulating film interposed between the gate electrode and a side surface of the semiconductor layer When,

前記半導体層の前記ゲート電極に覆われない領域に形成されたソース Zドレイン領 域とを有し、  A source Z drain region formed in a region of the semiconductor layer that is not covered by the gate electrode,

前記半導体層は、一対のソース/ドレイン領域を結ぶチャネル長方向と垂直な面 内における基体平面に平行方向の半導体層の幅 Wがその下方部分の幅より小さい 半導体層上部領域と、この半導体層上部領域の下方に位置し、当該半導体層の幅 Wが前記半導体層上部領域の幅より大きい半導体層主要部領域と、この半導体層 主要部領域の下方に位置し、当該半導体層の幅 Wが前記半導体層主要部領域の 幅より小さい半導体層下部領域を有し、  The semiconductor layer includes a semiconductor layer upper region in which a width W of the semiconductor layer in a direction perpendicular to a channel length direction connecting the pair of source / drain regions and parallel to the base plane is smaller than a width of a lower portion thereof. A semiconductor layer main portion region located below the upper region and having a width W of the semiconductor layer larger than the width of the semiconductor layer upper region; and a semiconductor layer main portion region located below the semiconductor layer main portion region and having a width W of the semiconductor layer. A semiconductor layer lower region smaller than a width of the semiconductor layer main portion region;

前記半導体層上部領域は、当該半導体層の側面が前記半導体層主要部領域に おける半導体層の側面よりも後退し、この後退した側面と前記ゲート電極の間に、前 記ゲート絶縁膜より厚い第 1端部絶縁体領域を有し、  In the semiconductor layer upper region, a side surface of the semiconductor layer is recessed from a side surface of the semiconductor layer in the semiconductor layer main portion region, and a portion of the semiconductor layer upper region which is thicker than the gate insulating film is provided between the recessed side surface and the gate electrode. Having one end insulator region,

前記半導体層下部領域は、当該半導体層の側面が前記半導体層主要部領域に おける半導体層の側面よりも後退し、この後退した側面と前記ゲート電極の間に、前 記ゲート絶縁膜より厚い第 2端部絶縁体領域を有することを特徴とする電界効果型ト ランジスタ。  In the semiconductor layer lower region, a side surface of the semiconductor layer is recessed from a side surface of the semiconductor layer in the semiconductor layer main portion region, and a gap between the recessed side surface and the gate electrode is thicker than the gate insulating film. A field-effect transistor having two end insulator regions.

[0078] (59)前記半導体層の上部にゲート絶縁膜よりも厚いキャップ絶縁層が設けられて レ、る発明 57又は 58の電界効果型トランジスタ。  (59) The field effect transistor according to invention 57 or 58, wherein a cap insulating layer thicker than a gate insulating film is provided on the semiconductor layer.

[0079] (60)発明 58の電界効果型トランジスタの製造方法であって、 (60) A method for manufacturing a field-effect transistor according to invention 58, comprising:

酸化剤透過性の第 1絶縁膜上に半導体層が設けられた基板を用意する工程と、 前記半導体層上に酸化剤透過性の第 2絶縁膜を形成する工程と、 前記第 2絶縁膜および前記半導体層をパターニングして、基体平面から突起した 半導体層とその上にパターニングされた第 2絶縁膜を形成する工程と、 Preparing a substrate provided with a semiconductor layer on the oxidant-permeable first insulating film; Forming an oxidant-permeable second insulating film on the semiconductor layer; patterning the second insulating film and the semiconductor layer to form a semiconductor layer protruding from a substrate plane and a second patterned semiconductor layer thereon; Forming an insulating film;

前記半導体層と第 2絶縁膜との界面および前記半導体層と第 1絶縁膜との界面に おいて、当該半導体層の側面が内側に後退するように酸化剤雰囲気中で当該半導 体層を酸化して、  At the interface between the semiconductor layer and the second insulating film and at the interface between the semiconductor layer and the first insulating film, the semiconductor layer is placed in an oxidizing atmosphere so that the side surface of the semiconductor layer recedes inward. Oxidize,

当該半導体層上部の幅 Wが当該半導体層上端に向力、うに従って徐々に小さくなる 半導体層上部領域と、これに応じて厚みが徐々に大きくなる第 1端部絶縁領域と、 当該半導体層下部の幅 Wが当該半導体層下端に向力、うに従って徐々に小さくなる 半導体層下部領域と、これに応じて厚みが徐々に大きくなる第 2端部絶縁領域を形 成する工程を有する電界効果型トランジスタの製造方法。  A semiconductor layer upper region in which the width W of the upper portion of the semiconductor layer gradually decreases toward the upper end of the semiconductor layer, a first end insulating region in which the thickness gradually increases accordingly, and a lower portion of the semiconductor layer. A field effect type having a step of forming a lower region of the semiconductor layer in which the width W of the semiconductor layer gradually decreases as it moves toward the lower end of the semiconductor layer, and a second end insulating region in which the thickness gradually increases accordingly. A method for manufacturing a transistor.

[0080] (61)前記第 2絶縁膜を除去して前記半導体層の上面を露出する工程と、 (61) removing the second insulating film to expose an upper surface of the semiconductor layer;

前記半導体層の上面および側面にゲート絶縁膜を形成する工程と、  Forming a gate insulating film on the top and side surfaces of the semiconductor layer;

ゲート電極材料を堆積し、このゲート電極材料堆積膜をパターユングしてゲート電 極を形成する工程と、  Depositing a gate electrode material and patterning the gate electrode material deposited film to form a gate electrode;

前記半導体層に不純物を導入してソース/ドレイン領域を形成する工程をさらに有 する発明 60の電界効果型トランジスタの製造方法。  Invention 60. The method for manufacturing a field-effect transistor according to Invention 60, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer.

[0081] (62)前記の突起した半導体の下には支持基板を有し、当該半導体層はこの支持 基板と一体に接続している発明 1一 6、 9一 24、 31— 44のいずれかの電界効果型ト ランジスタ。 (62) Any one of inventions 1, 6, 9-12, 31-44, wherein a support substrate is provided below the protruding semiconductor, and the semiconductor layer is integrally connected to the support substrate. Field-effect transistor.

[0082] (63)前記の突起した半導体の下には支持基板を有し、当該半導体層はこの支持 基板上に埋め込み絶縁膜を介して設けられている発明 1一 6、 9一 24、 31— 44、 57 一 59のいずれかの電界効果型トランジスタ。  (63) Inventions 1, 6, 9, 24, 31 wherein a supporting substrate is provided below the protruding semiconductor, and the semiconductor layer is provided on the supporting substrate via a buried insulating film. — Field effect transistor of any of 44, 57-59.

[0083] (64)前記張り出し部は、前記ゲート絶縁膜の表面に対する張り出し幅が 2nm以上 である発明 1の電界効果型トランジスタ。 (64) The field effect transistor according to Invention 1, wherein the overhang portion has an overhang width of 2 nm or more with respect to the surface of the gate insulating film.

[0084] (65)前記張り出し部は、前記ゲート絶縁膜の表面に対する張り出し幅が 20nm以 下である発明 1の電界効果型トランジスタ。 (65) The field effect transistor according to Invention 1, wherein the overhang portion has an overhang width of 20 nm or less with respect to the surface of the gate insulating film.

[0085] (66)前記張り出し部は、前記ゲート絶縁膜の表面に対する張り出し幅が当該グー ト絶縁膜の厚さの 10倍以下である発明 1、 2又は 3の電界効果型トランジスタ。 (66) The overhang portion has an overhang width relative to the surface of the gate insulating film. The field effect transistor according to Invention 1, 2 or 3, wherein the thickness of the insulating film is 10 times or less.

[0086] (67)基体平面から上方に突起した半導体層と、この半導体層の両側面上に設けら れたゲート電極と、このゲート電極と前記半導体層の側面の間に介在するゲート絶縁 膜と、前記ゲート電極に覆われなレ、領域に形成されたソース Zドレイン領域とを有し 前記半導体層は、第 1の絶縁層上に、この第 1の絶縁層とは異なる材料からなる第(67) A semiconductor layer projecting upward from the base plane, a gate electrode provided on both side surfaces of the semiconductor layer, and a gate insulating film interposed between the gate electrode and a side surface of the semiconductor layer And a source Z drain region formed in a region that is not covered with the gate electrode.The semiconductor layer is formed on a first insulating layer and is made of a material different from that of the first insulating layer.

2の絶縁層を介して設けられ、 2, provided through an insulating layer,

前記ゲート電極は、第 1の絶縁層上に第 2の絶縁層を介さずに直接第 1の絶縁層 に接する部分を有する電界効果型トランジスタ。  A field-effect transistor in which the gate electrode has a portion on the first insulating layer and directly in contact with the first insulating layer without through a second insulating layer.

[0087] なお、本発明においては、ゲート電極は、製造の容易さ、或いはトライゲート構造を 形成できる等の点から、半導体層を跨ぐようにその上部から相対する両側面上に延 在する形状をもつことが好ましレ、。 In the present invention, the gate electrode is formed so as to extend over the semiconductor layer and to extend on both sides facing each other so as to straddle the semiconductor layer from the viewpoint of ease of manufacture, formation of a tri-gate structure, and the like. It is preferable to have

[0088] なお、本発明において「基体表面」とは基板に平行 (水平)な任意の平面を意味す る。 [0088] In the present invention, "substrate surface" means any plane parallel (horizontal) to the substrate.

[0089] 本発明によれば、半導体層の側面にチャネルが形成される電界効果型トランジスタ において、半導体層上部コーナーにおける電位上昇を低下させ、寄生トランジスタの 影響を縮小することができる。  According to the present invention, in a field-effect transistor in which a channel is formed on a side surface of a semiconductor layer, an increase in potential at an upper corner of the semiconductor layer can be reduced, and the influence of a parasitic transistor can be reduced.

[0090] 本発明によれば、コーナー部を丸めなくとも、コーナー部の電位上昇を抑制し、寄 生トランジスタを抑制できる。あるいは、本発明によれば、コーナー部の電位上昇を 抑制するのに必要なコーナー部の丸め量を少なくすることができる。  According to the present invention, it is possible to suppress an increase in the potential of the corner portion and suppress the parasitic transistor without rounding the corner portion. Alternatively, according to the present invention, it is possible to reduce the amount of corner rounding required to suppress the rise in the potential of the corner.

[0091] 本発明によれば、キャップ絶縁層あるいは埋め込み絶縁膜を介してドレイン領域か らの電界がチャネル部に侵入し、短チャネルトランジスタの特性を劣化させることを防 ぐことができる。  According to the present invention, it is possible to prevent the electric field from the drain region from invading the channel portion via the cap insulating layer or the buried insulating film, thereby preventing the characteristics of the short-channel transistor from deteriorating.

[0092] 本発明によれば、上記各効果を得られるトランジスタを製造する方法を提供すること ができる。  [0092] According to the present invention, it is possible to provide a method for manufacturing a transistor that can obtain the above-described effects.

図面の簡単な説明  Brief Description of Drawings

[0093] [図 1]第一の実施形態を説明する断面図  [FIG. 1] A cross-sectional view illustrating a first embodiment.

[図 2]第一の実施形態を説明する断面図 [図 3]第一の実施形態を説明する断面図及び平面図FIG. 2 is a cross-sectional view illustrating a first embodiment. FIG. 3 is a cross-sectional view and a plan view illustrating a first embodiment.

[図 4]第一の実施形態を説明する断面図及び平面図FIG. 4 is a cross-sectional view and a plan view illustrating a first embodiment.

[図 5]第一の実施形態を説明する断面図及び平面図FIG. 5 is a cross-sectional view and a plan view illustrating a first embodiment.

[図 6]第一の実施形態を説明する断面図 FIG. 6 is a cross-sectional view illustrating a first embodiment.

[図 7]第一の実施形態を説明する断面図  FIG. 7 is a cross-sectional view illustrating a first embodiment.

[図 8]第一の実施形態を説明する平面図  FIG. 8 is a plan view illustrating a first embodiment.

[図 9]第一の実施形態の構造及び効果の説明図 FIG. 9 is an explanatory view of the structure and effects of the first embodiment.

[図 10]第二の実施形態を説明する断面図 FIG. 10 is a sectional view illustrating a second embodiment.

[図 11]第二の実施形態を説明する断面図  FIG. 11 is a cross-sectional view illustrating a second embodiment.

[図 12]第二の実施形態を説明する断面図  FIG. 12 is a sectional view illustrating a second embodiment.

[図 13]第二の実施形態を説明する断面図  FIG. 13 is a sectional view illustrating a second embodiment.

[図 14]第二の実施形態を説明する断面図  FIG. 14 is a sectional view illustrating a second embodiment.

[図 15]第二の実施形態を説明する断面図  FIG. 15 is a sectional view illustrating a second embodiment.

[図 16]第二の実施形態を説明する断面図  FIG. 16 is a sectional view illustrating a second embodiment.

[図 17]第二の実施形態を説明する断面図  FIG. 17 is a sectional view illustrating a second embodiment.

[図 18]第二の実施形態を説明する断面図及び平面図 FIG. 18 is a cross-sectional view and a plan view illustrating a second embodiment.

[図 19]第二の実施形態を説明する断面図及び平面図FIG. 19 is a cross-sectional view and a plan view illustrating a second embodiment.

[図 20]第二の実施形態を説明する断面図 FIG. 20 is a sectional view illustrating a second embodiment.

[図 21]第二の実施形態を説明する平面図  FIG. 21 is a plan view illustrating a second embodiment.

[図 22]第二の実施形態を説明する断面図  FIG. 22 is a cross-sectional view illustrating a second embodiment.

[図 23]第二の実施形態を説明する断面図及び平面図 FIG. 23 is a cross-sectional view and a plan view illustrating a second embodiment.

[図 24]第二の実施形態を説明する断面図及び平面図FIG. 24 is a cross-sectional view and a plan view illustrating a second embodiment.

[図 25]第二の実施形態を説明する断面図及び平面図FIG. 25 is a cross-sectional view and a plan view illustrating a second embodiment.

[図 26]第二の実施形態を説明する断面図 FIG. 26 is a sectional view illustrating a second embodiment.

[図 27]第二の実施形態を説明する平面図  FIG. 27 is a plan view illustrating a second embodiment.

[図 28]第二の実施形態を説明する断面図  FIG. 28 is a sectional view illustrating a second embodiment.

[図 29]第二の実施形態を説明する断面図  FIG. 29 is a sectional view illustrating a second embodiment.

[図 30]第二の実施形態を説明する断面図及び平面図 [図 31]第二の実施形態を説明する断面図及び平面図 FIG. 30 is a cross-sectional view and a plan view illustrating a second embodiment. FIG. 31 is a cross-sectional view and a plan view illustrating a second embodiment.

[図 32]第二の実施形態を説明する断面図  FIG. 32 is a cross-sectional view illustrating a second embodiment.

[図 33]第二の実施形態を説明する断面図  FIG. 33 is a sectional view illustrating a second embodiment.

[図 34]第二の実施形態を説明する断面図  FIG. 34 is a sectional view illustrating a second embodiment.

[図 35]第二の実施形態を説明する断面図  FIG. 35 is a cross-sectional view illustrating a second embodiment.

[図 36]第二の実施形態を説明する平面図  FIG. 36 is a plan view illustrating a second embodiment.

[図 37]第二の実施形態を説明する断面図  FIG. 37 is a cross-sectional view illustrating a second embodiment.

[図 38]第二の実施形態の効果を説明する平面図  FIG. 38 is a plan view illustrating the effect of the second embodiment.

[図 39]第二の実施形態の効果の説明図  [FIG. 39] An explanatory diagram of an effect of the second embodiment.

[図 40]第三の実施形態を説明する断面図及び平面図  FIG. 40 is a cross-sectional view and a plan view illustrating a third embodiment.

[図 41]第三の実施形態を説明する断面図  FIG. 41 is a sectional view illustrating a third embodiment.

[図 42]第三の実施形態を説明する断面図  FIG. 42 is a sectional view illustrating a third embodiment.

[図 43]第三の実施形態を説明する断面図  FIG. 43 is a cross-sectional view illustrating a third embodiment.

[図 44]第三の実施形態を説明する断面図  FIG. 44 is a cross-sectional view illustrating a third embodiment.

[図 45]第三の実施形態を説明する断面図  FIG. 45 is a cross-sectional view illustrating a third embodiment.

[図 46]第三の実施形態を説明する断面図  FIG. 46 is a sectional view illustrating a third embodiment.

[図 47]第三の実施形態を説明する断面図及び平面図  FIG. 47 is a cross-sectional view and a plan view illustrating a third embodiment.

[図 48]第三の実施形態を説明する断面図及び平面図  FIG. 48 is a cross-sectional view and a plan view illustrating a third embodiment.

[図 49]第三の実施形態を説明する断面図及び平面図  FIG. 49 is a cross-sectional view and a plan view illustrating a third embodiment.

[図 50]第三の実施形態を説明する断面図及び平面図  FIG. 50 is a cross-sectional view and a plan view illustrating a third embodiment.

[図 51]第三の実施形態を説明する断面図  FIG. 51 is a cross-sectional view illustrating a third embodiment.

[図 52]第三の実施形態を説明する断面図  FIG. 52 is a sectional view illustrating a third embodiment.

[図 53]第三の実施形態の効果の説明図  FIG. 53 is an explanatory diagram of an effect of the third embodiment.

[図 54]第二の実施形態及び第三の実施形態の効果の説明図 FIG. 54 is an explanatory diagram of effects of the second embodiment and the third embodiment

[図 55]第三の実施形態を説明する断面図 FIG. 55 is a cross-sectional view illustrating a third embodiment.

[図 56]第四の実施形態を説明する断面図  FIG. 56 is a cross-sectional view explaining a fourth embodiment.

[図 57]第四の実施形態を説明する断面図  FIG. 57 is a cross-sectional view illustrating a fourth embodiment.

[図 58]第四の実施形態を説明する断面図 [図 59]第四の実施形態を説明する断面図 FIG. 58 is a cross-sectional view illustrating a fourth embodiment. FIG. 59 is a cross-sectional view explaining a fourth embodiment.

[図 60]第四の実施形態を説明する断面図  FIG. 60 is a sectional view illustrating a fourth embodiment.

[図 61]第四の実施形態を説明する断面図及び平面図 FIG. 61 is a cross-sectional view and a plan view illustrating a fourth embodiment.

[図 62]第四の実施形態を説明する断面図及び平面図FIG. 62 is a cross-sectional view and a plan view illustrating a fourth embodiment.

[図 63]第四の実施形態を説明する断面図及び平面図FIG. 63 is a cross-sectional view and a plan view illustrating a fourth embodiment.

[図 64]第四の実施形態を説明する断面図 FIG. 64 is a cross-sectional view illustrating a fourth embodiment.

[図 65]第四の実施形態を説明する平面図  FIG. 65 is a plan view illustrating a fourth embodiment.

[図 66]第四の実施形態を説明する断面図  FIG. 66 is a sectional view illustrating a fourth embodiment.

[図 67]第五の実施形態を説明する断面図  FIG. 67 is a sectional view illustrating a fifth embodiment.

[図 68]第五の実施形態を説明する断面図  FIG. 68 is a sectional view illustrating a fifth embodiment.

[図 69]第五の実施形態を説明する断面図  [FIG. 69] A cross-sectional view illustrating a fifth embodiment.

園 70]好ましくない形態の断面図 Garden 70] Cross section of unfavorable form

[図 71]第六の形態を説明する断面図  FIG. 71 is a cross-sectional view illustrating a sixth embodiment.

[図 72]第六の実施形態を説明する断面図  [FIG. 72] A cross-sectional view illustrating a sixth embodiment.

[図 73]第六の実施形態を説明する断面図  FIG. 73 is a cross-sectional view illustrating a sixth embodiment.

[図 74]第六の実施形態を説明する断面図  FIG. 74 is a cross-sectional view illustrating a sixth embodiment.

[図 75]発明の他の実施形態を説明する平面図  FIG. 75 is a plan view illustrating another embodiment of the present invention.

[図 76]発明の他の実施形態を説明する平面図  FIG. 76 is a plan view illustrating another embodiment of the present invention.

[図 77]発明の他の実施形態を説明する平面図  FIG. 77 is a plan view illustrating another embodiment of the present invention.

[図 78]発明の他の実施形態を説明する平面図  FIG. 78 is a plan view illustrating another embodiment of the present invention.

[図 79]発明の他の実施形態を説明する平面図  FIG. 79 is a plan view illustrating another embodiment of the present invention.

[図 80]発明の実施形態を説明する平面図  FIG. 80 is a plan view illustrating an embodiment of the present invention.

園 81]従来の技術を説明する平面図 Garden 81] Plan view explaining conventional technology

園 82]従来の技術を説明する断面図 Garden 82] Cross-sectional view explaining conventional technology

園 83]従来の技術を説明する断面図 Garden 83] Cross-sectional view explaining conventional technology

園 84]従来の技術における課題の説明図 Garden 84] Illustration of problems in conventional technology

園 85]従来の技術を説明する断面図 Garden 85] Cross-sectional view explaining conventional technology

園 86]従来の技術における課題の説明図 [図 87]発明の他の実施形態を説明する断面図 Garden 86] Illustration of problems in conventional technology FIG. 87 is a sectional view for explaining another embodiment of the present invention.

[図 88]発明の他の実施形態を説明する断面図  FIG. 88 is a sectional view illustrating another embodiment of the present invention.

[図 89]発明の他の実施形態を説明する断面図  FIG. 89 is a sectional view illustrating another embodiment of the present invention.

[図 90]発明の他の実施形態を説明する断面図  FIG. 90 is a cross-sectional view illustrating another embodiment of the present invention.

[図 91]発明の他の実施形態を説明する断面図  FIG. 91 is a sectional view illustrating another embodiment of the present invention.

[図 92]従来の技術の問題点を説明する断面図  [FIG. 92] A cross-sectional view explaining a problem of a conventional technique.

[図 93]従来の技術の問題点を説明する断面図  [FIG. 93] A cross-sectional view illustrating a problem of the conventional technique.

[図 94]発明の他の実施形態を説明する断面図  FIG. 94 is a sectional view illustrating another embodiment of the present invention.

[図 95]発明の他の実施形態を説明する断面図  FIG. 95 is a cross-sectional view illustrating another embodiment of the invention.

[図 96]発明の他の実施形態を説明する断面図  FIG. 96 is a cross-sectional view illustrating another embodiment of the present invention.

[図 97]発明の他の実施形態を説明する断面図  FIG. 97 is a cross-sectional view illustrating another embodiment of the present invention.

[図 98]発明の他の実施形態を説明する断面図  FIG. 98 is a cross-sectional view illustrating another embodiment of the present invention.

[図 99]発明の他の実施形態を説明する断面図  FIG. 99 is a cross-sectional view illustrating another embodiment of the present invention.

[図 100]第一の実施形態の効果の説明図  [FIG. 100] An explanatory view of an effect of the first embodiment.

発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION

[0094] (第一の実施形態） [0094] (First embodiment)

[構造]  [Construction]

基板から上方に突起した半導体層 3上にキャップ絶縁層 8が設けられ、半導体層 3 とキャップ絶縁層 8を覆ってゲート電極 5が形成されるダブルゲート構造の FinFETに おいて、キャップ絶縁層 8を水平方向（半導体層 3が基板から突起する方向に対して 垂直な面内で、チャネル長方向に垂直な方向。図 1の断面においてはキャップ絶縁 層 8と半導体層 3が接触する面の延長方向。）に、ゲート電極 5に向かって突起させ、 キャップ絶縁層 8にゲート絶縁膜 4の表面から張り出した張り出し部を持たせる。その 例を図 1に示す。記号 Wextはキャップ絶縁層 8がゲート絶縁膜 4の表面から前記の 水平方向に突起した幅、すなわち張出し幅を示す。なお、「チャネル長方向」とは、一 対のソース/ドレイン領域を結ぶ方向をレ、う。  A cap insulating layer 8 is provided on the semiconductor layer 3 protruding upward from the substrate, and the cap insulating layer 8 is provided in the double-gate FinFET in which the gate electrode 5 is formed so as to cover the semiconductor layer 3 and the cap insulating layer 8. In the horizontal direction (in the plane perpendicular to the direction in which the semiconductor layer 3 protrudes from the substrate, in the direction perpendicular to the channel length direction. In the cross section in Figure 1, the extension of the surface where the cap insulating layer 8 contacts the semiconductor layer 3 Direction), and projecting toward the gate electrode 5 so that the cap insulating layer 8 has a protruding portion protruding from the surface of the gate insulating film 4. Figure 1 shows an example. The symbol Wext indicates the width of the cap insulating layer 8 projecting from the surface of the gate insulating film 4 in the horizontal direction, that is, the overhang width. Note that the “channel length direction” refers to a direction connecting a pair of source / drain regions.

[0095] 半導体層の側面にはゲート絶縁膜 4を介してゲート電極 5が設けられる。ゲート電極 The gate electrode 5 is provided on the side surface of the semiconductor layer with the gate insulating film 4 interposed therebetween. Gate electrode

5は適当な寸法にパターニングされており、ゲート電極に覆われない位置の半導体 層には第一導電型の不純物が高濃度に導入されたソース/ドレイン領域 6が形成さ れる。ゲート電極 5に覆われた半導体層であるチャネル形成領域 7には、ゲート電極 5に適当な電圧を印加することにより第一導電型のキャリアよりなるチャネルが形成さ れる。ゲート電極 5、ソース/ドレイン領域 6にはコンタクト領域を介して配線が接続さ れる。 5 is patterned to an appropriate size, and the semiconductor at the position not covered by the gate electrode The source / drain region 6 into which the impurity of the first conductivity type is introduced at a high concentration is formed in the layer. In the channel forming region 7, which is a semiconductor layer covered by the gate electrode 5, a channel made of the first conductivity type carrier is formed by applying an appropriate voltage to the gate electrode 5. Wiring is connected to the gate electrode 5 and the source / drain region 6 via a contact region.

[0096] なお、図 1 (a)は図 1 (b)の A— A'断面における断面図であり、従来例を示す図 81 の A— A'断面に相当する位置における断面図である。なお、図 1 (b)の平面図にお いては本来ソース Zドレイン領域 6がキャップ絶縁層 8に覆われており、ソース/ドレ イン領域 6は見えなレ、が、構造を解力 やすくするためにソース Zドレイン領域 6の位 置を透視的に示している。  FIG. 1 (a) is a cross-sectional view taken along the line AA ′ of FIG. 1 (b), and is a cross-sectional view at a position corresponding to the cross section AA ′ of FIG. 81 showing a conventional example. In the plan view of FIG. 1 (b), the source / drain region 6 is originally covered with the cap insulating layer 8, and the source / drain region 6 is not visible, but the structure is easily resolved. For this reason, the position of the source Z drain region 6 is shown transparently.

[0097] なお、本明細書においてはソース Zドレイン領域の導電型を第一導電型、ソース Z ドレイン領域とは異なる導電型を第二導電型と呼ぶ。  [0097] In this specification, the conductivity type of the source Z drain region is referred to as a first conductivity type, and a conductivity type different from the source Z drain region is referred to as a second conductivity type.

[0098] [製造方法]  [0098] [Manufacturing method]

(第一の実施形態の第一の製造方法）  (First Manufacturing Method of First Embodiment)

製造方法の一例を図 2から図 8を参照して説明する。なお、図 3 (a)、図 4 (a)、図 5 ( a)、図 7 (a)はそれぞれ平面図である図 3 (c)、図 4 (c)、図 5 (c)、図 8における A— A' 断面の断面図であり、図 3 (b)、図 4 (b)、図 5 (b)、図 7 (b)はそれぞれ平面図である 図 3 (c)、図 4 (c)、図 5 (c)、図 8における B-B'断面の断面図である。また、図 6 (a) 及び図 6 (b)は図 5 (c)の D-D'断面における形状を示す断面図である。また、本実 施形態を説明する各図面の A— A'断面の位置は従来例を示す図 81の A— A'断面 の位置に、本実施形態を説明する各図面の B - B'断面の位置は従来例を示す図 81 の B—B'断面の位置にそれぞれ相当する。  An example of the manufacturing method will be described with reference to FIGS. 3 (a), 4 (a), 5 (a), and 7 (a) are plan views of FIGS. 3 (c), 4 (c), 5 (c), and 5 (a), respectively. FIG. 3 is a cross-sectional view taken along line A—A ′ in FIG. 8, and FIGS. 3 (b), 4 (b), 5 (b), and 7 (b) are plan views, respectively. FIGS. 3 (c), 4 FIG. 9C is a cross-sectional view taken along the line BB ′ in FIG. 5C, FIG. 5C, and FIG. FIGS. 6 (a) and 6 (b) are cross-sectional views each showing a shape taken along the line DD ′ of FIG. 5 (c). The position of the cross section AA ′ of each drawing explaining this embodiment is the position of the cross section AA ′ of FIG. 81 showing the conventional example, and the position of the cross section BB ′ of each drawing explaining this embodiment. 81 correspond to the positions of the cross section BB 'in FIG. 81 showing the conventional example.

[0099] 第一の実施形態の電界効果型トランジスタを製造するためには、半導体層 3上にキ ヤップ絶縁層 8を形成したのち（図 2)、半導体層 3とキャップ絶縁層 8を適当な形状に パターユングし（図 3)、半導体層 3の側面がキャップ絶縁層 8の端部よりも内側に後 退するように、半導体層 3の側面をエッチングし、半導体層 3を細らせる（図 4)。そし て半導体層側面にゲート絶縁膜 4を形成し、ゲート電極材料を堆積したのち、ゲート 電極材料を RIE (リアクティブ'イオン'エッチング)等によりパターユングすることによ つてゲート電極 5を形成し、半導体層 3のうちゲート電極 5に覆われていない領域に 高濃度の第一導電型不純物を導入してソース/ドレイン領域 6を形成する（図 5)。そ の後層間絶縁膜 16を堆積して、通常の方法によりコンタクト 17及び配線 18を形成す る（図 7、図 8)。なお、ゲート電極を RIE等のエッチング工程により加工して形成する 際、エッチング工程の少なくとも後半において、等方性の強いエッチングを行レ、、突 起したキャップ絶縁層 8の下部に残留する余剰なゲート電極材料 26 (図 6 (a) )を除 去する工程をカ卩えることが望ましレ、。 [0099] In order to manufacture the field-effect transistor of the first embodiment, after forming the cap insulating layer 8 on the semiconductor layer 3 (FIG. 2), the semiconductor layer 3 and the cap insulating layer 8 are appropriately formed. The semiconductor layer 3 is etched to form a shape (FIG. 3), and the side of the semiconductor layer 3 is etched so that the side of the semiconductor layer 3 recedes inward from the end of the cap insulating layer 8 to make the semiconductor layer 3 thin ( (Figure 4). Then, a gate insulating film 4 is formed on the side surface of the semiconductor layer, a gate electrode material is deposited, and the gate electrode material is patterned by RIE (reactive 'ion' etching) or the like. Then, a gate electrode 5 is formed, and a high concentration first conductivity type impurity is introduced into a region of the semiconductor layer 3 which is not covered with the gate electrode 5 to form a source / drain region 6 (FIG. 5). Thereafter, an interlayer insulating film 16 is deposited, and a contact 17 and a wiring 18 are formed by a usual method (FIGS. 7 and 8). When the gate electrode is formed by processing using an etching process such as RIE, at least in the latter half of the etching process, highly isotropic etching is performed, and excess surplus remaining under the protruding cap insulating layer 8 is formed. It is desirable to remove the gate electrode material 26 (FIG. 6 (a)).

[0100] このような製造方法を採用することにより、第一の実施形態の素子構造を形成する ことが可能となる。  [0100] By employing such a manufacturing method, the element structure of the first embodiment can be formed.

[0101] (第一の実施形態の第二の製造方法）  (Second Manufacturing Method of First Embodiment)

製造方法の一例について、図 2から図 8を参照してより具体的に説明する。  An example of the manufacturing method will be described more specifically with reference to FIGS.

[0102] シリコンよりなる支持基板 1、その上に Si〇等の絶縁体よりなる坦め込み絶縁層 2、 さらにその上に単結晶シリコンよりなる半導体層 3が積層した SOI基板上に、キャップ 絶縁層 8を堆積する。キャップ絶縁層 8は例えば CVD法により堆積した Si〇膜とする [0102] A cap substrate is formed on an SOI substrate in which a supporting substrate 1 made of silicon, a filled insulating layer 2 made of an insulator such as Si〇, and a semiconductor layer 3 made of single crystal silicon are further stacked thereon. Deposit layer 8. The cap insulating layer 8 is, for example, a Si〇 film deposited by a CVD method.

。これにより図 2の形態が得られる。 . As a result, the configuration shown in FIG. 2 is obtained.

[0103] 次に、通常のリソグラフイエ程及び RIE等の通常のエッチング工程により、キャップ 絶縁層 8及び半導体層 3をパターニングし適当な形状に加工し、素子領域を形成す る。この段階で得られる形状を図 3に示す。なお、キャップ絶縁層 8及び半導体層 3は 、ともにフォトレジストをマスクにエッチングすることによりパターニングしても良ぐある いはフォトレジストをマスクにキャップ絶縁層 8だけをエッチングし、続いてキャップ絶 縁層 8をマスクに半導体層 3をエッチングすることによってパターニングしても良い。  Next, the cap insulating layer 8 and the semiconductor layer 3 are patterned and processed into an appropriate shape by a normal lithography process and a normal etching process such as RIE to form an element region. Figure 3 shows the shape obtained at this stage. Note that both the cap insulating layer 8 and the semiconductor layer 3 may be patterned by etching using a photoresist as a mask, or only the cap insulating layer 8 may be etched using a photoresist as a mask, followed by cap insulating. Patterning may be performed by etching the semiconductor layer 3 using the layer 8 as a mask.

[0104] 次に、等方性の強いエッチングを実施することによって、半導体層 3の側面をエッチ ングし、半導体層 3の側面が、キャップ絶縁層 8の側面よりも後退した形状に加工する 。この結果、図 4の形状が得られる。等方性の強いエッチングは、例えば CI、 HC1、 CNext, the side surface of the semiconductor layer 3 is etched by performing highly isotropic etching, and the side surface of the semiconductor layer 3 is processed into a shape recessed from the side surface of the cap insulating layer 8. As a result, the shape shown in FIG. 4 is obtained. Strongly isotropic etching, for example, CI, HC1, C

Fまたは HBrの何れかのエッチングガス、あるいはこれらを混合したエッチングガスを 用いて、バイアス電圧を低めに設定した RIEを行うことによって実施する。あるいは例 えば CFなどのガスを用いた等方性のプラズマエッチング装置によって行う。 This is performed by performing RIE with a bias voltage set low using an etching gas of either F or HBr, or an etching gas containing a mixture of these gases. Alternatively, for example, the etching is performed by an isotropic plasma etching apparatus using a gas such as CF.

[0105] 次に半導体層 3の側面にゲート絶縁膜 4を設けたのち、ポリシリコンを堆積し、これ を通常のリソグラフイエ程及び RIE工程によりエッチングすることによりパターニングし てゲート電極を形成し、続いて、ゲート電極をマスクに高濃度のイオン注入を行い、 熱処理を行うことにより、ゲート電極に覆われない位置の半導体層 3にソース/ドレイ ン領域 6を設け、図 5の形状を得る。ゲート電極を形成するためにポリシリコンをエツ チングしてゲート電極を形成する際、図 5 (c)の D—D'断面において図 6 (a)のように キャップ絶縁層 8の下部にポリシリコン 26が残留することを防ぐためには、ポリシリコン をエッチングする際に、通常の RIEを実施したのち、ポリシリコンに対する等方的なェ ツチングを加えれば、図 5 (c)の D—D'断面において図 6 (b)のようにキャップ絶縁層 の下部にポリシリコンが残留しない形状が得られる。なお、ゲート絶縁膜は、例えば半 導体層 3を熱酸化することによって設ける。また、ソース Zドレイン領域は垂直方向の イオン注入、斜めイオン注入あるいはプラズマドーピング等の不純物導入工程によつ て不純物を導入することにより形成する。 Next, after providing the gate insulating film 4 on the side surface of the semiconductor layer 3, polysilicon is deposited. The gate electrode is formed by patterning by etching in the usual lithography process and RIE process to form a gate electrode, followed by high-concentration ion implantation using the gate electrode as a mask and heat treatment to cover the gate electrode. The source / drain region 6 is provided in the semiconductor layer 3 at a position where there is not, and the shape shown in FIG. 5 is obtained. When the gate electrode is formed by etching polysilicon to form the gate electrode, as shown in FIG. 6A, the polysilicon is formed below the cap insulating layer 8 in the section taken along the line D-D 'in FIG. 5C. In order to prevent 26 from remaining, if the polysilicon is etched by performing normal RIE and then adding isotropic etching to the polysilicon, the D-D 'cross section in Fig. 5 (c) can be obtained. As shown in FIG. 6 (b), a shape is obtained in which no polysilicon remains under the cap insulating layer. The gate insulating film is provided by, for example, thermally oxidizing the semiconductor layer 3. Further, the source Z drain region is formed by introducing an impurity through an impurity introduction step such as vertical ion implantation, oblique ion implantation, or plasma doping.

[0106] 続いて、全体に絶縁膜を堆積してこれをエッチバックすることにより、ゲート側壁 14 を設ける。ゲート側壁 14をなす絶縁膜は、例えば Si〇単層膜、 Si N単層膜、 SiO Subsequently, a gate sidewall 14 is provided by depositing an insulating film on the whole and etching it back. The insulating film forming the gate side wall 14 is, for example, a single-layer film of Si〇, a single-layer film of SiN,

2 3 4 2 及び Si N力 なる多層膜などの絶縁膜を用いる。また、ゲート側壁 14をなす絶縁膜 An insulating film such as a multilayer film of 2 3 4 2 and SiN is used. Also, the insulating film forming the gate side wall 14

3 4 3 4

は CVD法等の製膜技術によって形成する。続いてソース/ドレイン領域 6の上部、 及びゲート電極 5の上部に金属を堆積し、熱処理することにより、ソース/ドレイン領 域 6の上部及びゲート電極 5の上部にシリサイド層 15を形成する。続いて、層間絶縁 膜 16を堆積し、これを平坦ィ匕したのち、ソース/ドレイン領域 6上部、及びゲート電極 5の上部にコンタクトホールを開口し、金属を坦め込むことによりコンタクト 17を形成し 、金属よりなる配線 18をコンタクト 17に接続し、図 7及び図 8の形状を得る。但し、図 7 (a)は図 8の A— A '断面の形状、図 7 (b)は図 8の B— B'断面の形状を示す。なお、コ ンタクト領域への金属の坦め込みと配線となる金属の堆積は同時に行っても良レ、。な お、コンタクト 17は配線 18の下部に位置する力 図 8においてはその位置を透視的 に示した。  Is formed by a film forming technique such as a CVD method. Subsequently, a metal is deposited on the source / drain region 6 and the gate electrode 5 and heat-treated to form a silicide layer 15 on the source / drain region 6 and the gate electrode 5. Subsequently, an interlayer insulating film 16 is deposited and flattened. After that, contact holes are opened in the upper portions of the source / drain regions 6 and the gate electrodes 5, and the contacts 17 are formed by filling metal. Then, the wiring 18 made of metal is connected to the contact 17 to obtain the shapes shown in FIGS. 7 (a) shows the cross-sectional shape taken along the line AA ′ in FIG. 8, and FIG. 7 (b) shows the cross-sectional shape taken along the line BB ′ in FIG. In addition, it is acceptable to carry out the metal loading into the contact area and the deposition of the metal to be the wiring at the same time. Note that the contact 17 is located at the lower part of the wiring 18. In FIG. 8, the position is shown in a transparent manner.

[0107] このような製造方法を採用することにより、第一の実施形態の素子構造を形成する ことが可能となる。  By employing such a manufacturing method, the element structure of the first embodiment can be formed.

[0108] [効果] 図 9 (a)の C_C'断面において、電位分布をシミュレーションした結果を図 9 (b)に示 す。図 9 (b)の縦軸は電位、横軸は位置であり、半導体層上端からの深さを示す。こ のシミュレーションにおいては半導体層中の不純物濃度を 4 X 1018cm 3とした。また、 電位の基準をソース電位とし、ソース電極の電位をゼロ Vとしている。図 9 (b)の左端 は半導体層の表面に相当する。図中ダブルゲート構造と示した破線は図 83の構造 についての計算結果、図中トライゲート構造と示した破線は図 82の構造についての 計算結果である。 [0108] [Effect] FIG. 9 (b) shows the result of simulating the potential distribution in the section C_C ′ in FIG. 9 (a). In FIG. 9B, the vertical axis represents the potential and the horizontal axis represents the position, and indicates the depth from the upper end of the semiconductor layer. In this simulation, the impurity concentration in the semiconductor layer was 4 × 10 18 cm 3 . The reference of the potential is the source potential, and the potential of the source electrode is zero V. The left end of FIG. 9B corresponds to the surface of the semiconductor layer. The dashed line shown as the double gate structure in the figure is the calculation result for the structure in FIG. 83, and the dashed line shown as the tri-gate structure in the figure is the calculation result for the structure in FIG.

[0109] 図 1の構造について、 Wextを 2nm、 10nm、 30nmとした場合の計算結果を実線で 示す。 Wextが 2nm、 10nm、 30nmのいずれの場合も通常ダブルゲート構造に比べ て電位の上昇が緩和されてレ、る。  [0109] For the structure of Fig. 1, the calculation results when Wext is 2 nm, 10 nm, and 30 nm are shown by solid lines. When Wext is 2nm, 10nm, or 30nm, the rise in potential is reduced compared to the normal double gate structure.

[0110] 横軸に Wext、縦軸に半導体層上部コーナー部における最大の電位をとり、シミュレ ーシヨン結果をプロットしたものを図 100に示す。なお、図 100 (a)と図 100 (b)のデ ータは同じであり、図 100 (a)は Wextの下限に関する説明を、図 100 (b)は Wextの 上限に関する説明をそれぞれ示したものである。但し、図 100においては半導体層 中の不純物濃度は 4 X 1018cm— 3であり、ゲート電圧は 0V (図 100では、この時のゲー ト電位を 0· 56Vととってレヽる）、 Wfmは 30nm、ゲート絶縁膜厚は 2nmである。 [0110] FIG. 100 shows a plot of the simulation results with the horizontal axis representing Wext and the vertical axis representing the maximum potential at the upper corner of the semiconductor layer. The data in Fig. 100 (a) and Fig. 100 (b) are the same, and Fig. 100 (a) shows the explanation for the lower limit of Wext, and Fig. 100 (b) shows the explanation for the upper limit of Wext. Things. However, in FIG. 100, the impurity concentration in the semiconductor layer is 4 × 10 18 cm− 3 , the gate voltage is 0 V (in FIG. 100, the gate potential at this time is 0.556 V, and the level is Wfm). Is 30 nm, and the gate insulating film thickness is 2 nm.

[0111] 図 1及び図 100から、 Wextが小さい領域では、 Wextの増加とともに上部コーナー 部の電位が低下しており、電位上昇を抑制する効果が増している。しかし、 Wextが大 きくなると、 Wextを増しても電位はあまり変化しなくなる。  [0111] According to Figs. 1 and 100, in the region where Wext is small, the potential at the upper corner portion decreases as Wext increases, and the effect of suppressing the potential rise increases. However, when Wext increases, the potential does not change much even if Wext is increased.

[0112] 図 100力ら、最大の効果の半分の効果が得られるのは Wextが 2nm以上の場合で あり、また Wextが 5nmまでの範囲では電位が大きく変化しており、 Wextが lOnmまで はある程度の傾きをもって電位が変化している。本実施形態の電界効果型トランジス タでは、上部コーナー部の電位を低下させられるだけの大きさに Wextが設定される ことが望ましいので、ある程度の（具体的には半分の）発明の効果を得るには Wextは 2nm以上が好ましぐ発明の効果を大きく得るためには Wextは 5nm以上が好ましく 、また最大の効果を得るには lOnm以上が好ましいといえる。  [0112] As shown in Fig. 100, half of the maximum effect is obtained when Wext is 2 nm or more, and when Wext is up to 5 nm, the potential changes greatly. The potential changes with a certain inclination. In the field-effect transistor of the present embodiment, it is desirable that Wext is set to a size that can lower the potential of the upper corner portion, so that a certain (specifically, half) effect of the invention is obtained. Wext is preferably 2 nm or more. In order to obtain a large effect of the present invention, Wext is preferably 5 nm or more, and lOnm or more is preferable for obtaining the maximum effect.

[0113] 一方、 Wextが lOnmを越えると電位の変化はゆるやかになり、 15nm以上では電位 の変化が飽和傾向を示す。電位の変化が飽和する領域で Wextを増しても、製造プ ロセスへの負担が増すだけで、電位を低減できないので、 Wextは 15nm以下が好ま しいと言える。また、プロセス上の原因による Wextのバラツキを考えて、 15nmに対し て 5nmの余裕を見るならば、 Wextは 20nm以下が好ましい。 [0113] On the other hand, when Wext exceeds lOnm, the change in potential becomes gradual, and when 15 nm or more, the change in potential tends to be saturated. Even if Wext is increased in the region where the potential change is saturated, Since the potential cannot be reduced simply by increasing the load on the process, Wext is preferably 15 nm or less. Also, considering the variation of Wext due to process causes, if a margin of 5 nm is provided for 15 nm, Wext is preferably 20 nm or less.

[0114] また、 Wextが大きすぎると、ゲート電極の加工が難しくなるという観点から考えると、 Wextは 20nm以下が好ましく、 15nm以下がより好ましいと考えられる。  [0114] From the viewpoint that processing of the gate electrode becomes difficult when Wext is too large, Wext is preferably 20 nm or less, and more preferably 15 nm or less.

[0115] なお、計算においては、ゲート絶縁膜の厚さを 2nmとしたので、ある程度の発明の 効果を得るのためには Wextはゲート絶縁膜厚の 1倍以上が好ましぐ発明の効果を 大きく得るためには Wextはゲート絶縁膜厚の 2. 5倍以上が好ましぐ最大の効果を 得るには 5倍以上が好ましいと言える。また、同じぐ Wextはゲート絶縁膜厚の 10倍 以下が好ましぐまた、プロセスのバラツキを無視して純粋に効果の観点から判断す るなら、 Wextはゲート絶縁膜厚の 7. 5倍以下がより好ましいと考えられる。  [0115] In the calculation, the thickness of the gate insulating film was set to 2 nm. Therefore, in order to obtain a certain effect of the present invention, Wext is required to have an effect of the present invention in which the gate insulating film is preferably at least one time the gate insulating film thickness. Wext should be at least 2.5 times the thickness of the gate insulating film to obtain a large value, and 5 times or more is preferable to obtain the maximum effect. In addition, the same Wext is preferred to be 10 times or less of the gate insulating film thickness, and if the judgment is made purely from the viewpoint of effect ignoring process variations, Wext is 7.5 times or less of the gate insulating film thickness. Is considered to be more preferable.

[0116] (第二の実施形態）  (Second Embodiment)

[構造]  [Construction]

第二の実施形態について、従来例を示す図面である図 81の A— A '断面に相当す る位置における断面図である、図 10から図 16及び図 26を参照して説明する。  A second embodiment will be described with reference to FIGS. 10 to 16 and FIG. 26, which are cross-sectional views at positions corresponding to the cross section taken along the line AA ′ of FIG. 81, which is a drawing showing a conventional example.

[0117] 第二の実施形態においては基板から上方に突起した半導体層 3の上部または下 部の一方、または基板から上方に突起した半導体層 3の上部及び下部の両方に SiO よりも誘電率が低い領域である低誘電率領域 10が設けられる。半導体層の側面に はゲート絶縁膜 4を介してゲート電極 5が設けられる。ゲート電極 5は適当な寸法にパ ターニングされており、ゲート電極に覆われない位置の半導体層には第一導電型の 不純物が高濃度に導入されたソース/ドレイン領域 6が形成される。ゲート電極 5に 覆われた半導体層であるチャネル形成領域 7には、ゲート電極 5に適当な電圧を印 加することにより第一導電型のキャリアよりなるチャネルが形成される。ゲート電極 5、 ソース Zドレイン領域 6にはコンタクト領域を介して配線が接続される。 [0117] In the second embodiment, one of the upper and lower portions of the semiconductor layer 3 projecting upward from the substrate, or both the upper and lower portions of the semiconductor layer 3 projecting upward from the substrate have a dielectric constant higher than that of SiO. A low dielectric constant region 10 which is a low region is provided. A gate electrode 5 is provided on a side surface of the semiconductor layer via a gate insulating film 4. The gate electrode 5 is patterned to an appropriate size, and a source / drain region 6 in which impurities of the first conductivity type are introduced at a high concentration is formed in a portion of the semiconductor layer which is not covered with the gate electrode. In the channel forming region 7 which is a semiconductor layer covered by the gate electrode 5, a channel made of carriers of the first conductivity type is formed by applying an appropriate voltage to the gate electrode 5. Wiring is connected to the gate electrode 5 and the source Z drain region 6 via a contact region.

[0118] 半導体層 3の上部に設けられた低誘電率領域 10、半導体層 3の下部に設けられた 低誘電率領域 10は、それぞれ半導体層の上部コーナー部 34、下部コーナー部 35 に形成される寄生トランジスタを抑制する作用がある。  [0118] The low dielectric constant region 10 provided above the semiconductor layer 3 and the low dielectric constant region 10 provided below the semiconductor layer 3 are formed in the upper corner portion 34 and the lower corner portion 35 of the semiconductor layer, respectively. Has the effect of suppressing parasitic transistors.

[0119] 以下、第二の実施形態の構造について、図 10から図 16及び図 26を参照してより 詳しく説明する。 Hereinafter, the structure of the second embodiment will be described with reference to FIGS. 10 to 16 and FIG. explain in detail.

[0120] (低誘電率領域、空洞について）  [0120] (Low dielectric constant region, cavity)

通常の FinFETにおいて、半導体層 3の上部に形成されるキャップ絶縁層 8の全体 または一部を Si〇よりも誘電率が低い領域である低誘電率領域 10により構成する。 ( 図 10 (a) )。また、半導体層 3の上下両方に低誘電率領域 10を設ける（図 10 (b)、図 l l (a) )。あるいは、半導体層 3の下部だけに低誘電率領域を設ける（図 11 (b)、図 1 1 (c)、記号 36は SiOよりなるキャップ絶縁層）。また、これら低誘電率領域 10を空洞 In a normal FinFET, the whole or a part of the cap insulating layer 8 formed on the semiconductor layer 3 is constituted by a low dielectric constant region 10 having a dielectric constant lower than that of Si〇. (Figure 10 (a)). Further, a low dielectric constant region 10 is provided both above and below the semiconductor layer 3 (FIG. 10 (b), FIG. 11 (a)). Alternatively, a low dielectric constant region is provided only below the semiconductor layer 3 (FIG. 11 (b), FIG. 11 (c), symbol 36 is a cap insulating layer made of SiO). In addition, these low dielectric regions 10

12によって形成する。低誘電率領域 10を構成する低誘電率材料は SiOの比誘電 率 3. 9よりも低い比誘電率を持つ。低誘電率材料の比誘電率は 3. 0以下であること 力 り望ましい。 Formed by 12. The low dielectric constant material forming the low dielectric constant region 10 has a relative dielectric constant lower than the relative dielectric constant of SiO of 3.9. It is strongly desirable that the relative dielectric constant of the low dielectric constant material be 3.0 or less.

[0121] 低誘電率領域 10は、その一部または全部がゲート電極の上端よりも低い位置に設 けられる（図 94)。特に、ゲート電極 5が半導体層 3を跨ぐときには、低誘電率領域 10 はゲート電極の下部に設けられる（図 10)。これらの形態により、半導体層の上方に 延在したゲート電極の側面から半導体層へ向う電界（図 93、図 92 (b)に示した電界 4 6の一部）、あるいはゲート電極の下面から半導体層へ向う電界（図 92 (b)に示した 電界 46の一部）の影響を緩和し、寄生トランジスタの影響を低減するという効果が得 られる。  [0121] The low dielectric constant region 10 is partially or entirely provided at a position lower than the upper end of the gate electrode (FIG. 94). In particular, when the gate electrode 5 straddles the semiconductor layer 3, the low dielectric constant region 10 is provided below the gate electrode (FIG. 10). With these configurations, an electric field (part of the electric field 46 shown in FIGS. 93 and 92 (b)) from the side of the gate electrode extending above the semiconductor layer to the semiconductor layer, or a semiconductor from the lower surface of the gate electrode The effect of reducing the effect of the electric field (part of the electric field 46 shown in FIG. 92 (b)) toward the layer and the effect of the parasitic transistor can be obtained.

[0122] 半導体層 3下部に低誘電率領域が設けられる場合、半導体層 3が存在しない領域 におレ、てゲート電極 5の下部にも低誘電率領域が設けられても良レ、（図 11)。この構 造には、ゲート電極 5の下部と支持基板間の容量を低減できるという長所がある。ま た、半導体層 3が存在しない領域では、ゲート電極 5の下部に低誘電率領域が設け られない構造（図 10 (b) )であっても良レ、。この構造には、半導体層 3内部における電 位分布が上下対称となるので、素子設計が容易になるという長所がある。また、この 構造には、 SiO膜に比べて一般に機械的に脆弱である低誘電率材料が、製造工程 中に表面に露出する面積を低減できるという長所もある。  [0122] When a low dielectric constant region is provided below the semiconductor layer 3, it is acceptable if a low dielectric constant region is also provided below the gate electrode 5 in a region where the semiconductor layer 3 does not exist. 11). This structure has an advantage that the capacitance between the lower part of the gate electrode 5 and the supporting substrate can be reduced. In a region where the semiconductor layer 3 does not exist, a structure in which a low dielectric constant region is not provided below the gate electrode 5 (FIG. 10B) is acceptable. This structure has an advantage that the potential distribution inside the semiconductor layer 3 is vertically symmetrical, so that the element design becomes easy. This structure also has the advantage that low dielectric constant materials, which are generally mechanically more fragile than SiO films, can reduce the surface area exposed during the manufacturing process.

[0123] また、半導体層の上部に Si〇よりも誘電率が低い材料よりなる領域を設けるだけで なぐゲート電極 5の側面に設けられる側壁であるゲート側壁 (例えば図 20、図 26、 図 28、図 35の記号 14の部分）の一部または全部が SiOよりも誘電率が低い材料で 形成されても良い。 [0123] Further, a gate sidewall (for example, FIG. 20, FIG. 26, or FIG. 28) which is a sidewall provided on the side surface of the gate electrode 5 only by providing a region made of a material having a lower dielectric constant than Si〇 on the semiconductor layer , Part or all of symbol 14 in FIG. 35) is made of a material having a lower dielectric constant than SiO. It may be formed.

[0124] (保護絶縁膜について）  [0124] (About protective insulating film)

また、半導体層 3と低誘電率領域 10の間に半導体層を熱酸化することなどにより形 成された薄い保護絶縁膜 13が形成されても良い。保護絶縁膜 13は低誘電領域と半 導体層との界面における界面準位などの欠陥を低減する効果がある。保護絶縁膜 1 3は Si〇と同じ力 \あるいは Si〇よりも高い誘電率を持って良レ、。また保護絶縁膜 13 は SiOよりも低い誘電率を持って良い。保護絶縁膜の厚さには特に制限はないが、 保護絶縁膜の厚さが低誘電率領域の厚さ（但し、厚さとは基板平面に垂直方向の幅 をいい、例えば図 13の断面においては上下方向の幅を言う。）より薄ければ、寄生ト ランジスタを抑制するという効果に対して望ましい。また、保護絶縁膜の厚さがゲート 絶縁膜の 3倍以下であれば、寄生トランジスタを抑制するという効果に対してさらに望 ましい。低誘電率領域 10が空洞 12である場合に、半導体層 3と低誘電率領域 10の 間に保護絶縁膜 13を介在させた場合の構造を図 13に示す。図 13 (a)は低誘電率 領域が半導体層の上部に設けられる場合、図 13 (b)は低誘電率領域が半導体層の 上部と下部に設けられる場合である。また、保護絶縁膜 13は空洞と接するゲート電 極の表面に形成されても良い（図 26)。  Further, a thin protective insulating film 13 formed by thermally oxidizing the semiconductor layer between the semiconductor layer 3 and the low dielectric constant region 10 may be formed. The protective insulating film 13 has an effect of reducing defects such as interface states at the interface between the low dielectric region and the semiconductor layer. The protective insulating film 13 has the same strength as Si〇 or has a higher dielectric constant than Si〇. The protective insulating film 13 may have a lower dielectric constant than SiO. Although there is no particular limitation on the thickness of the protective insulating film, the thickness of the protective insulating film is the thickness of the low dielectric constant region (however, the thickness refers to the width in the direction perpendicular to the substrate plane, for example, in the cross section of FIG. 13). Refers to the width in the vertical direction.) A smaller thickness is desirable for the effect of suppressing the parasitic transistor. If the thickness of the protective insulating film is three times or less the thickness of the gate insulating film, the effect of suppressing the parasitic transistor is more desirable. FIG. 13 shows a structure in a case where the low dielectric region 10 is a cavity 12 and a protective insulating film 13 is interposed between the semiconductor layer 3 and the low dielectric region 10. FIG. 13A shows the case where the low dielectric constant region is provided above the semiconductor layer, and FIG. 13B shows the case where the low dielectric constant region is provided above and below the semiconductor layer. Further, the protective insulating film 13 may be formed on the surface of the gate electrode in contact with the cavity (FIG. 26).

[0125] また、半導体層 3と、半導体層下部の低誘電率領域との間に、保護絶縁膜 13を設 けても良い。半導体層下部に設けられた保護絶縁膜 13を坦め込み保護絶縁膜 39と して図 12に示す。埋め込み保護絶縁膜 39を設ける目的は、半導体上部に設ける保 護絶縁膜 13を設ける目的と同じであり、低誘電率領域と半導体層との界面における 界面準位などの欠陥を低減することである。また、埋め込み保護絶縁膜 39は Si〇と 同じか、あるいは SiOよりも高い誘電率を持って良ぐ SiOよりも低い誘電率を持つ て良い点も半導体層上部に設ける保護絶縁膜 13と同様である。 [0125] A protective insulating film 13 may be provided between the semiconductor layer 3 and the low dielectric constant region below the semiconductor layer. FIG. 12 shows the protective insulating film 39 provided under the semiconductor layer as a protective insulating film 39. The purpose of providing the buried protective insulating film 39 is the same as the purpose of providing the protective insulating film 13 provided above the semiconductor, and is to reduce defects such as interface states at the interface between the low dielectric constant region and the semiconductor layer. . Also, the buried protective insulating film 39 is the same as Si〇, or has a higher dielectric constant than SiO, and may have a lower dielectric constant than SiO, similarly to the protective insulating film 13 provided above the semiconductor layer. is there.

[0126] (第一の実施形態と第二の実施形態の併用）  [0126] (Combined use of the first embodiment and the second embodiment)

第二の実施形態は、第一の実施形態と組み合わせて実施しても良い。  The second embodiment may be implemented in combination with the first embodiment.

[0127] 例えば、第一の実施形態において半導体層上のキャップ絶縁層 8の全体または一 部を低誘電率材料または空洞よりなる領域である低誘電率領域 10により構成しても 良い。これは、第一の実施形態の効果に第二の実施形態の効果をさらに加えること により、半導体層の上部コーナー部における寄生トランジスタをより強く抑制する作用 力 Sある。 For example, in the first embodiment, the entire or a part of the cap insulating layer 8 on the semiconductor layer may be constituted by the low dielectric constant region 10 which is a region made of a low dielectric constant material or a cavity. This is to add the effect of the second embodiment to the effect of the first embodiment. Accordingly, there is an action force S that more strongly suppresses the parasitic transistor at the upper corner portion of the semiconductor layer.

[0128] また、第一の実施形態において、半導体層下部の絶縁体の一部または全部を低誘 電率材料または空洞よりなる低誘電率領域により構成しても良い。すなわち、半導体 層上部に対して第一の実施形態を、半導体層下部に対して第二の実施形態の各種 構成を適用しても良レ、。これは半導体層上部コーナー部における寄生トランジスタを 第一の実施形態によって、半導体層の下部コーナー部 35における寄生トランジスタ を第二の実施形態によって抑制するものである。  In the first embodiment, part or all of the insulator below the semiconductor layer may be formed of a low dielectric constant region made of a low dielectric constant material or a cavity. In other words, various configurations of the first embodiment may be applied to the upper portion of the semiconductor layer, and various configurations of the second embodiment may be applied to the lower portion of the semiconductor layer. This suppresses the parasitic transistor at the upper corner portion of the semiconductor layer according to the first embodiment, and the parasitic transistor at the lower corner portion 35 of the semiconductor layer according to the second embodiment.

[0129] その例を図 15及び図 16に示す。これらはすべて図 1 (a)と同一断面における断図 面である。図 15 (a)は図 1の構造においてキャップ絶縁層を低誘電率領域 10で構成 した場合、図 15 (b)は図 1の構造にぉレ、てキャップ絶縁層 8を空洞 12よりなる低誘電 率領域 10と、保護絶縁膜 13よりなる構造によって構成した場合である。保護絶縁膜 13は半導体層 3と空洞 12との界面を保護するために設けられてレ、る。図 16 (a)は図 1の構造において半導体層 3の下部に低誘電率領域 10を設けた場合、図 16 (b)は 図 1の構造において半導体層 3の下部に空洞 12よりなる低誘電率領域 10を設け、空 洞 12と半導体層 3の界面及び空洞 12とゲート電極 5の界面に保護絶縁膜 13を設け た場合である。 FIGS. 15 and 16 show examples. These are all cross-sectional views in the same cross section as FIG. 1 (a). FIG. 15 (a) shows a case where the cap insulating layer is formed of the low dielectric constant region 10 in the structure of FIG. 1, and FIG. 15 (b) shows the structure of FIG. This is a case where it is configured by a structure including the dielectric constant region 10 and the protective insulating film 13. The protective insulating film 13 is provided to protect the interface between the semiconductor layer 3 and the cavity 12. FIG. 16 (a) shows a case where a low dielectric constant region 10 is provided below the semiconductor layer 3 in the structure of FIG. 1, and FIG. 16 (b) shows a low dielectric constant region having a cavity 12 below the semiconductor layer 3 in the structure of FIG. In this case, the protective region 13 is provided at the interface between the cavity 12 and the semiconductor layer 3 and at the interface between the cavity 12 and the gate electrode 5.

[0130] なお、第一の実施形態と、第二の実施形態は、図 15、図 16に示したものとは異な る形態において組み合わせても良い。  [0130] The first embodiment and the second embodiment may be combined in a different form from those shown in Figs.

[0131] [製造方法] [0131] [Production method]

(第二の実施形態の第一の製造方法）  (First manufacturing method of second embodiment)

製半導体層 3の上部に低誘電率領域 10を設ける場合の製造方法について、図 17 力 図 21を参照して説明する。なお、図 18 (a)、図 19 (a)、図 20 (a)はそれぞれ平 面図である図 21における A— A'断面の断面図であり、図 18 (b)、図 19 (b)、図 20 (b )はそれぞれ平面図である図 21における B— B'断面の断面図である。  A manufacturing method in the case where the low dielectric constant region 10 is provided above the semiconductor layer 3 will be described with reference to FIGS. FIGS. 18 (a), 19 (a) and 20 (a) are cross-sectional views taken along the line AA ′ in FIG. 21 which is a plan view, respectively. 20) and FIG. 20 (b) are cross-sectional views taken along the line BB ′ in FIG. 21 which is a plan view.

[0132] 製造方法の一例を説明する。第二の実施形態の電界効果型トランジスタを製造す るためには、半導体層 3上にキャップ絶縁層 8として低誘電率領域 10となる Si〇より も誘電率が低い材料よりなる低誘電率膜 30を堆積し (図 17)、半導体層 3と低誘電率 膜 10を適当な形状にパターユングする（図 18)。半導体側面にゲート絶縁膜 4を形 成し、ゲート電極材料を堆積したのち、ゲート電極材料を RIE等によりパターニング することにより、ゲート電極 5を形成し、半導体層 3のうちゲート電極 5に覆われていな い領域に高濃度の第一導電型不純物を導入してソース Zドレイン領域 6を形成する（ 図 19)。その後層間絶縁膜を堆積して、通常の方法によりコンタクト 17及び配線 18を 形成する（図 20、図 21)。 [0132] An example of the manufacturing method will be described. In order to manufacture the field-effect transistor of the second embodiment, a low-dielectric-constant film made of a material having a lower dielectric constant than that of Si 30 (Fig. 17), semiconductor layer 3 and low dielectric constant Putter the membrane 10 into a suitable shape (Fig. 18). A gate insulating film 4 is formed on the side surface of the semiconductor, a gate electrode material is deposited, and then the gate electrode material is patterned by RIE or the like to form a gate electrode 5, which is covered with the gate electrode 5 of the semiconductor layer 3. A high-concentration impurity of the first conductivity type is introduced into the unreacted region to form the source Z drain region 6 (FIG. 19). Thereafter, an interlayer insulating film is deposited, and the contact 17 and the wiring 18 are formed by a usual method (FIGS. 20 and 21).

[0133] このような製造方法を採用することにより、第二の実施形態の素子構造を形成する ことが可能となる。  By adopting such a manufacturing method, it is possible to form the element structure of the second embodiment.

[0134] (第二の実施形態の第二の製造方法）  (Second Manufacturing Method of Second Embodiment)

半導体層 3の上部に低誘電率領域 10を設ける場合の製造方法について、図 17か ら図 21を参照して、より詳しく説明する。  The manufacturing method in the case where the low dielectric constant region 10 is provided above the semiconductor layer 3 will be described in more detail with reference to FIGS.

[0135] シリコンよりなる支持基板 1、その上に Si〇よりなる埋め込み絶縁層 2、さらにその上 に単結晶シリコンよりなる半導体層 3が積層した SOI基板上に、前記低誘電率領域 1 0として、 SiOよりも誘電率が低い材料よりなる低誘電率絶縁膜 30を堆積する。  [0135] On a SOI substrate in which a support substrate 1 made of silicon, a buried insulating layer 2 made of Si〇, and a semiconductor layer 3 made of single crystal silicon are further stacked thereon, the low dielectric constant region 10 A low dielectric constant insulating film 30 made of a material having a lower dielectric constant than SiO is deposited.

低誘電率絶縁膜 30は例えば CVD法により堆積した SiOF膜とする。これにより図 17 の形態が得られる。  The low dielectric constant insulating film 30 is, for example, a SiOF film deposited by a CVD method. As a result, the configuration shown in FIG. 17 is obtained.

[0136] 次に、通常のリソグラフイエ程及び RIE等の通常のエッチング工程により、低誘電率 膜 30及び半導体層 3をパターニングして図 18の形状を得る。なお、低誘電率膜 30 及び半導体層 3は、ともにフォトレジストをマスクにエッチングすることによりパターニン グしても良く、あるいはフォトレジストをマスクに低誘電率膜 30だけをエッチングし、続 いて低誘電率膜 30をマスクに半導体層 3をエッチングすることによってパターニング しても良い。  Next, the low-dielectric-constant film 30 and the semiconductor layer 3 are patterned by a normal lithography process and a normal etching process such as RIE to obtain the shape shown in FIG. The low dielectric constant film 30 and the semiconductor layer 3 may be patterned by etching both using a photoresist as a mask, or only the low dielectric constant film 30 may be etched using a photoresist as a mask, followed by low dielectric constant. Patterning may be performed by etching the semiconductor layer 3 using the film 30 as a mask.

[0137] 次に半導体層 3の側面にゲート絶縁膜 4を設けたのち、ポリシリコンを堆積し、これ を通常のリソグラフイエ程及び RIE工程によりエッチングすることによりパターユングし てゲート電極を形成し、続いて、ゲート電極をマスクに高濃度のイオン注入を行い、 熱処理を行うことにより、ゲート電極に覆われない位置の半導体層 3にソース/ドレイ ン領域 6を設け、図 19の形状を得る。  Next, after a gate insulating film 4 is provided on the side surface of the semiconductor layer 3, polysilicon is deposited, and this is etched by a usual lithography process and RIE process to form a gate electrode by patterning. Then, high-concentration ion implantation is performed using the gate electrode as a mask, and heat treatment is performed to provide the source / drain regions 6 in the semiconductor layer 3 at positions not covered by the gate electrode, thereby obtaining the shape shown in FIG. .

[0138] 続いて、全体に絶縁膜を堆積してこれをエッチバックすることにより、ゲート側壁 14 を設ける。ゲート側壁 14をなす絶縁膜は、例えば Si〇または Si N多層膜、 Si〇及 Subsequently, an insulating film is deposited on the whole and etched back to form an insulating film. Is provided. The insulating film forming the gate side wall 14 is, for example, a Si〇 or SiN multilayer film,

2 3 4 2 び Si Nからなる多層膜などからなる。また、ゲート側壁 14をなす絶縁膜は CVD法等 It is composed of a multilayer film composed of 2 3 4 2 and SiN. In addition, the insulating film forming the gate side wall 14 is formed by CVD or the like.

3 4 3 4

の製膜技術によって形成する。続いてソース/ドレイン領域 6の上部、及びゲート電 極 5の上部に金属を堆積し、熱処理することにより、ソース Zドレイン領域 6の上部及 びゲート電極 5の上部にシリサイド層 15を形成する。続いて、層間絶縁膜 16を堆積し 、これを平坦ィ匕したのち、ソース/ドレイン領域 6上部、及びゲート電極 5の上部にコ ンタクトホールを開口し、金属を埋め込むことによりコンタクト 17を形成し、金属よりな る配線 18をコンタクト 17に接続し、図 20及び図 21の形状を得る。なお、コンタクト領 域への金属の坦め込みと配線となる金属の堆積は同時に行っても良レ、。なお、コンタ タト 17は配線 18の下部に位置する力 図 21においてはその位置を示した。なお、低 誘電率膜 30は低誘電率領域 10を成すものである。  Formed by the film forming technique described above. Subsequently, a metal is deposited on the source / drain region 6 and the gate electrode 5 and heat-treated to form a silicide layer 15 on the source Z drain region 6 and on the gate electrode 5. Subsequently, an interlayer insulating film 16 is deposited and flattened. After that, contact holes are opened in the upper portions of the source / drain regions 6 and the gate electrodes 5, and the contacts 17 are formed by embedding metal. Then, a wiring 18 made of metal is connected to the contact 17 to obtain the shapes shown in FIGS. It is acceptable to carry out metal loading in the contact area and deposition of metal to be wiring at the same time. The contact 17 is located at the lower part of the wiring 18 and its position is shown in FIG. The low dielectric constant film 30 forms the low dielectric constant region 10.

[0139] このような製造方法を採用することにより、第二の実施形態の素子構造を形成する ことが可能となる。  By adopting such a manufacturing method, it is possible to form the element structure of the second embodiment.

[0140] (第二の実施形態の第三の製造方法）  (Third Manufacturing Method of Second Embodiment)

半導体層 3の下部に低誘電率領域 10を設ける場合は、第二の実施形態の第一の 製造方法または第二の実施形態の第二の製造方法において以下の変更を加える。 坦め込み絶縁層の全てまたは一部を低誘電率膜 30によって形成する。また、キヤッ プ絶縁層 8は低誘電率膜であってもよぐ低誘電率膜でなくても良い。またキャップ絶 縁層 8を形成せず、半導体側面と上面にゲート絶縁膜を形成し、ゲート電極材料を 堆積したのち、ゲート電極材料を RIE等によりパターエングすることにより図 11 (b)の ようなトライゲート構造を形成しても良い。また、半導体層 3と低誘電率膜 10を適当な 形状にパターニングする際に、半導体層 3下部の低誘電率膜の一部または全部を半 導体層 3に覆われない領域においてエッチングすることにより、図 10 (b)のような形状 を形成しても良レ、。図 10 (b)は埋め込み絶縁膜のうち上部の領域が低誘電率膜によ り形成される S〇I基板を用いるとともに、半導体層 3下部の低誘電率膜を半導体層 3 に覆われなレ、領域にぉレ、てエッチングして得られる形状である。  When the low dielectric constant region 10 is provided below the semiconductor layer 3, the following changes are made in the first manufacturing method of the second embodiment or the second manufacturing method of the second embodiment. All or part of the embedded insulating layer is formed by the low dielectric constant film 30. Further, the cap insulating layer 8 may be a low dielectric constant film or a non-low dielectric constant film. Also, without forming the cap insulating layer 8, a gate insulating film is formed on the side and top surfaces of the semiconductor, a gate electrode material is deposited, and then the gate electrode material is patterned by RIE or the like, as shown in FIG. 11 (b). A tri-gate structure may be formed. When patterning the semiconductor layer 3 and the low dielectric constant film 10 into an appropriate shape, a part or the whole of the low dielectric constant film below the semiconductor layer 3 is etched in a region not covered by the semiconductor layer 3. It is acceptable to form the shape as shown in FIG. 10 (b). Fig. 10 (b) uses an S〇I substrate in which the upper region of the buried insulating film is formed of a low dielectric constant film, and the low dielectric constant film below the semiconductor layer 3 is not covered by the semiconductor layer 3. This is the shape obtained by etching the area and the area.

[0141] このような製造方法を採用することにより、第二の実施形態の素子構造を形成する ことが可能となる。 [0142] (第二の実施形態の第四の製造方法） [0141] By employing such a manufacturing method, it is possible to form the element structure of the second embodiment. (Fourth Manufacturing Method of Second Embodiment)

半導体層 3の上部に空洞 12よりなる低誘電率領域 10を設ける製造方法、及び半 導体層 3の上部に一旦空洞 12を設けたのち、空洞 12を SiOよりも誘電率が低い低 誘電率材料によって埋め戻すことにより半導体層 3の上部に低誘電率領域 10を設け る製造方法について図 14、及び図 22から図 28を参照して説明する。  A manufacturing method in which a low dielectric constant region 10 consisting of a cavity 12 is provided above a semiconductor layer 3, and a method in which a cavity 12 is provided once above a semiconductor layer 3, and then a low dielectric constant material having a dielectric constant lower than that of SiO. With reference to FIG. 14 and FIGS. 22 to 28, a description will be given of a manufacturing method for providing the low dielectric constant region 10 on the semiconductor layer 3 by backfilling.

[0143] なお、図 23 (a)、図 24 (a)、図 25 (a)、図 26 (a)、図 28 (a)はそれぞれ平面図であ る図 23 (c)、図 24 (c)、図 25 (c)、図 27における A— A'断面の断面図であり、図 23 ( b)、図 24 (b)、図 25 (b)、図 26 (b)、図 28 (b)はそれぞれ平面図である図 23 (c)、図 24 (c) ,図 25 (c)、図 27における B—B'断面の断面図である。  FIG. 23 (a), FIG. 24 (a), FIG. 25 (a), FIG. 26 (a), and FIG. 28 (a) are plan views of FIG. 23 (c) and FIG. 28 is a cross-sectional view taken along the line A--A 'in FIGS. 23 (c), 25 (c) and 27, and FIGS. 23 (b), 24 (b), 25 (b), 26 (b), and 28 ( b) is a cross-sectional view taken along the line BB 'in FIGS. 23 (c), 24 (c), 25 (c), and 27 which are plan views.

[0144] 半導体層 3上にダミー層 11を堆積し（図 22)、半導体層 3とダミー層 11を適当な形 状にパターニングし（図 23)、半導体側面にゲート絶縁膜を形成し、ゲート電極材料 を堆積したのち、ゲート電極材料を RIE等によりパターユングすることにより、半導体 層 3、ゲート絶縁膜 4、ダミー層 11を覆うようにゲート電極 5を形成し、半導体層 3のう ちゲート電極 5に覆われていない領域に高濃度の第一導電型不純物を導入してソー ス/ドレイン領域 6を形成する（図 24、図 14 (a) )。続いてダミー層 11をエッチングに より除去することによりゲート電極 5に覆われた半導体層 3上の領域に空洞 12を形成 する（図 25、図 14 (b) )。その後層間絶縁膜を堆積して、通常の方法によりコンタクト 及び配線を形成する（図 26、図 27)。  [0144] A dummy layer 11 is deposited on the semiconductor layer 3 (Fig. 22), and the semiconductor layer 3 and the dummy layer 11 are patterned into an appropriate shape (Fig. 23). After depositing the electrode material, the gate electrode material is patterned by RIE or the like to form a gate electrode 5 so as to cover the semiconductor layer 3, the gate insulating film 4, and the dummy layer 11, and the gate of the semiconductor layer 3 is formed. A source / drain region 6 is formed by introducing high-concentration first conductivity type impurities into a region not covered by the electrode 5 (FIGS. 24 and 14 (a)). Subsequently, the dummy layer 11 is removed by etching to form a cavity 12 in a region on the semiconductor layer 3 covered with the gate electrode 5 (FIGS. 25 and 14 (b)). Thereafter, an interlayer insulating film is deposited, and contacts and wirings are formed by a usual method (FIGS. 26 and 27).

[0145] また、ゲート電極 5に覆われた半導体層 3上の空洞 12に低誘電率材料を坦め戻し て、低誘電率領域 10を形成しても良い。  Further, the low-dielectric-constant region 10 may be formed by back-filling the low-dielectric-constant material in the cavity 12 on the semiconductor layer 3 covered with the gate electrode 5.

[0146] ダミー層 11には例えば CVDにより堆積した Si N膜を用いる、また空洞を形成する ためにはダミー層 11の Si N膜をリン酸を用いたウエットエッチング等のエッチングェ 程により除去する。  [0146] For the dummy layer 11, for example, a SiN film deposited by CVD is used, and in order to form a cavity, the SiN film of the dummy layer 11 is removed by an etching step such as wet etching using phosphoric acid. .

[0147] このような製造方法を採用することにより、第二の実施形態の素子構造を形成する ことが可能となる。  By adopting such a manufacturing method, it becomes possible to form the element structure of the second embodiment.

[0148] (第二の実施形態の第五の製造方法） (Fifth Manufacturing Method of Second Embodiment)

半導体層 3の上部に空洞 12よりなる低誘電率領域 10を設ける製造方法、および半 導体層 3の上部に設けた空洞 12に低誘電率材料を坦め戻して半導体層 3の上部に 低誘電率領域 10を設ける製造方法について、図 22から図 27を参照して、より詳しく 説明する。 A manufacturing method in which a low dielectric constant region 10 formed of a cavity 12 is provided above the semiconductor layer 3, and a low dielectric material is carried back into the cavity 12 provided above the semiconductor layer 3 so as to be provided above the semiconductor layer 3. The manufacturing method for providing the low dielectric constant region 10 will be described in more detail with reference to FIGS.

[0149] シリコンよりなる支持基板 1、その上に Si〇よりなる埋め込み絶縁層 2、さらにその上 に単結晶シリコンよりなる半導体層 3が積層した S〇I基板上に、ダミー層 11を堆積す る。ダミー層 11は例えば CVD法により堆積した Si N膜とする。これにより図 22の形 態が得られる。なお、ダミー層 11と半導体層 3の間にダミー層 11とは異なる絶縁膜よ りなるパッド絶縁膜、たとえば熱酸化によって形成した Si〇膜よりなるパッド絶縁膜を 形成しておいても良い。  [0149] A dummy layer 11 is deposited on an S〇I substrate in which a support substrate 1 made of silicon, a buried insulating layer 2 made of Si〇, and a semiconductor layer 3 made of single crystal silicon are further stacked thereon. You. The dummy layer 11 is, for example, a SiN film deposited by a CVD method. As a result, the configuration shown in FIG. 22 is obtained. A pad insulating film made of an insulating film different from the dummy layer 11, for example, a pad insulating film made of a Si film formed by thermal oxidation may be formed between the dummy layer 11 and the semiconductor layer 3.

[0150] 次に、通常のリソグラフイエ程及び RIE等の通常のエッチング工程により、ダミー層  Next, a dummy layer is formed by a normal lithography process and a normal etching process such as RIE.

11及び半導体層 3をパターユングして図 23の形状を得る。なお、ダミー層 11及び半 導体層 3は、ともにフォトレジストをマスクにエッチングすることによりパターユングして も良ぐあるいはフォトレジストをマスクにダミー層 11だけをエッチングし、続いてダミ 一層 11をマスクに半導体層 3をエッチングすることによって半導体層 3をパターニン グしても良い。また、ダミー層 11と半導体層 3の間にパッド絶縁膜が設けられる場合 には、パッド絶縁膜も同時にパターニングする。  The shape of FIG. 23 is obtained by patterning 11 and the semiconductor layer 3. The dummy layer 11 and the semiconductor layer 3 may be patterned by etching using a photoresist as a mask, or only the dummy layer 11 may be etched using a photoresist as a mask, and then the dummy layer 11 may be masked. The semiconductor layer 3 may be patterned by etching the semiconductor layer 3 first. When a pad insulating film is provided between the dummy layer 11 and the semiconductor layer 3, the pad insulating film is also patterned at the same time.

[0151] 次に半導体層 3の側面にゲート絶縁膜 4を設けたのち、ポリシリコンを堆積し、これ を通常のリソグラフイエ程及び RIE工程によりエッチングすることによりパターニングし てゲート電極を形成する。続いて、ゲート電極をマスクに高濃度のイオン注入を行い 、熱処理を行うことにより、ゲート電極に覆われない位置の半導体層 3にソース/ドレ イン領域 6を設け、図 24の形状を得る。なお、ゲート絶縁膜は、例えば半導体層 3を 熱酸化することによって設ける。また、ソース/ドレイン領域は垂直方向のイオン注入 、斜めイオン注入、プラズマドーピング等の不純物導入工程によって不純物を導入 することにより形成する。  Next, after providing the gate insulating film 4 on the side surface of the semiconductor layer 3, polysilicon is deposited, and this is etched by a usual lithography process and RIE process to form a gate electrode. Subsequently, high-concentration ion implantation is performed using the gate electrode as a mask, and heat treatment is performed to provide the source / drain region 6 in the semiconductor layer 3 at a position not covered by the gate electrode, thereby obtaining the shape shown in FIG. Note that the gate insulating film is provided, for example, by thermally oxidizing the semiconductor layer 3. The source / drain regions are formed by introducing impurities through an impurity introduction step such as vertical ion implantation, oblique ion implantation, and plasma doping.

[0152] 続いて、ダミー層 11を選択的にエッチングして除去することにより、ダミー層 11を空 洞 12に置きかえる。この時、ゲート電極下部のダミー層 11は図 24 (b)に矢印で示し たように、エッチング液またはエッチングガスが横方向に侵入することによって除去さ れる。ダミー層 11が Si N膜である場合には、エッチング液としてリン酸を用いれば良 レ、。また、空洞 12に隣接する半導体層 3及びゲート電極 5の表面を保護すること、ま たは空洞に隣接する界面に界面準位が発生することを防ぐ目的から、半導体層 3の 空洞 12に隣接する界面またはゲート電極 5の空洞 12に隣接する界面に保護絶縁膜 を設けても良い。半導体層 3の空洞 12に隣接する界面またはゲート電極 5の空洞 12 に隣接する界面を熱酸化して、保護絶縁膜 13を設けた場合の構造を図 25に示す。 なお、図 25 (c)におレ、て、保護絶縁膜 13は省略して描レ、てレ、る（全体が保護絶縁膜 13に覆われるので、保護絶縁膜 13を描くと構造が不明確になるため）。 Next, the dummy layer 11 is replaced with the cavity 12 by selectively etching and removing the dummy layer 11. At this time, the dummy layer 11 below the gate electrode is removed by the lateral penetration of the etching solution or etching gas as shown by the arrow in FIG. When the dummy layer 11 is a SiN film, phosphoric acid may be used as an etchant. In addition, to protect the surfaces of the semiconductor layer 3 and the gate electrode 5 adjacent to the cavity 12, Alternatively, a protective insulating film may be provided at the interface adjacent to the cavity 12 of the semiconductor layer 3 or at the interface adjacent to the cavity 12 of the gate electrode 5 for the purpose of preventing the generation of interface states at the interface adjacent to the cavity. . FIG. 25 shows a structure in which a protective insulating film 13 is provided by thermally oxidizing the interface adjacent to the cavity 12 of the semiconductor layer 3 or the interface adjacent to the cavity 12 of the gate electrode 5. In FIG. 25 (c), the protective insulating film 13 is omitted, and the drawing is omitted. (The entire structure is covered with the protective insulating film 13, so that the structure is not To be clear).

[0153] 続いて、全体に絶縁膜を堆積してこれをエッチバックすることにより、ゲート側壁 14 を設ける。ゲート側壁 14をなす絶縁膜は、例えば Si〇または Si N多層膜、 Si〇及 Subsequently, a gate sidewall 14 is provided by depositing an insulating film on the whole and etching it back. The insulating film forming the gate side wall 14 is, for example, a Si〇 or SiN multilayer film,

2 3 4 2 び Si Nからなる多層膜などからなる。また、ゲート側壁 14をなす絶縁膜は CVD法等 It is composed of a multilayer film composed of 2 3 4 2 and SiN. In addition, the insulating film forming the gate side wall 14 is formed by CVD or the like.

3 4 3 4

の製膜技術によって形成する。続いてソース/ドレイン領域 6の上部、及びゲート電 極 5の上部に金属を堆積し、熱処理することにより、ソース Zドレイン領域 6の上部及 びゲート電極 5の上部にシリサイド層 15を形成する。続いて、層間絶縁膜 16を堆積し 、これを平坦ィ匕したのち、ソース/ドレイン領域 6上部、及びゲート電極 5の上部にコ ンタクトホールを開口し、金属を埋め込むことによりコンタクト 17を形成し、金属よりな る配線 18をコンタクト 17に接続し、図 26及び図 27の形状を得る。但し、図 26 (a)は 図 27の A— A，断面の形状、図 26 (b)は図 27の Β_Β'断面の形状を示す。なお、コン タクト領域への金属の坦め込みと配線となる金属の堆積は同時に行っても良い。な お、コンタクト 17は配線 18の下部に位置する力 図 27においてはその位置を示した  Formed by the film forming technique described above. Subsequently, a metal is deposited on the source / drain region 6 and the gate electrode 5 and heat-treated to form a silicide layer 15 on the source Z drain region 6 and on the gate electrode 5. Subsequently, an interlayer insulating film 16 is deposited and flattened. After that, contact holes are opened in the upper portions of the source / drain regions 6 and the gate electrodes 5, and the contacts 17 are formed by embedding metal. Then, a wiring 18 made of metal is connected to the contact 17 to obtain the shapes shown in FIGS. However, FIG. 26 (a) shows the cross-sectional shape taken along the line AA in FIG. 27, and FIG. 26 (b) shows the cross-sectional shape taken along the line Β_Β ′ in FIG. Note that the filling of the metal into the contact region and the deposition of the metal to be the wiring may be performed simultaneously. The contact 17 is located at the lower part of the wiring 18 and its position is shown in Fig. 27.

[0154] また、本製造方法において、空洞を低誘電率材料で坦め戻しても良い。ここで空洞 に埋める低誘電率材料は、 SiOF等の連続膜であっても良ぐまた多孔質の材料であ つても良い。ダミー層 11を除去して空洞を形成したのち、あるいは空洞及び空洞内 の保護絶縁膜を形成したのち、 CVD法あるいはスピンコート法などで空洞中に低誘 電率材料を埋め込み、低誘電率材料をエッチバックすれば、低誘電率材料はゲート 電極に覆われた部分だけに残る。この構造を図 28に示す。 In the present manufacturing method, the cavities may be back filled with a low dielectric constant material. Here, the low dielectric constant material to be filled in the cavity may be a continuous film such as SiOF or a porous material. After removing the dummy layer 11 to form a cavity, or after forming a cavity and a protective insulating film in the cavity, a low dielectric constant material is buried in the cavity by a CVD method or a spin coating method to form a low dielectric constant material. Etch back the low-k material only in the area covered by the gate electrode. This structure is shown in FIG.

[0155] また、ソース Zドレイン領域に注入した不純物を活性化する熱処理など、高温の熱 処理工程を終えた後で、空洞を低誘電率材料で坦め戻す工程を実施するか、あるい はこれら高温の熱処理工程を終えた後で、空洞の形成及び空洞を低誘電率材料で 坦め戻す工程を実施すると、高温の熱処理が低誘電率材料に化学的または物理的 変化を与えることを防ぐことができる。 [0155] After a high-temperature heat treatment step such as a heat treatment for activating impurities implanted in the source Z drain region, a step of refilling the cavity with a low dielectric constant material is performed, or After completing these high temperature heat treatment steps, the formation of cavities and the cavities are made of low dielectric constant material. Performing the reconstitution step can prevent high-temperature heat treatment from causing a chemical or physical change to the low dielectric constant material.

[0156] このような製造方法を採用することにより、第二の実施形態の素子構造を形成する ことが可能となる。  [0156] By adopting such a manufacturing method, the element structure of the second embodiment can be formed.

[0157] (第二の実施形態の第六の製造方法）  (Sixth Manufacturing Method of Second Embodiment)

半導体層 3の下部に空洞 12よりなる低誘電率領域 10を設ける製造方法、及び半 導体層 3の下部に設けた空洞 12に低誘電率材料を坦め戻して、半導体層 3の下部 に低誘電率領域 10を設ける製造方法について、図 29から図 37を参照して説明する  A manufacturing method in which a low dielectric constant region 10 including a cavity 12 is provided below the semiconductor layer 3, and a low dielectric constant material is returned to the cavity 12 provided below the semiconductor layer 3 so that a low dielectric constant A manufacturing method for providing the dielectric constant region 10 will be described with reference to FIGS. 29 to 37.

[0158] 図 30 (a)、図 31 (a)、図 34は、それぞれ平面図である図 30 (c)、図 31 (c)、図 36の A— A'断面における断面図、図 30 (b)、図 31 (b)、図 35は、それぞれ平面図である 図 30 (c)、図 31 (c)、図 36の B—B '断面における断面図である。また図 32 (a)、図 3 3 (a)は図 30 (a)の断面において工程が進んだ状態での断面図、図 32 (b)、図 33 (b )、図 37は図 30 (b)の断面において工程が進んだ状態での断面図である。 FIGS. 30 (a), 31 (a), and 34 are plan views of FIGS. 30 (c), 31 (c), and 36, respectively. (b), FIG. 31 (b), and FIG. 35 are cross-sectional views taken along line BB ′ of FIG. 30 (c), FIG. 31 (c), and FIG. FIGS. 32 (a) and 33 (a) are cross-sectional views of the cross-section of FIG. 30 (a) in which the process has been advanced, and FIGS. 32 (b), 33 (b), and FIG. It is sectional drawing in the state where the process advanced in the cross section of b).

[0159] 坦め込み絶縁層上にもダミー層 11を設けて半導体層 3の下部にダミー層 11 (20) を設けた基板を用意する（図 29)。そして、半導体層 3を適当な形状にパターニング する際、半導体層の下部のダミー層についても同時にエッチングを施す（図 30、図 3 1)。その後、ゲート電極材料を成膜し、そのゲート電極材料膜を RIE等によりパター ニングすることによりゲート電極 5を形成し、半導体層 3のうちゲート電極 5に覆われて レ、ない領域に高濃度の第一導電型不純物を導入してソース/ドレイン領域 6を形成 する（図 32)。続いてダミー層 11をエッチングにより除去することにより半導体層 3の 下部の領域に空洞 12を形成する（図 33)。その後層間絶縁膜を堆積して、通常の方 法によりコンタクト及び配線を形成する（図 34、図 35、図 36)。  [0159] A substrate provided with a dummy layer 11 (20) below the semiconductor layer 3 by providing a dummy layer 11 also on the embedded insulating layer (FIG. 29). Then, when patterning the semiconductor layer 3 into an appropriate shape, the dummy layer below the semiconductor layer is simultaneously etched (FIGS. 30, 31). After that, a gate electrode material is formed, and the gate electrode material film is patterned by RIE or the like to form a gate electrode 5, and a high concentration is formed in a region of the semiconductor layer 3 which is not covered by the gate electrode 5. The source / drain region 6 is formed by introducing the first conductivity type impurity (FIG. 32). Subsequently, the dummy layer 11 is removed by etching to form a cavity 12 in a region below the semiconductor layer 3 (FIG. 33). After that, an interlayer insulating film is deposited, and contacts and wirings are formed by a usual method (FIGS. 34, 35, and 36).

[0160] ここで、半導体層の下部にダミー層を設け、半導体層の下部のダミー層を除去すれ ば半導体の下部に空洞を持った構造が得られる。また、半導体層 3の上下にダミー 層を設け、半導体層の上下のダミー層を除去すれば半導体の上下に空洞を持つ構 造が得られる。 Here, a structure having a cavity below the semiconductor can be obtained by providing a dummy layer below the semiconductor layer and removing the dummy layer below the semiconductor layer. In addition, a structure having cavities above and below the semiconductor can be obtained by providing dummy layers above and below the semiconductor layer 3 and removing the dummy layers above and below the semiconductor layer.

[0161] なお、半導体層の下部に空洞を設ける際に、半導体層が基板から剥離することを 防ぐためには、ソース/ドレイン領域など、半導体層の下部に空洞を設ける必要が無 レ、領域にぉレ、て、ダミー層の側面をダミー層除去工程にぉレ、てエッチングされなレ、 材料 (例えばダミー層の除去にリン酸を用いる場合は Si〇）で覆うと良い。 [0161] Note that when a cavity is provided below the semiconductor layer, the semiconductor layer may be separated from the substrate. In order to prevent this, it is not necessary to provide a cavity below the semiconductor layer, such as in the source / drain region, the region may not be etched, and the side surfaces of the dummy layer may not be etched by the dummy layer removing step. (For example, when phosphoric acid is used for removing the dummy layer, it is preferable to cover with Si〇).

[0162] また、半導体層 3の下部に設けられたダミー層を SiOより誘電率が低い低誘電率材 料により埋め戻して、半導体層 3の下部に低誘電率領域 10を形成しても良い。  [0162] Further, the low dielectric constant region 10 may be formed under the semiconductor layer 3 by burying the dummy layer provided under the semiconductor layer 3 with a low dielectric constant material having a lower dielectric constant than SiO. .

[0163] このような製造方法を採用することにより、第二の実施形態の素子構造を形成する ことが可能となる。  [0163] By adopting such a manufacturing method, the element structure of the second embodiment can be formed.

[0164] (第二の実施形態の第七の製造方法）  (Seventh Manufacturing Method of Second Embodiment)

半導体層 3の上部及び下部に空洞 12よりなる低誘電率領域 10を形成する製造方 法の例を、図 29から図 37を参照して、より具体的に説明する。  An example of a manufacturing method for forming the low dielectric constant region 10 including the cavity 12 above and below the semiconductor layer 3 will be described more specifically with reference to FIGS.

[0165] 半導体層の下部に空洞または低誘電率領域を設ける場合は、図 22から図 28を参 照して説明した製造方法において、図 29に示すように半導体層 3の上下にダミー層 11を設ける、図 30に示すようにパターユングした半導体層 3の側面に支持絶縁膜 21 を設ける、図 31に示すように一旦支持絶縁膜 21に覆われた半導体層 3の側面をチ ャネル形成領域において露出させるために半導体層 3に対して 2回目のエッチングを 実施する、という変更を加えれば良い。  In the case where a cavity or a low dielectric constant region is provided below the semiconductor layer, in the manufacturing method described with reference to FIGS. 22 to 28, as shown in FIG. The supporting insulating film 21 is provided on the side surface of the patterned semiconductor layer 3 as shown in FIG. 30, and the side surface of the semiconductor layer 3 once covered with the supporting insulating film 21 is formed as a channel forming region as shown in FIG. The second etching may be performed on the semiconductor layer 3 so that the semiconductor layer 3 is exposed.

[0166] 図 30 (a)、図 31 (a)、図 34は、それぞれ平面図である図 30 (c)、図 31 (c)、図 36の A— A'断面における断面図、図 30 (b)、図 31 (b)、図 34 (b)は、それぞれ平面図で ある図 30 (c)、図 31 (c)、図 36の B-B'断面における断面図である。また図 32 (a)、 図 33 (a)は図 30 (a)の断面において工程が進んだ状態での断面図、図 32 (b)、図 3 3 (b) ,図 37は図 30 (b)の断面において工程が進んだ状態での断面図である。  FIGS. 30 (a), 31 (a), and 34 are plan views of FIGS. 30 (c), 31 (c) and 36, respectively, and are sectional views taken along line A--A 'of FIG. (b), FIG. 31 (b), and FIG. 34 (b) are cross-sectional views taken along line BB ′ of FIG. 30 (c), FIG. 31 (c), and FIG. FIGS. 32 (a) and 33 (a) are cross-sectional views of the cross-section of FIG. 30 (a) in a state where the process has been advanced, and FIGS. 32 (b), 33 (b) and 37 are FIGS. It is sectional drawing in the state where the process advanced in the cross section of b).

[0167] シリコンよりなる支持基板 1、その上に Si〇よりなる埋め込み絶縁層 2、その上に下 部ダミー層 20、さらにその上に単結晶シリコンよりなる半導体層 3が積層した S〇I基 板上に、上部ダミー層 19を堆積する。上部ダミー層 19及び下部ダミー層 20は例え ば Si N膜とする。これにより図 29の形態が得られる。なお、単にダミー層 11をレ、う場 合は、上部ダミー層 19及び下部ダミー層 20の双方を指すものとする。  [0167] An S〇I-based substrate having a support substrate 1 made of silicon, a buried insulating layer 2 made of Si 上, a lower dummy layer 20 thereon, and a semiconductor layer 3 made of single-crystal silicon stacked thereon An upper dummy layer 19 is deposited on the plate. The upper dummy layer 19 and the lower dummy layer 20 are, for example, SiN films. As a result, the configuration shown in FIG. 29 is obtained. When the dummy layer 11 is simply referred to, it refers to both the upper dummy layer 19 and the lower dummy layer 20.

[0168] 次に、通常のリソグラフイエ程及び RIE等の通常のエッチング工程により、上部ダミ 一層 19、半導体層 3及び下部ダミー層 20をパターニングする。次に全体に支持絶縁 膜 21を堆積し、これをエッチバックし、図 30の形状を得る。次にチャネルが形成され る領域において半導体層 3の側面を露出するように、チャネルが形成される領域周辺 において、上部ダミー層 19、半導体層 3、下部ダミー層 20の積層構造を、支持絶縁 膜 21に隣接する部分においてエッチングして除去する。この工程により得られる形状 を図 31に示す。 Next, the upper dummy layer 19, the semiconductor layer 3, and the lower dummy layer 20 are patterned by a normal lithography process and a normal etching process such as RIE. Next, support insulation throughout A film 21 is deposited and etched back to obtain the shape shown in FIG. Next, the laminated structure of the upper dummy layer 19, the semiconductor layer 3, and the lower dummy layer 20 is formed around the region where the channel is formed so that the side surface of the semiconductor layer 3 is exposed in the region where the channel is formed. The portion adjacent to 21 is etched away. FIG. 31 shows the shape obtained by this step.

[0169] 以下、図 24から図 27を参照して説明した工程と同じ工程を実施してトランジスタを 完成させる。なお、図 32は図 24に、図 33は図 25に、図 34、図 35、図 36はそれぞれ 図 26 (a)、図 26 (b)、図 27に対応し、それぞれに対応する図面の形状を形成するェ 程が実施されることにより形成される形状を示す。  Hereinafter, the same steps as the steps described with reference to FIGS. 24 to 27 are performed to complete the transistor. FIG. 32 corresponds to FIG. 24, FIG. 33 corresponds to FIG. 25, and FIGS. 34, 35 and 36 correspond to FIGS. 26 (a), 26 (b) and 27, respectively. It shows the shape formed by performing the step of forming the shape.

[0170] 各工程における特徴を説明すると、半導体層 3の側面にゲート絶縁膜を形成したの ち、ゲート電極材料を堆積し、ゲート電極材料を加工してゲート電極を形成し、ソース /ドレイン領域 6に不純物を導入する工程では、半導体層の上部に上部ダミー層 19 、下部に下部ダミー層 20が形成されている（図 32)。また、ダミー層を除去して空洞 1 2形成する工程により、空洞 12は半導体層の上下に形成される。また、空洞内に保 護絶縁膜 13を設ける場合は保護絶縁膜 13は半導体層の上下に形成される（図 33、 図 34、図 35、図 37)。なお、図 34、図 35、図 36、図 37は、シリサイド層、層間絶縁 膜、コンタクト及び配線の形成を終えた状態を示す。また、半導体層 3の下部におい ては空洞部は半導体層全体にわたって形成されても良く（図 33、図 35)、またゲート 電極下部の一部の領域だけにおいて、半導体層 3の下部に空洞が形成されても良 レ、（図 37)。製造方法としては、下部ダミー層をすベて除去しても良ぐまた、下部ダミ 一層はゲート電極の下部に位置する一部の領域だけで除去しても良い。  [0170] The feature of each step is as follows. After forming a gate insulating film on the side surface of the semiconductor layer 3, a gate electrode material is deposited, and the gate electrode material is processed to form a gate electrode. In the step of introducing impurities into 6, an upper dummy layer 19 is formed above the semiconductor layer, and a lower dummy layer 20 is formed below the semiconductor layer (FIG. 32). Further, the cavity 12 is formed above and below the semiconductor layer by the step of forming the cavity 12 by removing the dummy layer. When the protective insulating film 13 is provided in the cavity, the protective insulating film 13 is formed above and below the semiconductor layer (FIGS. 33, 34, 35, and 37). FIGS. 34, 35, 36, and 37 show a state in which the formation of the silicide layer, the interlayer insulating film, the contact, and the wiring has been completed. In addition, a cavity may be formed over the entire semiconductor layer below the semiconductor layer 3 (FIGS. 33 and 35), and a cavity may be formed below the semiconductor layer 3 only in a part of the region below the gate electrode. It may be formed (Fig. 37). As a manufacturing method, the lower dummy layer may be entirely removed, or the lower dummy layer may be removed only in a part of the region located below the gate electrode.

[0171] また、支持絶縁膜 21を設ける目的は、半導体層の下部の下部ダミー層 20が除去さ れて空洞が形成された状態で、半導体層を支持することである。従って、ゲート電極 下部の一部の領域だけにおいて半導体層 3の下部に空洞が形成される場合（図 37) や、ゲート電極 5と埋め込み絶縁膜 2の接触面における接続によって半導体層を支 持するために充分な機械的強度が得られる場合は、支持絶縁膜 21を省略しても良 レ、。  [0171] The purpose of providing the supporting insulating film 21 is to support the semiconductor layer in a state where the lower dummy layer 20 below the semiconductor layer is removed to form a cavity. Therefore, when a cavity is formed below the semiconductor layer 3 only in a part of the region below the gate electrode (FIG. 37), the semiconductor layer is supported by the connection at the contact surface between the gate electrode 5 and the buried insulating film 2. Therefore, when sufficient mechanical strength is obtained, the supporting insulating film 21 may be omitted.

[0172] このような製造方法を採用することにより、第二の実施形態の素子構造を形成する ことが可能となる。 [0172] By adopting such a manufacturing method, the element structure of the second embodiment is formed. It becomes possible.

[0173] [効果]  [0173] [Effect]

本実施形態においては、半導体層上部に位置する一部の部分、あるいは半導体 層下部に位置する一部の部分、あるいは半導体層上部及び下部に位置する部分が 、 SiOよりも誘電率の低い材料よりなる領域である低誘電率領域によって置きかえら In this embodiment, a portion located above the semiconductor layer, a portion located below the semiconductor layer, or a portion located above and below the semiconductor layer has a lower dielectric constant than SiO. By the low dielectric constant region

2 2

れる。低誘電率領域はゲート電極と半導体層との電界を緩和する作用があるので、 半導体層上部に位置する一部の部分を低誘電率領域によって置きかえると、半導体 層上部コーナー部 34 (図 82、図 83)における電位上昇が抑制され、寄生トランジスタ の発生が抑制されて、トランジスタの特性が向上する。また、寄生トランジスタは下部 コーナー部 35 (図 82、図 83)においても発生するが、半導体層下部に位置する一部 の部分を低誘電率領域によって置きかえると、半導体層下部コーナー部における電 位上昇が抑制され、寄生トランジスタの発生が抑制され、トランジスタの特性が向上 する。  It is. Since the low dielectric constant region has a function of relaxing the electric field between the gate electrode and the semiconductor layer, if a portion located above the semiconductor layer is replaced by the low dielectric constant region, the upper corner portion of the semiconductor layer 34 (FIG. 82, The rise in potential in FIG. 83) is suppressed, the occurrence of parasitic transistors is suppressed, and transistor characteristics are improved. Parasitic transistors also occur in the lower corners 35 (Figs. 82 and 83), but if the lower part of the semiconductor layer is replaced by a low dielectric constant region, the potential rise in the lower corners of the semiconductor layer will increase. Is suppressed, the occurrence of a parasitic transistor is suppressed, and the characteristics of the transistor are improved.

[0174] より具体的な例として FinFETの半導体層の上部を空洞とした場合の電位分布を 図 39に示す。  [0174] As a more specific example, Fig. 39 shows a potential distribution in the case where a cavity is formed above the semiconductor layer of FinFET.

[0175] 図 84(a)及び図 84 (b)に比べると、コーナー部での等電位線の湾曲が著しく低減さ れており、コーナー部での電位上昇が抑制されている。これはコーナー部の寄生トラ ンジスタが抑制されていることを示す。  [0175] Compared with Fig. 84 (a) and Fig. 84 (b), the curvature of equipotential lines at the corners is significantly reduced, and the potential rise at the corners is suppressed. This indicates that the parasitic transistor at the corner is suppressed.

[0176] 図 9 (b)と同様に半導体層側面における電位分布をプロットしたものを図 54に示す 。なお、図 54 (a)は図 83のダブルゲート構造、図 54 (b)は図 82のトライゲート構造、 図 54 (c)は図 10 (a)の構造で、半導体層 3の上部に空洞が設けられた場合である。 図中の数字は半導体層上端での電位上昇量であり、図 10 (a)の構造では 63. 4mV である。この値は通常ダブルゲート構造の場合（186mV)、通常トライゲート構造の 場合（358mV)に比べて小さぐ本実施形態による寄生トランジスタ抑制効果は顕著 である。  FIG. 54 shows a plot of the potential distribution on the side surface of the semiconductor layer as in FIG. 9B. FIG. 54 (a) shows the double gate structure in FIG. 83, FIG. 54 (b) shows the tri-gate structure in FIG. 82, and FIG. 54 (c) shows the structure in FIG. 10 (a). Is provided. The number in the figure is the amount of potential rise at the upper end of the semiconductor layer, which is 63.4 mV in the structure of FIG. This value is smaller in the case of the normal double gate structure (186 mV) than in the case of the normal tri-gate structure (358 mV), and the parasitic transistor suppressing effect according to the present embodiment is remarkable.

[0177] なお、 FinFETにおける寄生トランジスタの発生は、半導体層の上部コーナーにお いて、下部コーナーに比べて顕著であるので、低誘電率領域を半導体層の上部に 設けること（図 10 (a)、図 10 (b)、図 11 (a)、図 12、図 13)が特に望ましい。また、寄 生トランジスタは下部コーナーにおいても発生するので、低誘電率領域を半導体層 の上部及び下部の両方に設けることがさらに望ましい（図 10 (b)、図 11 (a)、図 13 (b[0177] Since the occurrence of parasitic transistors in FinFETs is more prominent at the upper corner of the semiconductor layer than at the lower corner, a low dielectric constant region must be provided above the semiconductor layer (Fig. 10 (a) 10 (b), 11 (a), 12 and 13) are particularly desirable. In addition, Since a raw transistor also occurs at the lower corner, it is more desirable to provide a low dielectric constant region both above and below the semiconductor layer (see FIGS. 10 (b), 11 (a), and 13 (b)).

) )。 )).

[0178] また、キャップ絶縁層を低誘電率領域により形成するか、あるいはキャップ絶縁層の 一部を低誘電率材料により形成すると、ドレインからキャップ絶縁層を通ってチャネル に至る電界を抑制する作用も得られる。また、坦め込み絶縁膜を低誘電率領域で置 きかえる力、、あるいは埋め込み絶縁膜の一部を低誘電率材料で置きかえると、ドレイ ンから埋め込み絶縁膜を通ってチャネルに至る電界を抑制する作用も得られる。  [0178] When the cap insulating layer is formed using a low dielectric constant region or part of the cap insulating layer is formed using a low dielectric constant material, an action of suppressing an electric field from a drain to a channel through the cap insulating layer and the cap insulating layer. Is also obtained. Also, by replacing the buried insulating film in the low dielectric constant region or by replacing part of the buried insulating film with a low dielectric constant material, the electric field from the drain through the buried insulating film to the channel is suppressed. The effect of this is obtained.

[0179] ドレインからキャップ絶縁層あるいは坦め込み絶縁膜を通してチャネルに至る電界 は DIBL (ドレイン誘起障壁低下、ドレイン 'インデュースド 'バリア'ロアリング）と呼ば れるしきい電圧変動を始め短チャネルトランジスタにおける様々な特性劣化の原因と なるので、本実施形態は DIBLによるしきい値変動を抑制するなど、短チャネルトラン ジスタの特性を改善するという作用も持つ。  [0179] The electric field from the drain to the channel through the cap insulating layer or the filled insulating film causes a threshold voltage fluctuation called DIBL (drain-induced barrier lowering, drain 'induced' barrier 'lowering) to occur in short-channel transistors. The present embodiment also has the effect of improving the characteristics of the short-channel transistor, such as suppressing threshold value fluctuation due to DIBL, because it causes various characteristics degradation.

[0180] また、キャップ絶縁層 8を SiOよりも誘電率が低い材料で形成することに加えて、ゲ ート側壁 14も SiOよりも誘電率が低い材料で形成すると、 DIBLによるしきい値変動 の抑制など、短チャネルトランジスタの特性を改善するという作用をより強めることが できる。  [0180] In addition to forming the cap insulating layer 8 with a material having a dielectric constant lower than that of SiO and also forming the gate side wall 14 with a material having a dielectric constant lower than that of SiO, the threshold variation due to DIBL can be improved. And the effect of improving the characteristics of the short-channel transistor, such as suppression of the noise, can be enhanced.

[0181] また FinFETの下部に空洞を設ける場合、 FinFETにおける寄生トランジスタの抑 制という効果以外に、空洞上に設けられるトランジスタの性能向上効果として次のよう な効果が得られる。通常のプレーナ型の電界効果型トランジスタにおいて、半導体層 の下に空洞を設けることにより、寄生容量の低減、短チャネル効果の抑制を狙った構 造が従来提案されているが、本発明の構造では、縦型のチャネルに隣接したゲート 電極が空洞下部の坦め込み絶縁層に達するという特徴を有する。このため、チヤネ ノレ領域で発生した熱がゲート電極を経由して支持基板側に逃げやすいとレ、う長所を 持つ。また、チャネルが半導体側面にあるため、チャネル幅が大きい場合でも、空洞 でない領域とゲート電極が接触する領域同士の間隔を小さくでき、空洞でない領域と ゲート電極が接触する領域の密度を上げられるので、チャネル領域で発生した熱が ゲート電極を経由して基板側へ放出することが容易となる。図 38 (a)はプレーナ型の 従来構造の場合、図 38 (b)及び図 38 (c)が本発明の構造の場合である。なお、図 3 8 (c)は図 75のように複数の半導体層が配列する場合である。なお、図 38 (b)は図 3 6の A— A '断面に相当する位置での断面図、図 38 (b)は図 75の A— A '断面に相当 する位置での断面図、図 38 (a)はプレーナ型トランジスタのゲート電極に覆われたチ ャネル領域の、チャネル幅方向の断面である。なお、図 38中の矢印（記号 33)は、熱 の流れを表わし、記号 32はフィールド絶縁膜を表す。 When a cavity is provided below the FinFET, the following effect can be obtained as an effect of improving the performance of the transistor provided above the cavity, in addition to the effect of suppressing the parasitic transistor in the FinFET. Conventional planar-type field-effect transistors have conventionally been proposed to have a structure in which a cavity is provided below the semiconductor layer to reduce parasitic capacitance and suppress the short-channel effect. The feature is that the gate electrode adjacent to the vertical channel reaches the buried insulating layer below the cavity. This has the advantage that heat generated in the channel region can easily escape to the support substrate side via the gate electrode. In addition, since the channel is on the side surface of the semiconductor, even when the channel width is large, the distance between the non-hollow region and the region where the gate electrode contacts can be reduced, and the density of the non-hollow region and the region where the gate electrode contacts can be increased. In addition, heat generated in the channel region can be easily released to the substrate side via the gate electrode. Figure 38 (a) shows a planar type In the case of the conventional structure, FIGS. 38 (b) and 38 (c) show the case of the structure of the present invention. FIG. 38 (c) shows a case where a plurality of semiconductor layers are arranged as shown in FIG. FIG. 38 (b) is a cross-sectional view at a position corresponding to the AA ′ cross section in FIG. 36, and FIG. 38 (b) is a cross-sectional view at a position corresponding to the AA ′ cross section in FIG. 75. 38 (a) is a cross section in the channel width direction of a channel region covered with a gate electrode of a planar transistor. The arrow (symbol 33) in FIG. 38 indicates the flow of heat, and the symbol 32 indicates a field insulating film.

[0182] (第三の実施形態、第四の実施形態及び第五の実施形態に共通する特徴） (Features Common to Third, Fourth, and Fifth Embodiments)

[構造]  [Construction]

第三の実施形態、第四の実施形態及び第五の実施形態に共通する特徴を図 41、 図 55、図 56、図 57、図 59、図 60、図 66、図 67、図 68、図 69を参照して説明する。 図 41、図 55、図 56、図 57、図 59、図 60、図 66、図 67、図 68及び図 69は、従来構 造を説明する図 81の A— A'断面に相当する位置における断面図であり、従来構造 を説明する図 82 (a)及び図 83 (a)が示す断面に相当する断面における断面図であ る。  Features common to the third, fourth, and fifth embodiments are shown in FIGS. 41, 55, 56, 57, 59, 60, 66, 67, 68, and 68. This will be described with reference to FIG. FIGS. 41, 55, 56, 57, 59, 60, 66, 67, 68 and 69 show a conventional structure at a position corresponding to a section taken along the line AA ′ of FIG. 81. FIG. 82 is a cross-sectional view, corresponding to the cross-section shown in FIGS. 82 (a) and 83 (a), illustrating the conventional structure.

[0183] 第三の実施形態、第四の実施形態及び第五の実施形態の FinFETの半導体層 3 は基板面から突起した形態をもち、半導体層 3の両側面にはゲート絶縁膜 4を介して ゲート電極が設けられる。  [0183] The semiconductor layer 3 of the FinFET of the third, fourth, and fifth embodiments has a form protruding from the substrate surface, and the gate insulating film 4 is provided on both sides of the semiconductor layer 3 via the gate insulating film 4. A gate electrode is provided.

[0184] 半導体層には、半導体層主要部領域 43と、半導体層主要部領域 43の上部または 下部の少なくとも一方に設けられる半導体層端部領域 44が含まれる。  The semiconductor layer includes a semiconductor layer main portion region 43 and a semiconductor layer end region 44 provided on at least one of an upper portion and a lower portion of the semiconductor layer main portion region 43.

[0185] 半導体層主要部領域 43とは、二つのソース/ドレイン領域を結ぶ方向と垂直な面 内における半導体層の幅 Wfinが半導体層端部領域 44より大きい領域である。  The semiconductor layer main portion region 43 is a region in which the width Wfin of the semiconductor layer in a plane perpendicular to the direction connecting the two source / drain regions is larger than the semiconductor layer end region 44.

[0186] 半導体層端部領域 44とは、二つのソース/ドレイン領域を結ぶ方向と垂直な面内 における半導体層の幅 Wfinが半導体層主要部領域 43の幅より小さい領域、または 二つのソース/ドレイン領域を結ぶ方向と垂直な面内における半導体層の幅 Wfinが 半導体層主要部領域 43から離れるに従って半導体層主要部領域 43の幅より小さく 遷移する領域の二つの領域のうち一方の領域または両方の領域から構成され、半導 体層 3とゲート電極 5の間に端部絶縁体領域 27が設けられる領域である。  [0186] The semiconductor layer end region 44 is a region in which the width Wfin of the semiconductor layer in a plane perpendicular to the direction connecting the two source / drain regions is smaller than the width of the semiconductor layer main region 43, or the two source / drain regions. The width Wfin of the semiconductor layer in a plane perpendicular to the direction connecting the drain regions becomes smaller than the width of the semiconductor layer main region 43 as the distance from the semiconductor layer main region 43 increases, and one or both of the two regions of the transition region transition. This is a region in which an end insulator region 27 is provided between the semiconductor layer 3 and the gate electrode 5.

[0187] 端部絶縁体 27とは、半導体層 3とゲート電極 5の間に設けられ、絶縁体の最大の幅 We^ゲート絶縁膜 4の厚さよりも大きい絶縁体である。 [0187] The end insulator 27 is provided between the semiconductor layer 3 and the gate electrode 5, and has a maximum width of the insulator. We ^ is an insulator larger than the thickness of the gate insulating film 4.

[0188] ゲート電極 5は適当な寸法にパターニングされており、ゲート電極に覆われない位 置の半導体層には第一導電型の不純物が高濃度に導入されたソース/ドレイン領 域 6が形成される。ゲート電極 5に覆われた半導体層であるチャネル形成領域 7には 、ゲート電極 5に適当な電圧を印加することにより第一導電型のキャリアよりなるチヤ ネルが形成される。ゲート電極 5、ソース/ドレイン領域 6にはコンタクト領域を介して 配線が接続される。  [0188] The gate electrode 5 is patterned into an appropriate size, and a source / drain region 6 in which impurities of the first conductivity type are introduced at a high concentration is formed in the semiconductor layer at a position not covered by the gate electrode. Is done. In the channel forming region 7, which is a semiconductor layer covered by the gate electrode 5, a channel made of carriers of the first conductivity type is formed by applying an appropriate voltage to the gate electrode 5. Wiring is connected to the gate electrode 5 and the source / drain region 6 via a contact region.

[0189] 第三の実施形態、第四の実施形態及び第五の実施形態は半導体層 3の上部界面 がチャネルとしてほとんど寄与しない構造であるダブルゲート構造のトランジスタに適 用されても良く（図 41)、半導体層 3の上部界面にチャネルが形成される構造であるト ライゲート構造（図 42 (a) )のトランジスタに適用されても良レ、。なお、図 42 (a)のよう に半導体層端部領域 44、半導体層主要部領域 43の記号を図面中に省略している 場合は、半導体層 3のうち側面が端部絶縁体領域 27に接している部分が半導体層 端部領域 44、半導体層 3のうち側面が端部絶縁体領域 27に接しておらず、ゲート絶 縁膜に接している部分が半導体層主要部領域 43である。  The third, fourth, and fifth embodiments may be applied to a transistor having a double gate structure in which the upper interface of the semiconductor layer 3 hardly contributes as a channel (see FIG. 41), which can be applied to a transistor having a tri-gate structure (FIG. 42 (a)) in which a channel is formed at the upper interface of the semiconductor layer 3. When the symbols of the semiconductor layer end region 44 and the semiconductor layer main region 43 are omitted in the drawing as shown in FIG. 42 (a), the side surface of the semiconductor layer 3 corresponds to the end insulator region 27. The portion in contact is the semiconductor layer end region 44, and the side of the semiconductor layer 3 is not in contact with the end insulator region 27, and the portion in contact with the gate insulating film is the semiconductor layer main region 43.

[0190] 端部絶縁体領域 27は Si〇などの通常の絶縁体でもよぐまた低誘電率材料でも良 ぐまた空洞でも良い。端部絶縁体領域 27として空洞が設けられた場合を図 42 (b) に示す。端部絶縁体領域の全部または一部に SiOよりも誘電率が低い材料、あるい は空洞を用いると、電界集中を緩和する効果が大きくなるのでより好ましい。 [0190] The end insulator region 27 may be a normal insulator such as Si〇, a low dielectric constant material, or a cavity. FIG. 42 (b) shows a case where a cavity is provided as the end insulator region 27. It is more preferable to use a material having a lower dielectric constant than SiO or a cavity for all or a part of the end insulator region because the effect of alleviating electric field concentration is increased.

[0191] また、端部絶縁体領域 27とキャップ絶縁層は同一の材料であっても良ぐ異なる材 料であっても良い。また、端部絶縁体領域 27とキャップ絶縁層が同一の材料である 場合、両者が一体に形成されても良い。端部絶縁体領域 27とキャップ絶縁層が一体 に形成された例を図 42 (c)に示す。 [0191] The end insulator region 27 and the cap insulating layer may be the same material or different materials. When the end insulator region 27 and the cap insulating layer are made of the same material, both may be formed integrally. FIG. 42 (c) shows an example in which the end insulator region 27 and the cap insulating layer are integrally formed.

[0192] また、端部絶縁体領域 27が半導体層 3上のキャップ絶縁体 8と異なる材料であるか 、あるいは同じ材料であっても一体に形成されない場合、端部絶縁体領域 27が半導 体層 3上のキャップ絶縁体 8の一部領域に侵入する構造であっても良レ、。また、端部 絶縁体領域 27が半導体層 3上のゲート絶縁膜 4と異なる材料であるか、あるいは同じ 材料であっても一体に形成されない場合、端部絶縁体領域 27が半導体層 3上のゲ ート絶縁体 4の一部領域に侵入する構造であっても良レ、。端部絶縁体領域 27が半 導体層 3上のキャップ絶縁体 8の一部に侵入する構造を図 43 (a)に示す。 If the end insulator region 27 is made of a different material from the cap insulator 8 on the semiconductor layer 3 or is not formed integrally with the same material, the end insulator region 27 becomes semiconductive. A structure that penetrates into a part of the cap insulator 8 on the body layer 3 is acceptable. If the end insulator region 27 is made of a different material from the gate insulating film 4 on the semiconductor layer 3 or is not formed integrally with the same material, the end insulator region 27 is formed on the semiconductor layer 3. Get Even if the structure penetrates into a part of the heat insulator 4, it is acceptable. FIG. 43A shows a structure in which the end insulator region 27 penetrates a part of the cap insulator 8 on the semiconductor layer 3.

[0193] また、トライゲート構造のトランジスタにおいて、ゲート絶縁膜 4は半導体層 3と端部 絶縁体領域 27を覆うように形成されても良レ、。これは例えば端部絶縁体領域を形成 した後に、ゲート絶縁膜を CVD法などの膜堆積技術によって形成する場合に得られ る構造である。その例を図 43 (b)に示す。  In the transistor having a tri-gate structure, the gate insulating film 4 may be formed so as to cover the semiconductor layer 3 and the end insulator region 27. This is a structure obtained when, for example, a gate insulating film is formed by a film deposition technique such as a CVD method after forming an end insulator region. An example is shown in Figure 43 (b).

[0194] なお、図 42 (a)、図 42 (b)及び図 42 (c)、図 43 (a)及び図 43 (b)は従来構造を説 明する図 81の A— A'断面に相当する位置における断面図であり、従来構造を説明 する図 82 (a)及び図 83 (a)が示す断面に相当する断面における断面図である。  FIG. 42 (a), FIG. 42 (b) and FIG. 42 (c), FIG. 43 (a) and FIG. 43 (b) are cross-sectional views taken along the line AA ′ of FIG. FIG. 83 is a cross-sectional view at a corresponding position, which is a cross-sectional view corresponding to the cross-section shown in FIGS. 82 (a) and 83 (a) for explaining the conventional structure.

[0195] なお、半導体層主要部領域 43には、加工精度による要因（エッチングの精度）によ り、特に半導体層主要部領域 43中の上端または下端などの一部の領域でその幅が 変化する領域があっても良い。また、半導体領域 29において、加工精度などの要因 により半導体層の幅 Wfinがある程度の限度内（例えばプラスマイナス 20%以内、より 好ましくは 10%以内）におレ、て変化しても良レ、。  [0195] The width of the semiconductor layer main portion region 43 changes due to a factor due to processing accuracy (etching accuracy), particularly in a partial region such as the upper end or the lower end in the semiconductor layer main portion region 43. There may be an area to do. Further, in the semiconductor region 29, the width Wfin of the semiconductor layer may be changed within a certain limit (for example, within ± 20%, more preferably within 10%) due to factors such as processing accuracy. .

[0196] なお、各図面に記載したとおり、端部絶縁体 27とゲート電極 5との界面、ゲート絶縁 膜 4とゲート電極 5の界面が同一面内（断面図においては同一直線状）にあることが、 ゲート電極をカ卩ェする上で最も好ましい。  [0196] As described in each drawing, the interface between the end insulator 27 and the gate electrode 5, and the interface between the gate insulating film 4 and the gate electrode 5 are in the same plane (the same straight line in the cross-sectional view). This is most preferable for controlling the gate electrode.

[0197] しかし、端部絶縁体 27とゲート電極 5との界面力 ゲート絶縁膜 4とゲート電極 5の 界面が同一面内になくとも本発明の効果は得られる。  However, the effects of the present invention can be obtained even if the interface between the end insulator 27 and the gate electrode 5 is not in the same plane as the interface between the gate insulating film 4 and the gate electrode 5.

[0198] [効果]  [0198] [Effect]

第三の実施形態、第四の実施形態及び第五の実施形態においては、半導体層端 部領域において、半導体層とゲート電極の間に、ゲート絶縁膜よりも厚い絶縁体であ る端部絶縁体領域 27が設けられるので、端部絶縁体領域 27によって半導体層のコ ーナ一部（端部絶縁体領域 27が半導体層の上部に設けられた場合は上部コーナー 部、端部絶縁体領域 27が半導体層の下部に設けられた場合は下部コーナー部）に おける電位上昇を抑制し、寄生トランジスタを抑制するので、第一の課題を解決して トランジスタの特性が向上する。  In the third embodiment, the fourth embodiment, and the fifth embodiment, in the semiconductor layer end region, the end insulating film which is an insulator thicker than the gate insulating film is provided between the semiconductor layer and the gate electrode. Since the body region 27 is provided, a part of the corner of the semiconductor layer is formed by the end insulator region 27 (the upper corner portion and the end insulator region when the end insulator region 27 is provided above the semiconductor layer). In the case where 27 is provided below the semiconductor layer, the potential rise in the lower corner portion is suppressed, and the parasitic transistor is suppressed, so that the first problem is solved and the characteristics of the transistor are improved.

[0199] また、コーナー部において半導体層の上面の面方位、半導体層の側面の面方位 のいずれとも大きく異なる面方位が形成されなレ、か、あるいは形成されてもその面は 端部絶縁体に覆われるので、半導体層の上面の面方位、半導体層の側面の面方位 のいずれとも大きく異なる面方位を持った新たな寄生トランジスタが形成されることが なぐ第二の課題が発生しないので良好なトランジスタの特性が得られる。 [0199] Further, the plane orientation of the upper surface of the semiconductor layer and the plane orientation of the side surface of the semiconductor layer in the corner portion If a plane orientation significantly different from any of the above is not formed, or if it is formed, the surface is covered with the end insulator, so that both the plane orientation of the top surface of the semiconductor layer and the plane orientation of the side surface of the semiconductor layer Since the second problem does not occur unless a new parasitic transistor having a greatly different plane orientation is formed, good transistor characteristics can be obtained.

[0200] なお、端部絶縁体領域 27によって半導体層 3のコーナー部の寄生トランジスタを抑 制する効果は、半導体層 3上にキャップ絶縁層 8を持つダブルゲート構造に適用した 場合のほうが、厚い絶縁膜による電界緩和効果がより大きくなるので、トライゲート構 造に適用した場合に比べて大きい。但し、トライゲート構造の場合は、半導体層の上 部にもチャネルが形成されるので、ドレイン電流が大きいという点でダブルゲート構造 よりあ優れる。  [0200] The effect of suppressing the parasitic transistor at the corner of semiconductor layer 3 by end insulator region 27 is thicker when applied to a double-gate structure having cap insulating layer 8 on semiconductor layer 3. Since the effect of relaxing the electric field by the insulating film is greater, the effect is greater than when applied to a tri-gate structure. However, the tri-gate structure is superior to the double-gate structure in that the drain current is large because the channel is also formed above the semiconductor layer.

[0201] (第三の実施形態）  [0201] (Third embodiment)

[構造]  [Construction]

第三の実施形態による電界効果型トランジスタは、第三の実施形態、第四の実施 形態及び第五の実施形態に共通する特徴に加えて、半導体層端部領域 44の一部 分 (好ましくは半導体層端部領域 44の高さの 50%以上）、または半導体層端部領域 44の全部において半導体層の幅 Wtopがほぼ一定 (好ましくは半導体幅の変動量が プラスマイナス 20%以下、より好ましくは半導体幅の変動量がプラスマイナス 10%以 下）であるという特徴を有する。  The field-effect transistor according to the third embodiment has, in addition to the features common to the third, fourth, and fifth embodiments, a part of the semiconductor layer end region 44 (preferably, The width Wtop of the semiconductor layer is almost constant over the entirety of the semiconductor layer end region 44 or more than 50% of the height of the semiconductor layer end region 44 (preferably, the fluctuation amount of the semiconductor width is ± 20% or less, more preferably Has a characteristic that the fluctuation amount of the semiconductor width is ± 10% or less).

[0202] 半導体層主要部領域 43の上部に半導体層端部領域 44が設けられ、半導体層主 要部領域 43が半導体層下部領域 29をなし、半導体層端部領域 44が半導体層上部 領域 28をなす場合を例に、第三の実施形態による電界効果型トランジスタの構造を 図 40及び図 41に示す。なお、図 40 (a)は平面図である図 40 (c)の A— A'断面にお ける断面図、図 40 (b)は平面図である図 40 (c)の B— B '断面における断面図、図 41 は図 40 (a)を拡大して描レ、た断面図である。  [0202] A semiconductor layer end region 44 is provided above the semiconductor layer main region 43, the semiconductor layer main region 43 forms a semiconductor layer lower region 29, and the semiconductor layer end region 44 is a semiconductor layer upper region 28. The structure of the field-effect transistor according to the third embodiment is shown in FIGS. FIG. 40 (a) is a plan view, which is a cross-sectional view taken along the line AA ′ of FIG. 40 (c). FIG. 40 (b) is a plan view, which is a cross-sectional view taken along the line BB ′ 41 is a cross-sectional view of FIG. 40 (a) enlarged.

[0203] 第三の実施形態による FinFETの半導体層は、二つのソース Zドレイン領域を結 ぶ方向と垂直な面内における半導体層の幅が小さい領域である半導体層上部領域 28と、半導体層上部領域 28の下部に位置し、二つのソース Zドレイン領域を結ぶ方 向と垂直な面内における半導体層の幅が大きい領域である半導体層下部領域 29よ りなり、半導体層上部領域 28では半導体層の側面が半導体層下部領域 29における 半導体層の側面よりも後退した形態を持つ。図 41において、記号 Wtopは二つのソ ース/ドレイン領域を結ぶ方向と垂直な面内における半導体層上部領域 28の幅、 記号 Wfinは二つのソース/ドレイン領域を結ぶ方向と垂直な面内における半導体層 下部領域 29の幅を示す。 [0203] The semiconductor layer of the FinFET according to the third embodiment includes a semiconductor layer upper region 28 in which the width of the semiconductor layer is small in a plane perpendicular to the direction connecting the two source Z drain regions, and a semiconductor layer upper region. The semiconductor layer lower region 29, which is located below the region 28 and is a region where the width of the semiconductor layer is large in a plane perpendicular to the direction connecting the two source Z drain regions, In the upper semiconductor layer region 28, the side surface of the semiconductor layer is recessed from the side surface of the semiconductor layer in the lower semiconductor layer region 29. In FIG. 41, the symbol Wtop is the width of the semiconductor layer upper region 28 in a plane perpendicular to the direction connecting the two source / drain regions, and the symbol Wfin is the width in a plane perpendicular to the direction connecting the two source / drain regions. The width of the lower region 29 of the semiconductor layer is shown.

[0204] 半導体層上部領域 28とゲート電極 5の間には、端部絶縁体領域 27が設けられる。  [0204] An end insulator region 27 is provided between the semiconductor layer upper region 28 and the gate electrode 5.

半導体層上部領域 29とゲート電極 5の間には、ゲート絶縁膜 4が設けられる。そして 端部絶縁体領域 27の幅 Weiはゲート絶縁膜の厚さよりも大きい。  The gate insulating film 4 is provided between the semiconductor layer upper region 29 and the gate electrode 5. The width Wei of the end insulator region 27 is larger than the thickness of the gate insulating film.

[0205] ゲート電極 5は適当な寸法にパターニングされており、ゲート電極に覆われない位 置の半導体層には第一導電型の不純物が高濃度に導入されたソース Zドレイン領 域 6が形成される。ゲート電極 5に覆われた半導体層であるチャネル形成領域 7には 、ゲート電極 5に適当な電圧を印加することにより第一導電型のキャリアよりなるチヤ ネルが形成される。ゲート電極 5、ソース/ドレイン領域 6にはコンタクト領域を介して 配線が接続される。  [0205] The gate electrode 5 is patterned to an appropriate size, and a source Z drain region 6 in which impurities of the first conductivity type are introduced at a high concentration is formed in the semiconductor layer at a position not covered by the gate electrode. Is done. In the channel forming region 7, which is a semiconductor layer covered by the gate electrode 5, a channel made of carriers of the first conductivity type is formed by applying an appropriate voltage to the gate electrode 5. Wiring is connected to the gate electrode 5 and the source / drain region 6 via a contact region.

[0206] また、半導体層上部領域 28と半導体層下部領域 29の接続部は、できるだけ急峻 であることが第二の課題を解決する上で最も望ましい。すなわち、半導体層上部領域 28と半導体層下部領域 29のそれぞれの幅が、両者の接続部において不連続に変 化することが最も望ましい。  In order to solve the second problem, it is most desirable that the connection between the semiconductor layer upper region 28 and the semiconductor layer lower region 29 is as steep as possible. That is, it is most desirable that the width of each of the semiconductor layer upper region 28 and the semiconductor layer lower region 29 be discontinuously changed at the connection portion between them.

[0207] なお、半導体層上部領域 28、半導体下部領域 29には、加工の精度などの要因に より、それぞれのうち一部の領域でそれぞれの幅がそれぞれ Wtop、 Wfinと異なる領 域があっても良い。例えば、半導体層上部領域 28の上端または下端、半導体下部 領域 29の上端または下端において半導体層の幅が変化する領域があっても良い。  [0207] In the semiconductor layer upper region 28 and the semiconductor lower region 29, there are regions in which the widths are different from Wtop and Wfin, respectively, in some of the regions due to factors such as processing accuracy. Is also good. For example, there may be a region where the width of the semiconductor layer changes at the upper end or lower end of the semiconductor layer upper region 28 and the upper end or lower end of the semiconductor lower region 29.

[0208] 半導体層上部領域 28のうち、半導体層下部領域 29に接する領域に遷移領域 40 をもっても良い。この例を図 55に示す。遷移領域 40における遷移領域の最小勾配 4 1は 45度以下であることが望ましぐ 25度以下であることが特に望ましい。なお、図 5 5は図 41と同一断面における断面図を示す。なお、遷移領域の最小勾配 41とは遷 移領域 40における半導体層界面が基板面となす角度が最小になる位置において、 遷移領域 40における半導体層界面が基板面となす角度をいう。 [0209] また、半導体層上部領域 28のうち半導体層の幅が一定の領域、または半導体下 部領域 29において、加工精度などの要因により半導体層の幅がある程度の限度内（ しくは Wtopのプラスマイナス 10%以内、 Wfinのプラスマイナス 10%以内）において 変化しても良い。 The transition region 40 may be provided in a region of the semiconductor layer upper region 28 that is in contact with the semiconductor layer lower region 29. This example is shown in FIG. The minimum gradient 41 of the transition region in the transition region 40 is desirably 45 degrees or less, and particularly desirably 25 degrees or less. FIG. 55 shows a cross-sectional view of the same cross section as FIG. Note that the minimum gradient 41 of the transition region refers to the angle between the semiconductor layer interface in the transition region 40 and the substrate surface at the position where the angle between the semiconductor layer interface and the substrate surface in the transition region 40 is minimum. In the semiconductor layer upper region 28, the semiconductor layer has a constant width, or in the semiconductor lower region 29, the width of the semiconductor layer is within a certain limit due to factors such as processing accuracy (or the top of Wtop). (Less than minus 10%, plus or minus 10% of Wfin).

[0210] また、第三の実施形態がトライゲートトランジスタに適用された場合の形態を図 42 ( a)に示す。第三の実施形態において端部絶縁体領域 27として空洞が設けられた場 合を図 42 (b)に示す。端部絶縁体領域 27とキャップ絶縁層が一体に形成された例 を図 42 (c)に示す。端部絶縁体領域 27が半導体層 3上のキャップ絶縁体 8の一部に 侵入する構造を図 43 (a)に示す。ゲート絶縁膜を CVD法などの膜堆積技術によって 形成する場合に得られる構造の例を図 43 (b)に示す。なお、図 42 (a)、図 42 (b)及 び、図 42 (c)、図 43 (a)及び図 43 (b)は従来構造を説明する図 81の A— A'断面に 相当する位置における断面図であり、従来構造を説明する図 82 (a)及び図 83 (a)が 示す断面に相当する断面における断面図である。  FIG. 42 (a) shows an embodiment in which the third embodiment is applied to a tri-gate transistor. FIG. 42 (b) shows a case where a cavity is provided as the end insulator region 27 in the third embodiment. FIG. 42 (c) shows an example in which the end insulator region 27 and the cap insulating layer are integrally formed. FIG. 43A shows a structure in which the end insulator region 27 penetrates a part of the cap insulator 8 on the semiconductor layer 3. Figure 43 (b) shows an example of the structure obtained when the gate insulating film is formed by a film deposition technique such as the CVD method. FIGS. 42 (a), 42 (b), 42 (c), 43 (a) and 43 (b) correspond to a cross section taken along the line AA ′ of FIG. 81 illustrating the conventional structure. FIG. 83 is a cross-sectional view at a position, corresponding to the cross-section shown in FIGS. 82 (a) and 83 (a) for explaining the conventional structure.

[0211] また、半導体層上部領域 28のうち半導体層の幅が一定である位置における端部絶 縁体 27の厚さが一定である場合について主に説明した力 端部絶縁体 27の厚さは 、その最大値がゲート絶縁膜よりも厚ければ、一定でなくともよい。但し、発明の効果 を大きくするためには端部絶縁体 27の厚さが一定である領域において、端部絶縁体 27の厚さは 5nm以上で、かつゲート絶縁膜厚さの 3倍以上であることが好ましぐ端 部絶縁体 27の厚さが 5nm以上で、かつゲート絶縁膜厚さの 5倍以上であることがより 好ましい。  [0211] In addition, the thickness of the force end insulator 27 mainly described in the case where the thickness of the end insulator 27 at the position where the width of the semiconductor layer is constant in the semiconductor layer upper region 28 is constant is described. May not be constant as long as its maximum value is thicker than the gate insulating film. However, in order to enhance the effect of the present invention, in a region where the thickness of the end insulator 27 is constant, the thickness of the end insulator 27 is 5 nm or more and 3 times or more the gate insulating film thickness. More preferably, the thickness of the end insulator 27 is 5 nm or more, and more preferably 5 times or more the thickness of the gate insulating film.

[0212] なお、本明細書においてゲート絶縁膜 4の厚さ、あるいは端部絶縁体 27の厚さとは 、電界の起源であるゲート電極 5と各絶縁膜との界面から垂直方向の厚さを指す。従 つて図 85における半導体層 3の右上部コーナー部を拡大した図面である図 80 (a)に おいては厚さ t2ではなく厚さ tlを指し、図 66の右上部コーナー部を拡大した図面で ある図 80 (b)においては厚さ t4ではなく厚さ t3を指す。  [0212] In the present specification, the thickness of the gate insulating film 4 or the thickness of the end insulator 27 refers to the thickness in the vertical direction from the interface between the gate electrode 5 and each insulating film, which is the origin of the electric field. Point. Therefore, FIG. 80 (a), which is an enlarged view of the upper right corner of the semiconductor layer 3 in FIG. 85, indicates the thickness tl instead of the thickness t2, and shows the enlarged upper right corner of FIG. 66. In Fig. 80 (b), this indicates the thickness t3 instead of the thickness t4.

[0213] 従ってゲート電極 5と端部絶縁体領域 27との界面が図 66や図 80 (b)のように垂直 であれば、端部絶縁体領域 27の幅 Weiとレ、う用語と端部絶縁体領域 27の厚さとレ、う 用語は同義である。 Therefore, if the interface between the gate electrode 5 and the end insulator region 27 is vertical as shown in FIGS. 66 and 80 (b), the width Wei of the end insulator region 27 and the term Thickness of the insulator region 27 The terms are synonymous.

[0214] [製造方法]  [0214] [Manufacturing method]

(第三の実施形態の第一の製造方法）  (First Manufacturing Method of Third Embodiment)

第三の実施形態における製造方法の一例を図 44を参照して説明する。なお、図 4 4は従来例を説明する図 81の A— A'断面に相当する位置における形状を工程を追 つて示したものである。  An example of the manufacturing method according to the third embodiment will be described with reference to FIG. FIG. 44 shows the shape at a position corresponding to the cross section taken along the line AA ′ of FIG. 81 for explaining the conventional example, following the steps.

[0215] 半導体層 3上にキャップ絶縁層 8 (SiO等の絶縁膜層）を堆積し、通常のリソグラフ ィ及び RIE工程によりキャップ絶縁層 8と半導体層 3の上部を所望の幅に加工する（ 図 44 (a) )。次に SiO膜等の絶縁体膜の堆積とエッチバックを行レ、、キャップ絶縁層 の側面及び半導体層 3の側面に、端部絶縁体領域 27を形成する（図 44 (b) )。続い て、キャップ絶縁層 8と端部絶縁体領域 27をマスクに半導体層 3をエッチングする（図 44 (c) )。この工程によって露出した半導体層の側面にゲート絶縁膜 4を設け、続い てゲート電極材料を堆積したのち、通常のリソグラフィ及び RIE工程によりゲート電極 材料を加工してゲート電極 5を形成する。  [0215] A cap insulating layer 8 (an insulating film layer such as SiO) is deposited on the semiconductor layer 3, and the upper portions of the cap insulating layer 8 and the semiconductor layer 3 are processed into a desired width by a normal lithography and RIE process ( Figure 44 (a)). Next, an insulator film such as a SiO film is deposited and etched back, and an end insulator region 27 is formed on the side surface of the cap insulating layer and the side surface of the semiconductor layer 3 (FIG. 44 (b)). Subsequently, the semiconductor layer 3 is etched using the cap insulating layer 8 and the end insulator region 27 as a mask (FIG. 44 (c)). A gate insulating film 4 is provided on the side surface of the semiconductor layer exposed by this step, and subsequently, a gate electrode material is deposited. Then, the gate electrode material is processed by a usual lithography and RIE step to form a gate electrode 5.

[0216] 続いて半導体層 3のうちゲート電極 5に覆われていない領域に高濃度の第一導電 型不純物を導入してソース/ドレイン領域 6を形成する。その後層間絶縁膜を堆積し て、通常の方法によりコンタクト 17及び配線 18を形成する。  Subsequently, a source / drain region 6 is formed by introducing a high-concentration first conductivity type impurity into a region of the semiconductor layer 3 that is not covered by the gate electrode 5. Thereafter, an interlayer insulating film is deposited, and a contact 17 and a wiring 18 are formed by an ordinary method.

[0217] なお、このとき、半導体層 3上にキャップ絶縁層 8 (SiO等の絶縁膜層）を堆積し、 通常のリソグラフィ及び RIE工程によりキャップ絶縁層 8と半導体層 3の上部を所望の 幅に加工する図 44 (a)の工程において、エッチングされて露出した半導体層の上面 が水平でない場合には、図 55のような断面を持った形態が形成されるが、発明の効 果が得られることにはかわりがない。  [0217] At this time, a cap insulating layer 8 (an insulating film layer such as SiO) is deposited on the semiconductor layer 3, and the upper portions of the cap insulating layer 8 and the semiconductor layer 3 are formed to have a desired width by a normal lithography and RIE process. If the top surface of the semiconductor layer exposed by etching is not horizontal in the process of FIG. 44 (a), a form having a cross section as shown in FIG. 55 is formed, but the effect of the invention is obtained. It doesn't change.

[0218] このような製造方法を採用することにより、第三の実施形態の素子構造を形成する ことが可能となる。  [0218] By adopting such a manufacturing method, it is possible to form the element structure of the third embodiment.

[0219] (第三の実施形態の第二の製造方法）  (Second Manufacturing Method of Third Embodiment)

端部絶縁体領域 27を空洞とする場合の製造方法、及び端部絶縁体領域 27の空 洞を絶縁体で埋め戻す場合の製造方法の一例を図 45を参照して説明する。なお、 図 45は従来例を説明する図 81の A— A '断面に相当する位置における形状を工程を 追って示したものである。 An example of a manufacturing method when the end insulator region 27 is a cavity and an example of a manufacturing method when the cavity of the end insulator region 27 is backfilled with an insulator will be described with reference to FIG. FIG. 45 shows a process at a position corresponding to a section taken along line AA ′ of FIG. 81 for explaining a conventional example. It is shown later.

[0220] 半導体層 3上にキャップ絶縁層 8 (SiO等の絶縁膜層）を堆積し、通常のリソグラフ ィ及び RIE工程によりキャップ絶縁層 8と半導体層 3の上部を所望の幅に加工する（ 図 45 (a) )。次に Si N膜などのコーナーダミー層材料の堆積とエッチバックを行い Si [0220] A cap insulating layer 8 (an insulating film layer such as SiO) is deposited on the semiconductor layer 3, and the upper portions of the cap insulating layer 8 and the semiconductor layer 3 are processed into a desired width by a normal lithography and RIE process ( Figure 45 (a)). Next, corner dummy layer material such as SiN film is deposited and etched back

N側壁 37よりなるコーナーダミー層 22をキャップ絶縁層の側面及び半導体層 3の 側面に設ける。続いて Si〇膜等の第二の側壁材料の堆積とエッチバックを行レ、、コ ーナーダミー層 22の側面に、 SiO側壁 38を形成する（図 45 (b) )。続いて、キャップ 絶縁層、 Si N側壁 37よりなるコーナーダミー層、及び SiO側壁 38よりなる第二の側 壁をマスクに半導体層 3をエッチングする（図 45 (c) )。この工程によって露出した半 導体層の側面にゲート絶縁膜 4を設け、続いてゲート電極材料を堆積したのち、通常 のリソグラフィ及び RIE工程によりゲート電極材料を加工してゲート電極 5を形成する 。続いて Si N側壁 37よりなるコーナーダミー層 22を除去すれば、半導体層がゲート 電極から後退した領域に空洞 12よりなる端部絶縁体領域 27が形成される。次に半 導体層 3のうちゲート電極 5に覆われていない領域に高濃度の第一導電型不純物を 導入してソース/ドレイン領域 6を形成する。その後層間絶縁膜を堆積して、通常の 方法によりコンタクト 17及び配線 18を形成する。 The corner dummy layer 22 composed of the N side wall 37 is provided on the side surface of the cap insulating layer and the side surface of the semiconductor layer 3. Subsequently, a second sidewall material such as a Si〇 film is deposited and etched back, and an SiO sidewall 38 is formed on the side surface of the corner dummy layer 22 (FIG. 45B). Subsequently, the semiconductor layer 3 is etched using the cap insulating layer, the corner dummy layer composed of the SiN side wall 37, and the second side wall composed of the SiO side wall 38 as a mask (FIG. 45 (c)). A gate insulating film 4 is provided on the side surface of the semiconductor layer exposed by this step, and subsequently, a gate electrode material is deposited. Then, the gate electrode material is processed by a usual lithography and RIE step to form a gate electrode 5. Subsequently, if the corner dummy layer 22 composed of the SiN side wall 37 is removed, an end insulator region 27 composed of the cavity 12 is formed in a region where the semiconductor layer has receded from the gate electrode. Next, a high concentration first conductivity type impurity is introduced into a region of the semiconductor layer 3 which is not covered with the gate electrode 5 to form a source / drain region 6. Thereafter, an interlayer insulating film is deposited, and a contact 17 and a wiring 18 are formed by an ordinary method.

[0221] なお、 Si Nの堆積とエッチバックに続いて Si〇の堆積とエッチバックを行い第二の 側壁を形成するのは犠牲酸化膜除去工程や半導体層に対する洗浄工程によって、 半導体層の表面が除去されることにより、半導体層の側面が Si N側壁よりも内側に 入り、上部の Si N側壁が水平に突起したオーバーハング形状が形成されることを防 ぐためである、 SiO膜よりなる第二の側壁を設けておけば犠牲酸化膜を除去するェ 程において、第二の側壁も同時に後退するのでオーバーハング形状にならない。な お、ゲート電極を形成する工程に等方性エッチングを追加するなどしてオーバーハ ング形状が許容される場合には、第二の側壁を形成する工程を省略しても良い。 [0221] Note that the deposition and etchback of SiN followed by the deposition and etchback of SiN and the formation of the second sidewall are performed by removing the sacrificial oxide film and cleaning the semiconductor layer. Is formed of an SiO film to prevent the side surface of the semiconductor layer from entering the inner side of the SiN side wall and to prevent the upper SiN side wall from protruding horizontally to form an overhang shape. If the second side wall is provided, in the step of removing the sacrificial oxide film, the second side wall also retreats at the same time, so that it does not have an overhang shape. If the overhanging shape is allowed by adding isotropic etching to the step of forming the gate electrode, the step of forming the second side wall may be omitted.

[0222] また、空洞を低誘電率材料で埋め戻して、低誘電率材料よりなる端部絶縁体領域 2 7を形成しても良レ、。ここで空洞に坦める低誘電率材料は、 SiOF等の連続膜であつ ても良く、また多孔質の材料であっても良い。  [0222] Alternatively, the cavity may be backfilled with a low dielectric constant material to form an end insulator region 27 made of a low dielectric constant material. Here, the low dielectric constant material carried in the cavities may be a continuous film such as SiOF, or may be a porous material.

[0223] また、ソース Zドレイン領域に注入した不純物を活性化する熱処理など、高温の熱 処理工程を終えた後で、空洞を低誘電率材料で坦め戻す工程を実施するか、あるい はこれら高温の熱処理工程を終えた後で、空洞の形成及び空洞を低誘電率材料で 坦め戻す工程を実施すると、高温の熱処理が低誘電率材料に化学的または物理的 変化を与えることを防ぐことができる。 [0223] In addition, a high-temperature heat treatment such as a heat treatment for activating impurities implanted into the source Z drain region. After completing the treatment process, perform a process of refilling the cavity with a low-k material, or after completing these high-temperature heat treatment processes, form the cavity and fill the cavity with a low-k material. Performing the reversion step can prevent high-temperature heat treatment from causing a chemical or physical change in the low-k material.

[0224] このような製造方法を採用することにより、第三の実施形態の素子構造を形成する ことが可能となる。  [0224] By adopting such a manufacturing method, the element structure of the third embodiment can be formed.

[0225] (第三の実施形態の第三の製造方法）  (Third Manufacturing Method of Third Embodiment)

図 46から図 52を参照して第三の実施形態の製造方法の一例をより具体的に説明 する。図 47 (a)、図 48 (a)、図 49 (a)、図 50 (a)は平面図である図 47 (c)、 048 (c) 、図 49 (c)、図 50 (c)の A— A '断面における断面図、図 47 (b)、図 48 (b)、図 49 (b) 、図 50 (b)は平面図である、図 47 (c)、図 48 (c)、図 49 (c)、図 50 (c)の B—B，断面 における断面図である。図 51 (a)及び図 52は図 20 (a)と同一の断面における断面 図、図 51 (b)は図 20 (b)と同一の断面における断面図である。  An example of the manufacturing method according to the third embodiment will be described more specifically with reference to FIGS. Fig. 47 (a), Fig. 48 (a), Fig. 49 (a), Fig. 50 (a) are plan views Fig. 47 (c), 048 (c), Fig. 49 (c), Fig. 50 (c) A—A ′ cross section of FIG. 47 (b), FIG. 48 (b), FIG. 49 (b), and FIG. 50 (b) are plan views, and FIG. 47 (c) and FIG. 48 (c). FIG. 49 (c) and FIG. 50 (c) are cross-sectional views taken along line BB of FIG. FIGS. 51 (a) and 52 are cross-sectional views in the same cross section as FIG. 20 (a), and FIG. 51 (b) is a cross-sectional view in the same cross section as FIG. 20 (b).

[0226] シリコンよりなる支持基板 1、その上に Si〇よりなる埋め込み絶縁層 2、さらにその上 に単結晶シリコンよりなる半導体層 3が積層した SOI基板上に、キャップ絶縁層 8を堆 積する。この状態での断面を図 46に示す。  [0226] A cap insulating layer 8 is deposited on an SOI substrate in which a supporting substrate 1 made of silicon, a buried insulating layer 2 made of Si〇, and a semiconductor layer 3 made of single crystal silicon are further stacked thereon. . FIG. 46 shows a cross section in this state.

[0227] 次に、通常のリソグラフイエ程及び RIE等の通常のエッチング工程により、キャップ 絶縁層 8と半導体層 3のうちの上部をパターユングして図 47の形状を得る。なお、キ ヤップ絶縁層 8及び半導体層 3は、ともにフォトレジストをマスクにエッチングすること によりパターエングしても良ぐあるいはフォトレジストをマスクにキャップ絶縁層 8だけ をエッチングし、続いてキャップ絶縁層 8をマスクに半導体層 3をエッチングすることに よってパターユングしても良レ、。ここで、キャップ絶縁層 8は、その幅が前記半導体層 上部領域 28 (図 41参照）の幅 Wtopとほぼ同じで、前記半導体層下部領域 29の幅 W finよりも狭くなるようにパターユングされる。半導体層 3をエッチングする深さは、ほぼ 半導体層上部領域 28の高さ Htopに等しい。この状態を図 47に示す。  Next, the upper portion of the cap insulating layer 8 and the semiconductor layer 3 is patterned by a normal lithography process and a normal etching process such as RIE to obtain the shape shown in FIG. The cap insulating layer 8 and the semiconductor layer 3 may be patterned by etching using a photoresist as a mask, or only the cap insulating layer 8 may be etched using a photoresist as a mask. The patterning may be performed by etching the semiconductor layer 3 using the mask as a mask. Here, the cap insulating layer 8 is patterned so that its width is substantially the same as the width Wtop of the semiconductor layer upper region 28 (see FIG. 41) and is smaller than the width Wfin of the semiconductor layer lower region 29. You. The etching depth of the semiconductor layer 3 is substantially equal to the height Htop of the semiconductor layer upper region 28. This state is shown in FIG.

[0228] 次に、コーナーダミー層となる材料を堆積してこれをエッチバックすることにより、キ ヤップ絶縁層の側面と半導体層のうちエッチングされて露出された側面に、コーナー ダミー層 22を設ける。コーナーダミー層 22の材料は例えば Si Nとする。この工程に より得られる形態を図 48に示す。 Next, a material to be a corner dummy layer is deposited and etched back to provide a corner dummy layer 22 on the side surface of the cap insulating layer and the exposed side surface of the semiconductor layer. . The material of the corner dummy layer 22 is, for example, SiN. In this process The resulting form is shown in FIG.

[0229] 続いてキャップ絶縁層 8とコーナーダミー層 22をマスクに半導体層 3を RIE等のエツ チング工程によってパターニングして、素子領域を形成する。この工程により得られる 形態を図 49に示す。次にこの工程によって露出した半導体層の側面にゲート絶縁膜 4を設け、続いてゲート電極材料を堆積したのち、通常のリソグラフィ及び RIE工程に よりゲート電極材料を加工してゲート電極 5を形成する。この状態を図 50に示す。  Subsequently, using the cap insulating layer 8 and the corner dummy layer 22 as a mask, the semiconductor layer 3 is patterned by an etching process such as RIE to form an element region. The form obtained by this step is shown in FIG. Next, a gate insulating film 4 is provided on the side surface of the semiconductor layer exposed by this step, and then a gate electrode material is deposited. Then, the gate electrode material is processed by a normal lithography and RIE step to form a gate electrode 5. . This state is shown in FIG.

[0230] 続いて半導体層 3のうちゲート電極 5に覆われていない領域に高濃度の第一導電 型不純物を導入してソース/ドレイン領域 6を形成する。  Subsequently, a source / drain region 6 is formed by introducing a high-concentration first conductivity type impurity into a region of the semiconductor layer 3 which is not covered by the gate electrode 5.

[0231] 続いてコーナーダミー層 22をエッチングにより除去して、端部絶縁体領域 23となる 空洞 24を設ける。  [0231] Subsequently, the corner dummy layer 22 is removed by etching to provide a cavity 24 to be an end insulator region 23.

[0232] 続いて絶縁膜の堆積とエッチバックにより、ゲート電極側面にゲート側壁 14を設け たのちその後層間絶縁膜を堆積して、通常の方法によりコンタクト 17及び配線 18を 形成する。この状態を図 51に示す。  Subsequently, a gate sidewall 14 is provided on the side surface of the gate electrode by depositing and etching back an insulating film, and thereafter, an interlayer insulating film is deposited, and a contact 17 and a wiring 18 are formed by an ordinary method. This state is shown in FIG.

[0233] また、図 47の形状を形成後、コーナーダミー層となる材料を堆積してこれをエッチ バックするかわりに、端部絶縁体領域 23となる材料を堆積してこれをエッチバックす ることにより、キャップ絶縁層の側面と半導体層のうちエッチングされて露出された側 面に、端部絶縁体領域 23を設けても良い。端部絶縁体領域 23の材料は例えば Si〇 とする。あるいは端部絶縁体領域 23の材料は例えば SiOFなどの低誘電率材料と する。この場合、続いてキャップ絶縁層 8と端部絶縁体領域 23をマスクに半導体層 3 を RIE等のエッチング工程によってパターニングして、素子領域を形成する。以後、 コーナーダミー層 22をエッチングにより除去することを除いて、コーナーダミー層 22 を設けた場合と同様の工程を実施することにより、ゲート電極、ソース/ドレイン領域 、配線及びコンタクトを形成する。この場合に得られる形状を図 52に示す。図 52は図 51 (a)と同一の断面における断面図であり、図 51における空洞 24にかえて、端部 Si O領域 25が形成される。  After forming the shape shown in FIG. 47, instead of depositing a material to be a corner dummy layer and etching it back, a material to be an end insulator region 23 is deposited and etched back. Thus, the end insulator region 23 may be provided on the side surface of the cap insulating layer and the side surface of the semiconductor layer which is exposed by etching. The material of the end insulator region 23 is, for example, Si. Alternatively, the material of the end insulator region 23 is a low dielectric constant material such as SiOF. In this case, subsequently, the semiconductor layer 3 is patterned by an etching process such as RIE using the cap insulating layer 8 and the end insulator region 23 as a mask to form an element region. Thereafter, except that the corner dummy layer 22 is removed by etching, the same steps as those in the case where the corner dummy layer 22 is provided are performed to form a gate electrode, source / drain regions, wiring, and contacts. The shape obtained in this case is shown in FIG. FIG. 52 is a cross-sectional view of the same cross section as FIG. 51 (a), and an end SiO 2 region 25 is formed instead of the cavity 24 in FIG.

[0234] このような製造方法を採用することにより、第三の実施形態の素子構造を形成する ことが可能となる。  By employing such a manufacturing method, it is possible to form the element structure of the third embodiment.

[0235] [効果] 本実施形態においては、半導体層上部領域のうち端部に位置する一部の部分が、 端部絶縁体領域 27によって置きかえられる。端部絶縁体領域 27はゲート電極と半 導体層との電界を緩和する作用があるので、半導体層上部コーナー部における電位 上昇が抑制され、寄生トランジスタの発生が抑制され、トランジスタの特性を向上され る。 [0235] [Effect] In the present embodiment, a part of the semiconductor layer upper region located at the end is replaced by the end insulator region 27. Since the end insulator region 27 has a function of relaxing the electric field between the gate electrode and the semiconductor layer, a rise in the potential at the upper corner of the semiconductor layer is suppressed, the occurrence of a parasitic transistor is suppressed, and the characteristics of the transistor are improved. You.

[0236] より具体的な例として、半導体層がゲート電極から後退した領域に空洞を形成した 図 42 (b)の構造における電位分布を図 53に示す。なお、チャネルとなる半導体層の 上端は空洞の下端に隣接する部分である。図 84 (a)及び図 84 (b)に比べると、空洞 下部のコーナー部での等電位線の湾曲が著しく低減されており、コーナー部での電 位上昇が抑制されている。これはコーナー部の寄生トランジスタが抑制されていること を示す。  As a more specific example, FIG. 53 shows a potential distribution in the structure of FIG. 42 (b) in which a cavity is formed in a region where the semiconductor layer is recessed from the gate electrode. Note that the upper end of the semiconductor layer serving as a channel is a portion adjacent to the lower end of the cavity. Compared with Fig. 84 (a) and Fig. 84 (b), the curvature of equipotential lines at the corners below the cavity is significantly reduced, and the potential rise at the corners is suppressed. This indicates that the parasitic transistor at the corner is suppressed.

[0237] 図 9 (b)と同様に半導体層側面における電位分布をプロットしたものを図 54 (d)に 示す。図の左端は空洞の下部における半導体層の上端である。電位上昇は 30. 8m Vまで低減しており、本実施形態がコーナー部での電位上昇を抑制し、コーナー部 の寄生トランジスタが抑制する効果は顕著である。  FIG. 54 (d) shows a plot of the potential distribution on the side surface of the semiconductor layer as in FIG. 9 (b). The left end of the figure is the upper end of the semiconductor layer below the cavity. The potential rise is reduced to 30.8 mV, and this embodiment suppresses the potential rise at the corner and the effect of the parasitic transistor at the corner is remarkable.

[0238] なお、端部絶縁体領域の表面とゲート絶縁膜 4の表面（ゲート電極側の界面を表面 と記す）の位置は揃っていると、ゲート電極を加工しやすくなるので、好ましい。  [0238] It is preferable that the surface of the end insulator region and the surface of the gate insulating film 4 (the interface on the gate electrode side is referred to as surface) be aligned because the gate electrode can be easily processed.

[0239] 但し、両者はプロセス上の理由により一方が他方よりゲート電極側に突起しても、半 導体層上部コーナー部における電位上昇を抑制し、寄生トランジスタを抑制する効 果が得られる。例えば図 49 (a)の構造において、犠牲酸化工程と犠牲酸化膜に対す るウエットエッチング工程により、半導体層 3の側面がコーナーダミー層 22よりゲート 電極側から後退し、その結果図 51 (a)の構造において端部絶縁体領域 23の表面に 比べて、ゲート絶縁膜 4の表面が後退する場合などである。 However, even if one of them protrudes toward the gate electrode side from the other due to process reasons, the effect of suppressing the potential rise at the upper corner portion of the semiconductor layer and suppressing the parasitic transistor can be obtained. For example, in the structure shown in FIG. 49A, the side surface of the semiconductor layer 3 recedes from the gate electrode side with respect to the corner dummy layer 22 due to the sacrificial oxidation step and the wet etching step for the sacrificial oxide film. In this structure, the surface of the gate insulating film 4 recedes as compared with the surface of the end insulator region 23.

[0240] また、半導体層上部領域 28の側面が半導体層下部領域 29の側面に対して後退 せず、ゲート絶縁膜 4よりも厚い端部絶縁体領域 27が、ゲート電極側に突起した構造 を設けても、半導体層上部コーナー部における電位上昇を抑制し、寄生トランジスタ を抑制する効果が得られる。その構造の例を図 89に示す。この構造は、たとえば図 4 4の工程において、図 44 (c)の構造を形成後、第一実施形態の図 4 (a)の工程と同 様に、等方的なエッチングプロセスによってキャップ絶縁層 8及び端部絶縁体領域 2 7に対して選択的に半導体層 3を細らせた場合に得られる。図 90及び図 91に工程の 順を追って、工程中の形態を示す。これらは図 44と同一の断面について描いたもの であり、図 90 (a)、図 90 (b)、図 90 (c)及び図 91 (b)は、それぞれ図 44 (a)、図 44 (b )、図 44 (c)、図 44 (d)の工程に対応する。 In addition, the side surface of the semiconductor layer upper region 28 does not recede with respect to the side surface of the semiconductor layer lower region 29, and the end insulator region 27 thicker than the gate insulating film 4 has a structure protruding toward the gate electrode. Even if it is provided, the effect of suppressing the potential rise in the upper corner portion of the semiconductor layer and suppressing the parasitic transistor can be obtained. Fig. 89 shows an example of the structure. This structure is the same as that of the first embodiment shown in FIG. 4A after the formation of the structure shown in FIG. As described above, this is obtained when the semiconductor layer 3 is selectively narrowed with respect to the cap insulating layer 8 and the end insulator region 27 by an isotropic etching process. FIG. 90 and FIG. 91 show the configuration during the process in the order of the process. These are drawn on the same cross-section as Fig. 44.Fig. 90 (a), Fig. 90 (b), Fig. 90 (c), and Fig. 91 (b) show Fig. 44 (a), Fig. 44 ( b), corresponding to the steps in FIG. 44 (c) and FIG. 44 (d).

[0241] (第四の実施形態） [0241] (Fourth embodiment)

[構造]  [Construction]

第四の実施形態による電界効果型トランジスタは、第三の実施形態、第四の実施 形態及び第五の実施形態に共通する特徴に加えて、半導体層端部領域 44に半導 体層 3の幅が一定な領域を持たないという特徴を持つ。第四の実施形態による電界 効果型トランジスタの半導体層端部領域 44においては、半導体層主要部領域 43と の接続部から遠ざかるに従って、半導体層の幅が狭くなるという形態を持つ。また、 半導体層端部領域 44とゲート電極 5との間に設けられる端部絶縁体領域 27は、半 導体層端部領域 44と半導体層主要部領域 43との接続部力 遠ざ力るに従って厚く なる。端部絶縁体領域 27の膜厚の最大値はゲート絶縁膜厚よりも厚い。  The field effect transistor according to the fourth embodiment has a feature common to the third embodiment, the fourth embodiment, and the fifth embodiment. It has the feature that it does not have a constant width area. The semiconductor layer end region 44 of the field effect transistor according to the fourth embodiment has a form in which the width of the semiconductor layer becomes narrower as the distance from the connection portion with the semiconductor layer main region 43 increases. In addition, the end insulator region 27 provided between the semiconductor layer end region 44 and the gate electrode 5 forms a connection portion force between the semiconductor layer end region 44 and the semiconductor layer main region 43 as the force increases. It becomes thicker. The maximum value of the thickness of the end insulator region 27 is larger than the thickness of the gate insulating film.

[0242] 半導体層主要部領域 43の上部に半導体層端部領域 44が設けられ、半導体層主 要部領域 43が半導体層下部領域 29をなし、半導体層端部領域 44が半導体層上部 領域をなす場合を例に、第四の実施形態による電界効果型トランジスタの構造を図 5 6、図 57、図 59及び図 60に示す。なお、図 56、図 57、図 59及び図 60は従来構造 を説明する図 81の A— A'断面に相当する位置における断面図であり、従来構造を 説明する図 82 (a)及び図 83 (a)が示す断面に相当する断面における断面図である 。なお、記号 Wtopは半導体層端部領域の最小幅、記号 Weiは端部絶縁体領域の最 大幅、記号 Wfinは半導体層主要部領域の幅である。  [0242] A semiconductor layer end region 44 is provided above the semiconductor layer main region 43, the semiconductor layer main region 43 forms a semiconductor layer lower region 29, and the semiconductor layer end region 44 forms a semiconductor layer upper region. FIGS. 56, 57, 59, and 60 show the structure of the field-effect transistor according to the fourth embodiment, taking the case as an example. FIG. 56, FIG. 57, FIG. 59 and FIG. 60 are cross-sectional views taken along the line AA ′ of FIG. 81 illustrating the conventional structure, and FIG. 82 (a) and FIG. FIG. 2 is a cross-sectional view of a cross section corresponding to the cross section shown in FIG. The symbol Wtop is the minimum width of the semiconductor layer edge region, the symbol Wei is the maximum width of the edge insulator region, and the symbol Wfin is the width of the semiconductor layer main region.

[0243] 図 56及び図 57の形態は、キャップ絶縁層 8の下部に位置する半導体上部領域 28 の幅が一定の勾配をもって上部に向うに従って縮小する場合、図 59及び図 60の形 態は、キャップ絶縁層 8の下部に位置する半導体上部領域 28が曲率をもって上部に 向うに従って縮小する場合である。また図 56及び図 59はキャップ絶縁層 8をもつダ ブルゲート構造のトランジスタに第四の実施形態が適用された場合、図 57及び図 60 はキャップ絶縁層 8をもたず半導体層上部界面にゲート絶縁膜 4を持つトライゲート 構造のトランジスタに第四の実施形態が適用された場合である。図 56、図 57、図 59 または図 60のいずれにおいても、半導体上部領域 28とゲート電極 5の間に、端部絶 縁体領域 27が設けられ、端部絶縁体領域 27の少なくとも一部の位置においては、 端部絶縁体領域 27の幅 Wei力 ゲート絶縁膜 4よりも厚い。 [0243] When the width of the semiconductor upper region 28 located under the cap insulating layer 8 is reduced with a constant gradient toward the upper portion, the configurations of Figs. This is a case where the semiconductor upper region 28 located below the cap insulating layer 8 is reduced with curvature toward the upper portion. FIGS. 56 and 59 show FIGS. 57 and 60 when the fourth embodiment is applied to a double-gate transistor having a cap insulating layer 8. The case where the fourth embodiment is applied to a transistor having a tri-gate structure having the gate insulating film 4 at the upper interface of the semiconductor layer without the cap insulating layer 8 is shown. In any of FIG. 56, FIG. 57, FIG. 59 or FIG. 60, an end insulator region 27 is provided between the semiconductor upper region 28 and the gate electrode 5, and at least a part of the end insulator region 27 is provided. At the position, the width of the end insulator region 27 is thicker than the gate insulating film 4.

[0244] (第四の実施形態の第一の製造方法）  (First Manufacturing Method of Fourth Embodiment)

第四の実施形態における製造方法の一例として、図 56の形態を製造する方法を図 58を参照して説明する。なお、図 58は従来例を説明する図 81の A— A'断面に相当 する位置における形状を工程を追って示したものである。  As an example of the manufacturing method according to the fourth embodiment, a method of manufacturing the embodiment of FIG. 56 will be described with reference to FIG. FIG. 58 shows the shape at a position corresponding to the AA ′ cross section of FIG. 81 for explaining the conventional example, step by step.

[0245] 半導体層 3上にキャップ絶縁層 8 (SiO等の絶縁膜層）を堆積し、通常のリソグラフ ィ及び RIE工程によりキャップ絶縁層 8をカ卩ェし、さらに半導体層 3の上部をテーパー を持つように RIEによりエッチングする（図 58 (a) )。次に SiO膜等の絶縁体膜の堆積 とエッチバックを行い、キャップ絶縁層の側面及び半導体層 3の側面に、端部絶縁体 領域 27を形成する（図 58 (b) )。続いて、キャップ絶縁層 8と端部絶縁体領域 27をマ スクに半導体層をエッチングする（図 58 (c) )。この工程によって露出した半導体層の 側面にゲート絶縁膜 4を設け、続いてゲート電極材料を堆積したのち、通常のリソダラ フィ及び RIE工程によりゲート電極材料を加工してゲート電極 5を形成する。  [0245] A cap insulating layer 8 (an insulating film layer of SiO or the like) is deposited on the semiconductor layer 3, the cap insulating layer 8 is removed by a usual lithography and RIE process, and the upper portion of the semiconductor layer 3 is tapered. Etching is performed by RIE so that it has (Fig. 58 (a)). Next, an insulator film such as a SiO film is deposited and etched back to form an end insulator region 27 on the side surface of the cap insulating layer and the side surface of the semiconductor layer 3 (FIG. 58 (b)). Subsequently, the semiconductor layer is etched using the cap insulating layer 8 and the end insulator region 27 as a mask (FIG. 58 (c)). A gate insulating film 4 is provided on the side surface of the semiconductor layer exposed by this step, and after a gate electrode material is deposited, the gate electrode material is processed by a usual lithography and RIE step to form a gate electrode 5.

[0246] なお、半導体層 3の上部をテーパーを持つようにエッチングするには、例えば RIE を行う際に炭素を含むガスを混合するテーパーエッチング技術を用いる。例えば C1 に CHを混合することにより、エッチング中に徐々に炭素化合物を堆積させ、炭素化 合物が堆積した位置ではエッチングが進まないことを利用してテーパー形状を形成 する。 [0246] In order to etch the upper portion of the semiconductor layer 3 so as to have a taper, for example, a taper etching technique of mixing a gas containing carbon when performing RIE is used. For example, by mixing CH with C1, a carbon compound is gradually deposited during etching, and a tapered shape is formed by utilizing the fact that etching does not proceed at the position where the carbon compound is deposited.

[0247] 続いて半導体層 3のうちゲート電極 5に覆われていない領域に高濃度の第一導電 型不純物を導入してソース/ドレイン領域 6を形成する。その後層間絶縁膜を堆積し て、通常の方法によりコンタクト 17及び配線 18を形成する。  Subsequently, a high-concentration first conductivity type impurity is introduced into a region of the semiconductor layer 3 that is not covered with the gate electrode 5, to form a source / drain region 6. Thereafter, an interlayer insulating film is deposited, and a contact 17 and a wiring 18 are formed by an ordinary method.

[0248] なお、図 58 (c)の形状を形成する工程を終えたあとに、 RIE等のエッチング工程に よりキャップ絶縁層 8を除去したのちゲート絶縁膜 4を形成し、続く工程を実施すれば 図 57のようなトライゲート構造が得られる。なお、図 57は RIEによりキャップ絶縁層 8 を除去する際に、端部絶縁膜の上部も同時にエッチングした場合である。なお、 RIE 等のエッチング工程によりキャップ絶縁層 8を除去する場合は、キャップ絶縁層 8より も坦め込み絶縁層 2の厚さが大きいと、キャップ絶縁層のエッチングと同時に埋め込 み絶縁層のエッチングが進行しても、キャップ絶縁層が除去されても坦め込み絶縁 膜の一部が残留し支持基板が露出しない形態が得られるので好ましい。また、坦め 込み絶縁層の全体、表面、またはある深さの層に、キャップ絶縁層に対するエツチン グに耐性のある材料、例えば Si Nを用いると、キャップ絶縁層が除去されても坦め After the step of forming the shape of FIG. 58 (c) is completed, the cap insulating layer 8 is removed by an etching step such as RIE, and then the gate insulating film 4 is formed, and the subsequent steps are performed. Thus, a tri-gate structure as shown in FIG. 57 is obtained. Fig. 57 shows the cap insulating layer 8 by RIE. Is removed, the upper portion of the end insulating film is also etched at the same time. When the cap insulating layer 8 is removed by an etching process such as RIE, if the thickness of the buried insulating layer 2 is larger than that of the cap insulating layer 8, the etching of the buried insulating layer is performed simultaneously with the etching of the cap insulating layer. Even if the etching progresses or the cap insulating layer is removed, a part of the embedded insulating film remains and a form in which the supporting substrate is not exposed is obtained, which is preferable. In addition, if a material that is resistant to etching with respect to the cap insulating layer, for example, SiN, is used for the whole, the surface, or the layer at a certain depth of the filled insulating layer, even if the cap insulating layer is removed, the carrier is not removed.

3 4  3 4

込み絶縁膜の一部が残留し支持基板が露出しない形態が得られるので好ましい。  This is preferable because a part of the embedded insulating film remains and the supporting substrate is not exposed.

[0249] また、図 58の工程において、キャップ絶縁層 8を堆積しない工程を用いても、図 57 のようなトライゲート構造が得られる。この場合はレジストをマスクに半導体層 3をテー パーをつけてエッチングし、図 58 (a)においてキャップ絶縁層 8が無い形状を作成し たのち、ダブルゲート構造のトランジスタを製造する場合と同じ製造方法を実施すれ ば良い。 [0249] Further, even if a step in which the cap insulating layer 8 is not deposited is used in the step of FIG. 58, a tri-gate structure as shown in FIG. 57 is obtained. In this case, the semiconductor layer 3 is taped and etched using a resist as a mask, a shape without the cap insulating layer 8 is created in FIG. 58 (a), and then the same manufacturing process as when manufacturing a double-gate transistor is performed. The method should be implemented.

[0250] (第四の実施形態の第二の製造方法）  (Second Manufacturing Method of Fourth Embodiment)

製造方法の一例を図 61から図 65を参照して説明する。なお、図 61 (a)、図 62 (a) 、図 63 (a)、図 64 (a)はそれぞれ平面図である図 61 (c)、図 62 (c)、図 63 (c)、図 65 における A— A'断面の断面図であり、図 61 (b)、図 62 (b)、図 63 (b)、図 64 (b)はそ れぞれ平面図である図 61 (c)、図 62 (c)、図 63 (c)、図 65における Β_Β'断面の断 面図である。また、本実施形態を説明する各図面の Α— A'断面の位置は従来例を示 す図 81の A - A'断面の位置に、本実施形態を説明する各図面の B - B'断面の位置 は従来例を示す図 81の B— B '断面の位置にそれぞれ相当する。  One example of the manufacturing method will be described with reference to FIGS. FIGS. 61 (a), 62 (a), 63 (a) and 64 (a) are plan views of FIGS. 61 (c), 62 (c), 63 (c) and FIG. 61 (b), FIG. 62 (b), FIG. 63 (b), and FIG. 64 (b) are plan views of FIG. 61 (c). FIG. 66 is a cross-sectional view taken along the line Β_Β ′ of FIGS. 62 (c), 63 (c), and 65. In addition, the position of the Α-A ′ cross section of each drawing explaining the present embodiment is the same as the position of the BB cross section of FIG. 81 correspond to the positions of the cross section BB ′ in FIG. 81 showing the conventional example.

[0251] 第四の実施形態の電界効果型トランジスタを製造するためには、埋め込み絶縁層 2 上の半導体層 3上に例えば Si〇よりなるキャップ絶縁層 8を形成したのち（この時点  In order to manufacture the field-effect transistor of the fourth embodiment, a cap insulating layer 8 made of, for example, Si〇 is formed on the semiconductor layer 3 on the buried insulating layer 2 (at this time,

2  2

での形態は図 2に同じ）、半導体層 3とキャップ絶縁層 8を適当な形状にパターニング する（この時点での形態は図 3に同じ)。続けて、半導体層 3とキャップ絶縁層の界面 、及び半導体層 3と埋め込み絶縁層 2の界面において、半導体層 3の側面がキャップ 絶縁層 8の端部の位置よりも内側に後退するように、半導体層 3を熱酸化する。この 時、半導体層上部及び下部のコーナー部において厚く形成された酸化膜が、端部 絶縁体領域 27になる（図 61)。このような形態が形成されるのは、酸素ガスのなどの 酸化剤はキャップ絶縁層 8ゃ坦め込み絶縁膜を経由して半導体層の上面および下 面にも拡散し、その酸化剤は半導体層の両側面付近により多く拡散するため、半導 体層上部及び下部のコーナー部が丸みを持った形状に酸化されることによる。また、 この時、半導体層 3の側面には犠牲酸化膜層 44が形成される。次に、半導体層 3の 側面には犠牲酸化膜層 44をウエットエッチングなどのエッチング工程により除去し、 図 62の形態を得る。続いて半導体層の側面にゲート絶縁膜 4を設け（図 63)、続いて ゲート電極材料を堆積したのち、通常のリソグラフィ及び RIE工程によりゲート電極材 料をカ卩ェしてゲート電極 5を形成する。続いて半導体層 3のうちゲート電極 5に覆わ れていない領域に高濃度の第一導電型不純物を導入してソース/ドレイン領域を形 成する。その後層間絶縁膜を堆積して、通常の方法によりコンタクト及び配線を形成 する（図 64及び図 65)。 Then, the semiconductor layer 3 and the cap insulating layer 8 are patterned into an appropriate shape (the shape at this point is the same as in FIG. 3). Subsequently, at the interface between the semiconductor layer 3 and the cap insulating layer and at the interface between the semiconductor layer 3 and the buried insulating layer 2, the side surface of the semiconductor layer 3 recedes inward from the position of the end of the cap insulating layer 8, The semiconductor layer 3 is thermally oxidized. At this time, the oxide film thickly formed at the upper and lower corners of the semiconductor layer is This becomes insulator region 27 (Figure 61). This form is formed because the oxidizing agent such as oxygen gas diffuses into the upper and lower surfaces of the semiconductor layer via the cap insulating layer 8 and the insulating film embedded in the insulating layer. This is because the upper and lower corners of the semiconductor layer are oxidized into rounded shapes because they are more diffused near both sides of the layer. At this time, a sacrificial oxide film layer 44 is formed on the side surface of the semiconductor layer 3. Next, the sacrificial oxide film layer 44 is removed from the side surfaces of the semiconductor layer 3 by an etching process such as wet etching to obtain the configuration shown in FIG. Subsequently, a gate insulating film 4 is provided on the side surface of the semiconductor layer (FIG. 63), and after a gate electrode material is deposited, a gate electrode material is formed by a usual lithography and RIE process to form a gate electrode 5. I do. Subsequently, a high-concentration first conductivity type impurity is introduced into a region of the semiconductor layer 3 that is not covered with the gate electrode 5 to form a source / drain region. Thereafter, an interlayer insulating film is deposited, and contacts and wirings are formed by a usual method (FIGS. 64 and 65).

[0252] なお、図 61の形状を形成する工程を終えたあとに、ゲート絶縁膜を形成するよりも 前のある段階おいて RIE等のエッチング工程によりキャップ絶縁層 8を除去して、続く 工程を実施すれば図 60のようなトライゲート構造が得られる。なお、 RIE等のエッチ ング工程によりキャップ絶縁層 8を除去する場合は、キャップ絶縁層 8よりも埋め込み 絶縁層 2の厚さが大きいと、キャップ絶縁層のエッチングと同時に坦め込み絶縁層の エッチングが進行しても、キャップ絶縁層が除去されても埋め込み絶縁膜の一部が 残留し支持基板が露出しない形態が得られるので好ましい。また、埋め込み絶縁層 の全体、表面、またはある深さの層に、キャップ絶縁層に対するエッチングに耐性の ある材料、例えば Si Nを用いると、キャップ絶縁層が除去されても坦め込み絶縁膜 After the step of forming the shape of FIG. 61 is completed, the cap insulating layer 8 is removed by an etching process such as RIE at a certain stage before the formation of the gate insulating film, and a subsequent process is performed. Then, a tri-gate structure as shown in FIG. 60 is obtained. When removing the cap insulating layer 8 by an etching process such as RIE, if the thickness of the buried insulating layer 2 is larger than that of the cap insulating layer 8, the cap insulating layer is etched simultaneously with the etching of the cap insulating layer. This is preferable because a form in which a part of the buried insulating film remains even when the cap insulating layer is removed and the supporting substrate is not exposed can be obtained. Also, if a material that is resistant to etching of the cap insulating layer, for example, SiN, is used for the whole, surface, or a certain depth of the buried insulating layer, even if the cap insulating layer is removed, the embedded insulating film may be removed.

3 4  3 4

の一部が残留し支持基板が露出しない形態が得られるので好ましい。  Is preferable since a form in which a part of the substrate remains and the support substrate is not exposed can be obtained.

[0253] なお、トライゲート構造を形成する際に、キャップ絶縁層がない状態で丸め酸化を 行っても、従来例の図 85のような構造が得られるだけで、ゲート絶縁膜よりも厚いこと を特徴とする端部絶縁体領域 27は形成されないので、発明の効果は得られなレ、。ま た、従来例の図 85のような構造と通常のダブルゲートトランジスタ構造とを単に組み 合わせると、図 70のような形態となり、ゲート絶縁膜よりも厚い端部絶縁体領域 27を 有する構造は得られないため、本発明の効果は得られない。 [0254] なお、この製造方法において、坦め込み絶縁層が酸化剤を拡散しやすい場合、具 体的には埋め込み絶縁層が SiOである場合等には、半導体層下部にも端部絶縁体 領域 27が形成される。坦め込み絶縁層が酸化剤を拡散しにくい場合、具体的には 坦め込み絶縁層が Si Nである場合や、坦め込み絶縁層が SiOであっても膜厚が極 めて薄い場合 (例えば 10nm以下）である場合、半導体層下部には端部絶縁体領域 27が形成されない。 [0253] When a tri-gate structure is formed, even if rounded oxidation is performed without a cap insulating layer, a structure as shown in Fig. 85 of a conventional example can be obtained, and the thickness must be thicker than the gate insulating film. Since the end insulator region 27 is not formed, the effect of the present invention cannot be obtained. Further, if the conventional structure shown in FIG. 85 and the ordinary double gate transistor structure are simply combined, the structure shown in FIG. 70 is obtained, and the structure having the end insulator region 27 thicker than the gate insulating film is obtained. Since it cannot be obtained, the effect of the present invention cannot be obtained. [0254] In this manufacturing method, when the filled insulating layer easily diffuses an oxidizing agent, specifically when the buried insulating layer is SiO, the end insulator is also provided below the semiconductor layer. Region 27 is formed. When the filled insulating layer does not easily diffuse the oxidant, specifically, when the filled insulating layer is SiN, or when the filled insulating layer is SiO, but the film thickness is extremely thin If it is (for example, 10 nm or less), the end insulator region 27 is not formed below the semiconductor layer.

[0255] このような製造方法を採用することにより、第四の実施形態の素子構造を形成する ことが可能となる。  By adopting such a manufacturing method, it becomes possible to form the element structure of the fourth embodiment.

[0256] (効果） [0256] (Effect)

第四の実施形態は、第三の実施形態に比べて半導体層端部領域 44の高さを縮小 できるという長所がある。例えば図 55の半導体層上部領域 28において、遷移領域 4 0よりも上部の半導体層を除去した形態に相当し、構造が単純になるため、半導体層 の高さが縮小される。また、キャップ絶縁層 8に接する領域で半導体層 3を熱酸化す るだけで端部絶縁体領域 27を形成できるなど、製造方法も容易である。  The fourth embodiment has an advantage that the height of the semiconductor layer end region 44 can be reduced as compared with the third embodiment. For example, in the semiconductor layer upper region 28 of FIG. 55, this corresponds to a mode in which the semiconductor layer above the transition region 40 is removed, and the structure is simplified, so that the height of the semiconductor layer is reduced. Further, the manufacturing method is easy, for example, the end insulator region 27 can be formed only by thermally oxidizing the semiconductor layer 3 in the region in contact with the cap insulating layer 8.

[0257] 第四の実施形態は、図 56及び図 59に示した形態においては、半導体層上部領域 と半導体層下部領域の幅が急峻に変化しないため、両者の遷移が急峻な構造を持 つ第三の実施形態に比べて第二の課題を解決する効果にやや劣るが、図 85の従来 例に比べると、本実施形態では半導体層の上部では半導体層とゲート電極の間にゲ ート絶縁膜 4より厚い端部絶縁体 27が設けられて、半導体層上部領域の側面にはチ ャネルがほとんど形成されないので、第二の課題は十分に解決され、充分な素子性 能を得ることができる。また、半導体層の上部では半導体層とゲート電極の間にゲー ト絶縁膜 4より厚い端部絶縁体 27が設けられるため、第三の実施形態と同様に、第 一の課題を解決する能力に優れる。  [0257] The fourth embodiment has a structure in which the transition between the semiconductor layer upper region and the semiconductor layer lower region does not change sharply in the modes shown in Figs. Although the effect of solving the second problem is slightly inferior to that of the third embodiment, compared to the conventional example of FIG. 85, in this embodiment, a gate is provided between the semiconductor layer and the gate electrode above the semiconductor layer. Since the end insulator 27 thicker than the insulating film 4 is provided and the channel is hardly formed on the side surface of the upper region of the semiconductor layer, the second problem can be sufficiently solved, and sufficient element performance can be obtained. it can. Further, since an end insulator 27 thicker than the gate insulating film 4 is provided between the semiconductor layer and the gate electrode above the semiconductor layer, the ability to solve the first problem is achieved similarly to the third embodiment. Excellent.

[0258] (第五の実施形態）  (Fifth Embodiment)

[構造]  [Construction]

第五の実施形態による電界効果型トランジスタは、第三の実施形態、第四の実施 形態及び第五の実施形態に共通する特徴に加えて、半導体層端部領域 44が半導 体層主要部 43の下部に設けられ、半導体層主要部 43の下部に設けられた半導体 層端部領域 44 (半導体層下部端部領域 42)とゲート電極 5の間には、ゲート絶縁膜 4よりも厚い絶縁膜である端部絶縁体領域 27が設けられる。 The field effect transistor according to the fifth embodiment has a feature common to the third embodiment, the fourth embodiment, and the fifth embodiment. The semiconductor provided below 43 and the semiconductor layer provided below the main part 43 An end insulator region 27 which is an insulating film thicker than the gate insulating film 4 is provided between the layer end region 44 (semiconductor layer lower end region 42) and the gate electrode 5.

[0259] また、第五の実施形態による電界効果型トランジスタは、第三の実施形態、第四の 実施形態及び第五の実施形態に共通する特徴に加えて、半導体層端部領域 44が 半導体層主要部 43の上部と半導体層主要部 43の下部の両方に設けられ、半導体 層主要部 43の上部に設けられた半導体層端部領域 44とゲート電極 5の間、及び半 導体層主要部 43の下部に設けられた半導体層端部領域 44とゲート電極 5の間には 、ゲート絶縁膜 4よりも厚レ、絶縁膜である端部絶縁体領域 27が設けられる。  The field-effect transistor according to the fifth embodiment has a feature common to the third embodiment, the fourth embodiment, and the fifth embodiment. It is provided on both the upper portion of the main layer portion 43 and the lower portion of the main portion 43 of the semiconductor layer. Between the semiconductor layer end region 44 provided below 43 and the gate electrode 5, an end insulator region 27 which is thicker than the gate insulating film 4 and is an insulating film is provided.

[0260] [製造方法]  [0260] [Manufacturing method]

第五の実施形態の構造は、例えば第四の実施形態の第二の製造方法により製造 される。但し、埋め込み絶縁層 2は酸素などの酸化剤を拡散しやすい Si〇で構成さ れていることが、半導体層の下部に端部絶縁体領域 27を形成する上で望ましい。  The structure of the fifth embodiment is manufactured by, for example, the second manufacturing method of the fourth embodiment. However, it is preferable that the buried insulating layer 2 is made of Si which easily diffuses an oxidizing agent such as oxygen in order to form the end insulator region 27 below the semiconductor layer.

[0261] 端部絶縁膜 27を形成したのちに、キャップ絶縁層 8を除去すれば図 68の形態が、 キャップ絶縁層 8を除去しなければ図 66の形態力 それぞれ形成される。 If the cap insulating layer 8 is removed after the end insulating film 27 is formed, the configuration shown in FIG. 68 is formed, and if the cap insulating layer 8 is not removed, the configuration shown in FIG. 66 is formed.

[0262] [効果] [0262] [Effect]

第五の実施形態は、半導体層の下部コーナー部（半導体層の下端のコーナー部 分）における電位上昇を抑制し、半導体層の下部コーナー部における寄生トランジス タを抑制することにより、トランジスタの特性を向上させる効果を有する。  The fifth embodiment suppresses a rise in potential at a lower corner portion of the semiconductor layer (a lower corner portion of the semiconductor layer) and suppresses a parasitic transistor at a lower corner portion of the semiconductor layer, thereby improving the characteristics of the transistor. It has the effect of improving.

[0263] 半導体層主要部の上部および下部の両方に端部半導体領域が設けられ、半導体 層の上下両方に端部絶縁体領域 27を持つ構造では、半導体層の上部コーナー部 および下部コーナー部の両方における電位上昇を抑制し、半導体層の上部コーナ 一部及び下部コーナー部の両方において寄生トランジスタを抑制することができるの 、トランジスタの特性を向上される効果が顕著である。  [0263] In the structure in which the end semiconductor regions are provided on both the upper and lower portions of the main portion of the semiconductor layer and the end insulator regions 27 are provided on both the upper and lower sides of the semiconductor layer, the upper corner portion and the lower corner portion of the semiconductor layer are formed. Since the potential rise in both of them can be suppressed and the parasitic transistor can be suppressed in both the upper corner part and the lower corner part of the semiconductor layer, the effect of improving the characteristics of the transistor is remarkable.

[0264] (第六の実施形態）  [0264] (Sixth embodiment)

本発明の第一から第四の実施形態は、絶縁体上に半導体層が形成される FinFE Tだけではなぐ坦め込み絶縁層を持たなレ、 FinFETに適用されても良レ、。この例を 図 71 (a)、図 71 (b)、図 72 (a)、図 72 (b)、図 73に示す。それぞれ、図 1 (a)、図 10 ( a)、図 13 (a)、図 41、図 60において、坦め込み絶縁層 2を用いない形態である。 [0265] 第六の実施形態は、第一の実施形態から第四の実施形態の製造方法において、 坦め込み絶縁層を持つ基板である SOI基板にかえて、通常の半導体基板、典型的 にはシリコン基板を用いた場合に形成される。製造工程の途中における形状を図 74 (a)に示す。図 74 (a)は坦め込み絶縁層を持たない基板を用いた場合に、図 18 (a) に対応する図面である。図 74 (b)、図 74 (c)はソース Zドレイン領域が形成され、トラ ンジスタの構造が形成された状態での図面であり、それぞれ図 19 (a)及び、図 19 (b )に対応する。 The first to fourth embodiments of the present invention are not limited to FinFET, in which a semiconductor layer is formed on an insulator, and have no embedded insulating layer, and may be applied to FinFET. This example is shown in FIGS. 71 (a), 71 (b), 72 (a), 72 (b), and 73. Each of FIGS. 1 (a), 10 (a), 13 (a), FIGS. 41 and 60 does not use the embedded insulating layer 2. FIG. [0265] The sixth embodiment is different from the manufacturing method of the first embodiment to the fourth embodiment in that, instead of the SOI substrate which is a substrate having a buried insulating layer, a normal semiconductor substrate, typically Is formed when a silicon substrate is used. The shape during the manufacturing process is shown in FIG. FIG. 74 (a) is a drawing corresponding to FIG. 18 (a) when a substrate having no embedded insulating layer is used. FIGS. 74 (b) and 74 (c) show the state where the source Z drain region is formed and the transistor structure is formed, and correspond to FIGS. 19 (a) and 19 (b), respectively. I do.

[0266] また、これらチャネル形成領域の半導体層の下部に坦め込み絶縁層を持たない形 態においては、ゲート電極 5と支持基板 1との絶縁性を得るために、ゲート電極 5の下 に、ゲート電極下絶縁膜 31を設けることが望ましい。ゲート電極下絶縁膜 31は、例え ば半導体基板をエッチングにより加工して、凸状の半導体層 3を形成したのち、全面 に Si〇などの絶縁体を CVD法などの製膜技術によって堆積し、堆積した絶縁体を C [0266] Further, in a mode in which the insulating layer is not provided under the semiconductor layer in the channel formation region, in order to obtain insulation between the gate electrode 5 and the supporting substrate 1, the gate electrode 5 is provided under the semiconductor layer. It is desirable to provide an insulating film 31 under the gate electrode. The insulating film 31 below the gate electrode is formed, for example, by processing a semiconductor substrate by etching to form a convex semiconductor layer 3, and then depositing an insulator such as Si〇 on the entire surface by a film forming technique such as a CVD method. C deposited insulator

MP法などの平坦ィ匕技術によって平坦ィ匕したのち、半導体層 3の裾部における絶縁 体の膜厚が適当な膜厚になるまで、堆積した絶縁体をエッチバックすることによって 形成できる。ゲート電極下絶縁膜 31が形成されたあとは、坦め込み絶縁層を設ける 形態と同じ製造方法を適用して製造される。なお、ゲート電極下絶縁膜 31が SiOよ りも誘電率が低い材料で形成されると、ゲート電極と支持基板との間の寄生容量抑 制という点において望ましい。また、ゲート電極下絶縁膜 31を SiOよりも誘電率が低 い材料で形成すると、半導体層 3の下部コーナー 35における電界集中の抑制にも有 効である。 After flattening by a flattening technique such as the MP method, it can be formed by etching back the deposited insulator until the thickness of the insulator at the foot of the semiconductor layer 3 becomes an appropriate thickness. After the gate electrode lower insulating film 31 is formed, it is manufactured by applying the same manufacturing method as in the embodiment in which the embedded insulating layer is provided. It is desirable that the insulating film 31 below the gate electrode be formed of a material having a lower dielectric constant than SiO, in terms of suppressing parasitic capacitance between the gate electrode and the supporting substrate. In addition, when the insulating film 31 below the gate electrode is formed of a material having a lower dielectric constant than SiO, it is effective in suppressing the electric field concentration at the lower corner 35 of the semiconductor layer 3.

[0267] なお、第三の実施形態、第四の実施形態または第五の実施形態に対して第六の 実施形態が適用される場合、半導体層 3のうち側面が端部絶縁体領域 27に接して レ、る部分が半導体層端部領域 44である。また、半導体層 3のうち側面が端部絶縁体 領域 27に接しておらず、半導体層 3の側面がゲート絶縁膜を介してゲート電極に向 カ 、合う部分が半導体層主要部領域 43である。  When the sixth embodiment is applied to the third embodiment, the fourth embodiment or the fifth embodiment, the side surface of the semiconductor layer 3 corresponds to the end insulator region 27. The portion in contact with the semiconductor layer is the semiconductor layer end region 44. Further, the side surface of the semiconductor layer 3 is not in contact with the end insulator region 27, and the side surface of the semiconductor layer 3 faces the gate electrode via the gate insulating film, and a portion corresponding to the semiconductor layer main region 43. .

[0268] (発明の他の実施形態）  (Other Embodiments of the Invention)

本発明の各実施形態は、単一の半導体領域上に形成される FinFETに限られるも のではなぐチャネル形成領域をなす半導体層が複数の分離した FinFETに対して 適用しても良い。すなわち、図 75 (a)に示すように、それぞれチャネルが形成される 複数の半導体層からなるトランジスタに適用されても良ぐまた、図 75 (b)に示すよう に、それぞれチャネルが形成される複数の半導体層がゲートから離れた位置で互レ、 に接続されたトランジスタに適用されても良レ、。図 75 (a)及び図 75 (b)において A— A ，と示した位置が、各実施形態における A— A'断面の位置に相当する。 Embodiments of the present invention are not limited to FinFETs formed on a single semiconductor region, and a semiconductor layer forming a channel formation region is not limited to a FinFET formed on a single semiconductor region. May be applied. That is, as shown in FIG. 75 (a), the present invention may be applied to a transistor composed of a plurality of semiconductor layers each having a channel formed thereon, and each channel may be formed as shown in FIG. 75 (b). It may be applied to a transistor in which a plurality of semiconductor layers are connected to each other at a position away from the gate. The positions indicated by AA in FIGS. 75A and 75B correspond to the positions of the cross section AA 'in each embodiment.

[0269] また、本発明の各実施形態では半導体層 3の上部コーナー部または下部コーナー 部の一方、または半導体層 3の上部コーナー部および下部コーナー部の両方が丸 められた形状を持っても良い。第三の実施形態では、例えば図 41において半導体 層 3の下部コーナー部、半導体層 3において端部絶縁体領域の上端近傍に位置す るコーナー部、半導体層 3において端部絶縁体領域の下端近傍に位置するコーナ 一部の少なくとも一つが丸められた形状を持っても良い。  [0269] In each embodiment of the present invention, one of the upper corner portion and the lower corner portion of the semiconductor layer 3, or both the upper corner portion and the lower corner portion of the semiconductor layer 3 may have a rounded shape. good. In the third embodiment, for example, in FIG. 41, the lower corner portion of the semiconductor layer 3, the corner portion located near the upper end of the end insulator region in the semiconductor layer 3, the vicinity of the lower end of the end insulator region in the semiconductor layer 3 At least one of the corners may have a rounded shape.

[0270] 図 1 (a)の形態において上部コーナー部が丸められた形態を図 76に、図 10 (a)の 形態にぉレ、て上部コーナー部が丸められた形態を図 77 (a)に、図 10 (b)の形態に おいて上部コーナー部及び下部コーナー部が丸められた形態を図 77 (b)に、図 13 (a)の形態にぉレ、て上部コーナー部が丸められた形態を図 78 (a)に、図 13 (b)の形 態において上部コーナー部及び下部コーナー部が丸められた形態を図 78 (b)に、 図 41の形態で半導体層 3において端部絶縁体領域の上端近傍に位置するのコーナ 一部、半導体層 3において端部絶縁体領域の下端近傍に位置するのコーナー部の 両方が丸められた形態を図 79にそれぞれ示す。これらの形態は半導体層を熱酸化 することにより形成される。  [0270] Fig. 76 shows a form in which the upper corner is rounded in the form of Fig. 1 (a), and Fig. 77 (a) shows a form in which the upper corner is rounded in the form of Fig. 10 (a). FIG. 77 (b) shows the form in which the upper corner and the lower corner are rounded in the form of FIG. 10 (b), and FIG. 13 (a) shows the form in which the upper corner is rounded. FIG. 78 (a) shows the configuration of FIG. 78, FIG. 78 (b) shows the configuration in which the upper corner portion and the lower corner portion are rounded in the configuration of FIG. 13 (b), and FIG. FIG. 79 shows a form in which both the corner located near the upper end of the insulator region and the corner portion located near the lower end of the end insulator region in the semiconductor layer 3 are both rounded. These forms are formed by thermally oxidizing the semiconductor layer.

[0271] また、第一の実施形態において半導体層の上部コーナーが丸められるとともに、キ ヤップ絶縁層 8も丸められた形態を用いても良レ、（図 87、図 88)。このような形態は、 ゲート酸化膜の形成に先だって半導体層の犠牲酸化とウエットエッチングを実施する ことにより形成される。特に犠牲酸化工程における酸化膜厚が厚ぐ犠牲酸化膜の除 去に要するウエットエッチングが長時間を要する場合に、犠牲酸化によって半導体層 の角が丸くなるとともに、ウエットエッチング工程においてキャップ絶縁層の角がエツ チングされて丸くなつた場合に形成される。このような形態においては、半導体層上 端と同じ高さ及び半導体層上端よりも低い位置のうち、ゲート絶縁膜の表面がゲート 電極側から最も後退した位置におけるゲート絶縁膜表面 (ゲート電極側の界面のこと )に対して、キャップ絶縁層の少なくとも一部がゲート電極側に張り出していれば（張り 出し幅を Wextと図中に示す）、第一の実施形態と同様に上部コーナー部における電 界緩和効果が得られる。またこの張り出し幅 Wextの大きさについても、第一の実施形 態と同様に設定すれば良い。その他作用、原理についても第一の実施形態と同様で ある。また製造方法についても、上述したように犠牲酸化及び続くウエットエッチング 工程における特徴を除いて、第一の実施形態と同じである。なお、図 87のようにキヤ ップ絶縁層は半導体層の幅が最も広い位置におけるゲート絶縁膜の表面よりもグー ト電極側に突起していることが、上部コーナー部における電界緩和効果を得るために 最も好ましい。但し、図 88のようにキャップ絶縁層が半導体層の幅が最も広い位置に おけるゲート絶縁膜の表面よりもゲート電極側から後退していても、張り出し幅 Wext がゼロでなければ、上部コーナー部における電界緩和効果はある程度得られる。 In the first embodiment, the upper corner of the semiconductor layer may be rounded, and the cap insulating layer 8 may be rounded (FIGS. 87 and 88). Such a configuration is formed by performing sacrificial oxidation and wet etching of the semiconductor layer before forming the gate oxide film. In particular, when the wet etching required to remove the thick sacrificial oxide film in the sacrificial oxidation process requires a long time, the corner of the semiconductor layer is rounded by the sacrificial oxidation, and the corner of the cap insulating layer is removed in the wet etching process. Are formed when they are rounded by etching. In such a form, the surface of the gate insulating film is located at the same height as the upper end of the semiconductor layer and at a position lower than the upper end of the semiconductor layer. If at least a part of the cap insulating layer extends to the gate electrode side with respect to the surface of the gate insulating film at the position most receded from the electrode side (the interface on the gate electrode side) (the extension width is Wext in the figure) ), An electric field relaxation effect at the upper corner portion is obtained as in the first embodiment. Also, the size of the overhang width Wext may be set in the same manner as in the first embodiment. Other operations and principles are the same as those of the first embodiment. Also, the manufacturing method is the same as that of the first embodiment except for the features in the sacrificial oxidation and the subsequent wet etching step as described above. Note that, as shown in FIG. 87, the projection of the cap insulating layer on the side of the gate electrode beyond the surface of the gate insulating film at the position where the width of the semiconductor layer is the widest provides an electric field relaxation effect at the upper corner portion. Most preferred for. However, even if the cap insulating layer is recessed from the gate electrode side of the gate insulating film at the position where the width of the semiconductor layer is the widest as shown in FIG. In this case, the electric field relaxation effect can be obtained to some extent.

[0272] なお、図 88の構造のようにキャップ絶縁層 8と半導体層 3との接触面に平面部がほ とんど無い場合、あるいはキャップ絶縁層 8と半導体層 3との接触面に平面部が全く 無い場合においても、張り出し幅 Wextは図 88のように、水平方向（半導体層 3が基 板から突起する方向に対して垂直な面内で、チャネル長方向に垂直な方向。）にお いて定義される。 When the contact surface between the cap insulating layer 8 and the semiconductor layer 3 has almost no flat portion as in the structure in FIG. 88, or when the contact surface between the cap insulating layer 8 and the semiconductor layer 3 has a flat surface. Even when there is no portion, the overhang width Wext is horizontal (in the plane perpendicular to the direction in which the semiconductor layer 3 protrudes from the substrate and perpendicular to the channel length direction) as shown in FIG. Is defined in

[0273] コーナー部を丸めたことにより、第二の課題は完全には解消されなくなるが、本発 明の各実施形態とコーナー部を丸めるプロセスを組み合わせると、本発明の各実施 形態と組み合わせずに単にコーナー部を丸める場合に比べて、第一の課題を解消 できる電界緩和効果を得るために必要な丸め量を減らすことが可能となり、コーナー 部の極率半径を小さくすることができる。したがって、本発明の各実施形態とコーナ 一部を丸めるプロセスを組み合わせると、曲面を持った領域が縮小されるので、第二 の課題を完全に解消することはできなくとも、第二の課題を大幅に低減することがで きる。  [0273] Although the second problem is not completely solved by the rounding of the corner portion, the combination of each embodiment of the present invention with the process of rounding the corner portion does not combine with each embodiment of the present invention. Compared to the case where the corner is simply rounded, the amount of rounding required to obtain the electric field relaxation effect that can solve the first problem can be reduced, and the radius of curvature of the corner can be reduced. Therefore, when each embodiment of the present invention is combined with a process of rounding a part of a corner, a region having a curved surface is reduced, so that even if the second problem cannot be completely solved, the second problem can be solved. It can be greatly reduced.

[0274] (各実施形態における材料、寸法、形状、及びプロセス条件の具体例）  (Specific examples of materials, dimensions, shapes, and process conditions in each embodiment)

(第一の実施形態)から (第六の実施形態）、及び (その他の実施形態）における材 料、寸法、形状及びプロセス条件の具体例を挙げる。 [0275] (支持基板） Specific examples of materials, dimensions, shapes, and process conditions in (first embodiment) to (sixth embodiment) and (other embodiments) will be described. [0275] (Support substrate)

支持基板 1は、通常単結晶のシリコンウェハであるが、石英、ガラス、サファイア、あ るいはシリコン以外の半導体など、シリコン基板以外の基板が使われても良い。  The support substrate 1 is usually a single-crystal silicon wafer, but a substrate other than a silicon substrate such as quartz, glass, sapphire, or a semiconductor other than silicon may be used.

[0276] (坦め込み絶縁層 2) [0276] (Filled insulating layer 2)

坦め込み絶縁層 2は、通常 Si〇であるが、他の絶縁体であっても良ぐまた複数の 材料からなる多層膜であっても良レ、。また坦め込み絶縁層は多孔質 SiOや Si〇F等 The buried insulating layer 2 is usually made of Si, but may be another insulator or a multilayer film made of a plurality of materials. Also, the insulating layer to be filled is porous SiO, Si〇F, etc.

SiOよりも誘電率が低い低誘電率材料であっても良い。また、支持基板が石英、ガラ ス、サファイアなどの絶縁体である場合は、支持基板 1が坦め込み絶縁膜 2を兼ねて も良い。また、埋め込み絶縁層 2の厚さは通常 50nmから 2 x m程度、より典型的には 50nmから 200nmである力 必要に応じて 50nm以下あるいは 2 μ m以上であっても よい。 A low dielectric constant material having a lower dielectric constant than SiO may be used. When the support substrate is an insulator such as quartz, glass, or sapphire, the support substrate 1 may also serve as the insulating film 2 to be buried. The thickness of the buried insulating layer 2 is generally about 50 nm to 2 × m, more typically 50 nm to 200 nm. The thickness may be 50 nm or less or 2 μm or more as needed.

[0277] なお、第六の実施形態においては、埋め込み絶縁層 2を持たない構造が用いられ る。  In the sixth embodiment, a structure having no buried insulating layer 2 is used.

[0278] (半導体層 3)  [0278] (Semiconductor layer 3)

半導体層 3は単結晶であることが、オン電流の向上及びオフ電流の抑制という観点 から最も望ましいが、要求されるオン電流の仕様が低い場合、または要求されるオフ 電流の仕様が大きい場合は、アモルファス、多結晶など単結晶以外の材料であって も良い。  It is most preferable that the semiconductor layer 3 is a single crystal from the viewpoint of improving the on-current and suppressing the off-current, but when the required on-current specification is low or the required off-current specification is large, It may be a material other than a single crystal, such as amorphous, polycrystalline, or the like.

[0279] また、半導体層 3をシリコン以外の半導体層で置き換えても良レ、。また、二種類以上 の半導体の組み合わせによって置き換えて良レ、。  [0279] Also, it is acceptable to replace the semiconductor layer 3 with a semiconductor layer other than silicon. Also, it can be replaced by a combination of two or more semiconductors.

[0280] 半導体層は基板面から突起した形状を持つ。基板面は一般には支持基板 1の上 面であるが、埋め込み絶縁層 2と支持基板が一体化した構造の場合は埋め込み絶 縁層 2の上面である。ゲート下絶縁膜 31が設けられる場合はゲート下絶縁膜 31の上 面である。 [0280] The semiconductor layer has a shape protruding from the substrate surface. The substrate surface is generally the upper surface of the support substrate 1, but in the case of a structure in which the embedded insulating layer 2 and the support substrate are integrated, the substrate surface is the upper surface of the embedded insulating layer 2. When the under-gate insulating film 31 is provided, it is the upper surface of the under-gate insulating film 31.

[0281] 半導体層 3の高さ Hfm (図 82 (a)、図 83 (a)、図 71 (b)、図 72 (b)参照）は典型的に は 20nm力、ら 150nm、より典型的には 50nm力ら lOOnmであり、半導体層の幅 Wfm (図 82 (a)、図 83 (a)、図 72 (b)参照）は典型的には 5nmから lOOnmであり、より典 型的には 15nmから 50nmである。但し、 Hfm、 Wfinともこの範囲以外の値を用いても 良レ、。但し、チャネル形成領域の半導体層はゲート電極にしきい値電圧を印加した 状態で空乏化していることが、 FinFETの特性（Sファクタの縮小により代表される、 O N-OFF特性の急峻化等）を生かすという観点から望ましい。ゲート電極にしきい値 電圧を印加した状態で、半導体層の両側面から伸びた空乏層が互いに接触する完 全空乏化状態を実現するためには、通常 Wfinを 50nm以下、より典型的には 30nm 以下に設定することが好ましい。 The height Hfm of the semiconductor layer 3 (see FIG. 82 (a), FIG. 83 (a), FIG. 71 (b), and FIG. 72 (b)) is typically 20 nm, 150 nm, and more typical. The width of the semiconductor layer Wfm (see Fig. 82 (a), Fig. 83 (a), Fig. 72 (b)) is typically 5 nm to 100 nm, which is more typical. Is between 15 nm and 50 nm. However, even if Hfm and Wfin use values outside this range, Good les ,. However, the semiconductor layer in the channel formation region is depleted when a threshold voltage is applied to the gate electrode, which is a characteristic of FinFET (represented by a reduction in S factor, sharpening of ON-OFF characteristics, etc.). It is desirable from the viewpoint of utilizing In order to achieve a fully depleted state where the depletion layers extending from both sides of the semiconductor layer are in contact with each other with a threshold voltage applied to the gate electrode, Wfin is usually 50 nm or less, more typically 30 nm. It is preferable to set the following.

[0282] (ゲート絶縁膜 4) [0282] (Gate insulating film 4)

ゲート絶縁膜 4は、シリコンの熱酸化により形成したものであっても良ぐ他の方法に より形成した SiO膜であっても良い。例えばラジカル酸化によって形成した SiO膜を 用いても良い。また、ゲート絶縁膜を SiO以外の絶縁材料より置き換えて良レ、。また The gate insulating film 4 may be formed by thermal oxidation of silicon or may be a SiO film formed by another method. For example, an SiO film formed by radical oxidation may be used. Also, the gate insulating film should be replaced with an insulating material other than SiO. Also

、 SiOとそれ以外の絶縁膜との多層膜、あるいは Si〇以外の絶縁膜同士の多層膜 に置き換えて良い。また、ゲート絶縁膜を Hf〇、 HfSiOなどの高誘電率材料に置き 換えても良い。 And a multilayer film of SiO and other insulating films, or a multilayer film of insulating films other than Si〇. Further, the gate insulating film may be replaced with a high dielectric constant material such as Hf〇 or HfSiO.

[0283] ゲート絶縁膜の酸化膜換算膜厚は典型的には 1. 2nmから 3nmである。但し酸化 膜換算膜厚とは、ゲート絶縁膜を構成する絶縁膜の膜厚をゲート絶縁膜の誘電率で 割った商に Si〇の誘電率を乗じたものである。ゲート絶縁膜が多層膜である場合に は、各層について前記方法で酸化膜換算膜厚を求めてそれらを足し合わせたもので ある。  [0283] The equivalent oxide film thickness of the gate insulating film is typically 1.2 nm to 3 nm. However, the oxide equivalent film thickness is obtained by multiplying the quotient obtained by dividing the thickness of the insulating film constituting the gate insulating film by the dielectric constant of the gate insulating film by the dielectric constant of Si〇. When the gate insulating film is a multilayer film, the oxide film equivalent thickness is obtained for each layer by the above-described method, and these are added.

[0284] (ゲート電極 5)  [0284] (Gate electrode 5)

ゲート電極 5は、ポリシリコンなどの多結晶半導体であっても良ぐまた金属や金属 化合物等の多結晶半導体以外の導電体であっても良い。ゲート電極 5がポリシリコン などの多結晶半導体で構成される場合、典型的には、ゲート電極 5のポリシリコンに はチャネルと同じ導電型である第一導電型の不純物が高濃度に導入される。また、 ゲート電極は、置換ゲート（リプレースメント 'ゲートとも呼ばれる）プロセスにより形成し ても良い。すなわち、ー且ダミー材料によりゲート電極の形状を形成し、ソース Zドレ イン領域に第一導電型の不純物を高濃度に導入し、ダミー材料を絶縁膜で覆ったの ちに、ダミー材料を除去して得られた空洞中にゲート電極、あるいはゲート絶縁膜と ゲート電極を埋設する工程により形成しても良い。 [0285] ゲート電極材料がポリシリコン、多結晶シリコン一ゲルマニウム混晶等の半導体によ り形成される場合、ゲートへの不純物導入は、ソース/ドレインへの不純物導入と同 時に行っても良い。また、ゲート電極材料の堆積と同時に行っても良い。また、ゲート 電極材料を堆積し、ゲート電極の形状に加工する前に行っても良い。 The gate electrode 5 may be a polycrystalline semiconductor such as polysilicon or a conductor other than a polycrystalline semiconductor such as a metal or a metal compound. When the gate electrode 5 is made of a polycrystalline semiconductor such as polysilicon, typically, the first conductivity type impurity having the same conductivity type as the channel is introduced into the polysilicon of the gate electrode 5 at a high concentration. . Further, the gate electrode may be formed by a replacement gate (also called a replacement 'gate) process. That is, the shape of the gate electrode is formed with a dummy material, the first conductivity type impurity is introduced into the source Z drain region at a high concentration, the dummy material is covered with an insulating film, and then the dummy material is removed. A gate electrode or a gate insulating film and a gate electrode may be buried in the cavity thus obtained. [0285] When the gate electrode material is formed of a semiconductor such as polysilicon or polycrystalline silicon-germanium mixed crystal, the introduction of impurities into the gate may be performed at the same time as the introduction of impurities into the source / drain. Further, it may be performed simultaneously with the deposition of the gate electrode material. Alternatively, it may be performed before a gate electrode material is deposited and processed into the shape of the gate electrode.

[0286] また、ゲート電極は通常半導体層を跨ぐ構造を持つ。本発明は半導体層の上方と 半導体層の側面にゲート電極が配置され、半導体層の上方のゲートからの電界と半 導体層の側面のゲートからの電界によって、電界集中が起こるトランジスタにおいて、 電界集中を緩和するために特に有効である。  [0286] The gate electrode usually has a structure straddling the semiconductor layer. The present invention provides a transistor in which a gate electrode is disposed above a semiconductor layer and on a side surface of a semiconductor layer, and an electric field from the gate above the semiconductor layer and an electric field from a gate on the side surface of the semiconductor layer cause electric field concentration. It is particularly effective for alleviating.

[0287] また、半導体層の上方にゲート電極が配置されないが、半導体層の上端よりも上方 に延びたゲート電極の側面からの電界により電界集中が起こる FinFET (図 93。図 9 3は図 92と同じ位置に相当する断面図。）に対して、本発明を適用しても良い。半導 体層の上方にゲート電極が配置されなレ、 FinFETに第二実施形態を適用した場合 を図 94に、第三実施形態を適用した場合を図 95に示す。図 94は図 10に、図 95は 図 41に、それぞれ対応する断面図である。  [0287] Although a gate electrode is not arranged above a semiconductor layer, a FinFET in which electric field concentration occurs due to an electric field from the side surface of the gate electrode extending above the upper end of the semiconductor layer (Fig. 93; Fig. 93 is Fig. 92). The present invention may be applied to a cross-sectional view corresponding to the same position as in FIG. FIG. 94 shows the case where the second embodiment is applied to the FinFET where the gate electrode is not arranged above the semiconductor layer, and FIG. 95 shows the case where the third embodiment is applied. FIG. 94 is a sectional view corresponding to FIG. 10, and FIG. 95 is a sectional view corresponding to FIG.

[0288] (ソース/ドレイン領域 6)  [0288] (Source / drain region 6)

ソース/ドレイン領域 6には第一導電型の不純物が高濃度に導入される。なお、本 明細書においてソース/ドレイン領域とは、バルタトランジスタにおいて浅いソース/ ドレイン領域（エクステンション領域とも呼ばれる）と呼ばれる領域及び深レ、ソース/ド レイン領域と呼ばれる領域を全て含むものとする。 FinFETにおいて、ェクステンショ ン領域、深いソース/ドレイン領域の定義は一般に明確にされていなレ、が、例えば 図 75 (b)においてゲートに隣接する短冊状の領域に形成されるソース/ドレイン領 域とゲートから離れた位置で短冊状の領域が互いに接続された領域の双方を含むも のとする。また、ソース Zドレイン領域の寄生抵抗を縮小するために、ソース Zドレイ ン領域の一部にシリコンなどの半導体をェピタキシャル成長させることにより、ソース /ドレイン領域をなす半導体層の大きさを上方または面内方向に拡大する手法を組 み合わせても良い。  The source / drain region 6 is doped with a first conductivity type impurity at a high concentration. Note that in this specification, the source / drain regions include all regions called shallow source / drain regions (also called extension regions) and regions called deep / source / drain regions in a Balta transistor. In FinFET, the definition of the extension region and the deep source / drain region is not generally clarified, but, for example, the source / drain region formed in the strip-shaped region adjacent to the gate in FIG. It is assumed that the strip-shaped area at a position away from the gate includes both areas connected to each other. In addition, in order to reduce the parasitic resistance of the source Z drain region, a semiconductor such as silicon is epitaxially grown on a part of the source Z drain region, thereby increasing the size of the semiconductor layer forming the source / drain region. It is also possible to combine techniques for expanding in the plane.

[0289] 本発明では半導体層 3のうちゲート電極に覆われない部分にソース/ドレイン領域 が設けられる。但し、ゲート電極に覆われない部分に設けられるソース Zドレイン領域 に加えて、半導体層 3のうちゲート電極に覆われる領域に侵入したソース/ドレイン 領域が設けられても良い。半導体層 3のうちゲート電極に覆われる領域にソース/ド レイン領域が侵入する場合、半導体層 3のうちゲート電極に覆われない部分に設けら れるソース Zドレイン領域とゲート電極に覆わる部分に設けられるソース/ドレイン領 域は、通常連続的に接続する。 According to the present invention, a source / drain region is provided in a portion of the semiconductor layer 3 that is not covered by the gate electrode. However, the source Z drain region provided in the part not covered by the gate electrode In addition, a source / drain region that penetrates a region of the semiconductor layer 3 that is covered with the gate electrode may be provided. When the source / drain region enters the region of the semiconductor layer 3 covered by the gate electrode, the source / drain region provided in the portion of the semiconductor layer 3 not covered by the gate electrode and the portion covered by the gate electrode The provided source / drain regions are usually connected continuously.

[0290] また、ゲート電極に覆われた半導体層から、ある幅のオフセット領域を隔ててソース /ドレイン領域が設けられても良い。この場合寄生抵抗が増すためにドレイン電流が 減る代わり、ソース/ドレイン領域端の電界強度が減るので漏れ電流が減る。この構 造はドレイン電流の大きさよりも漏れ電流の低減が優先される DRAM (ダイナミック- ランダム .アクセス 'メモリー）のセルトランジスタに適用することが望ましレ、。  [0290] Further, a source / drain region may be provided with a certain width of an offset region from a semiconductor layer covered with a gate electrode. In this case, instead of the drain current decreasing due to an increase in parasitic resistance, the electric field strength at the end of the source / drain region decreases, so that the leakage current decreases. This structure is desirably applied to DRAM (dynamic-random access memory) cell transistors, in which the reduction of leakage current is prioritized over the magnitude of drain current.

[0291] (チャネル形成領域 7)  [0291] (Channel formation region 7)

チャネル形成領域 7には低濃度のァクセプタまたはドナー不純物が導入される。ゲ ート電極が第一導電型のポリシリコンである場合は、しきい値電圧を適当な値に設定 する必要から典型的には低濃度の第二導電型不純物がチャネル形成領域に導入さ れる。しかし、ゲート電極に第一導電型のポリシリコンあるいは第一導電型のポリシリ コンと仕事関数が同程度の材料を用いる場合においてもしきい値電圧が低く設定さ れる場合、あるいはゲート電極に金属、金属シリサイドなどの第一導電型のポリシリコ ンとは異なる仕事関数を持つ材料を用いる場合には、チャネル形成領域 7には不純 物を導入しないか、あるいは低濃度の第一導電型の不純物を導入しても良い。  A low concentration of ceptor or donor impurity is introduced into the channel forming region 7. When the gate electrode is polysilicon of the first conductivity type, a low concentration of the second conductivity type impurity is typically introduced into the channel formation region because the threshold voltage needs to be set to an appropriate value. . However, even if the first conductivity type polysilicon or the material having the same work function as the first conductivity type polysilicon is used for the gate electrode, if the threshold voltage is set low, or if the gate electrode is made of metal or metal, When a material having a work function different from that of the first conductivity type polysilicon such as silicide is used, no impurity is introduced into the channel formation region 7 or a low concentration of the first conductivity type impurity is introduced. May be.

[0292] また、チャネル形成領域のうちゲート電極に覆われたソース/ドレイン領域に隣接 した領域に、ゲート電極に覆われたソース/ドレイン領域に隣接しなレ、部分に比べて 第二導電型不純物がやや高く導入されたハロー領域を設けても良い。  [0292] In the channel formation region, a region adjacent to the source / drain region covered with the gate electrode is closer to the source / drain region covered by the gate electrode, and the second conductivity type is A halo region into which impurities are introduced slightly higher may be provided.

[0293] また、チャネル形成領域をなす半導体層 3の上部または下部において、第二導電 型不純物の濃度を高くすることにより、それぞれ半導体層 3の上部コーナー部または 下部コーナー部における電位上昇、およびこれに伴う寄生トランジスタを抑制する手 法を併用しても良い。  [0293] Further, by increasing the concentration of the second conductivity type impurity in the upper or lower part of the semiconductor layer 3 forming the channel formation region, the potential rise in the upper corner part or the lower corner part of the semiconductor layer 3, respectively, The method of suppressing the parasitic transistor accompanying the above may be used together.

[0294] チャネル形成領域をなす半導体層 3の上部において、第二導電型不純物の濃度を 高くする手法を、第一実施形態に適用した場合を図 96に、第二実施形態に適用した 場合を図 97に、第三実施形態に適用した場合を図 98及び図 99に示す。図 96は図 1、図 97は図 10、図 98及び図 99は図 41に、それぞれ対応する図面である。図中の 記号 47が第二導電型不純物の濃度が高い領域である。 [0294] FIG. 96 shows a case where the method of increasing the concentration of the second conductivity type impurity in the upper part of the semiconductor layer 3 forming the channel formation region is applied to the first embodiment, and is applied to the second embodiment. FIG. 97 shows the case, and FIGS. 98 and 99 show the case where the third embodiment is applied. 96 corresponds to FIG. 1, FIG. 97 corresponds to FIG. 10, and FIGS. 98 and 99 correspond to FIG. 41. Symbol 47 in the figure is a region where the concentration of the second conductivity type impurity is high.

[0295] 寄生トランジスタを抑制するために、 FinFETの半導体層の上部に高濃度部を設け る技術は特開平 6—302817号公報に記載されているが、本発明の各実施形態を併 用することにより、寄生トランジスタの抑制に必要な、半導体層上部の不純物濃度を 低めに設定できる。半導体層上部の不純物濃度が低めに設定されると、ソース/ドレ イン領域端と半導体層上部の高濃度部との間の電界強度が小さくなるので、ソース /ドレイン領域端と半導体層上部の高濃度部との間のリーク電流が低減される。 [0295] A technique of providing a high-concentration portion above a semiconductor layer of a FinFET to suppress a parasitic transistor is described in Japanese Patent Application Laid-Open No. 6-302817. Thus, the impurity concentration above the semiconductor layer, which is necessary for suppressing the parasitic transistor, can be set lower. If the impurity concentration in the upper part of the semiconductor layer is set lower, the electric field strength between the source / drain region end and the high concentration part in the upper part of the semiconductor layer becomes smaller, so that the height of the source / drain region end and the upper part of the semiconductor layer become higher. Leakage current between the impurity and the concentration portion is reduced.

[0296] (キャップ絶縁層 8)  [0296] (Cap insulating layer 8)

キャップ絶縁層 8は半導体層 3の上部に設けられる。また、ゲート電極 5が半導体層 3を跨ぐ構造（図 1など）では、キャップ絶縁層 8はゲート電極の下に設けられる。また 、ゲート電極 5が半導体層 3を跨ぐか、跨がないかにかかわらず、ゲート電極の上端よ りも低い位置に、キャップ絶縁層 8の少なくとも一部が置かれるように、キャップ絶縁層 8は配置される（図 94、図 95にゲート電極 5が半導体層 3を跨がない場合を示す。）。  The cap insulating layer 8 is provided on the semiconductor layer 3. In a structure in which the gate electrode 5 straddles the semiconductor layer 3 (FIG. 1, etc.), the cap insulating layer 8 is provided below the gate electrode. Also, regardless of whether the gate electrode 5 straddles the semiconductor layer 3 or does not straddle, the cap insulating layer 8 is arranged such that at least a part of the cap insulating layer 8 is located at a position lower than the upper end of the gate electrode. (The case where the gate electrode 5 does not straddle the semiconductor layer 3 is shown in FIGS. 94 and 95.)

[0297] キャップ絶縁層 8は、 Si〇膜あるいは Si N膜などの単層の絶縁膜であっても良ぐ [0297] The cap insulating layer 8 may be a single-layer insulating film such as a Si〇 film or a SiN film.

SiO膜、 Si N膜などの絶縁膜よりなる多層膜であっても良い。また、キャップ絶縁層It may be a multilayer film made of an insulating film such as a SiO film or a SiN film. Also, cap insulating layer

8の一部または全部が Si〇よりも低誘電率の材料で構成されても良い。また、キヤッ プ絶縁層 8の一部または全部が空洞で構成されても良レ、。キャップ絶縁層 8が空洞 及びその空洞の周囲に設けられる SiOなどの絶縁体よりなる保護絶縁膜により構成 されても良レ、。 Part or all of 8 may be made of a material having a lower dielectric constant than Si〇. It is also acceptable that part or all of the cap insulating layer 8 is formed of a cavity. The cap insulating layer 8 may be formed of a cavity and a protective insulating film made of an insulator such as SiO provided around the cavity.

[0298] キャップ絶縁層 8の厚さは、ゲート絶縁膜の 2倍以上、より典型的にはゲート絶縁膜 厚の 5倍以上である。キャップ絶縁層 8の厚さは、典型的には 10nm力、ら 100nm、より 典型的には 10nmから 50nmである力 ゲート絶縁膜厚に対して最低でも 2倍以上の 膜厚があればよいので、ゲート絶縁膜が薄い場合は 10nm以下であっても良レ、。な お、キャップ絶縁層 8の厚さとは、半導体層の上面から垂直な方向に見た厚さであり 、通常上下方向の厚さである。また、ゲート絶縁膜とキャップ絶縁層の材質が異なる 場合は、ゲート絶縁膜との厚さの比は換算膜厚 (物理的な膜厚を誘電率で割って得 た商に、定数 (通常は SiOの比誘電率）を乗じたもの）における比較である。 [0298] The thickness of the cap insulating layer 8 is at least twice the thickness of the gate insulating film, more typically at least five times the thickness of the gate insulating film. The thickness of the cap insulating layer 8 is typically 10 nm force, 100 nm or more, more typically 10 nm to 50 nm. If the gate insulating film is thin, the thickness may be 10 nm or less. Note that the thickness of the cap insulating layer 8 is a thickness as viewed in a direction perpendicular to the upper surface of the semiconductor layer, and is usually a thickness in the vertical direction. If the material of the gate insulating film and the material of the cap insulating layer are different, the ratio of the thickness to the gate insulating film is calculated as the converted film thickness (the physical film thickness is divided by the dielectric constant. Quotient multiplied by a constant (usually the relative dielectric constant of SiO).

2  2

[0299] (低誘電率領域 10)  [0299] (Low dielectric constant region 10)

半導体層の上部または半導体層下部に設けられる低誘電率領域 10の厚さは、典 型的には 10nm力、ら 100nm、より典型的には 20nmから 50nmである。 10nm以上の 厚さを持つことが、大きな効果を得るためには望ましい。  The thickness of the low dielectric constant region 10 provided above or below the semiconductor layer is typically 10 nm, typically 100 nm, more typically 20 to 50 nm. It is desirable to have a thickness of 10 nm or more to obtain a large effect.

[0300] 低誘電率領域の材料は、 SiOF、多孔質の Si〇、多孔質のシロキサン、あるいは Si [0300] The material in the low dielectric constant region is SiOF, porous Si〇, porous siloxane, or Si.

2  2

_〇_Si骨格を持つ低誘電率材料など、 Siを含み SiOよりも低誘電率の材料であつ  __________________________________

2  2

ても良い。これらの材料は有機材料よりなる低誘電率材料よりも熱処理工程に対する 耐性が高いという長所がある。また、低誘電率領域の材料はブラックダイヤモンド、ァ モルファスカーボン、有機材料よりなる低誘電率材料など、 Cを含み SiOよりも低誘  May be. These materials have the advantage that they are more resistant to the heat treatment process than low dielectric constant materials made of organic materials. In addition, materials in the low dielectric constant region include C, such as black diamond, amorphous carbon, and a low dielectric constant material made of an organic material.

2  2

電率の材料であっても良い。これらの材料は一般に熱処理工程に対する耐性が低い ので、熱酸化に代えて CVDでゲート絶縁膜を堆積する工程、低温の固相成長による ソース/ドレイン領域の活性化など、トランジスタの製造が低温条件で実施される場 合に適用されることが特に望ましい。また、低誘電率領域は空洞であってもよい。また 、低誘電率領域を多孔質の材料で形成し、低誘電率領域に多数の空洞が含まれる ようにしても良い。  It may be a material having electric conductivity. Since these materials generally have low resistance to the heat treatment process, transistor fabrication must be performed at low temperature conditions, such as the step of depositing a gate insulating film by CVD instead of thermal oxidation and the activation of source / drain regions by low-temperature solid phase growth. It is particularly desirable to apply when implemented. Further, the low dielectric constant region may be a cavity. Further, the low dielectric constant region may be formed of a porous material, and the low dielectric constant region may include many cavities.

[0301] (ダミー層 11) [0301] (Dummy layer 11)

コーナーダミー層 22は、製造工程において選択的に除去できる材料であれば良い 。たとえば、コーナーダミー層 22に Si Nを用いる場合は、リン酸によりコーナーダミ  The corner dummy layer 22 may be made of any material that can be selectively removed in the manufacturing process. For example, when SiN is used for the corner dummy layer 22,

3 4  3 4

一層 22を選択的にエッチングする。また、ゲート絶縁膜及び坦め込み絶縁層が Si N  Layer 22 is selectively etched. In addition, the gate insulating film and the filled insulating layer

3 などフッ酸によりエッチングされなレ、材料により構成される場合は、コーナーダミー層 3 If the material is not etched with hydrofluoric acid, or if it is made of a material, a corner dummy layer

4 Four

22に Si〇を用いて、フッ酸によりコーナーダミー層 22を選択的にエッチングする。  Using Si ダ ミ ー for 22, the corner dummy layer 22 is selectively etched with hydrofluoric acid.

2  2

[0302] (空洞 12)  [0302] (Cavity 12)

空洞内は真空であるカ あるいは適当な気体が侵入している。空洞 12内は固体材 料によって埋められない。  The inside of the cavity is filled with vacuum or a suitable gas. The cavity 12 is not filled with the solid material.

[0303] (ゲート側壁 14) [0303] (Gate side wall 14)

ゲート側壁 14は、 SiO膜あるいは Si N膜などの単層の絶縁膜であっても良ぐ Si  The gate sidewall 14 may be a single-layer insulating film such as a SiO film or a SiN film.

2 3 4  2 3 4

O膜、 Si N膜などの絶縁膜よりなる多層膜であっても良レ、。ゲート側壁 14の厚さは 通常 20nmから 150nmである力 素子の微細化が必要な場合等には 20nm以下とし ても良い。 A multilayer film made of an insulating film such as an O film or a SiN film is acceptable. The thickness of the gate sidewall 14 is If it is necessary to miniaturize the force element, which is usually from 20 nm to 150 nm, it may be set to 20 nm or less.

[0304] 半導体層 3の上部または下部に空洞 12を形成し、空洞の形成後にゲート側壁 14を 設ける場合、ゲート側壁 14となる絶縁膜を堆積する工程は、被覆性に劣る堆積技術 を用いて、空洞が坦まらないようにすることが望ましい。例えば、比較的ガス分圧の高 い条件で CVDを実施する。ゲート側壁 14が多層膜である場合には、最初に堆積す る絶縁膜だけを、被覆性に劣る堆積技術を用レ、て形成しても良い。  [0304] When the cavity 12 is formed above or below the semiconductor layer 3 and the gate side wall 14 is provided after the formation of the cavity, the step of depositing the insulating film to be the gate side wall 14 uses a deposition technique with poor coverage. It is desirable that the cavity is not filled. For example, CVD is performed under relatively high gas partial pressure conditions. When the gate side wall 14 is a multilayer film, only the insulating film to be deposited first may be formed by using a deposition technique having poor coverage.

[0305] (シリサイド層 15)  [0305] (Silicide layer 15)

シリサイド層 15は、典型的にはチタンシリサイド、コバルトシリサイド、ニッケルシリサ イド、あるいは白金シリサイド等の材料からなる力 これら以外のシリサイドを用いても 良レ、。シリサイド層 15は例えばチタン、コバルト、ニッケル、白金などの金属をスパッ タリング法などの堆積技術でソース/ドレイン領域上に堆積し、熱処理を行うことによ つて金属とシリコン層との間でシリサイド化反応を起こすことにより形成する。  The silicide layer 15 is typically made of a material such as titanium silicide, cobalt silicide, nickel silicide, or platinum silicide. The silicide layer 15 is formed, for example, by depositing a metal such as titanium, cobalt, nickel, or platinum on the source / drain region by a deposition technique such as a sputtering method and performing a heat treatment to form a silicide between the metal and the silicon layer. It is formed by causing a reaction.

[0306] (コンタクト 17及び配線 18)  [0306] (Contact 17 and wiring 18)

コンタクト 17及び配線 18は、通常のコンタクト形成工程及び通常の配線工程により 形成される。コンタクト 17及び配線 18は通常アルミ、銅などの金属により形成され、 T iNなど他の導電性材料が適宜組み合わされる。  The contact 17 and the wiring 18 are formed by a normal contact forming step and a normal wiring step. The contact 17 and the wiring 18 are usually formed of a metal such as aluminum or copper, and are appropriately combined with other conductive materials such as TiN.

[0307] (支持絶縁膜 21)  (Support insulating film 21)

支持絶縁膜 21は、通常 CVDなどの製膜技術によって堆積された SiOなどの絶縁 膜であるが、絶縁性が得られるならば、他の方法により形成された膜であっても良ぐ また Si〇以外の膜であっても良い。  The supporting insulating film 21 is usually an insulating film such as SiO deposited by a film forming technique such as CVD, but may be a film formed by another method as long as insulating properties can be obtained. Films other than 〇 may be used.

[0308] (コーナーダミー層 22)  [0308] (Corner dummy layer 22)

コーナーダミー層 22は、製造工程において選択的に除去できる材料であれば良いThe corner dummy layer 22 may be any material that can be selectively removed in the manufacturing process.

。たとえば、コーナーダミー層 22に Si Nを用いる場合は、リン酸によりコーナーダミ 一層 22を選択的にエッチングする。また、ゲート絶縁膜及び坦め込み絶縁層が Si N などフッ酸によりエッチングされなレ、材料により構成される場合は、コーナーダミー層. For example, when SiN is used for the corner dummy layer 22, the corner dummy layer 22 is selectively etched with phosphoric acid. If the gate insulating film and the filled insulating layer are made of a material that cannot be etched with hydrofluoric acid, such as SiN, a corner dummy layer

22に Si〇を用いて、フッ酸によりコーナーダミー層 22を選択的にエッチングする。 Using Si ダ ミ ー for 22, the corner dummy layer 22 is selectively etched with hydrofluoric acid.

[0309] (端部絶縁体領域 23、 27) 端部絶縁体領域（23、 27)は、絶縁性のある材料であれば良ぐ例えば Si〇、 Si N [0309] (End insulator regions 23, 27) The end insulator regions (23, 27) can be made of any insulating material, for example, Si〇, Si N

2 3 などの材料が挙げられる。また、電界集中を緩和するという観点からは、端部絶縁体 Materials such as 23 are listed. Also, from the viewpoint of reducing the electric field concentration, the end insulator

4 Four

領域 23、 27を、低誘電率領域 10と同様の低誘電率材料で形成することがより好まし レ、。たとえば、 SiOF、多孔質の材料、フッ素化カーボン、空洞などが挙げられる。  More preferably, the regions 23 and 27 are formed of the same low dielectric constant material as the low dielectric constant region 10. For example, SiOF, a porous material, fluorinated carbon, a cavity, and the like can be given.

[0310] 端部絶縁体領域（23、 27)の幅 Weiは半導体全体の幅 Wfinの半分よりも小さぐゲ ート酸化膜よりも厚ければ良レ、。典型的な上限は 15nm程度であり、より典型的には 5nmから 10nmである。端部絶縁体領域の高さ Htopについても特に制限はなレ、が、 一般的には上部領域 28も含んだ半導体層の全体の高さの半分以下であり、より典 型的には 5nmから 25nmである。  [0310] The width Wei of the end insulator region (23, 27) should be thicker than the gate oxide film, which is smaller than half the width Wfin of the entire semiconductor. A typical upper limit is on the order of 15nm, more typically 5nm to 10nm. The height Htop of the end insulator region is not particularly limited, but is generally less than half of the total height of the semiconductor layer including the upper region 28, more typically from 5 nm. 25 nm.

[0311] 端部絶縁体の幅 Weiは一定でなくとも良レ、が、少なくとも半導体層 3の上端部に接 する位置において、ゲート酸化膜の厚さよりも大きいことが第一の課題を解決するた めには望ましぐまた端部絶縁体の幅 Weiは一定でない場合、 Weiの最大値の典型 的な上限は 15nm程度であり、より典型的には 5nmから 10nmである。  [0311] The width Wei of the end insulator may be not constant, but the first problem is solved by being larger than the thickness of the gate oxide film at least at a position in contact with the upper end of the semiconductor layer 3. For this reason, if the width of the desired and end insulator Wei is not constant, a typical upper limit for the maximum value of Wei is on the order of 15 nm, more typically 5 nm to 10 nm.

[0312] (不純物の導入）  [0312] (Introduction of impurities)

イオン注入は、ソース/ドレイン領域、ゲート電極などの、高濃度領域には、典型的 には 5 X 1018cm— 3から 1 X 1021cm 3のドナー不純物もしくはァクセプタ不純物が導入 される。より典型的には、 3 X 1019cm— 3から l X 102Qcm 3のドナー不純物もしくはァク セプタ不純物が導入される。不純物の導入は例えばイオン注入、あるいは気相拡散 により行う。イオン注入時の典型的なドーズ量は 1 X 1014cm 2から 3 X 1015cm— 2、より 典型的には 3 X 1014cm— 2から 1 X 1015cm— 2である。 Ion implantation typically introduces 5 × 10 18 cm −3 to 1 × 10 21 cm 3 of donor or acceptor impurities into high concentration regions, such as source / drain regions and gate electrodes. More typically, 3 × 10 19 cm −3 to 1 × 10 2 Q cm 3 of donor or acceptor impurities are introduced. The impurity is introduced by, for example, ion implantation or vapor phase diffusion. Typical doses during ion implantation are 1 × 10 14 cm 2 to 3 × 10 15 cm— 2 , more typically 3 × 10 14 cm— 2 to 1 × 10 15 cm— 2 .

[0313] チャネル形成領域などの低濃度領域におけるネット不純物濃度（第一導電型不純 物濃度と、第二導電型不純物濃度の差の絶対値）は、典型的には 1 X 1017cm— 3から 1 X 1019cm— 3、より典型的には 5 X 1017cm— 3力 5 X 1018cm— 3である。但し、これらの 典型的な不純物濃度を各領域の主要部分に持つトランジスタにおいても、イオン注 入の条件によっては局所的にこれらの典型的な値を超える場合がある。 [0313] Net impurity concentration in the low concentration region such as the channel formation region (a first conductivity type impurity concentration, the absolute value of the difference of the second conductivity type impurity concentration) is typically 1 X 10 17 cm- 3 From 1 × 10 19 cm— 3 , more typically 5 × 10 17 cm— 3 force 5 × 10 18 cm— 3 . However, even in a transistor having a typical impurity concentration in a main part of each region, the transistor may locally exceed the typical value depending on ion implantation conditions.

[0314] また、寄生トランジスタの影響が特に顕著であるのは、チャネル形成領域領域にお ける第二導電型のネット不純物濃度が 1 X 1018cm— 3以上の場合であるので、本発明 を、チャネル形成領域領域における第二導電型のネット不純物濃度が 1 X 1018cm— 3 以上の電界効果型トランジスタに適用すると特に有効である。また、寄生トランジスタ の抑制以外の理由（ゲート絶縁膜の信頼性向上、ゲート絶縁膜の歩留まり向上、さら には第二実施形態の説明において記載したように短チャネル効果の抑制など）で電 界集中を緩和することを目的に、チャネル形成領域領域における第二導電型のネッ ト不純物濃度が 1 X 1018cm 3以下の電界効果型トランジスタ、さらにはチャネル形成 領域に不純物が導入されなレ、か、チャネル形成領域領域が第一導電型の電界効果 型トランジスタに、本発明の各実施形態を適用しても良い。 [0314] In addition, the influence of the parasitic transistor is particularly remarkable, since the net impurity concentration of the second conductivity type Keru Contact to the channel formation region region is the case of 1 X 10 18 cm- 3 or more, the present invention The concentration of the net impurity of the second conductivity type in the channel forming region is 1 × 10 18 cm— 3 It is particularly effective when applied to the above-described field-effect transistor. In addition, electric field concentration occurs for reasons other than the suppression of parasitic transistors (for example, improvement of the reliability of the gate insulation film, improvement of the yield of the gate insulation film, and suppression of the short channel effect as described in the description of the second embodiment). In order to alleviate the problem, a field effect transistor having a second conductivity type net impurity concentration of 1 × 10 18 cm 3 or less in the channel formation region, and furthermore, impurities are not introduced into the channel formation region. Alternatively, each embodiment of the present invention may be applied to a field-effect transistor in which a channel formation region is a first conductivity type.

[0315] ソース Zドレイン領域に導入する第一導電型の不純物、及びソース/ドレイン領域 に導入する第一導電型の不純物は、 nチャネルトランジスタの場合は n型の導電型を 持つドナー不純物を、 pチャネルトランジスタの場合は p型の導電型を持つァクセプタ 不純物を選べば良い。  [0315] The first conductivity type impurity introduced into the source Z drain region and the first conductivity type impurity introduced into the source / drain region are a donor impurity having an n type conductivity in the case of an n-channel transistor. In the case of a p-channel transistor, an impurity having a p-type conductivity may be selected.

[0316] ハロー領域に導入される第二導電型の不純物は、 nチャネルトランジスタの場合は p型の導電型を持つァクセプタ不純物を、 pチャネルトランジスタの場合は n型の導電 型を持つドナー不純物を選べば良レ、。  [0316] The impurity of the second conductivity type introduced into the halo region is an acceptor impurity having a p-type conductivity in the case of an n-channel transistor, and a donor impurity having an n-type conductivity in the case of a p-channel transistor. Good choice ,.

[0317] n型不純物の典型例はヒ素、リン、アンチモンである。 p型不純物は典型例はホウ素 、インジウムである。  [0317] Typical examples of the n-type impurity are arsenic, phosphorus, and antimony. Typical examples of the p-type impurity are boron and indium.

[0318] イオン注入した不純物の活性化は、イオン注入後、通常の電気炉によるァニール、 ランプアニールなどの加熱処理によって行う。なお、チャネル領域へ注入したイオン を活性化するための熱処理は、イオン注入直後に行っても良ぐソース/ドレイン領 域に導入した不純物を活性化するための熱処理で兼ねても良い。  [0318] Activation of the ion-implanted impurities is performed by a heat treatment such as annealing or lamp annealing in a normal electric furnace after the ion implantation. Note that the heat treatment for activating the ions implanted into the channel region may be performed immediately after the ion implantation, or may be combined with the heat treatment for activating the impurities introduced into the source / drain regions.

[0319] ソース/ドレイン領域への不純物の導入はゲート電極の形成後にゲート電極に覆 われていない領域に対して導入する方法を用いてもよぐまたゲート電極の形成より も前に、ソース/ドレイン領域が形成されるべき領域にあらかじめ不純物を導入して おく方法を用いても良い。  [0319] Impurity introduction into the source / drain regions may be performed by introducing the impurity into the region not covered by the gate electrode after the formation of the gate electrode. A method in which an impurity is previously introduced into a region where a drain region is to be formed may be used.

[0320] (ソース Zドレイン領域 6、コンタクト 17、配線 18の配置）  [0320] (Arrangement of source Z drain region 6, contact 17, wiring 18)

各実施形態におけるソース Zドレイン領域 6、層間絶縁膜 16、コンタクト 17、配線 1 8等、半導体装置を構成する各部分の配置は通常の FinFETと同様である。例えば 第一の実施形態を説明する図 8及び図 9に図示される配置と同じ配置をとる。 なお各実施形態においては、主に nチャネルトランジスタについて説明した力 S、 pチ ャネルトランジスタにおいては、極性を逆にすれば（例えば、 nチャネルトランジスタに おける電位上昇を、 pチャネルトランジスタにおいては電位低下と読みかえる。また、 n チャネルトランジスタにおけるしきい値電圧の低下を、 pチャネルトランジスタにおいて はしきい値電圧の上昇と読みかえる。また、電圧や電位が高いという記載を電圧ゃ電 位が低いと読みかえる。また、ドレイン電圧など印加電圧の符号を逆にする。）同様の 議論が成り立つ。 In each embodiment, the arrangement of each part constituting the semiconductor device, such as the source Z drain region 6, the interlayer insulating film 16, the contact 17, the wiring 18 and the like, is the same as that of a normal FinFET. For example, the arrangement is the same as that shown in FIGS. 8 and 9 for explaining the first embodiment. In each of the embodiments, when the polarity is reversed in the power S and p channel transistors described mainly for the n channel transistor (for example, the potential rise in the n channel transistor and the potential in the p channel transistor are reversed). A decrease in the threshold voltage of an n-channel transistor can be interpreted as a rise in the threshold voltage of a p-channel transistor, and an increase in the voltage or potential can be interpreted as a decrease in the voltage-to-potential. In addition, the sign of the applied voltage such as the drain voltage is reversed.) The same argument holds.

Claims

請求の範囲 The scope of the claims [1] 基体平面から上方に突起した半導体層と、この半導体層を跨ぐようにその上部から 相対する両側面上に延在するゲート電極と、このゲート電極と前記半導体層の側面 の間に介在するゲート絶縁膜と、前記半導体層上に設けられ前記ゲート電極下に位 置するキャップ絶縁層と、前記半導体層の前記ゲート電極に覆われない領域に形成 されたソース Zドレイン領域とを有し、  [1] A semiconductor layer protruding upward from the base plane, a gate electrode extending from the upper side to oppose both sides so as to straddle the semiconductor layer, and interposed between the gate electrode and a side surface of the semiconductor layer. A gate insulating film provided on the semiconductor layer, a cap insulating layer provided below the gate electrode, and a source Z drain region formed in a region of the semiconductor layer not covered by the gate electrode. , 前記キャップ絶縁層は、前記基体平面に平行方向であって一対のソース/ドレイン 領域を結ぶチャネル長方向に垂直な方向へ、前記ゲート絶縁膜の表面から張り出し た張り出し部を有することを特徴とする電界効果型トランジスタ。  The cap insulating layer has an overhanging portion extending from the surface of the gate insulating film in a direction parallel to the plane of the base and perpendicular to a channel length direction connecting the pair of source / drain regions. Field-effect transistor. [2] 前記張り出し部は、前記ゲート絶縁膜の表面に対する張り出し幅が 5nm以上であ る請求項 1記載の電界効果型トランジスタ。  2. The field effect transistor according to claim 1, wherein the overhang portion has an overhang width of 5 nm or more with respect to a surface of the gate insulating film. [3] 前記張り出し部は、前記ゲート絶縁膜の表面に対する張り出し幅が 5nm以上、 20η m以下である請求項 1記載の電界効果型トランジスタ。 3. The field effect transistor according to claim 1, wherein the overhang portion has an overhang width with respect to a surface of the gate insulating film of 5 nm or more and 20 ηm or less. [4] 前記張り出し部は、前記ゲート絶縁膜の表面に対する張り出し幅が当該ゲート絶縁 膜の厚さの 2. 5倍以上である請求項 1、 2又は 3記載の電界効果型トランジスタ。 4. The field-effect transistor according to claim 1, 2 or 3, wherein the overhang portion has an overhang width with respect to the surface of the gate insulating film that is 2.5 times or more the thickness of the gate insulating film. [5] 前記張り出し部は、前記ゲート絶縁膜の表面に対する張り出し幅が当該ゲート絶縁 膜の厚さの 2. 5倍以上、 10倍以下である請求項 1、 2又は 3記載の電界効果型トラン ジスタ。 5. The field effect transformer according to claim 1, 2 or 3, wherein the overhang portion has an overhang width with respect to the surface of the gate insulating film of not less than 2.5 times and not more than 10 times the thickness of the gate insulating film. Jista. [6] 前記張り出し部は、前記半導体層の基体平面に平行且つチャネル長方向に垂直 な方向の幅が最も広レ、位置におけるゲート絶縁膜表面に対して張り出してレ、る請求 項 1一 5のいずれ力 4項に記載の電界効果型トランジスタ。  [6] The projecting portion projects from the surface of the gate insulating film at a position where the width of the semiconductor layer in the direction parallel to the substrate plane and perpendicular to the channel length direction is the widest. The field-effect transistor according to item 4. [7] 請求項 1一 6のいずれ力 4項に記載の電界効果型トランジスタの製造方法であって 半導体層上にキャップ絶縁層を形成し、前記半導体層および前記キャップ絶縁層 をパターユングして基体平面から上方に突起した半導体層とその上にパターユング されたキャップ絶縁層を形成する工程と、  7. The method for manufacturing a field effect transistor according to claim 4, wherein a cap insulating layer is formed on a semiconductor layer, and the semiconductor layer and the cap insulating layer are patterned. Forming a semiconductor layer projecting upward from the plane of the base and a cap insulating layer patterned thereon; 前記キャップ絶縁層下の半導体層の側面が当該キャップ絶縁層の端部よりも内側 に後退するように、前記半導体層の側面をエッチングして当該半導体層を細らせる 工程と、 The side surface of the semiconductor layer is etched to narrow the semiconductor layer so that the side surface of the semiconductor layer below the cap insulating layer recedes inward from the end of the cap insulating layer. Process and 前記半導体層の側面にゲート絶縁膜を形成する工程とを有する電界効果型トラン ジスタの製造方法。  Forming a gate insulating film on a side surface of the semiconductor layer. [8] ゲート電極材料を堆積し、このゲート電極材料堆積膜をパターニングしてゲート電 極を形成する工程と、  [8] a step of depositing a gate electrode material and patterning the gate electrode material deposited film to form a gate electrode; 前記半導体層に不純物を導入してソース/ドレイン領域を形成する工程をさらに有 する請求項 7記載の電界効果型トランジスタの製造方法。  8. The method for manufacturing a field effect transistor according to claim 7, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer. [9] 基体平面から上方に突起した半導体層と、この半導体層の両側面上に設けられた ゲート電極と、このゲート電極と前記半導体層の側面の間に介在するゲート絶縁膜と 、前記ゲート電極に覆われなレ、領域に形成されたソース Zドレイン領域とを有し、 さらに、前記半導体層の上部でゲート電極の上端よりも低い位置に、 SiOよりも誘 [9] A semiconductor layer protruding upward from a base plane, a gate electrode provided on both side surfaces of the semiconductor layer, a gate insulating film interposed between the gate electrode and a side surface of the semiconductor layer, A source Z drain region formed in a region that is not covered with the electrode; and a lower electrode than the SiO at a position lower than the upper end of the gate electrode above the semiconductor layer. 2 電率が低い低誘電率領域を有することを特徴とする電界効果型トランジスタ。  (2) A field effect transistor having a low dielectric constant region having a low electric conductivity. [10] 前記半導体層の上部に接して、 SiOよりも誘電率が低い低誘電率領域を有する請 [10] A contract having a low dielectric constant region having a lower dielectric constant than SiO in contact with the upper portion of the semiconductor layer. 2  2 求項 9記載の電界効果型トランジスタ。  10. The field effect transistor according to claim 9. [11] 前記半導体層の上部に接して、 SiOまたは SiOよりも誘電率が高い保護絶縁膜が [11] In contact with the upper part of the semiconductor layer, SiO or a protective insulating film having a higher dielectric constant than SiO is formed. 2 2  twenty two 設けられ、この保護絶縁膜の上に SiOよりも誘電率が低い低誘電率領域を有する請  And a low dielectric constant region having a dielectric constant lower than that of SiO on the protective insulating film. 2  2 求項 9記載の電界効果型トランジスタ。  10. The field effect transistor according to claim 9. [12] 前記低誘電率領域が空洞よりなる請求項 9一 11のいずれか一項に記載の電界効 果型トランジスタ。 12. The field effect transistor according to claim 9, wherein the low dielectric constant region comprises a cavity. [13] 前記半導体層の下部に SiOよりも誘電率が低い低誘電率領域を有する請求項 9  13. A low dielectric constant region having a lower dielectric constant than SiO under the semiconductor layer. 2  2 一 12のいずれか一項に記載の電界効果型トランジスタ。  13. The field-effect transistor according to any one of 12. [14] 前記半導体層の下部に、 SiOよりも誘電率が低い低誘電率領域を有し、前記グー [14] A low dielectric constant region having a lower dielectric constant than SiO is provided below the semiconductor layer, 2  2 ト電極の下部には、 SiOよりも誘電率が低い低誘電率領域を有しない請求項 9  10. There is no low dielectric constant region having a lower dielectric constant than SiO under the gate electrode. 2 一 12 のレ、ずれか一項に記載の電界効果型トランジスタ。  2. The field-effect transistor according to claim 1, wherein [15] 前記半導体層の下部に設けられる前記低誘電率領域が空洞よりなる請求項 13又 は 14記載の電界効果型トランジスタ。 15. The field effect transistor according to claim 13, wherein the low dielectric constant region provided below the semiconductor layer comprises a cavity. [16] 前記半導体層は、第 1の絶縁層上に、この第 1の絶縁層とは異なる材料からなる第 [16] The semiconductor layer is formed on the first insulating layer using a material different from the material of the first insulating layer. 2の絶縁層を介して設けられ、 前記ゲート電極は、第 1の絶縁層上に第 2の絶縁層を介さずに直接第 1の絶縁層 に接する部分を有する請求項 9一 12のいずれか一項に記載の電界効果型トランジス タ。 2, provided through an insulating layer, The field-effect transistor according to claim 9, wherein the gate electrode has a portion on the first insulating layer that directly contacts the first insulating layer without interposing the second insulating layer. . [17] 第 2の絶縁層が SiOよりも誘電率が低い材料からなる請求項 16記載の電界効果 型トランジスタ。  17. The field effect transistor according to claim 16, wherein the second insulating layer is made of a material having a lower dielectric constant than SiO. [18] 第 2の絶縁層が空洞よりなる請求項 16記載の電界効果型トランジスタ。  [18] The field effect transistor according to claim 16, wherein the second insulating layer comprises a cavity. [19] 前記キャップ絶縁層の少なくとも一部が SiOよりも誘電率が低い低誘電率材料より なる請求項 1一 6のいずれか一項に記載の電界効果型トランジスタ。  [19] The field effect transistor according to any one of [16] to [16], wherein at least a part of the cap insulating layer is made of a low dielectric constant material having a dielectric constant lower than that of SiO. [20] 前記キャップ絶縁層の少なくとも一部に空洞を有する請求項 1一 6のいずれか一項 に記載の電界効果型トランジスタ。 [20] The field effect transistor according to any one of [16] to [16], wherein at least a part of the cap insulating layer has a cavity. [21] 前記半導体層と前記空洞の間に、 SiOまたは Si〇よりも誘電率が高い保護絶縁膜 を有する請求項 20記載の電界効果型トランジスタ。 21. The field effect transistor according to claim 20, further comprising a protective insulating film having a higher dielectric constant than SiO or Si between the semiconductor layer and the cavity. [22] 前記半導体層の下部に、 SiOよりも誘電率が低い低誘電率領域を有する請求項 1 一 6のレ、ずれか一項に記載の電界効果型トランジスタ。 22. The field-effect transistor according to claim 16, wherein a lower dielectric constant region having a lower dielectric constant than SiO is provided below the semiconductor layer. [23] 前記半導体層の下部に、 SiOよりも誘電率が低い低誘電率領域を有し、前記ゲー ト電極の下部には、 SiOよりも誘電率が低い低誘電率領域を有しない請求項 1一 6 のレヽずれか一項に記載の電界効果型トランジスタ。 [23] A low dielectric constant region having a lower dielectric constant than SiO below the semiconductor layer, and a low dielectric constant region having a lower dielectric constant than SiO is not formed below the gate electrode. 17. The field-effect transistor according to any one of items 1 to 6. [24] 前記低誘電率領域が空洞よりなる請求項 22又は 23記載の電界効果型トランジスタ 24. The field effect transistor according to claim 22, wherein the low dielectric constant region is formed of a cavity. [25] 請求項 9に記載の電界効果型トランジスタの製造方法であって、 [25] The method for manufacturing a field-effect transistor according to claim 9, 半導体層上に SiOよりも誘電率が低い材料を堆積して低誘電率膜を形成するェ 程と、  Depositing a material having a lower dielectric constant than SiO on the semiconductor layer to form a low dielectric constant film; 前記半導体層および前記低誘電率膜をパターニングして、基体平面から突起した 半導体層とその上にパターニングされた前記低誘電率膜からなる低誘電率領域を形 成する工程とを有する電界効果型トランジスタの製造方法。  Patterning the semiconductor layer and the low dielectric constant film to form a semiconductor layer protruding from a substrate plane and a low dielectric constant region composed of the low dielectric constant film patterned thereon. A method for manufacturing a transistor. [26] 前記の突起した半導体層の側面にゲート絶縁膜を形成する工程と、 [26] forming a gate insulating film on a side surface of the protruding semiconductor layer; ゲート電極材料を堆積し、このゲート電極材料堆積膜をパターニングしてゲート電 極を形成する工程と、 前記半導体層に不純物を導入してソース/ドレイン領域を形成する工程をさらに有 する請求項 25記載の電界効果型トランジスタの製造方法。 Depositing a gate electrode material and patterning the gate electrode material deposited film to form a gate electrode; 26. The method for manufacturing a field effect transistor according to claim 25, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer. [27] 請求項 9に記載の電界効果型トランジスタの製造方法であって、 [27] The method for producing a field-effect transistor according to claim 9, wherein 半導体層上にダミー層を形成する工程と、  Forming a dummy layer on the semiconductor layer; 前記半導体層および前記ダミー層をパターニングして、基体平面から突起した半 導体層とその上にパターユングされたダミー層を形成する工程と、  Patterning the semiconductor layer and the dummy layer to form a semiconductor layer protruding from the plane of the base and a dummy layer patterned on the semiconductor layer; 前記ダミー層を除去して前記半導体層上部に前記低誘電率領域として空洞を形成 する工程とを有する電界効果型トランジスタの製造方法。  Removing the dummy layer to form a cavity above the semiconductor layer as the low dielectric constant region. [28] 前記の突起した半導体層の側面にゲート絶縁膜を形成する工程と、 [28] a step of forming a gate insulating film on a side surface of the protruding semiconductor layer; ゲート電極材料を堆積し、このゲート電極材料堆積膜をパターニングしてゲート電 極を形成する工程と、  Depositing a gate electrode material and patterning the gate electrode material deposited film to form a gate electrode; 前記半導体層に不純物を導入してソース/ドレイン領域を形成する工程をさらに有 し、  Forming a source / drain region by introducing an impurity into the semiconductor layer; ゲート電極の形成後に前記ダミー層を除去することにより前記空洞よりなる低誘電 率領域を形成することを特徴とする請求項 27記載の電界効果型トランジスタの製造 方法。  28. The method according to claim 27, wherein the dummy layer is removed after forming the gate electrode to form a low dielectric constant region including the cavity. [29] 前記空洞を SiOよりも誘電率が低い材料で坦め戻す工程をさらに有する請求項 27  29. The method according to claim 27, further comprising the step of backfilling the cavity with a material having a lower dielectric constant than SiO. 2  2 又は 28記載の電界効果型トランジスタの製造方法。  29. The method for manufacturing a field-effect transistor according to 28. [30] 前記空洞を多孔質の材料で埋め戻す工程をさらに有する請求項 27又は 28記載の 電界効果型トランジスタの製造方法。 30. The method for manufacturing a field effect transistor according to claim 27, further comprising a step of backfilling the cavity with a porous material. [31] 基体平面から上方に突起した半導体層と、この半導体層の両側面上に設けられた ゲート電極と、このゲート電極と前記半導体層の側面の間に介在するゲート絶縁膜と[31] A semiconductor layer projecting upward from the plane of the base, a gate electrode provided on both side surfaces of the semiconductor layer, and a gate insulating film interposed between the gate electrode and a side surface of the semiconductor layer. 、前記半導体層の前記ゲート電極に覆われない領域に形成されたソース/ドレイン 領域とを有し、 Source / drain regions formed in a region of the semiconductor layer that is not covered by the gate electrode, 前記半導体層の上部の側面には、ゲート電極との間に、前記ゲート絶縁膜よりも厚 い端部絶縁体領域を有することを特徴とする電界効果型トランジスタ。  A field-effect transistor having an end insulator region thicker than the gate insulating film between the gate electrode and a side surface on an upper portion of the semiconductor layer. [32] 基体平面から上方に突起した半導体層と、この半導体層の両側面上に設けられた ゲート電極と、このゲート電極と前記半導体層の側面の間に介在するゲート絶縁膜と 、前記半導体層の前記ゲート電極に覆われない領域に形成されたソース/ドレイン 領域とを有し、 [32] A semiconductor layer protruding upward from the substrate plane, gate electrodes provided on both side surfaces of the semiconductor layer, and a gate insulating film interposed between the gate electrode and the side surface of the semiconductor layer. Source / drain regions formed in a region of the semiconductor layer that is not covered by the gate electrode, 前記半導体層は、一対のソース/ドレイン領域を結ぶチャネル長方向と垂直な面 内における基体平面に平行方向の半導体層の幅 Wがその下方部分の幅より小さレヽ 半導体層上部領域と、この半導体層上部領域の下方に位置し、当該半導体層の幅 The semiconductor layer includes a semiconductor layer upper region in which a width W of the semiconductor layer in a direction perpendicular to a channel length direction connecting the pair of source / drain regions and parallel to the substrate plane is smaller than a width of a lower portion thereof. The width of the semiconductor layer is located below the layer upper region. Wが前記半導体層上部領域の幅より大きい半導体層下部領域とを有し、 W has a semiconductor layer lower region larger than the width of the semiconductor layer upper region, 前記半導体層上部領域は、当該半導体層の側面が前記半導体層下部領域にお ける半導体層の側面よりも後退し、この後退した側面と前記ゲート電極の間に、前記 ゲート絶縁膜より厚い端部絶縁体領域を有することを特徴とする電界効果型トランジ スタ。  In the semiconductor layer upper region, a side surface of the semiconductor layer is recessed from a side surface of the semiconductor layer in the semiconductor layer lower region, and an end portion thicker than the gate insulating film is provided between the recessed side surface and the gate electrode. A field-effect transistor having an insulator region. [33] 前記半導体層上部の幅 Wが一定である請求項 32記載の電界効果型トランジスタ。  33. The field effect transistor according to claim 32, wherein a width W of the upper part of the semiconductor layer is constant. [34] 前記半導体層上部の幅 Wが連続的に変化し、これに応じて前記端部絶縁体領域 の厚みも連続的に変化している請求項 32記載の電界効果型トランジスタ。 34. The field-effect transistor according to claim 32, wherein the width W of the upper portion of the semiconductor layer continuously changes, and accordingly, the thickness of the end insulator region also changes continuously. [35] 前記半導体層上部の幅 Wは、当該半導体層の上端へ向かうに従って一定の勾配 をもって徐々に小さくなり、これに応じて前記端部絶縁体領域の厚みが当該半導体 層の上端へ向力うに従って徐々に大きくなる請求項 32記載の電界効果型トランジス タ。 [35] The width W of the upper part of the semiconductor layer gradually decreases with a constant gradient toward the upper end of the semiconductor layer, and accordingly, the thickness of the end insulator region is directed toward the upper end of the semiconductor layer. 33. The field effect transistor according to claim 32, wherein the field effect transistor gradually increases in size. [36] 前記半導体層上部の幅 Wは、当該半導体層の上端へ向かうに従って、当該半導 体層の側面が曲率をもつように徐々に小さくなり、これに応じて前記端部絶縁体領域 の厚みが当該半導体層の上端に向力うに従って徐々に大きくなる請求項 32記載の 電界効果型トランジスタ。  [36] The width W of the upper portion of the semiconductor layer gradually decreases toward the upper end of the semiconductor layer so that the side surface of the semiconductor layer has a curvature, and accordingly, the width of the end insulator region is reduced. 33. The field-effect transistor according to claim 32, wherein the thickness gradually increases as moving toward the upper end of the semiconductor layer. [37] 前記半導体層の幅 Wが、当該半導体層の下端部から上端部にかけて一定である 請求項 31記載の電界効果型トランジスタ。  37. The field effect transistor according to claim 31, wherein a width W of the semiconductor layer is constant from a lower end to an upper end of the semiconductor layer. [38] 基体平面から上方に突起した半導体層と、この半導体層の両側面上に設けられた ゲート電極と、このゲート電極と前記半導体層の側面の間に介在するゲート絶縁膜と 、前記半導体層の前記ゲート電極に覆われない領域に形成されたソース/ドレイン 領域とを有し、  [38] A semiconductor layer protruding upward from a base plane, a gate electrode provided on both side surfaces of the semiconductor layer, a gate insulating film interposed between the gate electrode and a side surface of the semiconductor layer, Source / drain regions formed in regions of the layer that are not covered by the gate electrode, 前記半導体層は、一対のソース/ドレイン領域を結ぶチャネル長方向と垂直な面 内における基体平面に平行方向の半導体層の幅 wがその下方部分の幅より小さい 半導体層上部領域と、この半導体層上部領域の下方に位置し、当該半導体層の幅The semiconductor layer has a surface perpendicular to a channel length direction connecting the pair of source / drain regions. The width w of the semiconductor layer in the direction parallel to the substrate plane is smaller than the width of the lower portion of the semiconductor layer, and the width of the semiconductor layer is located below the upper region of the semiconductor layer. Wが前記半導体層上部領域の幅より大きい半導体層下部領域とを有し、 W has a semiconductor layer lower region larger than the width of the semiconductor layer upper region, 前記半導体層上部領域は、前記半導体層下部領域に接続する部分に当該半導 体層の幅 wが連続的に変化する遷移領域を有し、この遷移領域端部から当該半導 体層の上端にかけて幅 Wが一定であり、  The semiconductor layer upper region has a transition region in which the width w of the semiconductor layer continuously changes at a portion connected to the semiconductor layer lower region, and an upper end of the semiconductor layer from an end of the transition region. The width W is constant over 当該半導体層上部領域と前記ゲート電極の間には、前記ゲート絶縁膜より厚い端 部絶縁体領域を有することを特徴とする電界効果型トランジスタ。  A field effect transistor having an end insulator region thicker than the gate insulating film between the semiconductor layer upper region and the gate electrode. [39] 前記半導体層の上部にゲート絶縁膜よりも厚いキャップ絶縁層が設けられている請 求項 31— 38のいずれか 1項に記載の電界効果型トランジスタ。  [39] The field-effect transistor according to any one of claims 31 to 38, wherein a cap insulating layer thicker than a gate insulating film is provided on the semiconductor layer. [40] 前記端部絶縁体領域が前記キャップ絶縁層とは異なる材料からなる請求項 39記 載の電界効果型トランジスタ。  40. The field effect transistor according to claim 39, wherein the end insulator region is made of a material different from that of the cap insulating layer. [41] 前記端部絶縁体領域が Si〇により構成される請求項 31— 39のいずれ力 1項に記 載の電界効果型トランジスタ。  41. The field-effect transistor according to claim 31, wherein the end insulator region is made of Si. [42] 前記端部絶縁体領域の少なくとも一部が SiOよりも誘電率が低い材料により構成さ れる請求項 31— 39のいずれ力 1項に記載の電界効果型トランジスタ。 42. The field-effect transistor according to any one of claims 31 to 39, wherein at least a part of the end insulator region is made of a material having a lower dielectric constant than SiO. [43] 前記端部絶縁体領域の少なくとも一部が多孔質の材料により構成される請求項 31 一 39のいずれか 1項に記載の電界効果型トランジスタ。 43. The field effect transistor according to claim 31, wherein at least a part of the end insulator region is made of a porous material. [44] 前記端部絶縁体領域の少なくとも一部が空洞により構成される請求項 31— 39のい ずれ力 1項に記載の電界効果型トランジスタ。 44. The field-effect transistor according to any one of claims 31 to 39, wherein at least a part of the end insulator region is constituted by a cavity. [45] 請求項 32記載の電界効果型トランジスタの製造方法であって、 [45] The method for manufacturing a field-effect transistor according to claim 32, 半導体層上に第 1絶縁膜を堆積し、この第 1絶縁膜および前記半導体層の上部を 所定の幅にパターユングする工程と、  Depositing a first insulating film on the semiconductor layer, and patterning the upper portion of the first insulating film and the semiconductor layer to a predetermined width; 第 2絶縁膜の堆積とエッチバックを行レ、、パターユングされた第 1絶縁膜の側面及 び半導体層の側面に、第 2絶縁膜からなる端部絶縁体領域を形成する工程と、 この端部絶縁体領域およびパターニングされた第 1絶縁膜をマスクに前記半導体 層をエッチングする工程と、  Depositing and etching back the second insulating film, and forming an end insulator region made of the second insulating film on the side surface of the patterned first insulating film and the side surface of the semiconductor layer; Etching the semiconductor layer using the end insulator region and the patterned first insulating film as a mask; 前記のエッチングにより露出した半導体層の側面にゲート絶縁膜を形成する工程と を有する電界効果型トランジスタの製造方法。 Forming a gate insulating film on the side surface of the semiconductor layer exposed by the etching; A method for manufacturing a field effect transistor having: [46] ゲート電極材料を堆積し、このゲート電極材料堆積膜をパターユングしてゲート電 極を形成する工程と、  [46] a step of depositing a gate electrode material and patterning the gate electrode material deposited film to form a gate electrode; 前記半導体層に不純物を導入してソース/ドレイン領域を形成する工程をさらに有 する請求項 45記載の電界効果型トランジスタの製造方法。  46. The method for manufacturing a field effect transistor according to claim 45, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor layer. [47] 請求項 32記載の電界効果型トランジスタの製造方法であって、 [47] The method for manufacturing a field-effect transistor according to claim 32, 半導体層上にキャップ絶縁層を堆積し、このキャップ絶縁層および前記半導体層 の上部を所定の幅にパターユングする工程と、  Depositing a cap insulating layer on the semiconductor layer, and patterning the cap insulating layer and the upper portion of the semiconductor layer to a predetermined width; ダミー層の堆積とエッチバックを行レ、、パターユングされたキャップ絶縁層の側面及 び半導体層の側面に、前記ダミー層からなるコーナーダミー層を形成する工程と、 このコーナーダミー層およびパターユングされた前記キャップ絶縁層をマスクに前 記半導体層をエッチングする工程と、  Depositing and etching back a dummy layer, forming a corner dummy layer made of the dummy layer on the side surface of the patterned cap insulating layer and the side surface of the semiconductor layer; Etching the semiconductor layer using the cap insulating layer as a mask, 前記のエッチングにより露出した半導体層の側面にゲート絶縁膜を形成する工程と 前記コーナーダミー層を除去して空洞よりなる端部絶縁体領域を形成する工程とを 有する電界効果型トランジスタの製造方法。  A method for manufacturing a field effect transistor, comprising: a step of forming a gate insulating film on a side surface of a semiconductor layer exposed by the etching; and a step of forming an end insulator region including a cavity by removing the corner dummy layer. [48] 請求項 32記載の電界効果型トランジスタの製造方法であって、 [48] The method for manufacturing a field-effect transistor according to claim 32, wherein 半導体層上にキャップ絶縁層を堆積し、このキャップ絶縁層および前記半導体層 の上部を所定の幅にパターニングする工程と、  Depositing a cap insulating layer on the semiconductor layer, and patterning the cap insulating layer and the upper portion of the semiconductor layer to a predetermined width; 第 1ダミー層の堆積とエッチバックを行レ、、パターニングされたキャップ絶縁層の側 面及び半導体層の側面に、第 1ダミー層からなる第 1コーナーダミー層を形成するェ 程と、  Depositing and etching back the first dummy layer, and forming a first corner dummy layer comprising the first dummy layer on the side surface of the patterned cap insulating layer and the side surface of the semiconductor layer; 第 2ダミー層の堆積とエッチバックを行い、第 1コーナダミー層の側面に、第 2ダミー 層からなる第 2コーナーダミー層を形成する工程と、  Depositing and etching back a second dummy layer to form a second corner dummy layer comprising a second dummy layer on a side surface of the first corner dummy layer; 第 1及び第 2コーナーダミー層並びにパターユングされた前記キャップ絶縁層をマ スクに前記半導体層をエッチングする工程と、  Etching the semiconductor layer using the first and second corner dummy layers and the patterned cap insulating layer as a mask; 前記のエッチングにより露出した半導体層の側面にゲート絶縁膜を形成する工程と 第 1コーナーダミー層を除去して空洞よりなる端部絶縁体領域を形成する工程とを 有する電界効果型トランジスタの製造方法。 Forming a gate insulating film on the side surface of the semiconductor layer exposed by the etching; Removing the first corner dummy layer to form an end insulator region comprising a cavity. [49] ゲート電極材料を堆積し、このゲート電極材料堆積膜をパターユングしてゲート電 極を形成する工程と、  [49] depositing a gate electrode material and patterning the gate electrode material deposited film to form a gate electrode; 前記半導体層に不純物を導入してソース/ドレイン領域を形成する工程をさらに有 し、  Forming a source / drain region by introducing an impurity into the semiconductor layer; ゲート電極の形成後に前記空洞よりなる端部絶縁体領域を形成することを特徴とす る請求項 47又は 48記載の電界効果型トランジスタの製造方法。  49. The method for manufacturing a field-effect transistor according to claim 47, wherein an end insulator region comprising the cavity is formed after forming the gate electrode. [50] 前記コーナーダミー層を除去して空洞を形成した後、この空洞に Si〇よりも誘電率 が低レ、低誘電率材料を埋め戻し、この低誘電率材料よりなる端部絶縁体領域を形成 する工程をさらに有する請求項 47又は 48記載の電界効果型トランジスタの製造方 法。 [50] After removing the corner dummy layer to form a cavity, the cavity is filled with a low dielectric constant material having a lower dielectric constant than that of Si〇, and an end insulator region made of the low dielectric constant material is embedded. 49. The method for manufacturing a field-effect transistor according to claim 47, further comprising a step of forming. [51] 請求項 35記載の電界効果型トランジスタの製造方法であって、  [51] The method for producing a field-effect transistor according to claim 35, 半導体層上に第 1絶縁膜を形成し、この第 1絶縁膜をパターニングする工程と、 パターニングされた第 1絶縁膜をマスクに、前記半導体層の上部を、その幅 Wが上 端に向力うに従って徐々に小さくなるテーパー形状を有するようにエッチングするェ 程と、  Forming a first insulating film on the semiconductor layer, and patterning the first insulating film; using the patterned first insulating film as a mask, the upper portion of the semiconductor layer has a width W directed toward the upper end; Etching so as to have a tapered shape that gradually becomes smaller as 第 2絶縁膜の堆積とエッチバックを行い、パターニングされた第 1絶縁膜の側面およ び半導体層のテーパー形状の側面に、第 2絶縁膜からなる端部絶縁体領域を形成 する工程と、  Depositing and etching back the second insulating film to form an end insulator region made of the second insulating film on the side surface of the patterned first insulating film and the tapered side surface of the semiconductor layer; この端部絶縁体領域およびパターユングされた第 1絶縁膜をマスクに前記半導体 層をエッチングする工程と、  Etching the semiconductor layer using the end insulator region and the patterned first insulating film as a mask; 前記のエッチングにより露出した半導体層の側面にゲート絶縁膜を形成する工程と を有する電界効果型トランジスタの製造方法。  Forming a gate insulating film on the side surface of the semiconductor layer exposed by the etching. [52] 前記のパターユングされた第 1絶縁膜及びその側面部分の第 2絶縁膜を除去して 前記半導体層の上面を露出する工程をさらに有し、 [52] The method further comprises a step of exposing the upper surface of the semiconductor layer by removing the patterned first insulating film and the second insulating film on a side surface thereof, 前記のゲート酸化膜の形成工程においては、前記半導体層の側面にカ卩えて、露出 した上面にもゲート酸化膜を形成する請求項 51記載の電界効果型トランジスタの製 造方法。 52. The field effect transistor according to claim 51, wherein, in the step of forming the gate oxide film, the gate oxide film is formed on the side surface of the semiconductor layer and the exposed upper surface is formed. Construction method. [53] ゲート電極材料を堆積し、このゲート電極材料堆積膜をパターユングしてゲート電 極を形成する工程と、  [53] depositing a gate electrode material and patterning the gate electrode material deposited film to form a gate electrode; 前記半導体層に不純物を導入してソース/ドレイン領域を形成する工程をさらに有 する請求項 51記載の電界効果型トランジスタの製造方法。  52. The method for manufacturing a field-effect transistor according to claim 51, further comprising a step of forming a source / drain region by introducing impurities into the semiconductor layer. [54] 請求項 36記載の電界効果型トランジスタの製造方法であって、 [54] The method for producing a field-effect transistor according to claim 36, 半導体層上に酸化剤透過性のキャップ絶縁層を形成する工程と、  Forming an oxidant-permeable cap insulating layer on the semiconductor layer; 前記キャップ絶縁層および前記半導体層をパターニングして、基体平面から突起し た半導体層とその上にパターユングされたキャップ絶縁層を形成する工程と、 前記半導体層と前記キャップ絶縁層との界面において、当該半導体層の側面が当 該キャップ絶縁層の端部よりも内側に後退するように酸化剤雰囲気中で当該半導体 層を酸化して、当該半導体層上部の幅 Wが当該半導体層上端に向力 に従って徐 々に小さくなる半導体層上部領域と、これに応じて厚みが徐々に大きくなる端部絶縁 領域を形成する工程とを有する電界効果型トランジスタの製造方法。  Patterning the cap insulating layer and the semiconductor layer to form a semiconductor layer protruding from the substrate plane and a cap insulating layer patterned thereon; and, at an interface between the semiconductor layer and the cap insulating layer. Then, the semiconductor layer is oxidized in an oxidant atmosphere such that the side surface of the semiconductor layer recedes inside the end of the cap insulating layer, and the width W of the upper portion of the semiconductor layer is directed toward the upper end of the semiconductor layer. A method for manufacturing a field-effect transistor, comprising: a step of forming an upper edge region of a semiconductor layer that gradually becomes smaller according to a force, and a step of forming an end insulating region that gradually becomes thicker accordingly. [55] 前記半導体層の側面にゲート絶縁膜を形成する工程と、 [55] forming a gate insulating film on a side surface of the semiconductor layer; ゲート電極材料を堆積し、このゲート電極材料堆積膜をパターユングしてゲート電 極を形成する工程と、  Depositing a gate electrode material and patterning the gate electrode material deposited film to form a gate electrode; 前記半導体層に不純物を導入してソース/ドレイン領域を形成する工程をさらに有 する請求項 54記載の電界効果型トランジスタの製造方法。  55. The method for manufacturing a field-effect transistor according to claim 54, further comprising a step of forming a source / drain region by introducing impurities into the semiconductor layer. [56] 前記キャップ絶縁層を除去して前記半導体層の上面を露出する工程と、 [56] removing the cap insulating layer to expose the upper surface of the semiconductor layer; 前記半導体層の上面および側面にゲート絶縁膜を形成する工程と、  Forming a gate insulating film on the top and side surfaces of the semiconductor layer; ゲート電極材料を堆積し、このゲート電極材料堆積膜をパターニングしてゲート電 極を形成する工程と、  Depositing a gate electrode material and patterning the gate electrode material deposited film to form a gate electrode; 前記半導体層に不純物を導入してソース/ドレイン領域を形成する工程をさらに有 する請求項 54記載の電界効果型トランジスタの製造方法。  55. The method for manufacturing a field-effect transistor according to claim 54, further comprising a step of forming a source / drain region by introducing impurities into the semiconductor layer. [57] 基体平面から上方に突起した半導体層と、この半導体層の両側面上に設けられた ゲート電極と、このゲート電極と前記半導体層の側面の間に介在するゲート絶縁膜と 、前記半導体層の前記ゲート電極に覆われない領域に形成されたソース/ドレイン 領域とを有し、 [57] A semiconductor layer protruding upward from the plane of the base, a gate electrode provided on both side surfaces of the semiconductor layer, a gate insulating film interposed between the gate electrode and a side surface of the semiconductor layer, Source / drain formed in areas of the layer not covered by the gate electrode And an area, 前記半導体層の上部の側面には、ゲート電極との間に、前記ゲート絶縁膜よりも厚 い第 1の端部絶縁体領域を有し、  On the upper side surface of the semiconductor layer, a first end insulator region thicker than the gate insulating film is provided between the semiconductor layer and the gate electrode; 前記半導体層の下部の側面には、ゲート電極との間に、前記ゲート絶縁膜よりも厚 い第 2の端部絶縁体領域を有することを特徴とする電界効果型トランジスタ。  A field-effect transistor having a second end insulator region, which is thicker than the gate insulating film, between a gate electrode and a lower side surface of the semiconductor layer. [58] 基体平面から上方に突起した半導体層と、この半導体層の両側面上に設けられた ゲート電極と、このゲート電極と前記半導体層の側面の間に介在するゲート絶縁膜と 、前記半導体層の前記ゲート電極に覆われない領域に形成されたソース/ドレイン 領域とを有し、 [58] A semiconductor layer protruding upward from the plane of the base, a gate electrode provided on both side surfaces of the semiconductor layer, a gate insulating film interposed between the gate electrode and a side surface of the semiconductor layer, Source / drain regions formed in regions of the layer that are not covered by the gate electrode, 前記半導体層は、一対のソース/ドレイン領域を結ぶチャネル長方向と垂直な面 内における基体平面に平行方向の半導体層の幅 Wがその下方部分の幅より小さレヽ 半導体層上部領域と、この半導体層上部領域の下方に位置し、当該半導体層の幅 Wが前記半導体層上部領域の幅より大きい半導体層主要部領域と、この半導体層 主要部領域の下方に位置し、当該半導体層の幅 Wが前記半導体層主要部領域の 幅より小さい半導体層下部領域を有し、  The semiconductor layer includes a semiconductor layer upper region in which a width W of the semiconductor layer in a direction perpendicular to a channel length direction connecting the pair of source / drain regions and parallel to the substrate plane is smaller than a width of a lower portion thereof. A semiconductor layer main portion region located below the layer upper region and having a width W of the semiconductor layer larger than the width of the semiconductor layer upper region; and a semiconductor layer width W positioned below the semiconductor layer main portion region. Has a semiconductor layer lower region smaller than the width of the semiconductor layer main portion region, 前記半導体層上部領域は、当該半導体層の側面が前記半導体層主要部領域に おける半導体層の側面よりも後退し、この後退した側面と前記ゲート電極の間に、前 記ゲート絶縁膜より厚い第 1端部絶縁体領域を有し、  In the semiconductor layer upper region, a side surface of the semiconductor layer is recessed from a side surface of the semiconductor layer in the semiconductor layer main portion region, and a portion of the semiconductor layer upper region which is thicker than the gate insulating film is provided between the recessed side surface and the gate electrode. Having one end insulator region, 前記半導体層下部領域は、当該半導体層の側面が前記半導体層主要部領域に おける半導体層の側面よりも後退し、この後退した側面と前記ゲート電極の間に、前 記ゲート絶縁膜より厚い第 2端部絶縁体領域を有することを特徴とする電界効果型ト ランジスタ。  In the semiconductor layer lower region, a side surface of the semiconductor layer is recessed from a side surface of the semiconductor layer in the semiconductor layer main portion region, and a gap between the recessed side surface and the gate electrode is thicker than the gate insulating film. A field-effect transistor having two end insulator regions. [59] 前記半導体層の上部にゲート絶縁膜よりも厚いキャップ絶縁層が設けられている請 求項 57又は 58記載の電界効果型トランジスタ。  59. The field effect transistor according to claim 57, wherein a cap insulating layer thicker than a gate insulating film is provided on the semiconductor layer. [60] 請求項 58記載の電界効果型トランジスタの製造方法であって、  [60] The method for manufacturing a field-effect transistor according to claim 58, wherein 酸化剤透過性の第 1絶縁膜上に半導体層が設けられた基板を用意する工程と、 前記半導体層上に酸化剤透過性の第 2絶縁膜を形成する工程と、  Preparing a substrate having a semiconductor layer provided on an oxidant-permeable first insulating film; and forming an oxidant-permeable second insulating film on the semiconductor layer; 前記第 2絶縁膜および前記半導体層をパターニングして、基体平面から突起した 半導体層とその上にパターニングされた第 2絶縁膜を形成する工程と、 前記半導体層と第 2絶縁膜との界面および前記半導体層と第 1絶縁膜との界面に おいて、当該半導体層の側面が内側に後退するように酸化剤雰囲気中で当該半導 体層を酸化して、 The second insulating film and the semiconductor layer were patterned to project from the substrate plane. Forming a semiconductor layer and a patterned second insulating film thereon; and forming the semiconductor layer at an interface between the semiconductor layer and the second insulating film and at an interface between the semiconductor layer and the first insulating film. The semiconductor layer is oxidized in an oxidizing atmosphere so that the side faces recede inward, 当該半導体層上部の幅 Wが当該半導体層上端に向力、うに従って徐々に小さくなる 半導体層上部領域と、これに応じて厚みが徐々に大きくなる第 1端部絶縁領域と、 当該半導体層下部の幅 Wが当該半導体層下端に向力、うに従って徐々に小さくなる 半導体層下部領域と、これに応じて厚みが徐々に大きくなる第 2端部絶縁領域を形 成する工程を有する電界効果型トランジスタの製造方法。  A semiconductor layer upper region in which the width W of the upper portion of the semiconductor layer gradually decreases toward the upper end of the semiconductor layer, a first end insulating region in which the thickness gradually increases accordingly, and a lower portion of the semiconductor layer. A field effect type having a step of forming a lower region of the semiconductor layer in which the width W of the semiconductor layer gradually decreases as it moves toward the lower end of the semiconductor layer, and a second end insulating region in which the thickness gradually increases accordingly. A method for manufacturing a transistor. [61] 前記第 2絶縁膜を除去して前記半導体層の上面を露出する工程と、 [61] a step of removing the second insulating film to expose an upper surface of the semiconductor layer; 前記半導体層の上面および側面にゲート絶縁膜を形成する工程と、  Forming a gate insulating film on the top and side surfaces of the semiconductor layer; ゲート電極材料を堆積し、このゲート電極材料堆積膜をパターニングしてゲート電 極を形成する工程と、  Depositing a gate electrode material and patterning the gate electrode material deposited film to form a gate electrode; 前記半導体層に不純物を導入してソース/ドレイン領域を形成する工程をさらに有 する請求項 60記載の電界効果型トランジスタの製造方法。  61. The method for manufacturing a field effect transistor according to claim 60, further comprising a step of introducing a dopant into the semiconductor layer to form a source / drain region. [62] 前記の突起した半導体の下には支持基板を有し、当該半導体層はこの支持基板と 一体に接続している請求項 1一 6、 9一 24、 31— 44のいずれか一項に記載の電界 効果型トランジスタ。 62. The semiconductor device according to claim 16, further comprising a support substrate below the protruding semiconductor, wherein the semiconductor layer is integrally connected to the support substrate. 3. The field effect transistor according to claim 1. [63] 前記の突起した半導体の下には支持基板を有し、当該半導体層はこの支持基板 上に埋め込み絶縁膜を介して設けられている請求項 1一 6、 9一 24、 31— 44、 57— 63. The semiconductor device according to claim 16, further comprising a supporting substrate below the protruding semiconductor, wherein the semiconductor layer is provided on the supporting substrate via a buried insulating film. , 57— 59のレ、ずれか一項に記載の電界効果型トランジスタ。 59. The field effect transistor according to item 59. [64] 前記張り出し部は、前記ゲート絶縁膜の表面に対する張り出し幅が 2nm以上であ る請求項 1記載の電界効果型トランジスタ。 64. The field effect transistor according to claim 1, wherein the overhang portion has an overhang width with respect to a surface of the gate insulating film of 2 nm or more. [65] 前記張り出し部は、前記ゲート絶縁膜の表面に対する張り出し幅が 20nm以下であ る請求項 1記載の電界効果型トランジスタ。 65. The field-effect transistor according to claim 1, wherein the overhang portion has an overhang width with respect to a surface of the gate insulating film of 20 nm or less. [66] 前記張り出し部は、前記ゲート絶縁膜の表面に対する張り出し幅が当該ゲート絶縁 膜の厚さの 10倍以下である請求項 1、 2又は 3記載の電界効果型トランジスタ。 66. The field-effect transistor according to claim 1, 2 or 3, wherein the overhang portion has an overhang width with respect to a surface of the gate insulating film that is 10 times or less the thickness of the gate insulating film. [67] 基体平面から上方に突起した半導体層と、この半導体層の両側面上に設けられた ゲート電極と、このゲート電極と前記半導体層の側面の間に介在するゲート絶縁膜と 、前記ゲート電極に覆われなレ、領域に形成されたソース/ドレイン領域とを有し、 前記半導体層は、第 1の絶縁層上に、この第 1の絶縁層とは異なる材料からなる第 2の絶縁層を介して設けられ、 [67] A semiconductor layer protruding upward from the substrate plane, and provided on both side surfaces of the semiconductor layer. A gate electrode, a gate insulating film interposed between the gate electrode and a side surface of the semiconductor layer, and a source / drain region formed in a region not covered by the gate electrode; Is provided on the first insulating layer via a second insulating layer made of a material different from the first insulating layer, 前記ゲート電極は、第 1の絶縁層上に第 2の絶縁層を介さずに直接第 1の絶縁層 に接する部分を有する電界効果型トランジスタ。  A field-effect transistor in which the gate electrode has a portion on the first insulating layer and directly in contact with the first insulating layer without through a second insulating layer.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7465998B2 (en) 2004-09-21 2008-12-16 Kabushiki Kaisha Toshiba Semiconductor device
JP2011097058A (en) * 2009-10-28 2011-05-12 Taiwan Semiconductor Manufacturing Co Ltd Formation of inter-device sti regions and intra-device sti regions using different dielectric materials
TWI556322B (en) * 2014-03-28 2016-11-01 英特爾股份有限公司 Semiconductor device using selectively regenerated top contact and method of fabricating the same
CN113972279A (en) * 2014-04-18 2022-01-25 索尼公司 Field effect transistor
WO2022234691A1 (en) * 2021-05-06 2022-11-10 ソニーセミコンダクタソリューションズ株式会社 Solid-state imaging device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1093093A (en) * 1996-09-18 1998-04-10 Toshiba Corp Semiconductor device and manufacturing method thereof
JP2002009289A (en) * 2000-06-20 2002-01-11 Nec Corp Field effect transistor and method for manufacturing the same
JP2002270850A (en) * 2001-03-13 2002-09-20 National Institute Of Advanced Industrial & Technology Double gate field effect transistor

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3175691B2 (en) * 1998-05-08 2001-06-11 日本電気株式会社 Method for manufacturing multilayer wiring semiconductor device
KR100304713B1 (en) * 1999-10-12 2001-11-02 윤종용 Semiconductor device having quasi-SOI structure and manufacturing method thereof
JP2002050767A (en) * 2000-08-04 2002-02-15 Mitsubishi Electric Corp Semiconductor device and manufacturing method thereof
US7029958B2 (en) * 2003-11-04 2006-04-18 Advanced Micro Devices, Inc. Self aligned damascene gate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1093093A (en) * 1996-09-18 1998-04-10 Toshiba Corp Semiconductor device and manufacturing method thereof
JP2002009289A (en) * 2000-06-20 2002-01-11 Nec Corp Field effect transistor and method for manufacturing the same
JP2002270850A (en) * 2001-03-13 2002-09-20 National Institute Of Advanced Industrial & Technology Double gate field effect transistor

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7465998B2 (en) 2004-09-21 2008-12-16 Kabushiki Kaisha Toshiba Semiconductor device
US7816242B2 (en) 2004-09-21 2010-10-19 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
JP2011097058A (en) * 2009-10-28 2011-05-12 Taiwan Semiconductor Manufacturing Co Ltd Formation of inter-device sti regions and intra-device sti regions using different dielectric materials
KR101229709B1 (en) * 2009-10-28 2013-02-05 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Forming inter-device sti regions and intra-devices sti regions using different dielectric materials
US8592918B2 (en) 2009-10-28 2013-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Forming inter-device STI regions and intra-device STI regions using different dielectric materials
US8846466B2 (en) 2009-10-28 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Forming inter-device STI regions and intra-device STI regions using different dielectric materials
TWI556322B (en) * 2014-03-28 2016-11-01 英特爾股份有限公司 Semiconductor device using selectively regenerated top contact and method of fabricating the same
US10727339B2 (en) 2014-03-28 2020-07-28 Intel Corporation Selectively regrown top contact for vertical semiconductor devices
CN113972279A (en) * 2014-04-18 2022-01-25 索尼公司 Field effect transistor
WO2022234691A1 (en) * 2021-05-06 2022-11-10 ソニーセミコンダクタソリューションズ株式会社 Solid-state imaging device

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