WO2004086513A1

WO2004086513A1 - A method of identifying a read-out signal

Info

Publication number: WO2004086513A1
Application number: PCT/AU2004/000396
Authority: WO
Inventors: Robert Clark; Neil Barrett; David Reilly; Tilo Buehler
Original assignee: Qucor Pty Ltd
Priority date: 2003-03-26
Filing date: 2004-03-26
Publication date: 2004-10-07
Also published as: WO2004086295A1

Abstract

The present invention provides a method of identifying a read-out signal from a signal-producing unit associated with a quantum device. For example, the signal-processing unit may comprise a quantum device such as a qubit. The signal-producing unit is capable of producing at least one valid signal and the method comprises storing a pattern of the or each valid signal. The method also comprises the steps of receiving the read-out signal from the signal-producing unit and comparing the pattern of the received read-out signal with at least one stored pattern of the or each valid signal. The present invention also provides an apparatus for identifying a read-out signal from the signal-producing unit associated with a quantum device.

Description

A METHOD OF IDENTIFYING A READ-OUT SIGNAL

Field of the Invention

The present invention relates to a method and apparatus for identifying a read-out signal and, more particularly, but not exclusively, to a method and an apparatus for identifying a read-out signal associated with a qubit of a quantum computer.

Background of the Invention

Quantum computers utilise quantum effects and therefore promise to have computing powers that are superior to those of conventional computers.

The "bits" of such quantum computers, are associated with "qubits". Examples of such nano-scale devices include quantum devices in which the spin of a nucleus or the location of an electron ("charge-qubits") provides information.

Single Electron Transistors (SETs) are extremely sensitive nano-scale devices and are currently used to control and determine the state of quantum devices such as qubits . A pair of SETs ^'may be used to read-out the state of a single qubit, and a read-out signal of the SETs indicates the state of the SETs. There are two valid states of the pair of SETs, namely high/low or low/high and these states are characteristic for the state of the qubit .

For reading out the qubit, quantum coherence time is a limitation and consequently the read-out process needs to be conducted in a very short period of time. Quantum systems are easily disturbed which results in de- coherence. For error correction more than one individual qubit is required to form a single "logic" qubit. Each logic qubit only has a limited number of possible valid read-out signals, but disturbance of the individual qubits quantum may result in a large number of additional signals which are not valid. As the possible valid states of the individual qubits are known, it is possible to distinguish the valid signals from invalid signals by analysing the read-out signals of the individual qubits which then enables to identify the state of the logic qubit. Both the level of background noise and also the frequency of the typically very small signals may be high which makes this task difficult.

Prior art signal analysis procedures typically include Fourier transformation which is a complex operation and therefore time-consuming operation. Further, Fourier transformation requires a high level of signal analysis and error correction.

Summary of the Invention

The present invention provides in a first aspect a method of identifying a read-out signal from a signal producing unit associated with a quantum device, the signal-producing unit being capable of producing at least one valid signal, the method comprising: storing a pattern of the or each valid signal, receiving the read-out signal from the signal- producing unit and comparing the pattern of the received read-out signal with at least one stored pattern of the or each valid signal so as to identify the read-out from the signal producing unit.

The method compares the pattern of the read-out signal directly with the at least one pattern of the or each previously stored valid signal rather than analysing the read-out signal using a Fourier transformation. This simplifies the procedure and therefore makes it possible to identify the read-out signal in less time which is a significant advantage in view of the limited coherence time .

The signal-producing unit typically comprises a quantum device. The. step of comparing typically comprises analysing if the read-out signal approximates, or is identical with, the at least one stored pattern of the or each valid signal.

For example, the step of comparing the pattern may comprise determining a probability that indicates how probable it is that the pattern of the read-out signal approximates or is identical with the at least one pattern of the or each valid signal. The determination of the probability typically is conducted independently for positive and negative parts of the signal . The step of comparing may also comprise analysing if the probability is above a predetermined threshold value.

The read-out signal may be an optical signal but typically is an electrical signal. The electrical signal may be an ac signal such as a modulated rf signal. The read-out signal may also be a digital signal . The read-out signal may comprise a series of pulses which may comprise a single valid signal. Alternatively, the read-out signal may comprise a series of pulses which may comprise more than one valid signals. For example, the series of pulses may comprise a succession of the same valid signals. In this case the method typically comprises the step of averaging the series of pulses to increase a level of the valid signal relative to a level of noise. For example, the signal-producing unit may be associated with at least one individual qubit such as a logic qubit which may be formed by 5 individual qubits. The step of storing a pattern of the or each valid signal may comprise storing patterns of valid read-out signals that are representative of valid read-out signals of single electron transistors (SETs) or similar devices. For example, a pair of SETs may be used to read-out each individual qubit. The step of storing typically comprises storing a pattern for each possible valid signal . For example, for one logic qubit that may comprise 5 individual qubits the number of possible valid signals is 2⁵=32 and in this case the step of storing a pattern typically comprises storing the 32 pattern of the valid signals. In general, the signal processing unit may be associated with at least one logical qubit each comprising n individual qubits and the step of storing a pattern comprises storing 1 to 2ⁿ different ones of the patterns for the or each logic qubit . The read-out signal may comprise a plurality of series of pulses that indicate the state of respective SETs. The pulses of each series may have substantially the same frequency. Alternatively, the pulses of different series may have different frequencies so that each series can be correlated with a respective SET by the frequency.

The present invention provides in a second aspect an apparatus for identifying a read-out signal from a signal producing unit associated with a quantum device, the signal-producing unit being capable of producing at least one valid signal, the apparatus comprising: a means for storing a pattern of the or each valid signal, a means for receiving the read-out signal from the signal-producing unit and a means for comparing the pattern of the received read-out signal with at least one stored pattern of the or each valid signal so as to identify the read-out signal.

For example, the signal-producing unit may be associated with at least one individual qubit and typically is associated with at least one logic qubit. In this case the signal processing unit may operate at a temperature at which the qubit operates such as a temperature below 30 mK. The apparatus may be an analogue electrical device. In this case, the device may be arranged for comparing analogue patterns of respective signals. Alternatively, the apparatus may be a digital device and arranged to compare digital patterns of respective signals.

The present invention provides in a third aspect a method of calibrating the above-defined apparatus, the method comprising: providing at least one valid signal form a signal- producing, and storing a pattern of the or each valid signal to establish a library of valid signals and thereby calibrate the apparatus .

The step of providing at least one valid signal typically comprises providing a series of valid signals and averaging the valid signals to reduce the relative level of noise. Brief Description of the Drawings

Features and advantages of the present invention will become apparent from the following description of an embodiment thereof, by way of example only, with reference to the accompanying drawings, in which:

Figure 1 is a schematic diagram of a known prior art detecting circuit for detecting the state of two Single Electron Transistors (SETs) ; Figure 2 is a schematic block diagram illustrating an overall circuit architecture for an embodiment of the present invention;

Figure 3 is a block circuit diagram of an apparatus in accordance with an embodiment of the present invention; Figure 4 is an equivalent circuit diagram for a detecting circuit used in the embodiment of Figure 3 to detect the state of a pair of SETs;

Figure 5 is a diagrammatic plan view of an arrangement for implementing an impedance matching circuit in integrated form for use with the embodiment of Figure 3;

Figure 6 is a plot illustrating the relationship of reflective power as a function of SET resistance for a detecting circuit of the embodiment of Figure 3; Figure 7 is a flow diagram illustrating operation of a signal processing unit used in the embodiment of Figure 3 ; and

Figure 8 is a block circuit diagram of an apparatus in accordance with a further embodiment of the present invention.

Description of Preferred Embodiments As discussed above, a pair of Single Electron Transistors (SETs) may be used to read-out the state of a single associated qubit.

In Figure 1 there is shown a schematic diagram of a known proposed detecting circuit 1 for detecting the state of first and second SETs 24 and 28 respectively, associated with a qubit.

The detecting circuit 1 includes first and second signal generators 10 and 12 respectively arranged to generate first and second high frequency signals of the order of 300 to 500 MHz, the frequency of the first signal generated by the first signal generator 10 being different to the frequency of the second signal generated by the second signal generator 12. The first and second SETs 24, 28 are associated with first and second inductors 22 and 26 respectively. Each inductor 22, 26 and associated SET 24, 28 forms a resonant tank circuit, with the first and second inductors 22,26 being selected so that a first tank circuit defined by the first SET 24 and the first inductor 22 is tuned to the first signal generated by the first single generator 10, and so that a second tank circuit defined by the second SET 28 and the second inductor 26 is tuned to the second signal generated by the second signal generator 12. The first and second tank circuits are interfaced with operative components 2 of the measuring circuit 1 through a conventional transmission line 11 of characteristic impedance of the order of 50Ω. By adjusting the operating conditions of the first and second SETs 24,28, the resistance of the SETs can be adjusted so that optimum impedance matching between the transmission line 11 and the first and second tank circuits for detecting the state of the SETs is obtained. During use, the first and second generated signals pass through first and second directional couplers 14 and 16 respectively and are combined in a combiner 18. The combined signals are directed to the transmission line 11 through a third directional coupler 20.

Since the presence or absence of an electron in a SET 24,28 affects the impedance of the SET, the impedance of the first and second tank circuits and thereby the reflection characteristics of the transmission line 11 will change depending on whether an electron is present in a SET. Accordingly, the first and second generated signals will be reflected from respective interfaces between the transmission line 11 and the first and second tank circuits with characteristics dependent on the state of the first and second SETs 24,28.

As mentioned above, in order to carry out satisfactory detection of the state of the first and second SETs 24,28, detection must be carried out during the coherence time of the SETs. For this purpose, the first and second SETs 24,28 must be cooled to a temperature of the order of 30 mK in order to maintain a coherence time sufficiently long to facilitate detection of the states of the first and second SETs 24,28. In addition, appropriate operation conditions must be created to facilitate stable reading of the SET states by adjusting the bias and short ramp-up times of approximately 20 ns to the SETs 24,28.

The reflected signals from the first and second SETs 24,28 are directed via directional coupler 20 through low noise amplifier 30 and further amplifier 32. A splitter 34 splits the signals which then pass through bandpass filters 36 and 38 before they are demodulated in mixers 40 and 42. Low pass filters 44 and 46 filter any residual carrier frequencies, providing an intermediate frequency signal due to modulation superimposed on the qubit gate electrodes SI and S2.

It should be noted that the arrangement illustrated in Figure 1 is merely a proposed circuit and although theoretically operational as proposed there are a number of practical difficulties faced for implementation of a practical circuit for reading out signals from SETs associated with a qubit . These problems include the requirement for quantum error correction (QEC) . To correct potential errors in read-out signals from a qubit it has been proposed to use more than one actual qubit to implement a single "logic" qubit. One proposal is to use five actual qubits for a single logic qubit. It will be appreciated that to control five actual qubits using similar circuit architecture to Figure 1, quite complex circuitry will be required (potentially reproducing the circuity of Figure 1 for each actual qubit) . Further, in order to implement a practical quantum computer a number of logic qubits will be required (although with a number of logic qubits in the order of hundreds, an extremely powerful computer would be produced) . There is a need for a circuit architecture which is simple compared to an extrapolation of the prior art architecture for implementing at least one logic qubit, which architecture can desirably be extended to implement a number of logic qubits. Desirably, the circuit would be at least partly integrated.

In a single logic qubit including five qubits (and 10 SETs) it is important to distinguish between the signals from each SET. In the prior art proposal of Figure 1 this is done by applying different frequencies to the SETs. It may not be practical to provide separate signal generators for a large number of SETs, or supply one complex generator which produces a supposition of all the signals.

Further, inductors are generally relatively large circuit components which do not lend themselves to integration. Ten inductors will be required to implement a single logic qubit in the proposed scheme of five actual qubits for purposes of QEC. For a number of logic qubits, many more inductors will be required.

Another problem faced for implementation of a practical computer is the requirement to maintain qubits at extremely low temperatures (in the order of mK) . To maintain all the control circuitry for the SETs, as well as the SETs, at such low temperatures is probably impractical, as any attempt to do this would probably be prohibitively expensive. On the other hand, to transfer signals from the SETs across a large temperature gradient to eg room temperature where control circuitry operates again would be impractical. The number of leads required by the Figure 1 proposal would be so great that maintaining the SETs and qubits at the appropriate low temperature would probably be extremely difficult if not impossible because of heat transfer over the leads to the control circuitry. Further, such connecting leads would have to cross relatively large distances which is a disadvantage for assembly of the equipment and for rapid changes in bias conditions.

The following description of a preferred embodiment of a control architecture is proposed for control of one logic qubit in the form of five actual qubits including 10 SETs. This architecture is proposed to enable provision of a single logic qubit which is continuously available for reading or writing data. An error correction algorithm continuously operates in a feedback loop, to maintain availability of a single logic qubit. Later on in this document we also discuss some extrapolations to the architecture for controlling multiple logic qubits in a quantum computer. The control architecture described may include digital signal processing means for processing signals by pattern matching in accordance with an embodiment of the present invention. A description of the embodiment of the present invention is given towards the end of this document as one option for implementing detection of states of the qubits within this overall architecture.

With reference to Figure 2, an overall architecture for a control apparatus for a single logic qubit comprised of five actual qubits is now described. As discussed above, the qubits must be operated at extremely low temperatures (approximately 30 mK) . The architecture proposed comprises a control chip 52 and a separate auxiliary control chip 50, for control of a qubit chip 52. The qubit chip 150 mounts five qubits and ten SETs (one pair associated with each qubit) .

The control chip 52 is arranged to directly control the logic qubit and in this embodiment provide for error correction without external control, and also to detect signals from the ten SETs. The control chip 52 is operated at very low temperatures, preferably at or close to the operating temperature of qubit chip 52. Preferably, the control chip 52 operates at less than 4.2 K and more preferably in the order of mK, preferably at or as close to 30 mK as possible. The auxiliary control chip 50 is arranged to provide data and commands to the control chip 52 and to determine status of the qubits by processing signals from the control chip 52. The auxiliary chip 50 is used to "initialise" the devices on the control chip for control of the qubit chip 54. The auxiliary control chip 50 may be operated at room temperature. It is believed that the splitting of the architecture to provide control chip 52 at mK temperature and an auxiliary control chip 50 at room temperature (RT) is an important advance. Conventional integrated circuit technology can be used for the auxiliary control chip 50, such as CMOS, for example. The control chip 52 is an integration of Rapid Single Flux Quantum (RSFQ) devices.

Another advantage of the proposed architecture is both the qubit chip 54 and control chip 52 are integrated circuits and are therefore appropriately compact and reproducible . Figure 3 is a circuit diagram of the architecture in accordance with this embodiment of the invention, in more detail. The auxiliary control chip is generally designated by reference to numeral 50 and the control chip is generally designated by reference numeral 52. As discussed above, in order to operate, the qubit chip 54 must be cooled to very low temperatures, in the order of 30 mK in this case. The control chip 52 will also be at 30 mK temperatures. The auxiliary control chip 51 is preferably at room temperature, which enables implementation of the auxiliary control chip 51 by conventional technologies. This provides flexibility in enabling choosing of off-shelf components and standard drop-in microprocessors to control the initialisation and measurement processes of the qubit. The auxiliary control chip 51 is the operation system, whereas the control chip 52 controls the specific rapid control of the signal inputs/outputs and gate biases for the qubit chip 54, in particular quantum error correction. In more detail, the auxiliary control chip 50 includes a processing means, in this embodiment including a RISC micro processor 56 coupled to a remote PC 58 via bus drivers 60 and interface 62. The remote PC 58 acts as an interface for a user and data and commands from the PC are input to the auxiliary control chip 50 and output data is received by the PC 58 from the auxiliary control chip 50. A user of the PC 58 may thus formulate "problems" for input as command instructions and data for eventual processing by the qubit chip 54 via the auxiliary chip 50 and control chip 52.

The auxiliary control chip 52 also includes a data bus 120 and address bus 121 for communication about the auxiliary control chip 52. The RISC microprocessor 56 also includes memory (as is conventional) .

Because of the large temperature difference between control chip 52 and auxiliary control chip 50, it is required that heat transfer is minimised. To this end, the architecture is arranged so that there are a minimal number of conductive connections between the auxiliary control chip 50 and control chip 52, to provide a minimal number of potential paths for heat transfer. Utilising optical signals to transmit data and commands down an optical cable 68 for control chip 52, from the auxiliary chip 50, facilitates this.

The auxiliary control chip 52 also includes a signal processing means, in this embodiment including signal processing circuitry 102 for receiving output signals from the control chip 52, analysing them and providing input data for the RISC microprocessor 56.

The auxiliary control chip 50 acts as a communications port directing the control chip 52 to follow particular sequences. One of the functions of the auxiliary control chip 50 is to initialise the qubit chip 54. Each SET has to be initialised and so an initialisation instruction is provided by the auxiliary control chip 50 triggering a series of gate bias conditions together with measurements and data analysis, culminating in a completion signal being returned to the auxiliary control chip 50.

Initialisation, comprising a series of gate bias changes to confirm the functionality of the qubits and leave them in a known state, is a relative slow procedure and so can be controlled from the auxiliary control circuit 50.

Instructions for initialisation are therefore downloaded from auxiliary control chip 50 via optical link 68 and the components that need to be programmed are selected by device select 74. For example, the downloaded instructions may turn components on or may comprise voltage instructions for voltage sequences required to set the SETs and qubits. These voltage instructions are stored in the control chip 52, and as the corresponding voltage sequences are only required for the initial set-up, the downloading of the instructions can be relatively slow.

The control chip 52 comprises a range of RSFQ devices. RSFQ devices are super-conducting devices which are able to operate at very low temperatures . The devices on the control chip include a code sequencer 76. The code sequencer 76 is programmed by the auxiliary control chip 50 and controls a series of voltage sequences for application to the qubit chip 54 and impedance matching circuits 82 via RF matching drivers 84, RF bias drivers 86, SET gate bias driver 78 and qubit gate bias drivers 80. Quantum error correction (QEC) is implemented in a feedback loop via the code sequencer 76.

In this embodiment, the signal generator means includes a pulse generator 88. Stored RSFQ sequences are also arranged to control RSFQ pulse generator 88 which generates groups of pulses which are split into ten sets of pulses by splitter 90 and directed to impedance matching circuits 82. The impedance matching circuits 82 are used to match the low impedance RSFQ circuits to the high impedance SETs (the impedance matching circuits will be described in more detail later) . Inductors in the impedance matching circuits 82 and the SETs form tank circuits equivalent to the tank circuits described in relation to Figure 1 (prior art) . In order to carry out error correction, each qubit of the qubit chip 54 requires a series of voltage sequences provided via the code sequencer 76 to set each qubit to a predetermined state. After a pause, the states of four qubits are measured (the fifth can be determined without measurement) . If a qubit is not in the expected state, an error occurs which can then be corrected. Dependent on the read-out information, the feedback loop affects a sequence of voltage changes which set the qubits to known status again if there was an error. This part of the process is constantly repeated during the operation of the control chip 52 and is therefore implemented in a very short time. The programme instructions for this error correction process are stored on the control chip 52 (code sequencer 76 and RSFQ pulse generator 88) , and are provided as bias drivers 84, RF matching drivers 86, set gate bias drivers 78 and qubit gate bias drivers 80. The general process for error correction is as follows : the sequence is encoded (series of gate voltage sequences) . There is a relatively long wait (compared with the encode sequence) for one error or no error to occur, then a decode sequence is applied to reconfigure the results to allow easier interpretation of the measured results, and then the results are corrected if necessary. Generally error correction in logic qubits is known in the prior art. The fifth qubit may be measured in some set up routines, but when running it will generally not be measured directly in this embodiment but will be inferred from measuring qubits 1 to 4.

Signals reflected via the impedance matching circuits 82 and the SETs are the read-out signals that contain information concerning the state of the qubits. The above-described error correction process involves a feedback loop from the qubits of the qubit chip 54 and associated SETs through the impedance matching circuits 82 (the reflected signals) , RF/RSFQ comparator 92 to code sequencer 76 and back to the qubit chip 54 via qubit gate bias drivers 80 and SET gate bias driver 78. Depending on the status of the qubits, the feedback loop provides a known voltage pulse output to correct the qubits for a particular set of measured inputs.

SET read-out signals are analogue signals which are not directly compatible with the pulsed digital RSFQ technology and the RF/RSFQ comparator 92 is used to generate SFQ pulses when the SET output signal exceeds the comparative value. The pulses from the SETs for a given qubit are then counted and compared. The outcome of the comparison is used in the feedback loop for error correction.

Readout signals may be processed in two ways. For the purposes of the error correction feedback loop, signals from each pair of SETS are applied to RF/RSFQ comparators 92 to determine the state of the SETs and this digital output is used in the QEC feedback loop. Further, this digital output may be uploaded by upload shift register 94, combiner 96, line driver 98 to the auxiliary control chip 50.

The RF/RSFQ comparator 92 therefore provides a link to the auxiliary control chip 50 to provide information on the status of the qubits and the SETs to the auxiliary control chip. For example, fine-tuning of voltages and/or frequencies may be required to set the SETs and the qubits to their most sensitive state. Such fine-tuning can be controlled by the auxiliary control chip 50. Upload shift register 94 is used for storing and uploading SET output signals in digital form to the auxiliary control chip 50. Combiner 96 combines signals from the upload shift register 94 for the auxiliary control chip 50. Line driver 98 amplifies the signal and converts it into a non-return-to-zero (NRZ) signal which is directed to shift register 64 of the auxiliary control chip 50. A bit error rate signal can also be monitored. These digital uploads may also be used to establish the status of the logic qubit for quantum computer processing.

Analogue signal outputs which are directed to squid/combiners 100 and 101. The RF/RSFQ comparators 92 block includes circuiting for sending analogue signals from the SETs (one-by-one) , bypassing comparators, to either one of the two squid/combiners 100 and 101. From the squid/combiners 100 and 101 the signals are sent to the digital signal processing unit 102 where they are received via analogue-to-digital converters 104 and 106 and low noise amplifier as 108 and 110. In this embodiment, the auxiliary control chip 50 includes the digital signal-processing unit 102 in which read-out signals are analysed to determine qubit status. In a variation of this embodiment the signal-processing unit 102 may be included in the control chip 52 and therefore may operate at a temperature at which the qubit chip 54 and the control chip 52 operate.

A clock signal from the RSFQ pulse generator 88 is also directed to digital signal processing unit 102 via analogue-to-digital converter 112 and low noise amplifier 114. The signals are analysed in the digital signal processing unit 102, which comprises digital signal processor 116 and a first-in-first-out units (FIFO) 118, 120 and 122 which regulate the data transmission rate. The analysis of signals in digital signal processing unit 102 also may be used to provide information on the status of the SETs to the auxiliary control circuit 50 which may be used for control of the control circuit 52 and to determine the status of the logic qubit for quantum computing. In this proposed architecture, therefore, there are two ways in which status of SETs of the qubit chip 54 can be obtained, either via the digital upload from comparators 92 to shift register 62 in the auxiliary control circuit 50, or from SQUID amplifiers 100, 101 upload to the digital signal processor 116.

The operation of the RF/RSFQ comparators 92 is described in more detail in the following: the SET output is an analogue signal which is not directly compatible with the pulsed digital RSFQ technology. A RSFQ comparator may be designed (DC to SFQ circuit) to generate SFQ pulses when the input signal exceeds a specific level. The pulses from the SETs for a given qubit can then be counted and compared. The outcome fro this comparison is used in a self correcting loop (using 4 measurement signals in the case of QEC) . The result of the last comparison for the 10 SETs can also be uploaded using a SQUID amplifier to the room temperature Auxiliary Control Chip on demand.

The SET signals, one part at a time, may be monitored directly while optimising the gate bias voltages and pulse generation source. During this operation the comparators are switched off to create a high impedance path to the QEC circuity. The two signals from the SET pair pass through a second set of amplifiers and then through two separate combiners to RT on two lines (the other 8 lines to the combiners from the remaining SETs are disabled) . When in QEC mode the SQUID amplifiers for the up link are switched off leaving an impedance, which needs to be as high as possible.

The SFQ pulse output from the comparators are not in phase and must pass through a flip flop circuit and sampled at a suitable clock frequency over the required measurement time. To reduce the size of the shift registers, logic circuitry eliminates counting like pulses and only counts if there is a difference in the lines. When one of the self clocked shift registers reach overflow it triggers a ^ΛDone Flag' and provides a signal to identify the status of the SETs.

Outputs from the control chip 52 to the auxiliary control chip 50 can be monitored SET gate bias and qubit gate biases and also the RF bias drivers and RF matching drivers in order to optimise operation of the circuit over time (upload from combiner 96 and line driver 98 digital outputs from RF/RSFQ comparator 92) , and can also be monitored to determine the status of the logic qubit (via squid amplifiers 100, 101 and digital signal processing 102 or vice upload from combiner 96) .

A separate power supply 71 and power conditioning circuit 73 is provided for power supply to the auxiliary control chip 50 and control chip 52. The power conditioning circuit 73 regulates four voltage outputs (RF generator, clocks, circuits, optical link as well as a common line) .

The temperature sensor 69 is included on the control chip 52 and inputs to A-D converters 70 on the auxiliary control chip 50 so that the temperature of the control chip 52 can be monitored via the auxiliary control chip 50. If necessary, devices can therefore be compensated for temperature drift. The downloads to the control chip 52 from the auxiliary control chip 50 are uni-directional without communication handshakes (asynchronous) .

Changes to the operational modes of the control chip use 100 ns time scales requiring GHz clock times (in the worse case) to control them. The reduced instruction set

(RISC) architecture has the advantage that most instructions take a single clock cycle. As a consequence the clock rate and hence device speed and power consumption is reduced as well. The more complex instructions, such as multiply for example, if they need to be executed in a single clock cycle then the ALU will need to be more complex. This approach has the advantage that the clock cycles may be in the order of a few hundred MHz rather than a few GHz . The ALU is the calculating engine of the auxiliary control chip 50 located in the RISC microprocessor 56. It may perform a variety of instructions ranging from simple Boolean logic through to Binary arithmetic and in some cases floating point arithmetic. The complexity of the ALU is heavily dependent on the width of the data words and the level of functionality provided.

Analogue signals are required to measure the status of each RF SET. The signal is generated initially as a SFQ pulse string which is then duplicated for each SET (RFSQ pulse generator 88 and splitter 90) prior to entering the matching circuits 82. Due to the broadening of the pulse as it passes through the matching circuits 82, the final signal to each SET is approximately a sine wave .

Ideally the input signal to the SETs needs to have the input frequency and voltage level changed for optimisation of the output signal. This can be achieved by generating rapid pulses close to each other (for example 10 at 300 GHz) and then stop and wait to repeat on the 5 GHz cycle (or at a lower frequency) . The power can be changed by adding or removing the number of pulses in the group of nominally 10 (The high frequency pulses have the same voltage level but the current in each pulse group is transformed to different sinusoidal peak voltages in the tank circuit) .

The pulse frequency is swept to find the resonant frequency of the impedance matching circuits and SETs. If the resonant frequencies are not identical, it is possible to adjust the frequencies individually using a master pulse generator and add or subtract pulses, but this adds further complexity and has not been included in this architecture . If required, the generated signals which are applied to the SETs may be provided with a characteristic which enables them to be identified, such that an associated SET responding to the signal can be identified (determination of status of SETS can then be made) . In the prior art, this would be achieved by generating ten signals having ten different frequencies. In the present invention, modulation of the signals input to the SETS may be achieved by modulating the impedance matching of the SETs with the impedance matching circuits, which results in a modulation of the amplitude of the respective reflected signal. In the embodiment of Figure 3, it is not necessary to provide each SET with a different characteristic as there are separate conductors provided for carrying the signals from each SET. The impedance matching circuits 82, however, still need to be "tuned" on set-up, for optimal operation.

Control of the impedance matching and the impedance matching circuits 82 will now be described. A description will firstly be given of operation of the impedance matching circuits 82 with reference to the equivalent circuit diagram shown in Figure 4. This diagram shows the equivalent circuit for impedance matching with one pair of SETs in the qubit chip 54.

As with the prior art detecting circuit 1 shown in Figure 1, first and second SETs 160, 161 have associated first and second inductors 162 and 163 respectively which define with their respective first or second SET 160, 161 first and second tank circuits having resonant frequencies defined by the inductors 162,163 and the parasitic capacitances of the SETs 160,161. The resonant frequencies define the operational frequencies of the SETS 160,161. In this example, the first SET 160 receives a first signal generated by a first signal generator 164 and the second SET 161 receives a second signal from a second signal generator 165. The inductors 162,163 are selected so as to ensure that the first tank circuit is tuned to the frequency of the first signal and so as to ensure that the second tank circuit is tuned to the frequency of the second signal. In operation of the circuit of Figure 3, signal generators 164 and 165 are in fact provided by RSFQ pulse generator 88 via splitter 90 as discussed above so the applied frequencies will be the same. Further, as will become clear later, the inductors 162, 163 in fact have the same value. Distinction between the signals applied to read out from the SETs is given not by providing frequency generator 164,165 of different frequency, but because separate lines are provided for each SET. As discussed briefly above, and as will be discussed in more detail later, it is possible with an alternative embodiment to distinguish between the signals applied to/readout from the SETs by modulating the impedance mismatch to provide different characteristics to the signals applied to the SETs.

Referring again to Figure 4, in this example, each SET 160, 161 can be considered to present a SET resistance in the range 26kΩ to <10MΩ in parallel with a SET parasitic capacitance. Accordingly, it will be understood that a change in the SET resistance has an effect on the input impedance of the SET, particularly at SET resistances less than 50kΩ, and has an effect on the amount of power reflected from the SET by virtue of impedance mismatch at the SET tank circuit - transmission line interface.

The detecting circuit 155 also includes first and second impedance matching circuits 166 and 167 associated with the first and second tank circuits respectively. Each of the first and second impedance matching circuits 166,167 includes a λ/4 transmission line portion 168 of essentially conventional construction having a characteristic impedance in this example of the order of 50Ω, a conductor portion 169 disposed adjacent to and extending along the length of the transmission line portion 168, and a dielectric portion 170 disposed between the transmission line portion 168 and the conductor portion 169. In this example, the dielectric portion 170 is formed of thin film silicon nitride although any suitable dielectric material is envisaged. It will be understood that by forming the first and second impedance matching circuits in this way, a capacitance is defined by each transmission line portion 168 and associated conductor portion 169 and dielectric portion 170 which has the effect of reducing the impedance of the transmission line significantly below the characteristic impedance of the transmission line portion 168.

In order to provide a degree of control over the output impedance of the matching circuits 166, 167, a variable resistor, in this example in the form of a FET 171 or similar device is connected between each conductor portion 169 and ground. The magnitude of resistance provided by each FET 171 or similar device is controlled in any suitable way, in this example using control units 172. In the implementation of Figure 3, the control units 172 are implemented by RF matching drivers 86.

It will be understood that by modifying the voltage applied to the gates of the FETs 171 or similar device, the resistance between the conductor portions 169 and ground and thereby the impedance of the matching circuits 166,167 may be controllably adjusted. A practical implementation of an impedance matching circuit 166,167 at integrated circuit-scale is shown in Figure 5.

As can be seen in Figure 5, a first end of the conductor portion 169 is connected to a first grounded port 173 and a second opposite end of the conductor portion 169 is connected to a second grounded port 6 174 through the variable resistor 17.

The dynamic range of the variable resistors 171 is generally in the range of 500Ω to 10,000Ω, although it will be understood that it is possible to use lower magnitude variable resistors by disposing the FET variable resistor 171 between the first end of the conducting portion 169 and the first grounded port 173 instead of between the second end of the conducting portion 169 and the second grounded portion 174.

For a quantum computing application as shown in Figure 4, it will be understood that the variable resistors 171 may be used to tune the impedance matching point between the impedance matching circuits 166,167 and the tank circuits such that the SETs 160,161 are tuned so as to cause optimum reflection conditions for distinguishing the states of the SETs.

In order to optimise detection of the states of the SETs, the SETs must be operated at their maximum sensitivity half way up a coulomb barrier (CB) peak where the transconductance is largest . In order to achieve this, the SET G-gate biases Gl, G2 must be adjusted to compensate for the charging A-gate potential. If both SETS 160, 161 are biased on the same side of a CB peak then their compensated signals move in opposite directions when a transfer of state occurs. This is because when the first SET 160 senses departure of an electron, the second SET 161 senses arrival of the electron.

In Figure 6, a plot is shown of reflected power as a function of variable resistor 171 resistance R and SET resistance. As shown in Figure 6, for variable resistor 171 resistances R between 500Ω and 10,000Ω, the curves are relatively steep over a relatively narrow range of SET resistances, and the location of the steep portions of the curves is dependent on the magnitude of the resistance R of the variable resistor 171. It can be seen, therefore, that in order to optimise the sensitivity of the SETs 160, 161 and obtain a maximum reflected power change between states of the SET, R should be chosen so that the change in SET resistance as a result of changing SET state corresponds to a steep portion of a curve.

It will also be understood, as discussed above, that for quantum computing applications, the variable resistors 171 may also be controlled by the control units 172 so as to modulate the signals supplied to the tank circuits. For example, by applying sine wave inputs of predetermined frequency to gates of the FET variable resistors 171 (RF matching drivers 86, Figure 3) , the impedance of the impedance matching circuit would be modified in accordance with the applied sine wave input, and the signal reflected from an interface with the output of the impedance matching circuit would also be modified in accordance with the applied sine wave input. By modulating each tank circuit input signal with a different modulation signature, the reflected signals from the SETs may be distinguished from each other. This is useful in an embodiment where output signals from the SETs can be taken out on one line at the same time to the auxiliary control circuit 50 for example. The signals from each SET can then be distinguished.

In the architecture of Figure 3, impedance matching circuits 82 are in integrated form, each SET having an associated inductor integrated in accordance with Figure 5 and impedance matching circuit .

As will be appreciated, a pair of inductors are required for the tank circuits for each pair of SETs associated with each qubit . Ten inductors are therefore required to implement one logic qubit. Inductors are normally bulky components, so the requirement for so many inductors can be a problem unless they can be kept to a relatively small size and low complexity. By operating the tank circuits at relatively high frequency (in this embodiment being between 1 and 10 GHz, this allows the inductors to be relatively small and simple, and facilitates integrated fabrication of multiple inductors and matching circuit arrangements .

The following is a description of signal processing in the digital signal processing unit 116 utilising a novel pattern matching process . Pattern matching can be implemented for analysing signals from each pair of SETs (as in the embodiment of Figure 3 where the analogue outputs from each pair of SETs are passed up to the digital signal processor 116) or for analysing outputs from all the SETs if all the outputs are passed up to the digital signal processor. The following description is of a pattern matching procedure for pattern matching outputs from all 10 SETs of the 5 qubit logic qubit. This pattern matching process may still be utilised for matching patents from a reduced number of qubit SETs e.g. for pattern matching for 2 or more SETs .

The following will describe the operation of the digital signal-processing unit 102. The read-out signals from the SETs form a signature (pattern) which is unique for any combination of SET signals. In this embodiment the pattern of a real time signal signature from the SETs is correlated with previously saved patterns corresponding to possible valid states of the logic qubit. Out of 10 SETs, the only valid possibilities are that 5 SETs will indicate one state and 5 SETs will indicate the other qubit state. Therefore, the number of valid possibilities is 2⁵ = 32.

To calibrate the digital signal-processing unit the 10 SETs are forced by voltage pulses into states which correspond to valid states of the logic qubit. The corresponding data strings are then saved in a memory of the digital signal-processing unit 102 so that a library of 32 saved valid patterns is established. Calibration may be done at initialisation of the control chip 52 by the auxiliary control chip 50, or may be done as a "once only" operation before initialisation. The following will describe in more detail the basic principle which is used to analyse the signal by the digital signal processing unit 102. For example, (fi, f₂, ... f_n) is a pattern of a read-out signal and (gι,g₂, ..g_n) is a saved pattern of valid signal. The digital signal-processing unit 102 correlates the signals according to eq. 1:

«.,---«_---.__«■_•.»-_._«_««..■■_«__._»__._..««.-.-._.«._..« ι

where f = 1/n έ| and g = l/n t&.

C is a number that is invariant to the gain and offset of the pattern g(t) and f (t) with limits between -1 and 1 depending on the positive or negative correlation between the signals.

For the fast operation of the signal-processing unit 102 it is advantageous if the correlation can be conducted in a steady manner. Any reference to an average would require to read all data before the correlation could be started and is therefore removed. Eq. 2 - 5 explain how this is achieved. The numerator of equation 1 is:

The denominator of equation 1 is:

and

Substituting equations 2, 3 and 4 into equation 1 results in:

fis-ι a

Eq. 5 is not dependent on an average of g(t) or f (t) and a correlation according to equation therefore can be conducted in a steady manner.

The correlation eq. 5 is implemented in software without necessarily normalising or averaging the signals prior to the calculation.

Note that in principle the control chip 52 may be arranged so that the SET output signals are of multiple carrier frequency, single carrier frequency or are digital. In this embodiment the read-out signals are of single frequency (and may be modulated to give different characteristics) , if required. However, the above-described algorithm (eq. 5) operates in the same manner for these three options. In each case 32 possible valid patterns (consisting of all the possible SET output signal combinations for ten SETs of a five qubit logic qubit) are stored in memory of device 102 and correlated against the incoming pattern associated with read-out signals of the SET. Once a pattern has been identified then the high and low status of each SET is known. The lower the correlation threshold, the more tolerant the correlation is to induced noise on the signal output.

Referring now to Figure 7, the operation of the digital signal-processing unit 102 used to analyse if the received read-out is a valid signal is now described in more detail. Note that in the embodiment of Figure 3, where signals are passed up to the digital signal processor 102 from a pair of SETs at a time, the number of valid patterns to be stored for a pair of SETs would be less than thirty-two. This description is for the processing of the signals from ten SETs associated with a five qubit logic qubit, being passed to the digital signal processor at the same time. Amendment to the process should be made accordingly to deal with signals from two SETs at a time, as in the Figure 3 embodiment. The SETs are initially set to a state that corresponds to a possible valid state of the logic qubit (200) . This is done for all 32 possible combinations and the digital processing unit 102 is then calibrated by saving the pattern in the memory of the digital processing unit 102 (202) . The saved pattern is optimised by reading the same signal many times and improving the signal-to-noise ratio of the saved pattern by saving the average of the read-out signals (204 and 206) .

The SET read-out signal 208 that contains information concerning the state of the logical qubit is then split (210 and 212) into a positive and negative signal and analysed separately. The data is then smoothed (214 and 216) and 64 correlations (32 positive and 32 negative) are conducted in parallel (218, 220 and 222) . The correlations implement the algorithm of equation 5. The values C for the correlations are then established (224 and 226) .

For both the positive and negative signal sections it is analysed if the correlation value is above a predetermined threshold value (228 and 230) of the signal. If the correlation is above the predetermined threshold value, the respective pattern is identified (232 and 234) . The identified signals derived from the positive and the negative sections of the signal are then compared with each other (236) and if the codes are identical, the process is complete (238) the qubit state is identified. Alternatively, if the value is below the threshold value for either the positive and negative sections of the signal or if the read-out signal derived from the positive and the negative sections of the signal are not identical, the data string is classified as an error (240) . To reduce the possibility of erroneous identification, the pattern of a saved valid pattern corresponding to an identified read-out signal is subtracted from the pattern of the input signal. This step enables to identify a range of common characteristics present in the 32 output signal combinations. The removal of such features reduces the error associated with the identified read-out signal .

It is to be appreciated that alternatively the digital signal processing unit 102 may be arranged for signal analysis by Fourier analysis which transforms the signal into its fundamental components. Further, it is to be appreciated that the processing unit 102 may not be arranged for identifying a read-out signal that is associated with all SETs, but may alternatively be arranged to process the read-out signals of individual SETs . i

Figure 8 shows an alternative embodiment of a control architecture in accordance with the present invention. Similar components have been given similar reference numerals. Again there is an auxiliary control circuit 50 and control circuit 52. In this embodiment the control circuit 52 does not implement quantum error correction in a feedback loop. Further, signals from the matching circuits 82 are passed via a combiner 500 into a single line to serial analogue to digital converter 501 and are then passed via line driver 502 and line receiver 503 to the auxiliary control chip 50. In this embodiment a shift register 504 passes a serial signal to a first in first out block 505 and digital signal processor 116. In this embodiment, therefore, all the signals from all ten SETs are provided at the same time to digital processor 116 and are processed by pattern matching as discussed above. The RSFQ ports generator 88 generates groups of approximately twenty pulses which are identical and of singular frequency in this embodiment. The pulses are then split into ten parallel series of pulses by splitter 90 and phase delayed relative to each other by line delay 510. The line delay 510 is controlled by delay control 511. The ten parallel series of pulses are modulated in matching circuits 82 by modulation signal of the modulators (RF matching drivers) 86, so as to give a characteristic signal to each signal being applied to a SET. The RSFQ memory has stored data for the control of the gate biases of the qubit chip.

The above description of an architecture and operation of the architecture for a single logic qubit implemented by 5 actual qubits . In order to provide a feasible quantum computer, more logic qubits will be needed, although a few hundred logic qubits will be sufficient to provide a very powerful computer. There are a number of possible architectures for control of multiple logic qubits, based on extrapolation of the above-described architecture.

In one arrangement, a separate control chip 52 may be provided for each logic qubit, and many control chips 52 may be controlled by a single auxiliary control chip 50. This architecture would still be somewhat complex, however.

An alternative would be to provide a number of logic qubits under the control of a single control chip 52. Signals from the control chip will be multiplexed to the multiple qubit chips.

Note that as development of quantum computers proceeds, the number of qubits required to implement a single logic qubit may fall, so that the above-proposed architecture may need to handle less actual qubits for a single logic qubit.

In the embodiment of Figure 3 , the impedance matching circuits 82 are shown as being on a separate block to the qubit chip 54. In application, the impedance matching circuits 82 may be integrated with the rest of the control chip 52, may be a separate integrated circuit or may be integrated with the qubit chip 54.

Modifications and variations as would be apparent to a skilled addressee are deemed to be within the scope of the present invention.

Claims

The Claims :

1. A method of identifying a read-out signal from a signal producing unit associated with a quantum device, the signal-producing unit being capable of producing at least one valid signal, the method comprising: storing a pattern of the or each valid signal, receiving the read-out signal from the signal- producing unit and comparing the pattern of the received read-out signal with at least one stored pattern of the or each valid signal so as to identify the read-out from the signal producing unit .

2. The method as claimed in claim 2 wherein the signal- producing unit comprises a quantum device.

3. The method as claimed in claim 1 or 2 wherein the step of comparing the pattern comprises analysing if the read-out signal approximates the at least one stored pattern of the or each valid signal.

4. The method as claimed in claim 3 wherein the step of comparing comprises determining a probability that indicates how probable it is that the pattern of the readout signal approximates the at least one pattern of the or each valid signal.

5. The method as claimed in claim 4 wherein the step of determining the probability is conducted independently for positive and negative parts of the signal .

6. The method as claimed in claims 4 or 5 wherein the step of comparing the pattern also comprises analysing if the probability is above a predetermined threshold value.

7. The method as claimed in any one of the preceding claims wherein the read-out signal comprises a series of pulses comprising a single valid signal .

8. The method as claimed in any one claims 1 to 6 wherein of the read-out signal comprises a series of pulses which comprise more than one valid signals.

9. The method as claimed in claim 8 comprising the step of averaging the series of pulses to increase a level of the valid signal relative to a level of noise.

10. The method as claimed in any one of the preceding claims wherein the signal-producing unit is associated with at least one individual qubit and the step of storing a pattern of the or each valid signals comprises storing patterns of valid read-out signals that are representative of valid read-out signals of single electron transistors (SETs) .

11. The method as claimed in any one of the preceding claims wherein the step of storing a pattern comprises storing a pattern for each possible valid signal.

12. The method as claimed in any one of claims 1 to 10 wherein the signal processing unit is associated with at least one logical qubit each comprising n individual qubits and the step of storing a pattern comprises storing 1 to 2ⁿ different ones of the patterns for the or each logic qubit.

13. The method as claimed in any one of the preceding claims wherein the read-out signal comprises a plurality of series of pulses that indicate the state of respective single electron transistors (SETs) .

14. An apparatus for identifying a read-out signal from a signal producing unit associated with a quantum device, the signal-producing unit being capable of producing at least one valid signal, the apparatus comprising: a means for storing a pattern of the or each valid signal, a means for receiving the read-out signal from the signa -producing unit and a means for comparing the pattern of the received read-out signal with at least one stored pattern of the or each valid signal so as to identify the read out signal.

15. The apparatus as claimed in claim 14 wherein the signal-producing unit is associated with at least one individual qubit .

16. The apparatus as claimed in claim 14 wherein the signal-producing unit is associated with at least one logic qubit.

17. The apparatus as claimed in claim 15 or 16 wherein the signal processing unit is arranged to operate at a temperature at which the qubit operates.

18. The apparatus as claimed in any one of claims 14 to 17 being an analogue electrical device.

19. The apparatus as claimed in claim 18 wherein the analogue electrical device is arranged for comparing analogue patterns of respective signals.

20. The apparatus as claimed in any one of claims 14 to 17 being a digital electrical device.

21. The apparatus as claimed in claim 20 wherein the digital electrical device is arranged for comparing digital patterns of respective signals.

22. A method of calibrating the apparatus as claimed in any one of claims 14 to 21, comprising: providing at least one valid signal form a signal- producing unit, and storing a pattern of the or each valid signal to establish a library of valid signals and thereby calibrate the apparatus .

23. The method as claimed in claim 22 wherein step of providing at least one valid signal comprises providing a series of valid signals and averaging the valid signals to reduce the relative level of noise.