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WO2004079789A2 - Isolation entre etages dans des transistors darlington - Google Patents

Isolation entre etages dans des transistors darlington Download PDF

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Publication number
WO2004079789A2
WO2004079789A2 PCT/US2004/006278 US2004006278W WO2004079789A2 WO 2004079789 A2 WO2004079789 A2 WO 2004079789A2 US 2004006278 W US2004006278 W US 2004006278W WO 2004079789 A2 WO2004079789 A2 WO 2004079789A2
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WO
WIPO (PCT)
Prior art keywords
base
region
emitter
contact
collector
Prior art date
Application number
PCT/US2004/006278
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English (en)
Other versions
WO2004079789A3 (fr
Inventor
Tat-Sing Paul Chow
Yi Tang
Original Assignee
Rensselaer Polytechnic Institute
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Publication date
Application filed by Rensselaer Polytechnic Institute filed Critical Rensselaer Polytechnic Institute
Publication of WO2004079789A2 publication Critical patent/WO2004079789A2/fr
Publication of WO2004079789A3 publication Critical patent/WO2004079789A3/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/641—Combinations of only vertical BJTs
    • H10D84/642—Combinations of non-inverted vertical BJTs of the same conductivity type having different characteristics, e.g. Darlington transistors

Definitions

  • the present invention relates generally to the field semiconductor devices and, in particular, to Darlington transistors.
  • Fig. 1 is a schematic cross-section of a conventional silicon Darlington transistor and Fig. 2 is a schematic equivalent circuit model thereof.
  • the Darlington transistor 10 is two BJTs (Base-Junction-Transistors) T1 and T2, cascaded together to provide higher current gain.
  • BJTs Base-Junction-Transistors
  • T1 and T2 BJTs
  • T1 and T2 BJTs
  • SiC Silicon Carbide
  • SiC has long been recognized as the choice for high voltage, high temperature, high power applications. With the development of power devices and power electronics, silicon power devices are reaching their material limits. Wide band gap materials such as SiC and GaN are therefore considered as an alternative for power electronics application especially under hostile environment. SiC is superior to silicon because of its wide band-gap, high critical electric field and superior thermal conductivity.
  • SiC BJTs suffer from trade-off between current gain and blocking voltage.
  • a monolithic Darlington transistor structure would ease the requirement on base drive current while maintaining the blocking voltage.
  • SiC Schottky rectifiers of 300V and 600V rating are commercially available from Infineon Technologies. SiC BJT with 1.8kV and current gain of 20 was also experimentally demonstrated (S-H. Ryu, A. K. Agarwal, R. Singh and J. W. Palmour, 58" Annual Device Research Conference, Denver, CO, June, 2000).
  • a problem to be solved by the present invention concerns the fact that in silicon, most bipolar junction transistors are made using double-diffusion, which means both the base region and the emitter region are formed by diffusion. All the SiC BJTs demonstrated to date used an epitaxial base, with the variation of either implanting emitter or using an epi-grown emitter. See: Y. Wang, W. Xie, J. A. Cooper, Jr., M. R. Meiloch and J. W. Palmour, Silicon Carbide and Related Materials Conf, pp. 809-812, Kyoto, Japan 1995; and Y. Tang, J. Fedlson, and T. P. Chow, 58" Annual Device Research Conference, Denver, CO, June, 2000.
  • a conductive collector contact and a semiconductor base region of opposite conductivity type, e.g. an N-epi region, are connected to the collector region.
  • First and spaced apart second semiconductor emitter regions of the one conductivity type are connected to the base region and a first conductive emitter contact is connected to the first emitter region with a second conductive emitter contact connected to the second emitter region.
  • a first conductive base contact is connected to the base region and is conductively connected to the first emitter contact.
  • a second conductive base contact is conductively isolated from the first base contact and is connected to the base region.
  • a resistive trench region extends at least partly into the base region for resistively separating the base region into a first base region communicating with the first emitter contact and the second base contact, and a second base region communicating with the first base contact and the second emitter contact.
  • the trench region extends either completely through the base region to completely separate the two parts of the base region from each other, or it extends partly into the base region to leave a high resistance gap which still serves to isolate the two parts of the base region from each other.
  • Fig. 1 is a schematic cross-section of a conventional silicon
  • Fig. 2 is a schematic equivalent circuit model of Fig. 1 ;
  • Fig. 3 is a schematic cross-section of a SiC Darlington transistor of the present invention
  • Fig. 4 is a schematic cross-section of a SiC Darlington transistor of another embodiment of the present invention
  • Fig. 5 is a graph plotting peak current gain against isolation trench depth from the junction of a trench having a 5 ⁇ m width to show simulated peak current gain for the device of the present invention
  • Fig. 6 is a graph plotting current gain against base-to-emitter voltage V BE for the device of the present invention.
  • FIG. 7 is a top plan view of a device fabricated according the present invention.
  • Fig. 8 is a graph plotting two curves of current gain against voltage V BE for the device of the present invention having emitter trenches of 0.7 ⁇ m and 0.55 ⁇ m depths;
  • Fig. 9 is a graph plotting two curves of current gain against collector arrent density forthe device of the present invention having emitter trenches of 0.7 ⁇ m and 0.55 ⁇ m depths;
  • Fig. 10 is a Gummel plot of current against voltage V BE for the device of the present invention at a collector voltage V CE of 7V;
  • Fig. 11 is a graph plotting curves of current gain against voltage
  • FIG. 12 is a graph plotting current against voltage V BE at various base currents to show the forward l-V characteristics of the Darlington transistor of the present invention
  • Fig. 13 is a graph plotting curves for the two transistors of a single stage BJTs of a device of the present invention, to show the common emitter current gain therefore
  • Fig. 14 is a graph plotting two curves like those of Fig. 13, for another device of the present invention
  • Fig. 15 is a graph plotting current gain against temperature to show the temperature dependence of the present invention.
  • Fig. 3 illustrates a Darlington transistor 20 of the present invention and the structure for one possible solution.
  • This solution is to isolate the two stages by a deep trench-etching 22 or oxide (e.g. SiO 2 ) or polysilicon, through the P-Base region 24 of the device which is epi-grown.
  • the top P+ epi-layer 42, 46 is epi-grown to ensure good P-contact and at the same time avoid high temperature annealing of P+ implantation.
  • the device is an implanted-emitter, epi-base BJT.
  • An alternative structure, an epi-emitter, epi-base BJT, can utilize the same structure for a SiC Darlington transistor.
  • Fig. 4 shows this alternative structure for the invention.
  • the P-Base layer 24 is partly etched at trench
  • the approach of the present invention ensures good isolation between the two stages when the region 26 is thin enough to provide a large enough resistor effect, as in Fig. 4, or if the trench 22 is etched through the junction to isolate the two stages completely as in Fig. 3.
  • the device of the present invention also has an N-Epi layer or semiconductor collector region of one conductivity type 28, connected to, and spanning a semiconductive base region 24 of opposite conductivity type having two P-Base regions 24a and 24b, as well as an N+Substrate 30 and conductive collector layer 32.
  • a conductor 34 connects a first emitter conductive layer 36 on the N+ emitter layer or first semiconductive emitter region 38 of the first stage transistor (T1 in Fig. 2) to the conductive base layer 40 on the P+ base layer or first semiconductor base region 42 of the second stage transistor (T2 in Fig. 2).
  • Conductive base layer 44 is connected to the base P+ layer 46 of the device 20 to form the base of the Darlington transistor, and conductive emitter layer 48 is connected to the emitter N+ layer 50 to form the emitter of the device.
  • Fig. 5 shows the peak current gain for the monolithic Darlington transistor at different trench depth. Trench width used is 5 ⁇ m. When the trench is not deep enough, the two stage BJTs are not isolated well, and the current gain approaches single stage current gain.
  • Fig 6 illustrates simulated peak current gain.
  • the present invention incorporates an internal resistor to aid in the turn-off of the device.
  • device turn-off sometimes takes a relatively long time if the device is turned off in an open- base configuration, because it takes time for the electron-hole plasma in the first and especially second stage BJT to recombine and disappear and restore the device to the blocking state. Therefore, a common solution in a silicon Darlington is to incorporate resistors between the base and emitter of the two transistors, providing a path for carriers to be drawn out of the device faster.
  • an internal resistor is put between the first stage and second stage base. Therefore during device turn-off, an additional current path is provided for fast switching of the device.
  • One concern related to the internal resistor is to make sure in the on- state, the internal resistor does not shunt the first stage BJT.
  • the forward drop across the resistor has to be larger than the built-in voltage of SiC junction (usually 2.5-3V). Therefore the design of the trench region 26 has to take that into consideration, assuming doping is 2x10 17 cm “3 in the P-Base region 24 and epi thickness is 1 ⁇ m for region N-Epi 28.
  • Breakdown voltage of the invention is close to that of the single stage
  • the novelty of the structure is that the breakdown voltage will not be degraded because of the deep trench. Because the trench is filled with oxide, the corner electric field will be different from the UMOSFET structure where the trench is filled with polysilicon with low potential, which will bring a high field point at the trench corner and cause pre-mature breakdown. In this structure, the electric field lines could go through the oxide, and other than the disrupt of the electric field concentration due to different dielectric constant, the breakdown will not occur at the trench corner. Therefore the blocking voltage will be like single stage BJTs, caused by drift layer, base punch through or termination.
  • the present invention has silicon applications. Both the structures of
  • Figs. 3 and 4 are also valid for silicon Darlington device structures. As mentioned, double-implanted Darlingtons can realize the isolation by implantation. However, if the base region is formed by blanket implant, the same structures can be used in silicon Darlingtons, so that an integrated resistor can be incorporate.
  • the invention has an epi-base, implanted-emitter, monolithic Darlington transistor with high peak current gain of 2000.
  • the nominal thickness and the doping of the P-Base or P-epi layer 24 and the N-Epi or N-drift layer 28 are 1 ⁇ m at 4x10 17 cm “3 and 12 ⁇ m at 4x10 15 cm “3 respectively.
  • the emitter implantation 38, 48 was done at 600°C using phosphorus with a total dose of 3 x 10 15 cm "3 , subsequently annealed at annealing temperature of 1400°C for 15 mins.
  • the two stage BJTs are isolated by isolation trench 22 of 1.7 ⁇ m as shown in Fig. 3. Emitter region 38 of the first stage BJT and base region 24b of the second stage BJT are connected using connecting metal Ti/Mo at 36, 34, 40.
  • base width can be adjusted by controlling the emitter trench depth and emitter implantation.
  • the emitter trench depth is increased from 0.55 ⁇ m to 0.7 ⁇ m, resulting in a base width of 0.25 ⁇ m instead of 0.4 ⁇ m.
  • the current gain of the single stage BJT is increased comparing to the previous case, as shown in Fig. 8.
  • a 2x increase in the single stage BJT current gain brought about further increase (4x) in the Darlington current gain, because of the relationship ⁇ D » ⁇ 1 ⁇ 2.
  • Table I the design parameters for different base widths is shown together with the measured peak gain for single stage BJT and Dariington transistor.
  • Fig. 10 Common emitter current gain is measured at a collector voltage of 7V, with the Gummel plot shown in Fig. 10. Device turns on when base-emitter junctions of both the BJTs are forward-biased. The maximum current gain is above 2000.
  • Fig. 9 shows the current gain versus collector current density plot. Comparison is shown for the two different emitter trench depth. It is observed that even though the peak current gain is increased, the current gain at 50A/cm 2 (-0.3A collector current) is lower than that of the previous results.
  • the present invention also provides an epi-base, implanted-emitter, monolithic Dariington transistor with high current gain (peak gain up to 450) in 4H-SiC.
  • an emitter trench first was formed using reactive ion etching (RIE).
  • the emitter implantation 38, 50 was then done at 600°C using phosphorus with a total dose of 3 x 10 15 cm "3 , with multiple implantations to achieve a box-profile with a junction depth of 0.3 ⁇ m.
  • the implants were subsequently annealed at different annealing temperatures (1200-1600°C).
  • the device was terminated with three-step trench termination. Therefore no additional implantation steps were needed.
  • the two stage BJTs were isolated by the isolation trench 22 of 1.7 ⁇ m.
  • the isolation trench was then filled with oxide.
  • Emitter region 38 of the first stage BJT and base region of the second stage BJT were connected using connecting metal Ti/Mo as noted, over oxide (e.g. SiO 2 ) as inter-level dielectric.
  • the device of the invention shown in top view in Fig. 7, has an area of
  • the device gain ⁇ D is expected to be ⁇ D ⁇ ⁇ 1 ⁇ 2 where ⁇ 1 and ⁇ 2 are the current gain of the first and second stages respectively.
  • the isolation is not effective, the current gain will be smaller because of current cross-coupling between the input and output stages.
  • Numerical simulations have been done for the design of good isolation trench. Simulated current flow lines for two isolation trench widths at 100A/cm 2 were modeled. For an isolation trench width of 2 ⁇ m, part of the base current was shown to be diverted directly to the second stage. This part of the base current acted as part of the base current from the second stage BJT, causing a decrease in the overall current gain. For good isolation, therefore, the initial stage base current fed the first stage BJT. Current from the emitter of first-stage BIT was equal to the base current of the second-stage, because of the shorting of the two stages.
  • Fig. 5 shows the simulated peak current gain as a function of the isolation trench depth with a trench width of 5 ⁇ m. As the trench depth is decreased to above the junction, the peak current gain approaches single-stage BJT gain, indicating all the base current from the first stage BJT flows into second stage BJT without being amplified. For the trench width simulated, the isolation trench depth need to be at least deeper than the junction, to ensure good isolation.
  • the optimized isolation trench depth is at least 0.2 ⁇ m deeper than the junction for trench width of 5 ⁇ m, corresponding to an overall isolation trench depth of 1.7 ⁇ m in our process.
  • the common emitter current gain is measured at a collector voltage of
  • the shorting terminal between first stage emitter and second stage base is also accessible, which enables the testing of single stage of constituent BJTs.
  • the individual current gain of the two single stage BJTs has been measured.
  • the peak current gain of T1 and T2 are 25 and 21 , respectively, as shown in Fig. 13.
  • the implanted-emitter, epi-base 4H-SiC Darlington transistor of the invention as shown in Fig. 7 has a maximum common emitter current gain above 80.
  • the forward drop at 0.3A ( ⁇ 50A/crn 2 ) is around 7.5V.
  • the Darlington transistor exhibits negative temperature effect of current gain.
  • the inter-stage isolation is achieved with trenches filled with oxide.
  • the shorting terminal between first stage emitter and second stage base is also accessible, which enables the testing of single stage of constituent BJTs.
  • the individual current gain of the two single stage BJTs has been measured and is shown in Fig. 14.
  • the blocking voltage of the devices is lower than expected for the epi thickness ( ⁇ 1500V expected).
  • ⁇ 1500V expected One reason is that the isolation trench between the two-stage BJTs causes pre-mature breakdown due to field crowding at the trench corner.
  • Numerical simulations show that the open- emitter breakdown voltage can be reduced as much as 40% when the isolation trench is 0.2 ⁇ rn deeper than the base/collector junction. Other causes for the low blocking voltage are still unknown at present.

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  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

L'invention concerne un transistor Darlington comprenant une zone collectrice semi-conductrice d'un type de conductivité permettant de former un collecteur pour le dispositif. Un contact de collecteur conducteur et une zone de base semi-conductrice d'un type de conductivité opposé sont connectés à la zone collectrice. Une première zone d'émission semi-conductrice et une seconde zone d'émission semi-conductrice espacée du premier type de conductivité sont connectées à la zone de base, un premier contact d'émission conducteur étant connecté à la première zone d'émission et un second contact d'émission conducteur étant connecté à la seconde zone d'émission. Un premier contact de base conducteur est connecté à la zone de base et connecté électriquement au premier contact d'émission. Un second contact de base conducteur est isolé électriquement du premier contact de base et connecté à la zone de base. Une zone de tranchée résistive s'étendant au moins en partie dans la zone de base permet de séparer la zone de base, de manière résistive, en une première zone de base communiquant avec le premier contact d'émission et le second contact de base et en une seconde zone de base communiquant avec le premier contact de base et le second contact d'émission.
PCT/US2004/006278 2003-03-05 2004-03-01 Isolation entre etages dans des transistors darlington WO2004079789A2 (fr)

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Cited By (21)

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WO2011008919A1 (fr) * 2009-07-15 2011-01-20 Cree, Inc. Transistors darlington à large bande interdite et à gain élevé et procédés de fabrication correspondants
US8193848B2 (en) 2009-06-02 2012-06-05 Cree, Inc. Power switching devices having controllable surge current capabilities
US8294507B2 (en) 2009-05-08 2012-10-23 Cree, Inc. Wide bandgap bipolar turn-off thyristor having non-negative temperature coefficient and related control circuits
US8330244B2 (en) 2006-08-01 2012-12-11 Cree, Inc. Semiconductor devices including Schottky diodes having doped regions arranged as islands and methods of fabricating same
US8354690B2 (en) 2009-08-31 2013-01-15 Cree, Inc. Solid-state pinch off thyristor circuits
US8415671B2 (en) 2010-04-16 2013-04-09 Cree, Inc. Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices
US8432012B2 (en) 2006-08-01 2013-04-30 Cree, Inc. Semiconductor devices including schottky diodes having overlapping doped regions and methods of fabricating same
US8541787B2 (en) 2009-07-15 2013-09-24 Cree, Inc. High breakdown voltage wide band-gap MOS-gated bipolar junction transistors with avalanche capability
CN103367416A (zh) * 2013-07-04 2013-10-23 西安电子科技大学 离子注入的一维电子气GaN基HEMT器件及制备方法
US8629509B2 (en) 2009-06-02 2014-01-14 Cree, Inc. High voltage insulated gate bipolar transistors with minority carrier diverter
US8710510B2 (en) 2006-08-17 2014-04-29 Cree, Inc. High power insulated gate bipolar transistors
US8835987B2 (en) 2007-02-27 2014-09-16 Cree, Inc. Insulated gate bipolar transistors including current suppressing layers
US9029945B2 (en) 2011-05-06 2015-05-12 Cree, Inc. Field effect transistor devices with low source resistance
US9117739B2 (en) 2010-03-08 2015-08-25 Cree, Inc. Semiconductor devices with heterojunction barrier regions and methods of fabricating same
US9142662B2 (en) 2011-05-06 2015-09-22 Cree, Inc. Field effect transistor devices with low source resistance
US9373617B2 (en) 2011-09-11 2016-06-21 Cree, Inc. High current, low switching loss SiC power module
US9640617B2 (en) 2011-09-11 2017-05-02 Cree, Inc. High performance power module
US9673283B2 (en) 2011-05-06 2017-06-06 Cree, Inc. Power module for supporting high current densities
WO2020074930A1 (fr) * 2018-10-12 2020-04-16 Search For The Next Ltd Procédés de fabrication d'un dispositif transistor
CN113474878A (zh) * 2018-10-12 2021-10-01 瑟其福耐斯特有限公司 制造晶体管器件的方法
US12289884B2 (en) 2021-05-21 2025-04-29 Stmicroelectronics (Rousset) Sas Integrated circuit comprising at least one bipolar transistor and a corresponding method of production

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US8432012B2 (en) 2006-08-01 2013-04-30 Cree, Inc. Semiconductor devices including schottky diodes having overlapping doped regions and methods of fabricating same
US8330244B2 (en) 2006-08-01 2012-12-11 Cree, Inc. Semiconductor devices including Schottky diodes having doped regions arranged as islands and methods of fabricating same
US9548374B2 (en) 2006-08-17 2017-01-17 Cree, Inc. High power insulated gate bipolar transistors
US8710510B2 (en) 2006-08-17 2014-04-29 Cree, Inc. High power insulated gate bipolar transistors
US9064840B2 (en) 2007-02-27 2015-06-23 Cree, Inc. Insulated gate bipolar transistors including current suppressing layers
US8835987B2 (en) 2007-02-27 2014-09-16 Cree, Inc. Insulated gate bipolar transistors including current suppressing layers
US8294507B2 (en) 2009-05-08 2012-10-23 Cree, Inc. Wide bandgap bipolar turn-off thyristor having non-negative temperature coefficient and related control circuits
US8193848B2 (en) 2009-06-02 2012-06-05 Cree, Inc. Power switching devices having controllable surge current capabilities
US8629509B2 (en) 2009-06-02 2014-01-14 Cree, Inc. High voltage insulated gate bipolar transistors with minority carrier diverter
US8541787B2 (en) 2009-07-15 2013-09-24 Cree, Inc. High breakdown voltage wide band-gap MOS-gated bipolar junction transistors with avalanche capability
US9478537B2 (en) 2009-07-15 2016-10-25 Cree, Inc. High-gain wide bandgap darlington transistors and related methods of fabrication
WO2011008919A1 (fr) * 2009-07-15 2011-01-20 Cree, Inc. Transistors darlington à large bande interdite et à gain élevé et procédés de fabrication correspondants
US8354690B2 (en) 2009-08-31 2013-01-15 Cree, Inc. Solid-state pinch off thyristor circuits
US9117739B2 (en) 2010-03-08 2015-08-25 Cree, Inc. Semiconductor devices with heterojunction barrier regions and methods of fabricating same
US8415671B2 (en) 2010-04-16 2013-04-09 Cree, Inc. Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices
US9142662B2 (en) 2011-05-06 2015-09-22 Cree, Inc. Field effect transistor devices with low source resistance
US9029945B2 (en) 2011-05-06 2015-05-12 Cree, Inc. Field effect transistor devices with low source resistance
US9673283B2 (en) 2011-05-06 2017-06-06 Cree, Inc. Power module for supporting high current densities
US11024731B2 (en) 2011-09-11 2021-06-01 Cree, Inc. Power module for supporting high current densities
US9373617B2 (en) 2011-09-11 2016-06-21 Cree, Inc. High current, low switching loss SiC power module
US9640617B2 (en) 2011-09-11 2017-05-02 Cree, Inc. High performance power module
US10141302B2 (en) 2011-09-11 2018-11-27 Cree, Inc. High current, low switching loss SiC power module
US10153364B2 (en) 2011-09-11 2018-12-11 Cree, Inc. Power module having a switch module for supporting high current densities
US11171229B2 (en) 2011-09-11 2021-11-09 Cree, Inc. Low switching loss high performance power module
CN103367416A (zh) * 2013-07-04 2013-10-23 西安电子科技大学 离子注入的一维电子气GaN基HEMT器件及制备方法
CN113474878A (zh) * 2018-10-12 2021-10-01 瑟其福耐斯特有限公司 制造晶体管器件的方法
US20210343582A1 (en) * 2018-10-12 2021-11-04 Search For The Next, LTD. Methods of manufacturing a transistor device
WO2020074930A1 (fr) * 2018-10-12 2020-04-16 Search For The Next Ltd Procédés de fabrication d'un dispositif transistor
US12289884B2 (en) 2021-05-21 2025-04-29 Stmicroelectronics (Rousset) Sas Integrated circuit comprising at least one bipolar transistor and a corresponding method of production

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WO2004079789A3 (fr) 2004-11-11

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