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WO2002009157A2 - Oxyde metallique alcalino-terreux sur des isolateurs de porte - Google Patents

Oxyde metallique alcalino-terreux sur des isolateurs de porte Download PDF

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Publication number
WO2002009157A2
WO2002009157A2 PCT/US2001/022652 US0122652W WO0209157A2 WO 2002009157 A2 WO2002009157 A2 WO 2002009157A2 US 0122652 W US0122652 W US 0122652W WO 0209157 A2 WO0209157 A2 WO 0209157A2
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layer
monocrystalline
oxide
compound semiconductor
earth metal
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PCT/US2001/022652
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WO2002009157A3 (fr
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Jamal Ramdani
Ravindranath Droopad
Lyndee Hilt
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Motorola, Inc.
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Priority to AU2001278949A priority Critical patent/AU2001278949A1/en
Publication of WO2002009157A2 publication Critical patent/WO2002009157A2/fr
Publication of WO2002009157A3 publication Critical patent/WO2002009157A3/fr

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Definitions

  • This invention relates generally to semiconductor structures and devices and to a method for their fabrication, and more specifically to compound semiconductor structures and devices and to the fabrication and use of semiconductor structures, devices, and integrated circuits that include a monocrystalline compound semiconductor material.
  • CMOS complementary metal oxide semiconductor
  • FIGS. 1 - 3 illustrate schematically, in cross section, device structures in accordance with various embodiments of the invention
  • FIG. 4 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch in the context of a host crystal and a grown crystalline overlayer
  • FIG. 5 illustrates a device structure including gate, source, and drain regions in accordance with an exemplary embodiment of the present invention.
  • FIG. 6 is similar to FIG. 5 and further illustrates a device structure including a gate, a source region, and a drain region formed on a Group IV monocrystalline semiconductor substrate in accordance with an exemplary embodiment of the present invention.
  • FIG. 1 illustrates schematically, in cross section, a portion of a semiconductor structure 100 in accordance with an embodiment of the invention.
  • Semiconductor structure 100 includes a monocrystalline compound semiconductor layer 101, an oxide template layer 103, and a monocrystalline alkali earth metal oxide layer 105.
  • the term "monocrystalline” shall have the meaning commonly used within the semiconductor industry.
  • the term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry.
  • Monocrystalline compound semiconductor layer 101 is a monocrystalline compound semiconductor substrate, such as a gallium arsenide substrate.
  • any native oxides e . g. , gallium oxide
  • any native oxides are removed from the surface of the monocrystalline compound semiconductor substrate to form a native oxide free gallium arsenide substrate.
  • oxide template layer 103 (and subsequently monocrystalline alkali earth metal oxide layer 105) may be grown epitaxially upon monocrystalline compound semiconductor layer 101. In this respect, terminating the surface of monocrystalline compound semiconductor layer
  • Terminating layer 102 allows for a stable, high dielectric constant or medium dielectric constant oxide to be grown on monocrystalline compound semiconductor layer 101. In addition, terminating layer 102 helps to initiate the growth of oxide template layer
  • terminating layer 102 helps to relieve the strain that might otherwise occur in oxide template layer 103 as a result of differences in the lattice constants of monocrystalline compound semiconductor layer 101 and oxide template layer 103. Relieving the strain in oxide template 103 aids in the growth of a high crystalline quality monocrystalline alkali earth metal oxide layer 105. Terminating layer 102 may form part of oxide template layer 103, but is nevertheless illustrated as a separate layer for purpose of description.
  • monocrystalline compound semiconductor layer 101 is a gallium arsenide substrate
  • monocrystalline compound semiconductor layer 101 may be terminated by forming layer 102 comprising gallium, and then exposing layer 102 to strontium and oxygen to form a monolayer of oxide template layer 103 having a thickness in the range of about 4-5 Angstroms (A) .
  • terminating layer 102 may be exposed to a strontium (or barium) gallium oxide layer, for example, to aid in the growth of oxide template layer 103.
  • Exposing terminating layer 102 to an alkali earth metal and oxygen forms oxide template 103 having the form alkali earth metal-gallium- oxygen ⁇ e . g.
  • oxide template layer 103 may include using a monolayer of strontium oxide (e.g., SrO) followed by a layer of titanium oxide (e.g., Ti0 2 ) .
  • oxide template layer 103 could be one or more monolayers thick, such as about 1 - 10 monolayers. In this way, oxide template layer 103 will provide a substantially stable oxide for CMOS applications, for example .
  • monocrystalline alkali earth metal oxide layer 105 may be formed overlying oxide template layer 103. Suitable monocrystalline alkali earth metal oxide layer 105 materials chemically bond to the surface of oxide template layer 103 at selected sites and provide sites for the nucleation of the epitaxial growth of the subsequent monocrystalline alkali earth metal oxide layer 105.
  • Monocrystalline alkali earth metal oxide layer 105 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying layer.
  • the resulting monocrystalline alkali earth metal oxide layer 105 may have a thickness of about 2-100 nm, such as about 5-10 nm.
  • the material could be an oxide or nitride having a lattice structure substantially matched to the underlying layer and to any subsequently applied overlying material.
  • monocrystalline alkali earth metal oxide layer 105 may be of the form strontium-barium- titanium-oxygen (Sr x Ba 1 _ x Ti0 3 , where x ranges from 0 to 1) , an alkali earth metal tin oxide (e.g., BaSn0 3 ) , and/or the like.
  • FIG. 2 illustrates, in cross section, a portion of a semiconductor structure 200 in accordance with a further embodiment of the invention.
  • Structure 200 is similar to the previously described semiconductor structure 100, except that structure 200 also includes an impurity doped layer (or impurity doped region) 207 positioned in monocrystalline compound semiconductor layer 101 and underlying oxide template layer 103.
  • Impurity doped layer 207 is typically a compound semiconductor material (e.g., gallium arsenide) including an n or p type dopent or impurity (e.g., silicon) typically used in CMOS manufacturing .
  • impurity doped layer 207 is formed in monocrystalline compound semiconductor layer 101 at the interface between monocrystalline compound semiconductor layer 101 and oxide template layer 103.
  • impurity doped layer 207 has a thickness in the range of approximately 5-500 nm and varies from about 1 - 10 monolayers.
  • Impurity doped layer 207 has a thickness in the range of approximately 5-500 nm and varies from about 1 -
  • a source region 217 and a drain 219 region may be formed, e.g., via doping, diffusion, or ion implantation, in impurity doped layer 207 to form structure 500, illustrated in FIG. 5.
  • layers 103 and 105 are formed over layer 207, and a conductive electrode 215 (e.g., a gate electrode, a patterned metal electrode, or the like) is formed on monocrystalline alkali earth metal oxide layer 105 in alignment with source 217 and drain 219 regions in order to provide an insulated gate structure of an insulated field effect transistor, for example.
  • FIG. 3 schematically illustrates, in cross section, a portion of a semiconductor structure 300 in accordance with another exemplary embodiment of the invention.
  • Structure 300 is similar to structures 100 and 200, except that structure 300 includes an oxide template layer 309, a Group IV monocrystalline semiconductor substrate 311, and optionally impurity doped layer 207.
  • structure 300 also includes an amorphous intermediate layer 315 positioned between Group IV monocrystalline semiconductor substrate 311 and oxide template layer 309.
  • Amorphous intermediate layer 315 is grown on Group IV monocrystalline semiconductor substrate 311, at the interface between Group IV monocrystalline semiconductor substrate 311 and the growing oxide template layer 309, by the oxidation of Group IV monocrystalline semiconductor substrate 311 during the growth of oxide template layer 309.
  • Amorphous intermediate layer 315 helps to relieve the strain in oxide template layer 309 and by doing so, aids in the growth of a high crystalline quality monocrystalline alkali earth metal oxide layer 105.
  • amorphous intermediate layer 315 serves to relieve strain that might otherwise occur in the monocrystalline oxide template layer 309 as a result of differences in the lattice constants of Group IV, monocrystalline semiconductor substrate 311 and oxide template layer 309. If such strain is not relieved by amorphous intermediate layer 315, the strain may cause defects in the crystalline structure of oxide template layer 309. Defects in the crystalline structure of oxide template layer 309, in turn, would make it difficult to achieve a high quality crystalline structure in monocrystalline alkali earth metal oxide layer 105.
  • Amorphous intermediate layer 315 is preferably an oxide formed by the oxidation of the surface of Group IV monocrystalline semiconductor substrate 311, and more preferably is composed of a silicon oxide.
  • amorphous intermediate layer 315 is sufficient to relieve strain attributed to mismatches between the lattice constants of Group IV monocrystalline semiconductor substrate 311 and oxide template layer 309. Typically, amorphous intermediate layer 315 has a thickness in the range of approximately 0.5-5 nm.
  • Oxide template layer 309 is similar to oxide template layer 103 in FIGS. 1 and 2, but is positioned between monocrystalline compound semiconductor layer 101 and Group IV monocrystalline semiconductor substrate 311. Oxide template layer 309 is formed overlying Group IV monocrystalline semiconductor substrate 311 (e.g., a silicon substrate) . Oxide template layer 309 helps to initiate the growth of monocrystalline compound semiconductor layer 101 on oxide template layer 309.
  • Oxide template layer 309 is preferably a substantially stable monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying substrate and with the overlying compound semiconductor material.
  • the material of oxide template layer 309 could be an oxide or nitride having a lattice structure substantially matched to the substrate and to the subsequently applied semiconductor material.
  • Oxide template layer 309 is preferably grown on the underlying substrate. Once oxide template layer 309 is formed, monocrystalline compound semiconductor layer 101 may be epitaxially grown overlying oxide template layer 309.
  • Oxide template layer 309 could be one or more monolayers thick, such as having a thickness of about 1 - 10 monolayers .
  • Structure 300 may also include a terminating layer 313 between oxide template layer 309 and monocrystalline compound semiconductor layer 101.
  • a terminating layer 313 By terminating (i.e., stabilizing) the surface of oxide template layer 309 with a monolayer of strontium (or barium) oxide (e.g., SrO or BaO) or a titanium oxide (e.g., Ti0 2 ) to form terminating layer 313, monocrystalline compound semiconductor layer 101 may be grown epitaxially upon oxide template layer 309.
  • a terminating the surface of oxide template layer 309 allows for a terminating layer 313 to be formed. Terminating layer 313 facilitates the growth of monocrystalline compound semiconductor layer 101 overlying oxide template layer 309.
  • Terminating layer 313 may form part of oxide template layer 309; however, layer 313 is conveniently illustrated as a separate layer for purpose of description. As discussed above in connection with FIGS. 1 and 2, subsequent layers may be formed on monocrystalline compound semiconductor layer 101 as discussed above in connection with FIGS. 1 and 2.
  • FIG. 6 illustrates an exemplary embodiment of the present invention, which is similar to structure 500, except structure 600 further includes a gate 221, a source
  • FIG. 4 illustrates graphically the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal.
  • Curve 401 illustrates the boundary of high crystalline quality material .
  • the area to the right of curve 401 represents layers that has a large number of defects. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly.
  • monocrystalline epitaxial layers in excess of about 20 nm may have defects .
  • monocrystalline compound semiconductor layer 101 is a (100) oriented monocrystalline gallium arsenide wafer and oxide template layer 103 is a layer of strontium barium titanate.
  • Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate (e.g., strontium titanate, barium titanate, or the like) material by 45° with respect to the crystal orientation of the gallium arsenide substrate wafer.
  • the crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation.
  • oxide template layer 103 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation.
  • the lattice constants of oxide template layer 103 and the monocrystalline substrate must be substantially matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved.
  • the terms "substantially equal” and “substantially matched” mean that there is sufficient similarity between the lattice constants to permit the growth of a high quality crystalline layer on the underlying layer .
  • oxide template layer 103 must be of high crystalline quality.
  • substantial matching between the crystal lattice constant of the host crystal (i.e., monocrystalline compound semiconductor layer 101) and the grown crystal (i.e., monocrystalline alkali earth metal oxide layer 105) is desired. With properly selected materials this substantial matching of lattice constants is achieved as a result of rotation of the crystal orientation of the grown crystal with respect to the orientation of the host crystal. If the host crystal is' gallium arsenide, aluminum gallium arsenide, zinc selenide, or zinc sulfur selenide and oxide template layer
  • 103 is monocrystalline Sr ⁇ a ⁇ JTiO. , substantial matching of crystal lattice constants of the two materials is achieved, wherein the crystal orientation of the grown layer is rotated by 45° with respect to the orientation of oxide template layer 103.
  • oxide template layer 103 material is a strontium or barium zirconate or a strontium or barium hafnate or barium tin oxide and monocrystalline alkali earth metal oxide layer 105 is indium phosphide or gallium indium arsenide or aluminum indium arsenide
  • substantial matching of crystal lattice constants can be achieved by rotating the orientation of the grown crystal layer (i.e., monocrystalline alkali earth metal oxide layer 105) by 45° with respect to the host crystal layer.
  • a crystalline semiconductor buffer (or oxide) layer between the host crystal and the grown compound semiconductor layer can be used to reduce strain in the grown monocrystalline alkali earth metal oxide layer 105 that might result from small differences in lattice constants. Better crystalline quality in the grown monocrystalline alkali earth metal oxide layer 105 can thereby be achieved.
  • monocrystalline compound semiconductor layer 101 is a monocrystalline substrate such as a monocrystalline gallium arsenide substrate.
  • a compound semiconductor material of monocrystalline compound semiconductor layer 101 can be selected, as needed for a particular semiconductor structure, from any of the Group IIIA and VA elements (III-V semiconductor compounds), mixed III-V compounds, Group II (A or B) and VIA elements (II-VI semiconductor compounds) , and/or mixed II-VI compounds.
  • monocrystalline compound semiconductor layer 101 includes materials from Group ill and V of the periodic table. Examples of Group III materials include aluminum, gallium, indium, and the like.
  • Group V materials include phosphorous, arsenic, tin, and the like.
  • suitable compound semiconductor materials include gallium indium arsenide (GalnAs) , gallium aluminum arsenide (GaAlAs) , gallium indium phosphide (GalnP) , aluminum indium arsenide
  • monocrystalline compound semiconductor layer 101 may include one or more layers, e.g., GalnAs and/or AlInAs overlying a layer of InP.
  • Monocrystalline compound semiconductor layer 101 may be prepared by Molecular Beam Epitaxy (MBE) , chemical vapor deposition (CVD) , metal organic chemical vapor deposition (MOCVD) , migration enhanced epitaxy (MEE) , atomic layer epitaxy (ALE) , physical vapor deposition (PVD) , chemical solution deposition (CSD) , pulsed laser deposition (PLD) , or the like.
  • MBE Molecular Beam Epitaxy
  • CVD chemical vapor deposition
  • MOCVD metal organic chemical vapor deposition
  • MEE migration enhanced epitaxy
  • ALE atomic layer epitaxy
  • PVD physical vapor deposition
  • CSSD chemical solution deposition
  • PLD pulsed laser deposition
  • Terminating layer 102 is typically a thin film of gallium, aluminum, or another material used in monocrystalline compound semiconductor layer 101.
  • terminating layer 102 may be a monolayer of gallium in a gallium arsenide monocrystalline compound semiconductor layer 101 (or a monolayer of aluminum in a gallium aluminum arsenide monocrystalline compound semiconductor layer 101) deposited by way of MBE, MOCVD, ALE, or MEE.
  • Oxide template layer 103 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying layer and with the overlying material.
  • the material of oxide template layer 103 could be an oxide or nitride having a lattice structure substantially matched to the underlying layer and to the subsequently applied overlying material .
  • oxide template layer 103 Materials that are suitable for oxide template layer 103 include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for oxide template layer 103.
  • metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alka
  • these materials are insulators, although strontium ruthenate, for example, is a conductor.
  • these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements and have a perovskite crystalline structure.
  • the metal oxides or nitride may include three or more different metallic elements.
  • oxide template layer 103 may include an element from monocrystalline compound semiconductor layer 101 and oxygen.
  • oxide template layer 103 may be of the form A-gallium-oxygen (A-Ga-O) and/or A-aluminum- oxygen (A-Al-0) for a gallium arsenide substrate, or A- indium-oxygen (A-In-O) for an indium phosphide substrate, where A is an alkali earth metal.
  • oxide template layer 103 may be a thin layer of A-Ga-O (e.g., one monolayer) .
  • oxide template layer 103 includes strontium gallium oxide (e.g., SrGa 2 0 4 ) , barium gallium oxide (e.g., BaGa 2 0 3 ) , a thin layer of gallium and a thin layer of strontium-oxygen (Sr-0) , a thin layer of gallium and a thin layer of barium-oxygen
  • In-Sn-0 indium-tin-oxygen
  • tin-indium-oxygen e.g., Snln 2 0 4
  • Sn-O tin-oxygen
  • Oxide template layer 103 may be epitaxially grown on the underlying layer. For example, using any of the methods discussed above with forming layer 101.
  • Materials that are suitable for monocrystalline alkali earth metal oxide layer 105 include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide.
  • nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for monocrystalline alkali earth metal oxide layer 105.
  • Most of these materials are insulators, although strontium ruthenate, for example, is a conductor.
  • these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements. In some specific applications, the metal oxides or nitride may include three or more different metallic elements.
  • Monocrystalline alkali earth metal oxide layer 105 may be epitaxially grown overlying oxide template layer 103 using MBE, MOCVD, ALE, or MEE, among other processes.
  • Group IV monocrystalline semiconductor substrate 311 in accordance with an embodiment of the invention, is a monocrystalline semiconductor wafer, preferably of large diameter.
  • the wafer can be of a material from Group IV of the periodic table, and preferably a material from Group
  • Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like.
  • Group IV monocrystalline semiconductor substrate 311 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry.
  • oxide template layer 309 Materials that are suitable for oxide template layer 309 include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for oxide template layer 309.
  • metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline
  • oxide template materials chemically bond to the surface of oxide template layer 309 at selected sites and provide sites for the nucleation of the epitaxial growth of the subsequent monocrystalline compound semiconductor layer 101.
  • oxide template layer 309 include strontium titanium oxide (SrTi0 3 ) , barium titanium oxide (BaTi0 3 ) , or the like.
  • Appropriate materials for terminating layer 313 for a gallium arsenide substrate include an atomic layer of strontium-oxygen (SrO) , titanium-oxygen (TiO) , gallium- strontium-oxygen (Ga-Sr-O) , arsenic-strontium-oxygen (As- Sr-O) , titanium-arsenic-oxygen (Ti-As-O) , titanium- gallium-oxygen (Ti-Ga-O) , or the like.
  • strontium-oxygen SrO
  • TiO titanium-oxygen
  • Ga-Sr-O gallium- strontium-oxygen
  • As- Sr-O arsenic-strontium-oxygen
  • Ti-As-O titanium-arsenic-oxygen
  • Ti-Ga-O titanium- gallium-oxygen
  • Another example includes terminating monocrystalline compound semiconductor layer 101 with indium by depositing a monolayer of indium and exposing the indium layer of monocrystalline compound semiconductor layer 101 to tin and oxygen to form an indium-tin-oxygen (InSnO) oxide having one or more monolayers.
  • Appropriate materials for terminating layer 313 for an indium phosphide substrate include an atomic layer of barium-titanium-oxygen (Ba-Ti- 0) , indium-tin-oxygen (In-Sn-0) , indium-tin-phosphorous (In-Sn-P) , or the like.
  • the following example illustrates a process, in accordance with one embodiment of the invention, for fabricating a semiconductor structure such as the structures depicted in FIGS. 1, 2, and 5.
  • the process starts by providing a monocrystalline compound semiconductor substrate comprising gallium arsenide or indium phosphide, for example.
  • the compound semiconductor substrate is a gallium arsenide wafer having a (100) orientation.
  • the substrate is preferably oriented on axis or, at most, about 2°-6° off axis.
  • At least a portion of the compound semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures.
  • bare in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material.
  • bare gallium arsenide is highly reactive and readily forms a native oxide.
  • the term “bare” is intended to encompass such a native oxide.
  • the native oxide layer In order to epitaxially grow a monocrystalline oxide layer overlying the monocrystalline compound semiconductor substrate, the native oxide layer must first be substantially removed to expose the crystalline structure of the underlying substrate. The following process is preferably carried out by molecular beam epitaxy (MBE) , although other epitaxial processes may also be used in accordance with the present invention.
  • MBE molecular beam epitaxy
  • the native oxide can be removed by thermal desorption, where the substrate is heated to about 600-650 °C under a flow of arsenic to obtain a substantially arsenic stable surface. At this time, the arsenic flow is typically turned off, whereby a gallium stable surface results (e.g., the terminating layer) .
  • the resultant surface is a gallium, oxide-free surface.
  • Reflection of High Energy Electron Deflection (RHEED) may be used to monitor the shift from an arsenic stable surface to a gallium stable surface, for example.
  • the resultant surface exhibits an ordered 4x2 gallium stabilized structure having a terminating layer (e.g., one atomic layer) of gallium in this example.
  • a stochiometric surface is desired to maintain the stability of the surface.
  • the terminating layer may be exposed to strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus.
  • strontium the substrate is then heated to a temperature of about 400-650 °C .
  • the resultant surface which exhibits an ordered 4x2 structure, includes strontium, oxygen, and gallium.
  • the ordered 4x2 structure forms an oxide template (e.g., one monolayer) for the ordered growth of an overlying layer of a monocrystalline oxide.
  • the oxide template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer.
  • the native oxide can be removed and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkali earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 400-650 °C. At this temperature, a solid state reaction takes place between the strontium oxide and the native oxide causing the reduction of the native oxide and leaving an ordered 4x2 structure with strontium, oxygen, and gallium remaining on the substrate surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer.
  • an alkali earth metal oxide such as strontium oxide, strontium barium oxide, or barium oxide
  • the substrate is cooled to a temperature in the range of about 300-650 °C and a layer of strontium titanate is grown on the template layer by MBE.
  • the MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources.
  • the ratio of strontium and titanium is approximately 1:1.
  • the partial pressure of oxygen is initially set at a minimum value to grow stochiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute.
  • an impurity doped layer may be formed to provide an active region.
  • the active region allows for subsequent formation of a source region and a drain region, for example. Alternatively, such regions may be formed prior to removing the gallium oxide, for example, by doping a portion of the substrate.
  • each of the variations of compound semiconductor ⁇ materials and monocrystalline oxide layers uses an appropriate template for initiating the growth of the subsequent layer.
  • the terminating layer and/or template oxide may include a thin layer of gallium, aluminum, or indium, respectively, as a precursor to depositing an alkaline earth metal oxide.
  • Each of these depositions helps to form a template for the deposition of a monocrystalline alkali earth metal oxide layer .
  • An alternate embodiment of the present invention illustrates a process for fabricating a semiconductor structure such as the structures depicted in FIGS. 3 and 6. The process starts by providing a monocrystalline semiconductor substrate comprising silicon or germanium.
  • the semiconductor substrate is a silicon wafer having a (100) orientation.
  • the substrate is preferably oriented on axis or, at most, about 0.5-6° off axis. At 5. least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures.
  • the term "bare” in this context means that the surface in the portion of the substrate has been cleaned to remove any 0 oxides, contaminants, or other foreign material.
  • bare silicon is highly reactive and readily forms a native oxide.
  • the term "bare” is intended to encompass such a native oxide.
  • a thin silicon oxide may also be intentionally grown on the semiconductor 5 substrate, although such a grown oxide is not essential to the process in accordance with the invention.
  • the native oxide layer In order to epitaxially grow a monocrystalline oxide layer overlying the monocrystalline substrate, the native oxide layer must first be removed to expose the 0 crystalline structure of the underlying substrate.
  • the following process is preferably carried out by MBE, although other epitaxial processes may also be used in accordance with the present invention.
  • the native oxide can be removed by first thermally depositing a thin layer 5 of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus. In the case where strontium is used, the substrate is then heated to a temperature of about 750 C° to cause the strontium to 0 react with the native silicon oxide layer.
  • the strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface.
  • the resultant surface which exhibits an ordered 2x1 structure, includes strontium, oxygen, and silicon.
  • the ordered 2x1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide.
  • the template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer.
  • the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkali earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750 °C.
  • the substrate is cooled to a temperature in the range of about 200-800 °C and a layer of strontium titanate is grown on the template layer by molecular beam epitaxy.
  • the MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources. The ratio of strontium and titanium is approximately 1:1.
  • the partial pressure of oxygen is initially set at a minimum value to grow stochiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value.
  • the overpressure of oxygen causes the growth of an amorphous silicon oxide layer at the interface between the underlying substrate and the growing strontium titanate layer.
  • the growth of the silicon oxide layer results from the diffusion of oxygen through the growing strontium titanate layer to the interface where the oxygen reacts with silicon at the surface of the underlying substrate.
  • the strontium titanate grows as an ordered monocrystal with the crystalline orientation rotated by 45° with respect to the ordered 2x1 crystalline structure of the underlying substrate.
  • the monocrystalline strontium titanate is capped by a template layer that is conducive to the subsequent growth of an epitaxial layer of a desired compound semiconductor material.
  • the MBE growth of the strontium titanate monocrystalline layer can be capped by terminating the growth with 1-2 monolayers of titanium, 1-2 monolayers of titanium-oxygen or with 1-2 monolayers of strontium-oxygen.
  • arsenic is deposited to form a Ti-As bond, a Ti-O-As bond or a Sr-O- As . Any of these form an appropriate template for deposition and formation of a gallium arsenide monocrystalline layer. Following the formation of the template, gallium is subsequently introduced to the reaction with the arsenic and gallium arsenide forms. Alternatively, gallium can be deposited on the capping layer to form a Sr-O-Ga bond, and arsenic is subsequently introduced with the gallium to form a gallium arsenide substrate. Once a gallium arenside layer is formed, the subsequent layers described in connection with FIGS.
  • 1, 2, and 5 may be formed in accordance with the process described above.
  • the following non-limiting, illustrative examples illustrate various combinations of materials useful in structures 100, 200, and 300 in accordance with various alternative embodiments of the invention. These examples are merely illustrative, and it is not intended that the invention be limited to these illustrative examples.
  • monocrystalline compound semiconductor layer 101 is a gallium arsenide substrate oriented in the (100) direction.
  • the gallium arsenide substrate can be, for example, a substrate as is commonly used in making CMOS integrated circuits and other compound semiconductor devices.
  • terminating layer 102 is an atomic layer of gallium, which is exposed to strontium and oxygen to form oxide template layer 103 .
  • oxide template layer 103 is a monocrystalline layer of gallium-strontium-oxygen (e.g., SrGa,0 4 ) .
  • the resulting oxide template layer 103 is Sr ⁇ a ⁇ TiO j where z ranges from 0 to 1. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of monocrystalline compound semiconductor layer 101.
  • monocrystalline compound semiconductor layer 101 is a layer of gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs) having a thickness of about 1 nm to about 100 micrometers ( ⁇ ) and preferably a thickness of about 0.5 ⁇ to 10 ⁇ m. The thickness generally depends on the application for which the layer is being prepared.
  • oxide template layer 103 is formed by capping (i.e., terminating or stabilizing) monocrystalline compound semiconductor layer 101.
  • oxide template layer 103 is preferably 1 - 10 monolayers of strontium gallium oxide (e.g., SrGa 2 0 4 ) .
  • monocrystalline alkali earth metal oxide layer 105 is formed overlying oxide template layer 103.
  • monocrystalline alkali earth metal oxide layer 105 is strontium-titanium-oxygen (SrTi0 3 ) .
  • impurity doped layer 207 is formed within or overlying monocrystalline compound semiconductor layer 101, and in any event underlying oxide template layer 309.
  • impurity doped layer 207 is a layer of gallium arsenide doped in order to provide source and drain regions for a transistor.
  • monocrystalline compound semiconductor layer 101 is an indium phosphide substrate oriented in the (100) direction.
  • the indium phosphide substrate can be, for example, a substrate as is commonly used in making CMOS integrated circuits.
  • terminating layer 102 is an atomic layer of indium formed using MBE, MOCVD, ALE, or MEE, which is exposed to tin and oxygen to form oxide template layer 103 .
  • oxide template layer 103 is a monocrystalline layer of indium-tin-oxygen (e.g., In-Sn-O) .
  • the resulting oxide template layer 103 is Sr z Ba 1 _ z Ti0 3 where z ranges from 0 to 1. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of monocrystalline compound semiconductor layer 101.
  • monocrystalline compound semiconductor layer 101 is a layer of indium phosphide having a thickness of about 1 nm to about 100 micrometers ( ⁇ m) and preferably a thickness of about 0.5 ⁇ to 10 ⁇ m. The thickness generally depends on the application for which the layer is being prepared.
  • oxide template layer 103 is formed by capping (i.e., terminating or stabilizing) monocrystalline compound semiconductor layer 101.
  • oxide template layer 103 is preferably 1 - 10 monolayers (e.g, 1-2 monolayers) of tin indium oxide.
  • monocrystalline alkali earth metal oxide layer 105 is formed overlying oxide template layer 103 by way of MBE, MOCVD, ALE, or MEE.
  • monocrystalline alkali earth metal oxide layer 105 is an alkali earth metal tin oxide having a thickness of about 8-11 nm.
  • impurity doped layer 207 is formed within or overlying monocrystalline compound semiconductor layer 101, and in any event, underlying oxide template layer 309.
  • impurity doped layer 207 is a layer of gallium indium arsenide (or aluminum indium arsenide) overlying the indium phosphide substrate and doped in order to provide source and drain regions for a transistor.
  • a patterned metal electrode may be formed overlying monocrystalline alkali earth metal oxide layer 105.

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Abstract

L'invention concerne des couches épitaxiales de haute qualité d'oxydes stables pouvant être développées sur des substrats de matériau semi-conducteur de composant. Le substrat semi-conducteur de composant (101) peut se terminer par une couche atomique de gallium, par exemple, (pour un substrat d'arséniure de gallium), formant une couche terminale (102). La couche d'oxyde (103) est une couche d'oxyde monocristalline espacée de la tranche semi-conductrice de composant par une couche de modèle d'oxyde recouvrant le substrat semi-conducteur de composant au moyen de la couche terminale. La couche de modèle d'oxyde (103) dissipe la déformation et permet également le développement d'une couche d'oxyde monocristalline de haute qualité. Tout décalage entre ladite couche d'oxyde monocristalline et le substrat semi-conducteur de composant sous-jacent est atténué grâce à la couche de modèle d'oxyde.
PCT/US2001/022652 2000-07-21 2001-07-18 Oxyde metallique alcalino-terreux sur des isolateurs de porte WO2002009157A2 (fr)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10303875A1 (de) * 2003-01-31 2004-08-19 Technische Universität Clausthal Struktur, insbesondere Halbleiterstruktur, sowie Verfahren zur Herstellung einer Struktur
WO2005093846A1 (fr) * 2004-03-12 2005-10-06 Hewlett-Packard Development Company, L.P. Dispositif semi-conducteur a canal fabrique a partir d'oxyde multicomposant
US20180331196A1 (en) * 2009-12-25 2018-11-15 Yuji Sone Field-effect transistor, semiconductor memory display element, image display device, and system
US10475930B2 (en) 2016-08-17 2019-11-12 Samsung Electronics Co., Ltd. Method of forming crystalline oxides on III-V materials

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US5962883A (en) * 1994-03-23 1999-10-05 Lucent Technologies Inc. Article comprising an oxide layer on a GaAs-based semiconductor body
US5767543A (en) * 1996-09-16 1998-06-16 Motorola, Inc. Ferroelectric semiconductor device having a layered ferroelectric structure
EP0926739A1 (fr) * 1997-12-24 1999-06-30 Texas Instruments Incorporated Structure et procédé pour un transistor à effet de champ du type MIS
JP2001144087A (ja) * 1999-11-12 2001-05-25 Natl Research Inst For Metals Ministry Of Education Culture Sports Science & Technology ５族元素による酸化物／半導体界面の安定化方法と安定化半導体

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10303875A1 (de) * 2003-01-31 2004-08-19 Technische Universität Clausthal Struktur, insbesondere Halbleiterstruktur, sowie Verfahren zur Herstellung einer Struktur
DE10303875B4 (de) * 2003-01-31 2006-03-16 Technische Universität Clausthal Struktur, insbesondere Halbleiterstruktur, sowie Verfahren zur Herstellung einer Struktur
WO2005093846A1 (fr) * 2004-03-12 2005-10-06 Hewlett-Packard Development Company, L.P. Dispositif semi-conducteur a canal fabrique a partir d'oxyde multicomposant
CN100530696C (zh) * 2004-03-12 2009-08-19 惠普开发有限公司 具有多组分氧化物制备的沟道的半导体器件
US8314420B2 (en) 2004-03-12 2012-11-20 Hewlett-Packard Development Company, L.P. Semiconductor device with multiple component oxide channel
US20180331196A1 (en) * 2009-12-25 2018-11-15 Yuji Sone Field-effect transistor, semiconductor memory display element, image display device, and system
US11271085B2 (en) * 2009-12-25 2022-03-08 Ricoh Company, Ltd. Field-effect transistor having amorphous composite metal oxide insulation film, semiconductor memory, display element, image display device, and system
US10475930B2 (en) 2016-08-17 2019-11-12 Samsung Electronics Co., Ltd. Method of forming crystalline oxides on III-V materials
US11081590B2 (en) 2016-08-17 2021-08-03 Samsung Electronics Co., Ltd. Metal oxide semiconductor field effect transistor with crystalline oxide layer on a III-V material

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