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WO2002009159A2 - Structure d'oxyde metallique en film mince et son procede de fabrication - Google Patents

Structure d'oxyde metallique en film mince et son procede de fabrication Download PDF

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Publication number
WO2002009159A2
WO2002009159A2 PCT/US2001/022679 US0122679W WO0209159A2 WO 2002009159 A2 WO2002009159 A2 WO 2002009159A2 US 0122679 W US0122679 W US 0122679W WO 0209159 A2 WO0209159 A2 WO 0209159A2
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layer
monocrystalline
perovskite oxide
growing
perovskite
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PCT/US2001/022679
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English (en)
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WO2002009159A3 (en
Inventor
Kurt Eisenbeiser
Jeffrey M. Finder
Jamal Ramdani
Ravindranath Droopad
William Jay Ooms
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Motorola, Inc.
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Priority to JP2002514770A priority Critical patent/JP2004505444A/ja
Priority to AU2001276989A priority patent/AU2001276989A1/en
Publication of WO2002009159A2 publication Critical patent/WO2002009159A2/fr
Publication of WO2002009159A3 publication Critical patent/WO2002009159A3/en

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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02—Epitaxial-layer growth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/16—Oxides
    • C30B29/22—Complex oxides
    • C30B29/32—Titanates; Germanates; Molybdates; Tungstates
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02269—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by thermal evaporation
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/074—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing
    • H10N30/076—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing by vapour phase deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0296—Processes for depositing or forming copper oxide superconductor layers
    • H10N60/0576—Processes for depositing or forming copper oxide superconductor layers characterised by the substrate
    • H10N60/0604—Monocrystalline substrates, e.g. epitaxial growth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H10D1/684—Capacitors having no potential barriers having dielectrics comprising perovskite structures the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers

Definitions

  • This invention relates generally to microelectronic structures and devices and to a method for their fabrication, and more specifically to thin-film, metallic oxide structures and devices and to the fabrication and use of thin-film, metallic oxide structures and devices.
  • metallic oxides exhibit desirable characteristics such as piezoelectric, ferroelectric, ferromagnetic, colossal magnetic resistance, and super conductivity properties. Such oxides may be included or used in connection with microelectronic devices that take advantage of these characteristics. For example, metallic oxides may be used to form ferroelectric memory devices and the like.
  • the desirable characteristics of the metallic oxide films increase as the crystallinity of the oxide film increases.
  • superconductive materials exhibit the highest conductivity when the material is in a monocrystalline form.
  • integration of such oxides with semiconductor components to form devices such as memory devices is also desirable. Accordingly, methods and apparatus for growing thin-film, monocrystalline metallic oxides on semiconductor substrates are desired.
  • a large area thin film of high quality monocrystalline metallic oxide material was available at low cost, a variety of semiconductor devices could advantageously be fabricated using that film at a low cost compared to the cost of fabricating such devices on a bulk wafer of the metallic oxide material or in an epitaxial film of such material on a bulk wafer of oxide material .
  • a thin film of high quality monocrystalline metallic oxide material could be realized on a bulk wafer such as a silicon wafer, an integrated device structure could be achieved that took advantage of the best properties of both the silicon and the metallic oxide material .
  • FIGS. 1 - 3 illustrate schematically, in cross section, device structures in accordance with various embodiments of the invention
  • FIG. 4 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer .
  • FIG. 1 illustrates schematically, in cross section, a portion of a microelectronic structure 20 in accordance with an embodiment of the invention.
  • Microelectronic structure 20 includes a monocrystalline substrate 22, accommodating buffer layer 24 comprising a monocrystalline material, and a layer 26 of a monocrystalline metallic oxide material.
  • accommodating buffer layer 24 comprising a monocrystalline material
  • a layer 26 of a monocrystalline metallic oxide material in this context, the term
  • monocrystalline shall have the meaning commonly used within the semiconductor industry.
  • the term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry.
  • structure 20 also includes an amorphous intermediate layer 28 positioned between substrate 22 and accommodating buffer layer 24.
  • Structure 20 may also include a template layer 30 between the accommodating buffer layer and monocrystalline oxide layer 26.
  • the template layer helps to initiate the growth of the metallic oxide layer on the accommodating buffer layer.
  • the amorphous intermediate layer helps to relieve the strain in the accommodating buffer layer and, by doing so, aids in the growth of a high crystalline quality accommodating buffer layer.
  • Substrate 22 in accordance with an embodiment of the invention, is a monocrystalline semiconductor wafer, preferably of large diameter.
  • the wafer can be of a material from Group IV of the periodic table, and preferably a material from Group IVA.
  • Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like.
  • Substrate 22 can also be of a compound semiconductor material.
  • the compound semiconductor material of substrate 22 can be selected, as needed for a particular semiconductor structure, from any of the Group IIIA and VA elements (III-V semiconductor compounds) , mixed III-V compounds, Group II (A or B) and VIA elements (II-VI semiconductor compounds), and mixed II-VI compounds.
  • Examples include gallium arsenide (GaAs) , gallium indium arsenide (GalnAs) , gallium aluminum arsenide (GaAlAs) , indium phosphide (InP) , cadmium sulfide (CdS) , cadmium mercury telluride (CdHgTe) , zinc selenide (ZnSe) , zinc sulfur selenide (ZnSSe) , and the like.
  • GaAs gallium arsenide
  • GaAs gallium indium arsenide
  • GaAlAs gallium aluminum arsenide
  • InP indium phosphide
  • CdS cadmium sulfide
  • CdHgTe cadmium mercury telluride
  • ZnSe zinc selenide
  • ZnSSe zinc sulfur selenide
  • substrate 22 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry.
  • Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate.
  • amorphous intermediate layer 28 is grown on substrate 22 at the interface between substrate 22 and the growing accommodating buffer layer by the oxidation of substrate 22 during the growth of layer 24. The amorphous intermediate layer serves to relieve strain that might otherwise occur in the monocrystalline accommodating buffer layer as a result of differences in the lattice constants of the substrate and the buffer layer.
  • lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by the amorphous intermediate layer, the strain may cause defects in the crystalline structure of the accommodating buffer layer. Defects in the crystalline structure of the accommodating buffer layer, in turn, would make it difficult to achieve a high quality crystalline structure in monocrystalline metallic oxide layer 26.
  • Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying substrate and with the overlying metallic oxide material.
  • the material could be an oxide or nitride having a lattice structure matched to the substrate and to the subsequently applied metallic oxide material .
  • Materials that are suitable for the accommodating buffer layer include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for the accommodating buffer layer.
  • metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates
  • these materials are insulators, although strontium ruthenate, for example, is a conductor.
  • these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements. In some specific applications, the metal oxides or nitride may include three or more different metallic elements.
  • Amorphous interface layer 28 is preferably an oxide formed by the oxidation of the surface of substrate 22, and more preferably is composed of a silicon oxide.
  • the thickness of layer 28 is sufficient to relieve strain attributed to mismatches between the lattice constants of substrate 22 and accommodating buffer layer 24.
  • layer 28 has a thickness in the range of approximately 0.5-5 run.
  • the metallic oxide material of layer 26 can be selected, as desired for a particular structure or application.
  • layer 26 can include a metallic oxide material having a desired property such as a material which exhibits piezoelectric, pyroelectric, ferromagnetic, colossal magneto resistive, or super conductive characteristics.
  • Such materials include monoclinic, tetragonal, cubic, or perovskite metallic oxide structures with the a general chemical formula AB0 3 where A is selected from the group consisting of lead, lanthanum, niobium, scandium, and combinations thereof, and B is selected from the group consisting of zirconium, titanium, and combinations thereof:
  • (Pb,La,Na,Sc) (Zr,Ti)0 3 e.g., PbZrTi0 3 , PbNbZrTi0 3 , PbScZrTi0 3 , PbSrNbZrTi0 3 , PbLiZrTiO., PbTi0 3 ; ABO.
  • A is selected from the group consisting of strontium, barium, calcium, and combinations thereof and B is selected from the group consisting of zirconium, hafnium, titanium, and combinations thereof: (Sr,Ba, Ca) (Zr, Hf , i) 0 3 , e.g., SrTiO., BaTi0 3 , BaSrTi0 3 , CaTi0 3 , BaZr0 3 ; ACoO- where A is selected from the group consisting of lanthanum, strontium, barium, zirconium, and combinations thereof: (La,Sr,Ba, Zr)Co0 3 , e.g., LaSrCo0 3 , LaZrCo0 3 ; ABMnO.
  • A is a rare earth element (e.g., lanthanum) and B is an alkali earth metal element (e.g., calcium, barium, or strontium): (La, Sr, Ba, Ca)Mh0 3 , e.g., LaSrMn0 3 , LaCaMhO.; ABa 2 Cu 3 O n where A is selected from the group consisting of yttrium, praseodymium, and combinations thereof and n is 7 or 8: (Y, Pr)Ba 2 Cu 3 0 7 _ 8 , e.g., YBa 2 Cu 3 0, YPrBa 2 Cu 3 0; ARu0 3 where A is selected from the group consisting of strontium, barium, and combinations thereof: (Sr, Ba) Ru0 3 ; PbA0 3 where A is selected from the group consisting of magnesium, niobium, and combinations thereof :
  • Alkali earth metal element e.g., calcium, barium,
  • template layer 30 has a thickness ranging from about one to about ten onolayers .
  • FIG. 2 illustrates, in cross section, a portion of a microelectronic structure 40 in accordance with a further embodiment of the invention.
  • Structure 40 is similar to the previously described structure 20, except that an additional buffer layer 32 is positioned between accommodating buffer layer 24 and layer of monocrystalline metallic oxide material 26.
  • the additional buffer layer is positioned between optional template layer 30 (or layer 24 if no template layer exists) and the overlying layer of moncrystalline metallic oxide material.
  • the additional buffer layer formed of a monocrystalline oxide material, serves to provide a lattice compensation when the lattice constant of the accommodating buffer layer cannot be adequately matched to the overlying metallic oxide material layer.
  • FIG. 3 schematically illustrates, in cross section, a portion of a microelectronic structure 34 in accordance with another exemplary embodiment of the invention.
  • Structure 34 is similar to structure 20, except that structure 34 includes an amorphous layer 36, rather than accommodating buffer layer 24 and amorphous interface layer 28, and an additional metallic oxide layer 38.
  • amorphous layer 36 may be formed by first forming an accommodating buffer layer and an amorphous interface layer in a similar manner to that described above. Monocrystalline metallic oxide layer 38 is then formed (by epitaxial growth) overlying the monocrystalline accommodating buffer layer. The accommodating buffer layer is then exposed to an anneal process to convert the monocrystalline accommodating buffer layer to an amorphous layer.
  • Amorphous layer 36 formed in this manner comprises materials from both the accommodating buffer and interface layers, which amorphous layers may or may not amalgamate. Thus, layer 36 may comprise one or two amorphous layers.
  • amorphous layer 36 between substrate 22 and metallic oxide layer 38 relieves stresses between layers 22 and 38 and provides a true compliant substrate for subsequent processing--e.g. , metallic oxide layer 26 formation.
  • the processes previously described above in connection with FIGS. 1 and 2 are adequate for growing monocrystalline metallic oxide layers over a monocrystalline substrate.
  • the process described in connection with FIG. 3, which includes transforming a monocrystalline accommodating buffer layer to an amorphous oxide layer may be better for growing monocrystalline metallic oxide layers because it allows any strain in layer 38 to relax prior to forming layer 26.
  • Metallic oxide layer 38 may include any of the materials described throughout this application in connection with either of metallic oxide layer 26 or additional buffer layer 32.
  • layer 38 may include the perovskite metallic oxides listed above as materials suitable for layer 26.
  • layer 38 serves as an anneal cap during layer 36 formation and as a template for subsequent metallic oxide layer 26 formation. Accordingly, layer 38 is preferably thick enough to provide a suitable template for layer 26 growth (at least one monolayer) and thin enough to allow layer 38 to form as a substantially defect free monocrystalline metallic oxide (often less than about ten monolayers) .
  • monocrystalline metallic oxide layer 38 comprises a metallic oxide material (e.g., a material discussed above in connection with layer 26) that is thick enough to use a film for a desired microelectronic device.
  • a microelectronic structure in accordance with the present invention does not include layer 26.
  • the microelectronic structure in accordance with this embodiment only includes one metallic oxide layer disposed above amorphous oxide layer 36.
  • monocrystalline substrate 22 is a silicon substrate oriented in the (100) direction.
  • the silicon substrate can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 200- 300 mm.
  • accommodating buffer layer 24 is a monocrystalline layer of Sr.Ba 1.z Ti0 3 where z ranges from 0 to 1 and the amorphous intermediate layer is a layer of silicon oxide (SiO x ) formed at the interface between the silicon substrate and the accommodating buffer layer. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of the subsequently formed layer 26.
  • the accommodating buffer layer can have a thickness of about 2 to about 100 nanometers (run) and preferably has a thickness of about 10 nm. In general, it is desired to have an accommodating buffer layer thick enough to isolate the metallic oxide layer from the substrate to obtain the desired properties. Layers thicker than 100 nm usually provide little additional benefit while increasing cost unnecessarily; however, thicker layers may be fabricated if needed.
  • the amorphous intermediate layer of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1.5-2.5 nm.
  • metallic oxide material layer 26 is a layer of strontium ruthenate (SrRu0 3 ) having a thickness of about 5 to about 500 nm and preferably a thickness of about 10 to about 100 nm. The thickness generally depends on the application for which the layer is being prepared.
  • SrRu0 3 strontium ruthenate
  • a structure is provided that is suitable for the growth of an epitaxial film of (Pb, La,Nb, Sc) (Zr,Ti)0 3 film overlying a silicon substrate.
  • the substrate is preferably a silicon wafer as described above.
  • a suitable accommodating buffer layer material is Sr x Ba._ x Ti0 3 , where x ranges from 0 to 1, having a thickness of about 2-100 nm and preferably a thickness of about 5-15 nm.
  • the metallic oxide material can be, for example PbZrTi0 3 , having a thickness of about 50 nm to about 500 nm.
  • substrate 22 is a monocrystalline substrate such as a monocrystalline silicon or gallium arsenide substrate.
  • the crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation.
  • accommodating buffer layer 24 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation.
  • the lattice constants of the accommodating buffer layer and the monocrystalline substrate must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved.
  • the terms "substantially equal” and “substantially matched” mean that there is sufficient similarity between the lattice constants to permit the growth of a high quality crystalline layer on the underlying layer .
  • FIG. 4' graphically illustrates the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal.
  • Curve 42 illustrates the boundary of high crystalline quality material. The area to the right of curve 42 represents layers that tend to be polycrystalline. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly. As a reference point, for example, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm cannot be achieved.
  • substrate 22 is a (100) or (111) oriented monocrystalline silicon wafer and accommodating buffer layer 24 is a layer of strontium barium titanate.
  • Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material by 45° with respect to the crystal orientation of the silicon substrate wafer.
  • the inclusion in the structure of amorphous interface layer 28, a silicon oxide layer in this example, if it is of sufficient thickness, serves to reduce strain in the titanate monocrystalline layer that might result from any mismatch in the lattice constants of the host silicon wafer and the grown titanate layer.
  • a high quality, thick, monocrystalline titanate layer is achievable.
  • layer 26 is a layer of epitaxially grown metallic oxide material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation.
  • the lattice constant of layer 26 differs from the lattice constant of substrate 22.
  • the accommodating buffer layer must be of high crystalline quality.
  • substantial matching between the crystal lattice constant of the host crystal, in this case, the monocrystalline accommodating buffer layer, and the grown crystal is desired.
  • a crystalline buffer layer between the host oxide and the grown metallic oxide layer can be used to reduce strain in the grown monocrystalline metallic oxide layer that might result from small differences in lattice constants. Better crystalline quality in the grown monocrystalline metallic oxide layer can thereby be achieved.
  • the following example illustrates a process, in accordance with one embodiment of the invention, for fabricating a microelectronic structure such as the structures depicted in FIGS. 1 - 3.
  • the process starts by providing a monocrystalline semiconductor substrate comprising silicon or germanium.
  • the semiconductor substrate is a silicon wafer having a (100) orientation.
  • the substrate is preferably oriented on axis or, at most, about 0.5° off axis.
  • At least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures.
  • the term "bare" in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material.
  • bare silicon is highly reactive and readily forms a native oxide.
  • the term "bare" is intended to encompass such a native oxide.
  • a thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process in accordance with the invention.
  • the native oxide layer In order to epitaxially grow a monocrystalline oxide layer overlying the monocrystalline substrate, the native oxide layer must first be removed to expose the crystalline structure of the underlying substrate. The following process is preferably carried out by molecular beam epitaxy (MBE) , although other epitaxial processes may also be used in accordance with the present invention.
  • MBE molecular beam epitaxy
  • the native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus.
  • strontium the substrate is then heated to a temperature of about 750° C to cause the strontium to react with the native silicon oxide layer.
  • the strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface.
  • the resultant surface which exhibits an ordered 2x1 structure, includes strontium, oxygen, and silicon.
  • the ordered 2x1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide.
  • the template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer .
  • the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkali earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750°C. At this temperature, a solid state reaction takes place between the strontium oxide and the native silicon oxide, causing the reduction of the native silicon oxide and leaving an ordered 2x1 structure with strontium, oxygen, and silicon remaining on the substrate surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer.
  • an alkali earth metal oxide such as strontium oxide, strontium barium oxide, or barium oxide
  • the substrate is cooled to a temperature in the range of about 200-800°C and a layer of strontium titanate is grown on the template layer by molecular beam epitaxy.
  • the MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources.
  • the ratio of strontium and titanium is approximately 1:1.
  • the partial pressure of oxygen is initially set at a minimum value to grow stochiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value.
  • the overpressure of oxygen causes the growth of an amorphous silicon oxide layer at the interface between the underlying substrate and the growing strontium titanate layer.
  • the growth of the silicon oxide layer results from the diffusion of oxygen through the growing strontium titanate layer to the interface where the oxygen reacts with silicon at the surface of the underlying substrate.
  • the strontium titanate grows as an ordered monocrystal with the crystalline orientation rotated by 45° with respect to the ordered 2x1 crystalline structure of the underlying substrate. Strain that otherwise might exist in the strontium titanate layer because of the small mismatch in lattice constant between the silicon substrate and the growing crystal is relieved in the amorphous silicon oxide intermediate layer.
  • the monocrystalline strontium titanate may be capped by a template layer that is conducive to the subsequent growth of an epitaxial layer of a desired metallic oxide material.
  • the MBE growth of the strontium titanate monocrystalline layer can be capped by terminating the growth with 1-2 monolayers of titanium, 1-2 monolayers of titanium-oxygen or with 1-2 monolayers of strontium-oxygen.
  • the metallic oxide material is grown using MBE or other suitable techniques .
  • the structure illustrated in FIG. 2 can be formed by the process discussed above with the addition of an additional buffer layer deposition step.
  • the buffer layer is formed overlying the template or accommodating buffer layer before the deposition of the monocrystalline metallic oxide layer. If the buffer layer is an oxide superlattice, such a superlattice can be deposited, by MBE for example, on the template described above.
  • Structure 34 may be formed by growing an accommodating buffer layer, forming an amorphous oxide layer over substrate 22, and growing metallic oxide layer 38 over the accommodating buffer layer, as described above.
  • the accommodating buffer layer and the amorphous oxide layer are then exposed to an anneal process sufficient to change the crystalline structure of the accommodating buffer layer from monocrystalline to amorphous, thereby forming an amorphous layer such that the combination of the amorphous oxide layer and the now amorphous accommodating buffer layer form a single amorphous oxide layer 36.
  • Layer 26 is then subsequently grown over layer 38.
  • the anneal process may be carried out subsequent to growth of layer 26.
  • layer 36 is formed by exposing substrate 22, the accommodating buffer layer, the amorphous oxide layer, and layer 38 to a rapid thermal anneal process with a peak temperature of about 700°C to about 1000°C and a process time of about 10 seconds to about 10 minutes.
  • suitable anneal processes may be employed to convert the accommodating buffer layer to an amorphous layer in accordance with the present invention.
  • laser annealing or "conventional" thermal annealing processes may be used to form layer 36.
  • an overpressure of one or more constituents of layer 30 may be required to prevent degradation of layer 38 during the anneal process.
  • layer 38 of structure 34 may include any materials suitable for either of layers 32 or 26.
  • any deposition or growth methods described in connection with either layer 32 or 26 may be employed to deposit layer 38.
  • the process described above illustrates a process for forming a semiconductor structure including a silicon substrate, an overlying oxide layer, and a monocrystalline metallic oxide layer by the process of molecular beam epitaxy.
  • the process can also be carried out by the process of chemical vapor deposition (CVD) , metal organic chemical vapor deposition (MOCVD) , migration enhanced epitaxy (MEE) , atomic layer epitaxy (ALE) , physical vapor deposition (PVD) , chemical solution deposition (CSD) , pulsed laser deposition (PLD) , or the like.
  • CVD chemical vapor deposition
  • MOCVD metal organic chemical vapor deposition
  • MEE migration enhanced epitaxy
  • ALE atomic layer epitaxy
  • PVD physical vapor deposition
  • CSSD chemical solution deposition
  • PLD pulsed laser deposition
  • other monocrystalline accommodating buffer layers such as alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates, peroskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown.
  • other metallic oxide layers can be deposited overlying the monocrystalline oxide accommodating buffer layer.
  • the metallic oxide may be grown via PLD, by ablating a target of the desired material with an eximer laser and heating the substrate to a temperature of about 300 °C to about 500 °C
  • Each of the variations of metallic oxide materials and monocrystalline oxide accommodating buffer layer may use an appropriate template for initiating the growth of the respective layer.
  • suitable template materials may be grown according to the methods described above in connection with growing layer 26.

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Abstract

Des couches d'oxyde métallique épitaxiales de haute qualité peuvent être tirées sous recouvrement de grandes plaquettes de silicium en tirant tout d'abord une couche tampon d'adaptation sur une plaquette en silicium. La couche tampon d'adaptation est une couche d'oxyde monocristallin, espacée de la plaquette en silicium par une couche d'interface amorphe d'oxyde de silicium. La couche d'interface amorphe dissipe les contraintes et permet le tirage d'une couche tampon d'adaptation en oxyde monocristallin de haute qualité. La couche d'interface amorphe prend en ligne de compte tout manque de concordance entre la couche tampon d'adaptation et le substrat en silicium sous-jacent.
PCT/US2001/022679 2000-07-24 2001-07-19 Structure d'oxyde metallique en film mince et son procede de fabrication WO2002009159A2 (fr)

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AU2001276989A AU2001276989A1 (en) 2000-07-24 2001-07-19 Thin-film metallic oxide structure and process for fabricating same

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US7072093B2 (en) 2003-04-30 2006-07-04 Hewlett-Packard Development Company, L.P. Optical interference pixel display with charge control
CN100359648C (zh) * 2002-05-03 2008-01-02 飞思卡尔半导体公司 其上具有半导体器件的单晶氧化物的生长方法
JP2008120100A (ja) * 2008-02-12 2008-05-29 Seiko Epson Corp ヘッドの製造方法及びプリンタの製造方法
CN101913860A (zh) * 2010-08-19 2010-12-15 西北工业大学 一种钛酸铋基高居里温度压电陶瓷及其制备方法
JP2012151174A (ja) * 2011-01-17 2012-08-09 Ricoh Co Ltd 電界効果型トランジスタ、表示素子、画像表示装置、及びシステム
CN115418718A (zh) * 2022-09-07 2022-12-02 武汉大学 基于二维尖晶石型铁氧体薄膜的产品及其制备方法和应用

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US10697090B2 (en) * 2017-06-23 2020-06-30 Panasonic Intellectual Property Management Co., Ltd. Thin-film structural body and method for fabricating thereof
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US7072093B2 (en) 2003-04-30 2006-07-04 Hewlett-Packard Development Company, L.P. Optical interference pixel display with charge control
DE102004058958A1 (de) * 2004-12-08 2006-06-14 Forschungszentrum Jülich GmbH Material mit hoher Bandlücke und Dielektrizitätskonstante
DE102004058958B4 (de) * 2004-12-08 2006-10-26 Forschungszentrum Jülich GmbH Halbleiter-Bauelement aus einem Material mit hoher Bandlücke und Dielektrizitätskonstante
JP2008120100A (ja) * 2008-02-12 2008-05-29 Seiko Epson Corp ヘッドの製造方法及びプリンタの製造方法
CN101913860A (zh) * 2010-08-19 2010-12-15 西北工业大学 一种钛酸铋基高居里温度压电陶瓷及其制备方法
CN101913860B (zh) * 2010-08-19 2012-11-21 西北工业大学 一种钛酸铋基高居里温度压电陶瓷及其制备方法
JP2012151174A (ja) * 2011-01-17 2012-08-09 Ricoh Co Ltd 電界効果型トランジスタ、表示素子、画像表示装置、及びシステム
CN115418718A (zh) * 2022-09-07 2022-12-02 武汉大学 基于二维尖晶石型铁氧体薄膜的产品及其制备方法和应用

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