+

WO2002003420A2 - Architectures de radio a circuit integre - Google Patents

Architectures de radio a circuit integre Download PDF

Info

Publication number
WO2002003420A2
WO2002003420A2 PCT/US2001/016730 US0116730W WO0203420A2 WO 2002003420 A2 WO2002003420 A2 WO 2002003420A2 US 0116730 W US0116730 W US 0116730W WO 0203420 A2 WO0203420 A2 WO 0203420A2
Authority
WO
WIPO (PCT)
Prior art keywords
layer
circuit
monocrystalline
semiconductor
radio
Prior art date
Application number
PCT/US2001/016730
Other languages
English (en)
Other versions
WO2002003420A3 (fr
Inventor
Thomas A. Freeburg
Gary W. Grube
Original Assignee
Motorola, Inc., A Corporation Of The State Of Delaware
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola, Inc., A Corporation Of The State Of Delaware filed Critical Motorola, Inc., A Corporation Of The State Of Delaware
Priority to AU2001263398A priority Critical patent/AU2001263398A1/en
Publication of WO2002003420A2 publication Critical patent/WO2002003420A2/fr
Publication of WO2002003420A3 publication Critical patent/WO2002003420A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/08—Manufacture or treatment characterised by using material-based technologies using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies

Definitions

  • This invention relates generally to radio architectures and to methods for their fabrication. More specifically, this invention relates to improved radio architectures in which multiple radio integrated circuit functions are combined into a reduced number of integrated circuits having both monocrystalline silicon substrates and compound semiconductor materials .
  • GaAs gallium arsenide
  • Radio architectures in particular typically include a relatively standard set of circuits which often include silicon-based circuits and GaAs-based circuits.
  • most radio architectures include an RF receiver amplifier, audio circuitry, processing circuitry, transmitter driver circuitry and a transmitting amplifier, as well as other circuits.
  • the semiconductor substrate of the integrated circuit is typically either silicon or GaAs. While GaAs often provides better performance than silicon, it is more expensive than silicon, and can be more difficult to manufacture. In view of the added expense, the choice to use GaAs is often made because the operational parameters of the circuit favor GaAs.
  • there often are several different integrated circuits some of which are silicon-based, and some of which are GaAs-based.
  • Another problem with these devices is that, even though a majority of the weight of the device is the battery, the battery life is often too short. Thus, it would be desirable to reduce the power requirements of the device so that battery life can be extended without increasing the size and weight of the batteries. Also related to the weight gains associated with the combination of multiple functions within a single device extra weight associated with duplicate components. This often occurs because it may be easier to simply relocate a functional set of integrated circuits to another device to combine the devices, rather than actually integrating the functionality of the circuits to reduce the number of components. Another reason that these portable electronic devices include duplicate components is that they may operate in multiple bands, which may require different integrated circuits.
  • a still further consideration is the ever increasing desire for smaller, and smaller devices, such as "wearable” devices that may, for example, be attached to a pair of glasses.
  • wearable devices such as "wearable” devices that may, for example, be attached to a pair of glasses.
  • power considerations continue to increase. Devices need to operate over extended periods of time with little to no power drain.
  • FIGs. 1, 2, 3, 9, 10 illustrate schematically, in cross section, device structures that can be used in accordance with various embodiments of the invention.
  • FIG. 4 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer.
  • FIG. 5 is a high resolution Transmission Electron Micrograph (TEM) of illustrative semiconductor material manufactured in accordance with what is shown herein.
  • TEM Transmission Electron Micrograph
  • FIG. 6 is an x-ray diffraction taken on an illustrative semiconductor structure manufactured in accordance with what is shown herein.
  • FIG. 7 illustrates a high resolution Transmission Electron Micrograph of a structure including an amorphous oxide layer.
  • FIG. 8 illustrates an x-ray diffraction spectrum of a structure including an amorphous oxide layer.
  • FIGs. 11-15 include illustrations of cross- sectional views of a portion of an integrated circuit that includes a compound semiconductor portion, a bipolar portion, and an MOS portion in accordance with what is shown herein.
  • FIGs. 16-22 include illustrations of cross- sectional views of a portion of another integrated circuit that includes a semiconductor laser and a MOS transistor in accordance with what is shown herein.
  • FIG. 18 is a schematic diagram of a conventional two-way radio.
  • FIG. 19 is a schematic diagram of a two-way radio constructed in accordance with the principles of the present invention.
  • FIG. 20 is an illustrative top-view of the integrated circuit radio of FIG. 19.
  • FIG. 21 is an illustrative cross-sectional view of the integrated circuit radio of FIG. 19. Skilled artisans will appreciate that in many cases elements in certain FIGs. are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in certain FIGs. may be exaggerated relative to other elements to help to improve understanding of what is being shown.
  • the present invention involves semiconductor structures of particular types.
  • these semiconductor structures are sometimes referred to as "composite semiconductor structures" or “composite integrated circuits” because they include two (or more) significantly different types of semiconductor devices in one integrated structure or circuit.
  • one of these two types of devices may be silicon-based devices such as CMOS devices, and the other of these two types of devices may be compound semiconductor devices such GaAs devices.
  • Illustrative composite semiconductor structures and methods for making such structures are disclosed in Ramdani et al .
  • FIG. 1 illustrates schematically, in cross section, a portion of a semiconductor structure 20 which may be relevant to or useful in connection with certain embodiments of the present invention.
  • Semiconductor structure 20 includes a monocrystalline substrate 22, accommodating buffer layer 24 comprising a monocrystalline material, and a layer 26 of a monocrystalline compound semiconductor material.
  • monocrystalline shall have the meaning commonly used within the semiconductor industry.
  • the term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry.
  • structure 20 also includes an amorphous intermediate layer 28 positioned between substrate 22 and accommodating buffer layer 24.
  • Structure 20 may also include a template layer 30 between accommodating buffer layer 24 and compound semiconductor layer 26.
  • template layer 30 helps to initiate the growth of compound semiconductor layer 26 on accommodating buffer layer 24.
  • Amorphous intermediate layer 28 helps to relieve the strain in accommodating buffer layer 24 and by doing so, aids in the growth of a high crystalline quality accommodating buffer layer 24.
  • Substrate 22 in accordance with one embodiment, is a monocrystalline semiconductor wafer, preferably of large diameter.
  • the wafer can be of a material from Group IV of the periodic table, and preferably a material from Group IVA.
  • Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like.
  • substrate 22 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry.
  • Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate 22.
  • amorphous intermediate layer 28 is grown on substrate 22 at the interface between substrate 22 and the growing accommodating buffer layer 24 by the oxidation of substrate 22 during the growth of layer 24.
  • Amorphous intermediate layer 28 serves to relieve strain that might otherwise occur in monocrystalline accommodating buffer layer 24 as a result of differences in the lattice constants of substrate 22 and buffer layer 24.
  • lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by amorphous intermediate layer 28, the strain may cause defects in the crystalline structure of accommodating buffer layer 24.
  • Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with underlying substrate 22 and with overlying compound semiconductor material 26.
  • the material could be an oxide or nitride having a lattice structure matched to substrate 22 and to the subsequently applied semiconductor material 26.
  • Materials that are suitable for accommodating buffer layer 24 include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for accommodating buffer layer 24.
  • metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates
  • these materials are insulators, although strontium ruthenate, for example, is a conductor.
  • these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements. In some specific applications, the metal oxides or nitride may include three or more different metallic elements.
  • Amorphous interface layer 28 is preferably an oxide formed by the oxidation of the surface of substrate 22, and more preferably is composed of a silicon oxide.
  • the thickness of layer 28 is sufficient to relieve strain attributed to mismatches between the lattice constants of substrate 22 and accommodating buffer layer 24.
  • layer 28 has a thickness in the range of approximately 0.5-5 nm.
  • the compound semiconductor material of layer 26 can be selected, as needed for a particular semiconductor structure, from any of the Group IIIA and VA elements (III-V semiconductor compounds) , mixed III- V compounds, Group II (A or B) and VIA elements (II-VI semiconductor compounds), and mixed II-VI compounds.
  • Examples include gallium arsenide (GaAs) , gallium indium arsenide (GalnAs) , gallium aluminum arsenide (GaAlAs) , indium phosphide (InP), cadmium sulfide (CdS) , cadmium mercury telluride (CdHgTe) , zinc selenide (ZnSe) , zinc sulfur selenide (ZnSSe), and the like.
  • Suitable template 30 materials chemically bond to the surface of the accommodating buffer layer 24 at selected sites and provide sites for the nucleation of the epitaxial growth of the subsequent compound semiconductor layer 26. Appropriate materials for template 30 are discussed below.
  • FIG. 2 illustrates, in cross section, a portion of a semiconductor structure 40 in accordance with a further embodiment.
  • Structure 40 is similar to the previously described semiconductor structure 20 except that an additional buffer layer 32 is positioned between accommodating buffer layer 24 and layer of monocrystalline compound semiconductor material 26.
  • additional buffer layer 32 is positioned between the template layer 30 and the overlying layer 26 of compound semiconductor material.
  • Additional buffer layer 32 formed of a semiconductor or compound semiconductor material, serves to provide a lattice compensation when the lattice constant of accommodating buffer layer 24 cannot be adequately matched to the overlying monocrystalline compound semiconductor material layer 26.
  • FIG. 3 schematically illustrates, in cross section, a portion of a semiconductor structure 34 in accordance with another exemplary embodiment of the invention.
  • Structure 34 is similar to structure 20, except that structure 34 includes an amorphous layer 36, rather than accommodating buffer layer 24 and amorphous interface layer 28, and an additional semiconductor layer 38.
  • amorphous layer 36 may be formed by first forming an accommodating buffer layer and an amorphous interface layer in a similar manner to that described above. Monocrystalline semiconductor layer 26 is then formed (by epitaxial growth) overlying the monocrystalline accommodating buffer layer. The accommodating buffer layer is then exposed to an anneal process to convert the monocrystalline accommodating buffer layer to an amorphous layer. Amorphous layer 36 formed in this manner comprises materials from both the accommodating buffer and interface layers, which amorphous layers may or may not amalgamate. Thus, layer 36 may comprise one or two amorphous layers . Formation of amorphous layer 36 between substrate 22 and semiconductor layer 38 (subsequent to layer 38 formation) relieves stresses between layers 22 and 38 and provides a true compliant substrate for subsequent processing--e. g. , compound semiconductor layer 26 formation.
  • semiconductor layer 38 may include any of the materials described throughout this application in connection with either of compound semiconductor material layer 26 or additional buffer layer 32.
  • layer 38 may include monocrystalline Group IV or monocrystalline compound semiconductor materials.
  • semiconductor layer 38 serves as an anneal cap during layer 36 formation and as a template for subsequent semiconductor layer 26 formation. Accordingly, layer 38 is preferably thick enough to provide a suitable template for layer 26 growth (at least one monolayer) and thin enough to allow layer 38 to form as a substantially defect free monocrystalline semiconductor compound.
  • semiconductor layer 38 comprises compound semiconductor material (e.g., a material discussed above in connection with compound semiconductor layer 26) that is thick enough to form devices within layer 38.
  • compound semiconductor material e.g., a material discussed above in connection with compound semiconductor layer 26
  • a semiconductor structure in accordance with the present invention does not include compound semiconductor layer 26.
  • the semiconductor structure in accordance with this embodiment only includes one compound semiconductor layer disposed above amorphous oxide layer 36.
  • monocrystalline substrate 22 is a silicon substrate oriented in the (100) direction.
  • Silicon substrate 22 can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 200-300 mm.
  • accommodating buffer layer 24 is a monocrystalline layer of Sr 2 Ba ⁇ - z Ti0 3 where z ranges from 0 to 1 and amorphous intermediate layer 28 is a layer of silicon oxide (SiO x ) formed at the interface between silicon substrate 22 and accommodating buffer layer 24. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of the subsequently formed layer 26.
  • Accommodating buffer layer 24 can have a thickness of about 2 to about 100 nanometers (nm) and preferably has a thickness of about 10 nm. In general, it is desired to have an accommodating buffer layer 24 thick enough to isolate compound semiconductor layer 26 from substrate 22 to obtain the desired electrical and optical properties. Layers thicker than 100 nm usually provide little additional benefit while increasing cost unnecessarily; however, thicker layers may be fabricated if needed.
  • the amorphous intermediate layer 28 of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1.5-2.5 nm.
  • compound semiconductor material layer 26 is a layer of gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs) having a thickness of about 1 nm to about 100 micrometers ( ⁇ m) and preferably a thickness of about 0.5 ⁇ m to 10 ⁇ m. The thickness generally depends on the application for which the layer is being prepared.
  • a template layer 30 is formed by capping the oxide layer. Template layer 30 is preferably 1-10 monolayers of Ti-As, Sr-O-As, Sr-Ga-O, or Sr-Al-O. By way of a preferred example, 1-2 monolayers 30 of Ti-As or Sr-Ga-O have been shown to successfully grow GaAs layers 26.
  • monocrystalline substrate 22 is a silicon substrate as described above.
  • Accommodating buffer layer 24 is a monocrystalline oxide of strontium or barium zirconate or hafnate in a cubic or orthorhombic phase with an amorphous intermediate layer 28 of silicon oxide formed at the interface between silicon substrate 22 and accommodating buffer layer 24.
  • Accommodating buffer layer 24 can have a thickness of about 2-100 nm and preferably has a thickness of at least 5 nm to ensure adequate crystalline and surface quality and is formed of a monocrystalline SrZr0 3 , BaZr0 3 , SrHf0 3 , BaSn0 3 or BaHf0 3 .
  • a monocrystalline oxide layer of BaZr0 3 can grow at a temperature of about 700 degrees C.
  • the lattice structure of the resulting crystalline oxide exhibits a 45 degree rotation with respect to the substrate 22 silicon lattice structure.
  • An accommodating buffer layer 24 formed of these zirconate or hafnate materials is suitable for the growth of compound semiconductor materials 26 in the indium phosphide (InP) system.
  • the compound semiconductor material 26 can be, for example, indium phosphide (InP), indium gallium- arsenide (InGaAs), aluminum indium arsenide, (AlInAs) , or aluminum gallium indium arsenic phosphide (AlGalnAsP) , having a thickness of about 1.0 nm to 10 ⁇ m.
  • a suitable template 30 for this structure is 1-10 monolayers of zirconium-arsenic (Zr-As), zirconium-phosphorus (Zr-P) , hafnium-arsenic (Hf-As) , hafnium-phosphorus (Hf-P) , strontium-oxygen-arsenic (Sr-O-As), strontium-oxygen- phosphorus (Sr-O-P) , barium-oxygen-arsenic (Ba-O-As) , indium-strontium-oxygen (In-Sr-O) , or barium-oxygen- phosphorus (Ba-O-P) , and preferably 1-2 monolayers of one of these materials.
  • the surface is terminated with 1-2 monolayers of zirconium followed by deposition of 1-2 monolayers of arsenic to form a Zr-As template 30.
  • a monocrystalline layer 26 of the compound semiconductor material from the indium phosphide system is then grown on template layer 30.
  • the resulting lattice structure of the compound semiconductor material 26 exhibits a 45 degree rotation with respect to the accommodating buffer layer 24 lattice structure and a lattice mismatch to (100) InP of less than 2.5%, and preferably less than about 1.0%
  • a structure is provided that is suitable for the growth of an epitaxial film of a II-VI material overlying a silicon substrate 22.
  • the substrate 22 is preferably a silicon wafer as described above.
  • a suitable accommodating buffer layer 24 material is Sr x Ba ⁇ - x Ti0 3 , where x ranges from 0 to 1, having a thickness of about 2-100 nm and preferably a thickness of about 5-15 nm.
  • the II-VI compound semiconductor material 26 can be, for example, zinc selenide (ZnSe) or zinc sulfur selenide (ZnSSe) .
  • a suitable template 30 for this material system includes 1-10 monolayers of zinc-oxygen (Zn-O) followed by 1-2 monolayers of an excess of zinc followed by the selenidation of zinc on the surface.
  • a template 30 can be, for example, 1-10 monolayers of strontium-sulfur (Sr-S) followed by the ZnSeS.
  • This embodiment of the invention is an example of structure 40 illustrated in FIG. 2.
  • Substrate 22, monocrystalline oxide layer 24, and monocrystalline compound semiconductor material layer 26 can be similar to those described in example 1.
  • an additional buffer layer 32 serves to alleviate any strains that might result from a mismatch of the crystal lattice of the accommodating buffer layer and the lattice of the monocrystalline semiconductor material.
  • Buffer layer 32 can be a layer of germanium or a GaAs, an aluminum gallium arsenide (AlGaAs), an indium gallium phosphide (InGaP) , an aluminum gallium phosphide (AlGaP) , an indium gallium arsenide (InGaAs) , an aluminum indium phosphide (AllnP) , a gallium arsenide phosphide (GaAsP) , or an indium gallium phosphide (InGaP) strain compensated superlattice.
  • AlGaAs aluminum gallium arsenide
  • InGaP aluminum gallium phosphide
  • AlGaP aluminum indium phosphide
  • AllnP aluminum indium phosphide
  • GaAsP gallium arsenide phosphide
  • InGaP indium gallium phosphide
  • buffer layer 32 includes a GaAs x P ⁇ - x superlattice, wherein the value of x ranges from 0 to 1.
  • buffer layer 32 includes an In y Ga ⁇ _ y P superlattice, wherein the value of y ranges from 0 to 1.
  • compositions of other materials may also be similarly varied to manipulate the lattice constant of layer 32 in a like manner.
  • the superlattice can have a thickness of about 50-500 nm and preferably has a thickness of about 100-200 nm.
  • the template for this structure can be the same of that described in example 1.
  • buffer layer 32 can be a layer of monocrystalline germanium having a thickness of 1-50 nm and preferably having a thickness of about 2-20 nm.
  • a template layer of either germanium-strontium (Ge-Sr) or germanium- titanium (Ge-Ti) having a thickness of about one monolayer can be used as a nucleating site for the subsequent growth of the monocrystalline compound semiconductor material layer.
  • the formation of the oxide layer is capped with either a monolayer of strontium or a monolayer of titanium to act as a nucleating site for the subsequent deposition of the monocrystalline germanium.
  • the monolayer of strontium or titanium provides a nucleating site to which the first monolayer of germanium can bond.
  • buffer layer 32 is inserted between accommodating buffer layer 24 and overlying monocrystalline compound semiconductor material layer 26.
  • Buffer layer 32 a further monocrystalline semiconductor material, can be, for example, a graded layer of indium gallium arsenide (InGaAs) or indium aluminum arsenide (InAlAs) .
  • buffer layer 32 includes InGaAs, in which the indium composition varies from 0 to about 47%. Buffer layer 32 preferably has a thickness of about 10-30 nm.
  • Varying the composition of buffer layer 32 from GaAs to InGaAs serves to provide a lattice match between the underlying monocrystalline oxide material 24 and the overlying layer 26 of monocrystalline compound semiconductor material.
  • Such a buffer layer 32 is especially advantageous if there is a lattice mismatch between accommodating buffer layer 24 and monocrystalline compound semiconductor material layer 26.
  • Substrate material 22, template layer 30, and monocrystalling compound semiconductor material layer 26 may be the same as those described above in connection with example 1.
  • Amorphous layer 36 is an amorphous oxide layer which is suitably formed of a combination of amorphous intermediate layer materials (e.g., layer 28 materials as described above) and accommodating buffer layer materials (e.g., layer 24 materials as described above) .
  • amorphous layer 36 may include a combination of SiOx and SrzBal-z Ti03 (where z ranges from 0 to 1), which combine or mix, at least partially, during an anneal process to form amorphous oxide layer 36.
  • amorphous layer 36 may vary from application to application and may depend on such factors as desired insulating properties of layer 36, type of semiconductor material comprising layer 26, and the like. In accordance with one exemplary aspect of the present embodiment, layer 36 thickness is about 2 nm to about 100 nm, preferably about 2-10 nm, and more preferably about 5-6 nm.
  • Layer 38 comprises a monocrystalline compound semiconductor material that can be grown epitaxially over a monocrystalline oxide material such as material used to form accommodating buffer layer 24. In accordance with one embodiment of the invention, layer 38 includes the same materials as those comprising layer 26. For example, if layer 26 includes GaAs, layer 38 also includes GaAs. However, in accordance with other embodiments of the present invention, layer 38 may include materials different from those used to form layer 26. In accordance with one exemplary embodiment of the invention, layer 38 is about 1 monolayer to about 100 nm thick.
  • substrate 22 is a monocrystalline substrate such as a monocrystalline silicon substrate.
  • the crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation.
  • accommodating buffer layer 24 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation.
  • the lattice constants of accommodating buffer layer 24 and monocrystalline substrate 22 must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved.
  • FIG. 4 illustrates graphically the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal.
  • Curve 42 illustrates the boundary of high crystalline quality material. The area to the right of curve 42 represents layers that tend to be polycrystalline. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly. As a reference point, for example, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm cannot be achieved.
  • substrate 22 is a (100) or (111) oriented monocrystalline silicon wafer and accommodating buffer layer 24 is a layer of strontium barium titanate.
  • Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material 24 by 45° with respect to the crystal orientation of the silicon substrate wafer 22.
  • the inclusion in the structure of amorphous interface layer 28, a silicon oxide layer in this example, if it is of sufficient thickness, serves to reduce strain in the titanate monocrystalline layer 24 that might result from any mismatch in the lattice constants of the host silicon wafer 22 and the grown titanate layer 24. As a result, a high quality, thick, monocrystalline titanate layer 24 is achievable. Still referring to FIGs.
  • layer 26 is a layer of epitaxially grown monocrystalline material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation.
  • the lattice constant of layer 26 differs from the lattice constant of substrate 22.
  • accommodating buffer layer 24 must be of high crystalline quality.
  • substantial matching between the crystal lattice constant of the host crystal, in this case, monocrystalline accommodating buffer layer 24, and grown crystal 26 is desired. With properly selected materials this substantial matching of lattice constants is achieved as a result of rotation of the crystal orientation of grown crystal 26 with respect to the orientation of host crystal 24.
  • grown crystal 26 is gallium arsenide, aluminum gallium arsenide, zinc selenide, or zinc sulfur selenide and accommodating buffer layer 24 is monocrystalline Sr x Ba ⁇ _ x Ti0 3 , substantial matching of crystal lattice constants of the two materials is achieved, wherein the crystal orientation of grown layer 26 is rotated by 45° with respect to the orientation of the host monocrystalline oxide 24.
  • host material 24 is a strontium or barium zirconate or a strontium or barium hafnate or barium tin oxide and compound semiconductor layer 26 is indium phosphide or gallium indium arsenide or aluminum indium arsenide
  • substantial matching of crystal lattice constants can be achieved by rotating the orientation of grown crystal layer 26 by 45° with respect to host oxide crystal 24.
  • a crystalline semiconductor buffer layer 32 between host oxide 24 and grown compound semiconductor layer 26 can be used to reduce strain in grown monocrystalline compound semiconductor layer 26 that might result from small differences in lattice constants. Better crystalline quality in grown monocrystalline compound semiconductor layer 26 can thereby be achieved.
  • the following example illustrates a process, in accordance with one embodiment, for fabricating a semiconductor structure such as the structures depicted in FIGs. 1-3.
  • the process starts by providing a monocrystalline semiconductor substrate 22 comprising silicon or germanium.
  • semiconductor substrate 22 is a silicon wafer having a (100) orientation.
  • Substrate 22 is preferably oriented on axis or, at most, about 0.5° off axis.
  • At least a portion of semiconductor substrate 22 has a bare surface, although other portions of the substrate, as described below, may encompass other structures.
  • the term "bare” in this context means that the surface in the portion of substrate 22 has been cleaned to remove any oxides, contaminants, or other foreign material.
  • bare silicon is highly reactive and readily forms a native oxide.
  • the term "bare” is intended to encompass such a native oxide .
  • a thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process.
  • the native oxide layer In order to epitaxially grow a monocrystalline oxide layer 24 overlying monocrystalline substrate 22, the native oxide layer must first be removed to expose the crystalline structure of underlying substrate 22.
  • the following process is preferably carried out by molecular beam epitaxy (MBE) , although other epitaxial processes may also be used in accordance with the present invention.
  • MBE molecular beam epitaxy
  • the native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus.
  • the substrate 22 is then heated to a temperature of about 750°C to cause the strontium to react with the native silicon oxide layer.
  • the strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface.
  • the resultant surface which exhibits an ordered 2x1 structure, includes strontium, oxygen, and silicon.
  • the ordered 2x1 structure forms a template for the ordered growth of an overlying layer 24 of a monocrystalline oxide.
  • the template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer 24.
  • the native silicon oxide can be converted and the surface of substrate 22 can be prepared for the growth of a monocrystalline oxide layer 24 by depositing an alkali earth metal oxide, such as strontium oxide or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750°C. At this temperature a solid state reaction takes place between the strontium oxide and the native silicon oxide causing the reduction of the native silicon oxide and leaving an ordered 2x1 structure with strontium, oxygen, and silicon remaining on the substrate 22 surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer 24.
  • an alkali earth metal oxide such as strontium oxide or barium oxide
  • the substrate is cooled to a temperature in the range of about 200-800°C and a layer 24 of strontium titanate is grown on the template layer by molecular beam epitaxy.
  • the MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources. The ratio of strontium and titanium is approximately 1:1.
  • the partial pressure of oxygen is initially set at a minimum value to grow stochiometric strontium titanate at a growth rate of about 0.3-0.5 n per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value.
  • the overpressure of oxygen causes the growth of an amorphous silicon oxide layer 28 at the interface between underlying substrate 22 and the growing strontium titanate layer 24.
  • the growth of silicon oxide layer 28 results from the diffusion of oxygen through the growing strontium titanate layer 24 to the interface where the oxygen reacts with silicon at the surface of underlying substrate 22.
  • the strontium titanate grows as an ordered monocrystal 24 with the crystalline orientation rotated by 45° with respect to the ordered 2x1 crystalline structure of underlying substrate 22. Strain that otherwise might exist in strontium titanate layer 24 because of the small mismatch in lattice constant between silicon substrate 22 and the growing crystal 24 is relieved in amorphous silicon oxide intermediate layer 28.
  • the monocrystalline strontium titanate is capped by a template layer 30 that is conducive to the subsequent growth of an epitaxial layer of a desired compound semiconductor material 26.
  • the MBE growth of strontium titanate monocrystalline layer 24 can be capped by terminating the growth with 1-2 ' monolayers of titanium, 1-2 monolayers of titanium-oxygen or with 1-2 monolayers of strontium-oxygen.
  • arsenic is deposited to form a Ti-As bond, a Ti-O-As bond or a Sr-O-As.
  • gallium arsenide monocrystalline layer 26 Any of these form an appropriate template 30 for deposition and formation of a gallium arsenide monocrystalline layer 26. Following the formation of template 30, gallium is subsequently introduced to the reaction with the arsenic and gallium arsenide 26 forms. Alternatively, gallium can be deposited on the capping layer to form a Sr-O-Ga bond, and arsenic is subsequently introduced with the gallium to form the GaAs.
  • FIG. 5 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with the present invention.
  • Single crystal SrTi03 accommodating buffer layer 24 was grown epitaxially on silicon substrate 22. During this growth process, amorphous interfacial layer 28 is formed which relieves strain due to lattice mismatch. GaAs compound semiconductor layer 26 was then grown epitaxially using template layer 30.
  • FIG. 6 illustrates an x-ray diffraction spectrum taken on structure including GaAs compound semiconductor layer 26 grown on silicon substrate 22 using accommodating buffer layer 24.
  • the peaks in the spectrum indicate that both the accommodating buffer layer 24 and GaAs compound semiconductor layer 26 are single crystal and (100) orientated.
  • the structure illustrated in FIG. 2 can be formed by the process discussed above with the addition of an additional buffer layer 32 deposition step.
  • Buffer layer 32 is formed overlying template layer 30 before the deposition of monocrystalline compound semiconductor layer 26. If buffer layer 32 is a ⁇ compound semiconductor superlattice, such a superlattice can be deposited, by MBE for example, on the template 30 described above. If instead buffer layer 32 is a layer of germanium, the process above is modified to cap strontium titanate monocrystalline layer 24 with a final layer of either strontium or titanium and then by depositing germanium to react with the strontium or titanium. The germanium buffer layer 32 can then be deposited directly on this template 30.
  • Structure 34 may be formed by growing an accommodating buffer layer, forming an amorphous oxide layer over substrate 22, and growing semiconductor layer 38 over the accommodating buffer layer, as described above.
  • the accommodating buffer layer and the amorphous oxide layer are then exposed to an anneal process sufficient to change the crystalline structure of the accommodating buffer layer from monocrystalline to amorphous, thereby forming an amorphous layer such that the combination of the amorphous oxide layer and the now amorphous accommodating buffer layer form a single amorphous oxide layer 36.
  • Layer 26 is then subsequently grown over layer 38.
  • the anneal process may be carried out subsequent to growth of layer 26.
  • layer 36 is formed by exposing substrate 22, the accommodating buffer layer, the amorphous oxide layer, and semiconductor layer 38 to a rapid thermal anneal process with a peak temperature of about 700°C to about 1000°C and a process time of about 1 to about 10 minutes.
  • suitable anneal processes may be employed to convert the accommodating buffer layer to an amorphous layer in accordance with the present invention.
  • laser annealing or "conventional" thermal annealing processes in the proper environment
  • an overpressure of one or more constituents of layer 30 may be required to prevent degradation of layer 38 during the anneal process.
  • the anneal environment preferably includes an overpressure of arsenic to mitigate degradation of layer 38.
  • layer 38 of structure 34 may include any materials suitable for either of layers 32 or 26. Accordingly, any deposition or growth methods described in connection with either layer 32 or 26, may be employed to deposit layer 38.
  • FIG. 7 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with the embodiment of the invention illustrated in FIG. 3.
  • TEM Transmission Electron Micrograph
  • a single crystal SrTi03 accommodating buffer layer was grown epitaxially on silicon substrate 22. During this growth process, an amorphous interfacial layer forms as described above.
  • GaAs layer 38 is formed above the accommodating buffer layer and the accommodating buffer layer is exposed to an anneal process to form amorphous oxide layer 36.
  • FIG. 8 illustrates an x-ray diffraction spectrum taken on a structure including GaAs compound semiconductor layer 38 and amorphous oxide layer 36 formed on silicon substrate 22.
  • the peaks in the spectrum indicate that GaAs compound semiconductor layer 38 is single crystal and (100) orientated and the lack of peaks around 40 to 50 degrees indicates that layer 36 is amorphous.
  • the process described above illustrates a process for forming a semiconductor structure including a silicon substrate 22, an overlying oxide layer, and a monocrystalline gallium arsenide compound semiconductor layer 26 by the process of molecular beam epitaxy.
  • the process can also be carried out by the process of chemical vapor deposition (CVD) , metal organic chemical vapor deposition (MOCVD) , migration enhanced epitaxy (MEE) , atomic layer epitaxy (ALE) , physical vapor deposition (PVD) , chemical solution deposition (CSD) , pulsed laser deposition (PLD) , or the like.
  • CVD chemical vapor deposition
  • MOCVD metal organic chemical vapor deposition
  • MEE migration enhanced epitaxy
  • ALE atomic layer epitaxy
  • PVD physical vapor deposition
  • CSSD chemical solution deposition
  • PLD pulsed laser deposition
  • monocrystalline accommodating buffer layers 24 such as alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown.
  • other III-V and II-VI monocrystalline compound semiconductor layers 26 can be deposited overlying monocrystalline oxide accommodating buffer layer 24.
  • each of the variations of compound semiconductor materials 26 and monocrystalline oxide accommodating buffer layer 24 uses an appropriate template 30 for initiating the growth of the compound semiconductor layer.
  • accommodating buffer layer 24 is an alkaline earth metal zirconate
  • the oxide can be capped by a thin layer of zirconium.
  • the deposition of zirconium can be followed by the deposition of arsenic or phosphorus to react with the zirconium as a precursor to depositing indium gallium arsenide, indium aluminum arsenide, or indium phosphide respectively.
  • monocrystalline oxide accommodating buffer layer 24 is an alkaline earth metal hafnate, the oxide layer can be capped by a thin layer of hafnium.
  • hafnium is followed by the deposition of arsenic or phosphorous to react with the hafnium as a precursor to the growth of an indium gallium arsenide, indium aluminum arsenide, or indium phosphide layer 26, respectively.
  • strontium titanate 24 can be capped with a layer of strontium or strontium and oxygen
  • barium titanate 24 can be capped with a layer of barium or barium and oxygen.
  • Each of these depositions can be followed by the deposition of arsenic or phosphorus to react with the capping material to form a template 30 for the deposition of- a compound semiconductor material layer 26 comprising indium gallium arsenide, indium aluminum arsenide, or indium phosphide.
  • FIG. 9 illustrates schematically, in cross section, a device structure 50 in accordance with a further embodiment.
  • Device structure 50 includes a monocrystalline semiconductor substrate 52, preferably a monocrystalline silicon wafer.
  • Monocrystalline semiconductor substrate 52 includes two regions, 53 and 54.
  • An electrical semiconductor component generally indicated by the dashed line 56 is formed, at least partially, in region 53.
  • Electrical component 56 can be a resistor, a capacitor, an active semiconductor component such as a diode or a transistor or an integrated circuit such as a CMOS integrated circuit.
  • electrical semiconductor component 56 can be a CMOS integrated circuit configured to perform digital signal processing or another function for which silicon integrated circuits are well suited.
  • the electrical semiconductor component in region 53 can be formed by conventional semiconductor processing as well known and widely practiced in the semiconductor industry.
  • a layer of insulating material 58 such as a layer of silicon dioxide or the like may overlie electrical semiconductor component 56.
  • Insulating material 58 and any other layers that may have been formed or deposited during the processing of semiconductor component 56 in region 53 are removed from the surface of region 54 to provide a bare silicon surface in that region.
  • bare silicon surfaces are highly reactive and a native silicon oxide layer can quickly form on the bare surface.
  • a layer of barium or barium and oxygen is deposited onto the native oxide layer on the surface of region 54 and is reacted with the oxidized surface to form a first template layer (not shown) .
  • a monocrystalline oxide layer is formed overlying the template layer by a process of molecular beam epitaxy. Reactants including barium, titanium and oxygen are deposited onto the template layer to form the monocrystalline oxide layer.
  • the partial pressure of oxygen is kept near the minimum necessary to fully react with the barium and titanium to form monocrystalline barium titanate layer.
  • the partial pressure of oxygen is then increased to provide an overpressure of oxygen and to allow oxygen to diffuse through the growing monocrystalline oxide layer.
  • the oxygen diffusing through the barium titanate reacts with silicon at the surface of region 54 to form an amorphous layer of silicon oxide on second region 54 and at the interface between silicon substrate 52 and the monocrystalline oxide.
  • Layers 60 and 62 may be subject to an annealing process as described above in connection with FIG. 3 to form a single amorphous accommodating layer.
  • the step of depositing the monocrystalline oxide layer is terminated by depositing a second template layer 60, which can be 1-10 monolayers of titanium, barium, barium and oxygen, or titanium and oxygen.
  • a layer 66 of a monocrystalline compound semiconductor material is then deposited overlying second template layer 64 by a process of molecular beam epitaxy. The deposition of layer 66 is initiated by depositing a layer of arsenic onto template 64. This initial step is followed by depositing gallium and arsenic to form monocrystalline gallium arsenide 66.
  • strontium can be substituted for barium in the above example.
  • a semiconductor component is formed in compound semiconductor layer 66.
  • Semiconductor component 68 can be formed by processing steps conventionally used in the fabrication of gallium arsenide or other III-V compound semiconductor material devices.
  • Semiconductor component 68 can be any active or passive component, and preferably is a semiconductor laser, light emitting diode, photodetector, heterojunction bipolar transistor (HBT) , high frequency MESFET, or other component that utilizes and takes advantage of the physical properties of compound semiconductor materials.
  • HBT heterojunction bipolar transistor
  • a metallic conductor schematically indicated by the line 70 can be formed to electrically couple device 68 and device 56, thus implementing an integrated device that includes at least one component formed in silicon substrate 52 and one device formed in monocrystalline compound semiconductor material layer 66.
  • illustrative structure 50 has been described as a structure formed on a silicon substrate 52 and having a barium (or strontium) titanate layer 60 and a gallium arsenide layer 66, similar devices can be fabricated using other substrates, monocrystalline oxide layers and other compound semiconductor layers as described elsewhere in this disclosure.
  • FIG. 10 illustrates a semiconductor structure 72 in accordance with a further embodiment.
  • Structure 72 includes a monocrystalline semiconductor substrate 74 such as a monocrystalline silicon wafer that includes a region 75 and a region 76.
  • An electrical component schematically illustrated by the dashed line 78 is formed in region 75 using conventional silicon device processing techniques commonly used in the semiconductor industry.
  • a monocrystalline oxide layer 80 and an intermediate amorphous silicon oxide layer 82 are formed overlying region 76 of substrate 74.
  • a template layer 84 and subsequently a monocrystalline semiconductor layer 86 are formed overlying monocrystalline oxide layer 80.
  • an additional monocrystalline oxide layer 88 is formed overlying layer 86 by process steps similar to those used to form layer 80, and an additional monocrystalline semiconductor layer 90 is formed overlying monocrystalline oxide layer 88 by process steps similar to those used to form layer 86.
  • at least one of layers 86 and 90 are formed from a compound semiconductor material. Layers 80 and 82 may be subject to an annealing process as described above in connection with FIG. 3 to form a single amorphous accommodating layer.
  • a semiconductor component generally indicated by a dashed line 92 is formed at least partially in monocrystalline semiconductor layer 86.
  • semiconductor component 92 may include a field effect transistor having a gate dielectric formed, in part, by monocrystalline oxide layer 88.
  • monocrystalline semiconductor layer 90 can be used to implement the gate electrode of that field effect transistor.
  • monocrystalline semiconductor layer 86 is formed from a group III-V compound and semiconductor component 92 is a radio frequency amplifier that takes advantage of the high mobility characteristic of group III-V component materials.
  • an electrical interconnection schematically illustrated by the line 94 electrically interconnects component 78 and component 92. Structure 72 thus integrates components that take advantage of the unique properties of the two monocrystalline semiconductor materials.
  • the illustrative composite semiconductor structure or integrated circuit 102 shown in FIGs. 6-10 includes a compound semiconductor portion 1022, a bipolar portion 1024, and a MOS portion 1026.
  • a p-type doped, monocrystalline silicon substrate 110 is provided having a compound , semiconductor portion 1022, a bipolar portion 1024, and an MOS portion 1026.
  • the monocrystalline silicon substrate 110 is doped to form an N + buried region 1102.
  • a lightly p-type doped epitaxial monocrystalline silicon layer 1104 is then formed over the buried region 1102 and the substrate 110.
  • a doping step is then performed to create a lightly n-type doped drift region 1117 above the N + buried region 1102. The doping step converts the dopant type of the lightly p-type epitaxial layer within a section of the bipolar region 1024 to a lightly n-type monocrystalline silicon region.
  • a field isolation region 1106 is then formed between the bipolar portion 1024 and the MOS portion 1026.
  • a gate dielectric layer 1110 is formed over a portion of the epitaxial layer 1104 within MOS portion 1026, and the gate electrode 1112 is then formed over the gate dielectric layer 1110.
  • Sidewall spacers 1115 are formed along vertical sides of the gate electrode 1112 and gate dielectric layer 1110.
  • a p-type dopant is introduced into the drift region 1117 to form an active or intrinsic base region 1114.
  • An n-type, deep collector region 1108 is then formed within the bipolar portion 1024 to allowelectrical connection to the buried region 1102.
  • Selective n-type doping is performed to form N + doped regions 1116 and the ⁇ emitter region 1120.
  • N + doped regions 1116 are formed within layer 1104 along adjacent sides of the gate electrode 1112 and are source, drain, or source/drain regions for the MOS transistor.
  • the N + doped regions 1116 and emitter region 1120 have a doping concentration of at least 1E19 atoms per cubic centimeter to allow ohmic contacts to be formed.
  • a p-type doped region is formed to create the inactive or extrinsic base region 1118 which is a P + doped region (doping concentration of at least 1E19 atoms per cubic centimeter) .
  • processing steps have been performed but are not illustrated or further described, such as the formation of well regions, threshold adjusting implants, channel punchthrough prevention implants, field punchthrough prevention implants, as well as a variety of masking layers.
  • the formation of the device up to this point in the process is performed using conventional steps. As illustrated, a standard N-channel MOS transistor has been formed within the MOS region 1026, and a vertical NPN bipolar transistor has been formed within the bipolar portion 1024. As of this point, no circuitry has been formed within the compound semiconductor portion 1022.
  • the accommodating buffer layer 124 is then formed over the substrate 110 as illustrated in FIG. 12.
  • the accommodating buffer layer will form as a monocrystalline layer over the properly prepared (i.e., having the appropriate template layer) bare silicon surface in portion 1022.
  • the portion of layer 124 that forms over portions 1024 and 1026 may be polycrystalline or amorphous because it is formed over a material that is not monocrystalline, and therefore, does not nucleate monocrystalline growth.
  • the accommodating buffer layer 124 typically is a monocrystalline metal oxide or nitride layer and typically has a thickness in a range of approximately 2-100 nanometers.
  • the accommodating buffer layer is approximately 5-15 nm thick.
  • an amorphous intermediate layer 122 is formed along the uppermost silicon surfaces of the integrated circuit 102.
  • This amorphous intermediate layer 122 typically includes an oxide of silicon and has a thickness and range of approximately 1-5 nm. In one particular embodiment, the thickness is approximately 2 nm.
  • a template layer 126 is then formed and has a thickness in a range of approximately one to ten monolayers of a material.
  • the material includes titanium-arsenic, strontium-oxygen-arsenic, or other similar materials as previously described with respect to FIGs. 1-5.
  • Layers 122 and 124 may be subject to an annealing process as described above in connection with FIG. 3 to form a single amorphous accommodating layer.
  • a monocrystalline compound semiconductor layer 132 is then epitaxially grown overlying the monocrystalline portion of accommodating buffer layer 124 (or over the amorphous accommodating layer if the annealing process described above has been carried out) as shown in FIG. 13.
  • the portion of layer 132 that is grown over portions of layer 124 that are not monocrystalline may be polycrystalline or amorphous.
  • the monocrystalline compound semiconductor layer can be formed by a number of methods and typically includes a material such as gallium arsenide, aluminum gallium arsenide, indium phosphide, or other compound semiconductor materials as previously mentioned.
  • the thickness of the layer is in a range of approximately 1-5,000 nm, and more preferably 100-500 nm.
  • each of the elements within the template layer are also present in the accommodating buffer layer 124, the monocrystalline compound semiconductor material 132, or both. Therefore, the delineation between the template layer 126 and its two immediately adjacent layers disappears during processing. Therefore, when a transmission electron microscopy (TEM) photograph is taken, an interface between the accommodating buffer layer 124 and the monocrystalline compound semiconductor layer 132 is seen.
  • TEM transmission electron microscopy
  • sections of the compound semiconductor layer 132 and the accommodating buffer layer 124 are removed from portions overlying the bipolar portion 1024 and the MOS portion 1026 as shown in FIG. 14.
  • an insulating layer 142 is then formed over the substrate 110.
  • the insulating layer 142 can include a number of materials such as oxides, nitrides, oxynitrides, low-k dielectrics, or the like. As used herein, low-k is a material having a dielectric constant no higher than approximately 3.5.
  • a transistor 144 is then formed within the monocrystalline compound semiconductor portion 1022.
  • a gate electrode 148 is then formed on the monocrystalline compound semiconductor layer 132.
  • Doped regions 146 are then formed within the monocrystalline compound semiconductor layer 132.
  • the transistor 144 is a metal- semiconductor field-effect transistor (MESFET) . If the MESFET is an n-type MESFET, the doped regions 146 and monocrystalline compound semiconductor layer 132 are also n-type doped. If a p-type MESFET were to be formed, then the doped regions 146 and monocrystalline compound semiconductor layer 132 would have just the opposite doping type. The heavier doped (N + ) regions 146 allow ohmic contacts to be made to the monocrystalline compound semiconductor layer 132.
  • This particular embodiment includes an n-type MESFET, a vertical NPN bipolar transistor, and a planar n-channel MOS transistor.
  • transistors including P-channel MOS transistors, p-type vertical bipolar transistors, p-type MESFETs, and combinations of vertical and planar transistors, can be used.
  • other electrical components such as resistors, capacitors, diodes, and the like, may be formed in one or more of the portions 1022, 1024, and 1026.
  • An insulating layer 152 is formed over the substrate 110.
  • the insulating layer 152 may include an etch-stop or polish-stop region that is not illustrated in FIG. 15.
  • a second insulating layer 154 is then formed over the first insulating layer 152. Portions of layers 154, 152, 142, 124, and 122 are removed to define contact openings where the devices are to be interconnected. Interconnect trenches are formed within insulating layer 154 to provide the lateral connections between the contacts.
  • interconnect 1562 connects a source or drain region of the n-type MESFET within portion 1022 to the deep collector region 1108 of the NPN transistor within the bipolar portion 1024.
  • the emitter, region 1120 of the NPN transistor is connected to one of the doped regions 1116 of the n-channel MOS transistor within the MOS portion 1026.
  • the other doped region 1116 is electrically connected to other portions of the integrated circuit that are not shown.
  • a passivation layer 156 is formed over the interconnects 1562, 1564, and 1566 and insulating layer 154. Other electrical connections are made to the transistors as illustrated as well as to other electrical or electronic components within the integrated circuit 102 but are not illustrated in the FIGs. Further, additional insulating layers and interconnects may be formed as necessary to form the proper interconnections between the various components within the integrated circuit 102.
  • active "devices for both compound semiconductor and Group IV semiconductor materials can be integrated into a single integrated circuit. Because there is some difficulty in incorporating both bipolar transistors and MOS transistors within a same integrated circuit, it may be possible to move some of the components within bipolar portion into the compound semiconductor portion 1022 or the MOS portion 1024. Therefore, the requirement of special fabricating steps solely used for making a bipolar transistor can be eliminated. Therefore, there would only be a compound semiconductor portion and a MOS portion to the integrated circuit.
  • an integrated circuit can be- formed such that it includes an optical laser in a compound semiconductor portion and an optical interconnect (waveguide) to a MOS transistor within a Group IV semiconductor region of the same integrated circuit.
  • FIGs. 16-22 include illustrations of one embodiment .
  • FIG. 16 includes an illustration of a cross- section view of a portion of an integrated circuit 160 that includes a monocrystalline silicon wafer 161.
  • An amorphous intermediate layer 162 and an accommodating buffer layer 164 similar to those previously described, have been formed over wafer 161.
  • Layers 162 and 164 may be subject to an annealing process as described above in connection with FIG. 3 to form a single amorphous accommodating layer.
  • the layers needed to form the optical laser will be formed first, followed by the layers needed for the MOS transistor.
  • the lower mirror layer 166 includes alternating layers of compound semiconductor materials.
  • the first, third, and fifth films within the optical laser may include a material such as gallium arsenide, and the second, fourth, and sixth films within the lower mirror layer 166 may include aluminum gallium arsenide or vice versa.
  • Layer 168 includes the active region that will be used for photon generation.
  • Upper mirror layer 170 is formed in a similar manner to the lower mirror layer 166 and includes alternating films of compound semiconductor materials.
  • the upper mirror layer 170 may be p-type doped compound semiconductor materials
  • the lower mirror layer 166 may be n-type doped compound semiconductor materials.
  • Another accommodating buffer layer 172 is formed over the upper mirror layer 170.
  • the accommodating buffer layers 164 and 172 may include different materials. However, their function is essentially the same in that each is used for making a transition between a compound semiconductor layer and a monocrystalline Group IV semiconductor layer.
  • Layer 172 may be subject to an annealing process as described above in connection with FIG. 3 to form an amorphous accommodating layer.
  • a monocrystalline Group IV semiconductor layer 174 is formed over the accommodating buffer layer 172.
  • the monocrystalline Group IV semiconductor layer 174 includes germanium, silicon germanium, silicon germanium carbide, or the like.
  • the MOS portion is processed to form electrical components within this upper monocrystalline Group IV semiconductor layer 174.
  • a field isolation region 171 is formed from a portion of layer 174.
  • a gate dielectric layer 173 is formed over the layer 174, and a gate electrode 175 is formed over the gate dielectric layer 173.
  • Doped regions 177 are source, drain, or source/drain regions for the transistor 181, as shown.
  • Sidewall spacers 179 are formed adjacent to the vertical sides of the gate electrode 175.
  • Other components can be made within at least a part of layer 174. These other components include other transistors (n-channel or p-channel), capacitors, transistors, diodes, and the like.
  • a monocrystalline Group IV semiconductor layer is epitaxially grown over one of the doped regions 177.
  • An upper portion 184 is P+ doped, and a lower portion 182 remains substantially intrinsic (undoped) as illustrated in FIG. 17.
  • the layer can be formed using a selective epitaxial process.
  • an insulating layer (not shown) is formed over the transistor 181 and the field isolation region 171.
  • the insulating layer is patterned to define an opening that exposes one of the doped regions 177.
  • the selective epitaxial layer is formed without dopants.
  • the entire selective epitaxial layer may be intrinsic, or a p-type dopant can be added near the end of the formation of the selective epitaxial layer. If the selective epitaxial layer is intrinsic, as formed, a doping step may be formed by implantation or by furnace doping. Regardless how the P+ upper portion 184 is formed, the insulating layer is then removed to form the resulting structure shown in FIG. 17.
  • the next set of steps is performed to define the optical laser 180 as illustrated in FIG. 18.
  • the field isolation region 171 and the accommodating buffer layer 172 are removed over the compound semiconductor portion of the integrated circuit. Additional steps are performed to define the upper mirror layer 170 and active layer 168 of the optical laser 180.
  • the sides of the upper mirror layer 170 and active layer 168 are substantially coterminous.
  • Contacts 186 and 188 are formed for making electrical contact to the upper mirror layer 170 and the lower mirror layer 166, respectively, as shown in FIG. 18.
  • Contact 186 has an annular shape to allow light (photons) to pass out of the upper mirror layer 170 into a subsequently formed optical waveguide.
  • An insulating layer 190 is then formed and patterned to define optical openings extending to the contact layer 186 and one of the doped regions 177 as shown in FIG. 19.
  • the insulating material can be any number of different materials, including an oxide, nitride, oxynitride, low-k dielectric, or any combination thereof.
  • a higher refractive index material 202 is then formed within the openings to fill them and to deposit the layer over the insulating layer 190 as illustrated in FIG. 20. With respect to the higher refractive index material 202, "higher" is in relation to the material of the insulating layer 190 (i.e., material 202 has a higher refractive index compared to the insulating layer 190) .
  • a relatively thin lower refractive index film (not shown) could be formed before forming the higher refractive index material 202.
  • a hard mask layer 204 is then formed over the high refractive index layer 202. Portions of the hard mask layer 204, and high refractive index layer 202 are removed from portions overlying the opening and to areas closer to the sides of FIG. 15.
  • a deposition procedure (possibly a dep-etch process) is performed to effectively create sidewalls sections 212.
  • the sidewall sections 212 are made of the same material as material 202.
  • the hard mask layer 204 is then removed, and a low refractive index layer 214 (low relative to material 202 and layer 212) is formed over the higher refractive index material 212 and 202 and exposed portions of the insulating layer 190.
  • the dash lines in FIG. 21 illustrate the border between the high refractive index materials 202 and 212. This designation is used to identify that both are made of the same material but are formed at different times.
  • a passivation layer 220 is then formed over the optical laser 180 and MOSFET transistor 181.
  • interconnects can include other optical waveguides or may include metallic interconnects .
  • other types of lasers can be formed.
  • another type of laser can emit light (photons) horizontally instead of vertically. If light is emitted horizontally, the MOSFET transistor could be formed within the substrate 161, and the optical waveguide would be reconfigured, so that the laser is properly coupled (optically connected) to the transistor.
  • the optical waveguide can include at least a portion of the accommodating buffer layer. Other configurations are possible.
  • the compound semiconductor portion may include light emitting diodes, photodetectors, diodes, or the like
  • the Group IV semiconductor can include digital logic, memory arrays, and most structures that can be formed in conventional MOS integrated circuits.
  • a monocrystalline Group IV wafer can be used in forming only compound semiconductor electrical components over the wafer.
  • the wafer is essentially a "handle" wafer used during the fabrication of the compound semiconductor electrical components within a monocrystalline compound semiconductor layer overlying the wafer. Therefore, electrical components can be formed within III-V or II-VI semiconductor materials over a wafer of at least approximately 200 millimeters in diameter and possibly at least approximately 300 millimeters .
  • a relatively inexpensive "handle" wafer overcomes the fragile nature of the compound semiconductor wafers by placing them over a relatively more durable and easy to fabricate base material. Therefore, an integrated circuit can be formed such that all electrical components, and particularly all active electronic devices, can be formed within the compound semiconductor material even though the substrate itself may include a Group IV semiconductor material. Fabrication costs for compound semiconductor devices should decrease because larger substrates can be processed more economically and more readily, compared to the relatively smaller and more fragile, conventional compound semiconductor wafers.
  • FIG. 23 illustrates a conventional two-way radio architecture 300.
  • Radio 300 includes an RF switch 302 that couples the radio circuitry to an antenna 304.
  • Switch 302 switches radio 300 between RECEIVE mode, when it is connected to an RF receiver amplifier 306, and TRANSMIT mode, when it connected to a transmitter final amplifier 308. While in RECEIVE mode, the input signal comes from antenna 304 through switch 302 into RF amp 306 and into a mixer 310, which also receives an input signal from a buffer 312.
  • Mixer 310 mixes the desired input signal from RF amp 306 with a buffered version from buffer 312 of the signal from synthesizer 330.
  • the result is a difference signal that has a lower frequency than the original signal from RF amp 306, so that is easier to detect encoded modulation.
  • Oscillator 332 provides synthesizer 330 with a fixed, highly accurate frequency reference signal that enables synthesizer 330 to produce a wide range of frequencies to mixer 310 so that the desired signal may be further amplified and the encoded modulation detected.
  • Detector 316 analyzes the signal to determine which portions of the signal are the desired information, such as voice or data.
  • the resultant signal is passed on to a digital signal processor (DSP) 318.
  • DSP digital signal processor
  • DSP 318 operates in conjunction with a central processor unit (CPU) 320 and a memory unit 322 to provide an output signal to an audio circuit 324.
  • Audio circuit 324 further processes the input signal before outputting the signal through a speaker 326 " .
  • Speaker 326 may be a conventional speaker, such as those in cellular phones, or it may be a micro-speaker located within a "wearable" cellphone, for example, that may be mounted to a pair of glasses or be worn as an earpiece.
  • voice input signals come into the radio through a microphone 328 directly to DSP 318.
  • DSP 318 processes the signals and sends the processed signal to a frequency synthesizer 330.
  • Synthesizer 330 is coupled to an oscillator 332 to produce a signal that is sent to transmitter (TX) driver circuit 334.
  • Driver circuit 334 drives TX final amplifier 308, which transmits the signal out of antenna 304 (because TRANSMIT mode is enabled, RF switch 302 is now connected between antenna 304 and TX final amp 308) .
  • ICs integrated circuits
  • CPU 320, DSP 318, memory 322 and audio circuit 324 will likely always be manufactured using silicon substrates.
  • CPU 320 and DSP 318 will likely be CMOS circuits, and may even be combined into a single IC.
  • RF amp 306 and TX driver 334 will likely be GaAs ICs because RF performance is more important in those circuits.
  • Other circuit components may be fabricated from silicon or GaAs depending on the operational parameters of the individual radio.
  • radio 300 One problem with conventional radios, such as radio 300, is the amount of additional power wasted due to the interconnections between all of the individual ICs. The additional power losses result in reduced battery life, and/or requirements for bigger/heavier batteries — all being highly undesirable qualities from the consumer's perspective.
  • Other problems related to the high number of individual ICs include: the relatively large size of the radio, the limited bandwidth of operation, and the difficulty in combining multiple functions within a single device (e.g., pager and cell phone) .
  • radios constructed in accordance with the present invention in which numerous radio circuits are fabricated on a single integrated circuit (IC) that includes conventional silicon-based circuits and compound-based circuits, such as gallium arsenide.
  • IC integrated circuit
  • compound-based circuits such as gallium arsenide.
  • the inclusion of these circuits on a single IC provides numerous benefits, not the least of which is the power savings due to the significant reduction in the number of board traces between ICs, as well as a reduction in size required for the radio circuits.
  • the reduced size and power requirements enable reductions in the size and weight of the radios.
  • the reduced size and power requirements may be utilized to enable the manufacturer to include additional functionality in the radio without increasing size or weight.
  • the reduction in size of the radio circuitry may permit the manufacturer to increase the size of the display so that a useable web-browsing feature can be provided.
  • FIG. 24 shows a schematic illustration of a radio 400 constructed in accordance with the principles of the present invention.
  • each of the circuits and components of radio 400 has the same suffix as the circuits and components of previously described radio 300, and operates in basically the same manner.
  • RF amplifier 306 receives the input signal from antenna 304 through RF switch 302
  • RF amplifier 406 receives the input signal from antenna 404 through RF switch 402.
  • radio 400 may have improved operational capabilities, such as a higher frequency of operation and/or higher bandwidth due to the inclusion of RF circuits and processing circuitry on a single IC even though the RF circuits are fabricated on a compound substrate and the processing circuits are fabricated on a silicon substrate.
  • RF circuits and processing circuitry may have improved operational capabilities, such as a higher frequency of operation and/or higher bandwidth due to the inclusion of RF circuits and processing circuitry on a single IC even though the RF circuits are fabricated on a compound substrate and the processing circuits are fabricated on a silicon substrate.
  • Persons skilled in the art will also appreciate that the advantages of the present invention may accomplished even if only a single compound substrate circuit and a single silicon substrate circuit are included on an IC, and that, under no circumstances, does the present invention require that all of the radio circuits be included in a single IC.
  • FIG. 24 shows substantially all of the radio circuits on a single monolithic integrated circuit 401, with RF switch 402, antenna 404, TX final amplifier 408, speaker 426, and microphone 428 being individual components.
  • TX final amp 408 is shown as an individual IC due to power requirements, it may be practical, as the size and heat dispersion requirements of power transistors are reduced, to include TX final amp 408 on TC 401 so that all of the circuitry for a two-way radio would be included on a single IC chip.
  • FIG. 24 shows substantially all of the radio circuits on a single monolithic integrated circuit 401, with RF switch 402, antenna 404, TX final amplifier 408, speaker 426, and microphone 428 being individual components.
  • TX final amp 408 is shown as an individual IC due to power requirements, it may be practical, as the size and heat dispersion requirements of power transistors are reduced, to include TX final amp 408 on TC 401 so that all of the circuitry for a two-way radio would be included
  • RF amp 406, mixer 410, buffer 412, amp 414, detector circuit 416, DSP 418, CPU 420, memory 422, audio circuit 424, synthesizer 430, oscillator 432, and TX driver 434 are all included on monolithic IC 401.
  • FIGs. 25 and 26 show further illustrations of monolithic OC 401 of radio 400.
  • each of the individual circuits may be fabricated on single monolithic IC 401 even though the individual circuits may require different substrate bases. All of the circuits, as previously described, are formed starting from a single silicon substrate 450. The circuits themselves utilize external connections through I/.O pads 403 which are located around the entire periphery of IC 401.
  • An amorphous intermediate layer (not shown in FIGs. 24-25) is formed between substrate 450 and an accommodating buffer layer (not shown in FIGs. 24-25).
  • an accommodating buffer layer On top of the accommodating buffer layer (or on top of a template layer — not shown in FIGs. 24-25 — as previously described) , a layer of monocrystalline compound semiconducting material is formed.
  • This layer which may for example be gallium arsenide, is used to fabricate the RF circuits on the same IC as the processing circuits.
  • FIG. 24 shows each of the GaAs-based circuit extending higher from the silicon substrate 450 than the processing circuits (e.g., audio circuit 424).
  • processing circuitry may, for example, be embedded within substrate 450 itself so that, in reality, it may not extend beyond the upper surface of substrate 450 as is illustrated in FIG. 24.
  • the methods according to this invention can further include forming integrated electronic circuitry in an electronic layer as needed and in accordance with the processes outlined throughout FIGs. 1-22.
  • the electronic layer can be the substrate surface layer, the compound semiconductor layer, another semiconductor layer, or any combination thereof.
  • the terms "comprises,” “comprising, “ or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but may also include other elements not expressly listed or inherent to such process, method, article, or apparatus .

Landscapes

  • Recrystallisation Techniques (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne des structures semi-conductrices de radios bidirectionnelles, et des procédés de fabrication de ces structures. La structure intégrée comprend un circuit intégré monolithique unique (401) sur lequel des circuits de traitement, tels qu'une UC (420) ou un processeur de signal numérique (418), sont fabriqués dans une structure substrat en silicium. Par l'utilisation d'une couche intermédiaire, une matière semi-conductrice composée, telle que AsGa, peut être déposée en couches sur le substrat en silicium. Cette matière composée peut alors s'utiliser pour les circuits RF dans la radio. Les circuits RF et les circuits de traitement peuvent ainsi être fabriqués sur un CI unique, ce qui réduit les impératifs de puissance et de taille du dispositif assemblé.
PCT/US2001/016730 2000-06-30 2001-05-21 Architectures de radio a circuit integre WO2002003420A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001263398A AU2001263398A1 (en) 2000-06-30 2001-05-21 Integrated circuit radio architectures

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US60723900A 2000-06-30 2000-06-30
US09/607,239 2000-06-30

Publications (2)

Publication Number Publication Date
WO2002003420A2 true WO2002003420A2 (fr) 2002-01-10
WO2002003420A3 WO2002003420A3 (fr) 2002-06-06

Family

ID=24431410

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/016730 WO2002003420A2 (fr) 2000-06-30 2001-05-21 Architectures de radio a circuit integre

Country Status (2)

Country Link
AU (1) AU2001263398A1 (fr)
WO (1) WO2002003420A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11158575B2 (en) * 2018-06-05 2021-10-26 Macom Technology Solutions Holdings, Inc. Parasitic capacitance reduction in GaN-on-silicon devices

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5596205A (en) * 1993-07-12 1997-01-21 Peregrine Semiconductor Corporation High-frequency wireless communication system on a single ultrathin silicon on sapphire chip

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5596205A (en) * 1993-07-12 1997-01-21 Peregrine Semiconductor Corporation High-frequency wireless communication system on a single ultrathin silicon on sapphire chip

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11158575B2 (en) * 2018-06-05 2021-10-26 Macom Technology Solutions Holdings, Inc. Parasitic capacitance reduction in GaN-on-silicon devices
US11929364B2 (en) 2018-06-05 2024-03-12 Macom Technology Solutions Holdings, Inc. Parasitic capacitance reduction in GaN devices
US12266523B2 (en) 2018-06-05 2025-04-01 Macom Technology Solutions Holdings, Inc. Parasitic capacitance reduction in GaN-on-silicon devices

Also Published As

Publication number Publication date
AU2001263398A1 (en) 2002-01-14
WO2002003420A3 (fr) 2002-06-06

Similar Documents

Publication Publication Date Title
US7067856B2 (en) Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same
US20020008234A1 (en) Mixed-signal semiconductor structure, device including the structure, and methods of forming the device and the structure
US7161227B2 (en) Structure and method for fabricating semiconductor structures and devices for detecting an object
US20020030246A1 (en) Structure and method for fabricating semiconductor structures and devices not lattice matched to the substrate
WO2002001648A1 (fr) Structure a semi-conducteur, dispositif, circuit, et procede
US20030026575A1 (en) Structure and method for fabricating semiconductor optical waveguide structures utilizing the formation of a compliant substrate
WO2002003467A1 (fr) Circuits integres empiles verticalement comprenant des ports a grande largeur de bande
US6714768B2 (en) Structure and method for fabricating semiconductor structures and polarization modulator devices utilizing the formation of a compliant substrate
US20030020107A1 (en) Structure and method for fabricating semiconductor capacitor structures utilizing the formation of a compliant structure
US20030010998A1 (en) Apparatus and techniques for implementing wireless communication between integrated transmitters and integrated receivers
US20030020121A1 (en) Semiconductor structure for monolithic switch matrix and method of manufacturing
US20030017625A1 (en) Structure and method for fabricating an optical device in a semiconductor structure
US20030015712A1 (en) Fabrication of an optical communication device within a semiconductor structure
US20020190270A1 (en) Semiconductor structure for spacial power combining and method of fabrication
US20030015697A1 (en) Fabrication of an optical transmitter within a semiconductor structure
WO2002003420A2 (fr) Architectures de radio a circuit integre
US20030022408A1 (en) Fabrication of an arrayed waveguide grating device
US20020175347A1 (en) Hybrid semiconductor input/output structure
US20030017621A1 (en) Fabrication of buried devices within a semiconductor structure
US20030034551A1 (en) Fabrication of devices for a mesh network within a semiconductor structure
US20020127757A1 (en) Apparatus and method for electrical isolation

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载