WO2002001363A1

WO2002001363A1 - Memory control device, and memory control method

Info

Publication number: WO2002001363A1
Application number: PCT/JP2001/005412
Authority: WO
Inventors: Daisuke Kondou; Yasushi Ueda; Toru Aoki
Original assignee: Matsushita Electric Industrial, Co., Ltd.
Priority date: 2000-06-27
Filing date: 2001-06-25
Publication date: 2002-01-03

Abstract

A memory control device for controlling a DRAM, wherein data recorded in the DRAM is positively captured into a register. The memory control device comprises a capturing clock generating circuit (11) for generating a clock, a delay regulating circuit (12) for performing on the clock a delay regulating processing that effects delaying with a variable delay value and outputting the processed clock as a capturing clock, and a read-data register (13) for reading and storing data recorded in a memory based on the capturing clock.

Description

Specification

Memory control device and memory control method

Technical field '

The present invention relates to a memory control, and more particularly to a memory control having a characteristic with respect to a timing at which data recorded in a DRAM is taken into a read data register.

Background art

2. Description of the Related Art Conventionally, as a memory control device relating to the timing of taking data recorded in a DRAM into a read register, the one described in Japanese Patent Application Laid-Open No. 11-285585 is known. For specific examples of determining the storage timing of read data in DRAM control, see Figs.

This will be described using 3. The entire disclosure of the above-mentioned Japanese Patent Application Laid-Open No. 11-212855 is incorporated herein by reference in its entirety.

FIG. 12 is a configuration diagram of a conventional memory control device and t-RAM. In the figure, reference numeral 101 denotes a memory control device, which includes an enable signal generation unit 111, a delay circuit 112, and a read data storage register 113. Reference numeral 121 denotes a DRAM: and 122 denotes a data bus which is a data path between the memory control device 101 and the DRAM 121. The operation of the conventional memory control device having the above configuration is as follows. When reading data recorded in the DRAM 121, the enable signal generator 111 indicates the value of Higii or Low. The enable signal is output to the DRAM 121. The DRAM 121 outputs the read data on the data path 122 when the enable signal is Low, that is, when the active state is activated.

On the other hand, in the memory control device 101, the enable signal generated by the rice pull signal generation unit 111 is also output to the delay circuit 112. The enable signal input to the delay circuit 1 1 2 has its polarity inverted and is used as a trigger signal delayed by the setup time of the read data storage register 1 13 as a read data storage register 1 1 Output to 3. Here, as shown in Fig. 13, the setup time is the time during which stable input data must be added before the trigger signal rises in order to load normal data into the read data storage register. is there. The read data storage register 113 takes in the read data that has been output from the DRAM 121 and is fixed on the data bus 122 by using a trigger signal. However, in the above configuration, the DRAM outputs read data to the data bus 122 by outputting an enable signal.However, in the case of a DRAM such as a synchronous DRAM (SDRAM), for example, all the operations are performed by a clock. Synchronous, when a read command is output to such an SDRAM, read data is output on the read bus after a predetermined time has elapsed after the command is accepted, and this type of memory control is determined. Devices also exist. In such a memory controller, the “predetermined time” and the time during which data is determined on the read path are all uniquely set with respect to the rising edge of the clock of the SDRAM. Thus, data can be output without using an enable signal.

By the way, if you try to increase the data transfer speed by using a DRAM with a high-speed page mode and a thin DRAM, etc. The time that the data is fixed on the data bus 1 2 2 is naturally shortened. The read data storage register 113 must take in the read data at the fixed time.

However, if the timing of the data capture given by the trigger signal is fixed, wiring delay occurs due to temperature changes, etc., and the capture timing is set at a time when the read data is not fixed on the data bus 122. Possibilities arise. Also, the wiring delay varies depending on the distance between the memory controller 101 and the DRAM 122, so that it is necessary to reset the data fetch timing every time the wiring is performed. For example, when a designed circuit is implemented as an LSI, if the wiring distance to the storage register is long, the read data from the DRAM, which is the input signal of the LSI, means that the read data has not yet been determined at the rise of the trigger signal. , Setup time is not satisfied and data cannot be stored. Therefore, in order to adjust the rise time of the trigger signal in consideration of those wiring delays, it is necessary to reset the data acquisition timing. This is the same in a memory control device that does not use an enable signal and is used for an SDRAM or the like. Disclosure of the invention

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a memory control device capable of acquiring read data at an optimal acquisition timing even when a wiring delay occurs in a data path. aimed to.

In order to achieve the above object, a first invention (corresponding to claim 1) includes a clock generation circuit for generating a clock,

A delay adjustment process for delaying the variable delay value with a variable delay value And a delay adjustment circuit that outputs the captured clock.

A memory control device comprising: a read data register for reading data stored in a memory based on the fetch clock and storing the read data.

A second aspect of the present invention (corresponding to claim '2) is the present invention, wherein the delay adjustment circuit starts the delay adjustment processing based on an environmental change around the memory control device.

A third aspect of the present invention (corresponding to claim 3) is the present invention, wherein the delay adjustment circuit starts the delay adjustment processing at a predetermined cycle. A fourth aspect of the present invention (corresponding to claim 4) is the above-described aspect of the present invention, wherein the delay adjustment circuit starts delay adjustment processing based on an error detection or error correction operation for the memory.

A fifth aspect of the present invention (corresponding to claim 5) is the above-mentioned aspect of the present invention, wherein the delay adjustment circuit varies the delay value based on an environmental change around the memory control device.

A sixth aspect of the present invention (corresponding to claim 6) is the present invention, wherein the delay adjustment circuit varies the delay value based on a predetermined cycle.

A seventh aspect of the present invention (corresponding to claim 7) is that the delay adjustment circuit has one or a plurality of delay elements,

The present invention is the above-mentioned invention in which the clock delay processing is performed by passing the clock through a predetermined number of the delay elements.

An eighth aspect of the present invention (corresponding to claim 8) is the above-described aspect of the present invention, wherein the delay adjustment circuit can adjust a delay amount in the delay adjustment processing by external control. -Further, a ninth invention (corresponding to claim 9) is a comparison data register for storing the same data as data to be recorded in the memory, A comparison circuit that compares the data stored in the read data register with the data stored in the comparison data register, wherein a predetermined address in the memory is set in the comparison data register; After the data is written, the read data register reads the predetermined data, and the comparison circuit reads the predetermined data in the read data register and the predetermined data in the comparison data register. The present invention is the above-mentioned present invention, which performs a write / read confirmation process for collating with the data of the above.

Further, a tenth aspect of the present invention (corresponding to claim 10) further comprises a register whose contents can be rewritten from the outside,

The present invention is the above-described present invention, wherein the comparison circuit performs the write Z read confirmation process using the data set in the register.

The eleventh present invention (corresponding to claim 11) is the present invention in which the register is at least set to the predetermined address of the memory.

According to a twelfth aspect of the present invention (corresponding to claim 12), the delay adjustment circuit performs the delay adjustment processing after the end of the write / read confirmation processing.

After the delay adjustment processing is performed, the comparison circuit performs write Z read repetition confirmation processing for performing the write / read confirmation processing again, and performs the write Z read confirmation processing or the write / read confirmation processing. And the delay value is optimized by the write Z-read repetition confirmation processing.

A thirteenth aspect of the present invention (corresponding to claim 13) is the above-described aspect of the present invention, in which the delay adjustment circuit performs the delay adjustment processing when a control signal is input from the outside.

A fourteenth aspect of the present invention (corresponding to claim 14) is that the external signal is The present invention is the signal indicating that the power of the memory control device is turned on.

A fifteenth aspect of the present invention (corresponding to claim 15) is the present invention, wherein the external signal is a signal indicating initialization or reset of the memory control device.

A sixteenth aspect of the present invention (corresponding to claim 16) is the present invention, wherein the external signal is a signal indicating a return from the sleep state of the memory control device.

The seventeenth invention (corresponding to claim 17) further comprises an arbitration circuit for confirming the access of the block having the access right to the memory and determining the access priority of the block. ,

When the arbitration circuit at least confirms that the block is not accessing the memory, the delay adjustment circuit is the present invention that performs the delay adjustment processing. .

The eighteenth aspect of the present invention (corresponding to claim 18) is that, when the arbitration circuit confirms that the block is accessing the memory, the delay adjustment circuit performs the delay adjustment processing. The present invention does not perform the above.

Further, a nineteenth invention (corresponding to claim 19) further comprises a counter for counting the number of times that can be set externally or by the register, wherein the arbitration circuit is configured so that the block accesses the memory. The delay adjustment circuit does not perform the delay adjustment processing, increments the value of the counter, and performs the delay adjustment processing when the value of the counter reaches a predetermined value. It is an invention.

Further, the 20th invention (corresponding to claim 20) further includes a timer for measuring time,

On the basis of the time measurement of the timer, the delay adjustment circuit In the present invention, the delay adjustment processing is performed every interval.

A twenty-first invention (corresponding to claim 21) is the present invention, wherein the predetermined time can be set in the register.

The second 2 of the present invention (corresponding to claim 2 2) is provided with further temperature monitor for measuring the temperature, ¹

The delay adjustment circuit according to the present invention, wherein the delay adjustment circuit performs the delay adjustment processing based on a temperature change of the block having an access right to the memory.

According to a twenty-third aspect of the present invention (corresponding to claim 23), a predetermined temperature can be set in the register.

The present invention is the above-described present invention, wherein when the temperature monitor detects the predetermined temperature, the delay adjustment processing is performed. '

A twenty-fourth aspect of the present invention (corresponding to claim 24) further includes a voltage monitor for measuring a voltage,

The delay adjusting circuit according to the present invention performs the delay adjusting process based on a block having an access right to the memory or a voltage change of the memory control device.

According to a twenty-fifth aspect of the present invention (corresponding to claim 25), a predetermined voltage can be set in the register,

The present invention is the above-described present invention, wherein the delay adjustment process is performed when the voltage monitor detects a voltage equal to or higher than the predetermined voltage.

A twenty-sixth aspect of the present invention (corresponding to claim 26) is a method for detecting an error when an error detection block having an access right to the memory detects an error by accessing the memory. When the number of error detections per specific number of codewords becomes larger than a predetermined number, the delay adjustment circuit is the present invention that performs the delay adjustment processing. A twenty-seventh aspect of the present invention (corresponding to claim 27) is characterized in that when an error correction block having an access right to the memory performs error correction by accessing the memory, However, when the number of times becomes larger than a predetermined number, the delay adjustment circuit performs the delay adjustment processing. ¹

The twenty-eighth invention (corresponding to claim 28) is characterized in that, when the number of times that the block having access right to the memory writes data to the memory reaches a predetermined number, The delay adjusting circuit is the present invention that performs the delay adjusting process.

A twentieth invention (corresponding to claim 29) is the invention described above, wherein the predetermined number of times can be set in the register.

According to the present invention as described above, the provision of the delay adjustment circuit enables the read data capture timing to be adjusted even during actual operation, and sets the capture timing at a time when the read data is always determined. Will be able to be captured. This makes it possible to perform the layout without considering the wiring delay between the memory controller and the DRAM.

A thirty-fifth aspect of the present invention (corresponding to claim 30) includes: a clock generation step of generating a clock;

A delay adjusting step of performing a delay adjustment process of delaying the mouthpiece with a variable delay value and outputting the captured clock.

A read data register storing step of reading data recorded in a memory and storing the read data in a read data register based on the capture clock.

Further, in the thirty-first aspect of the present invention (corresponding to claim 31), the delay adjustment step is characterized in that the delay adjustment processing is performed based on an environmental change around the memory controller. The present invention is to start the above. · A thirty-second aspect of the present invention (corresponding to claim 32) is the present invention, wherein the delay adjustment step starts the delay adjustment processing at a predetermined cycle.

A thirty-third aspect of the present invention (corresponding to claim 33) is the present invention in which the delay adjustment step starts a delay adjustment process based on an error detection or error correction operation for the memory.

A thirty-fourth aspect of the present invention (corresponding to claim 34) includes: a comparison data register storing step of storing the same data as the data to be recorded in the memory in the comparison data register;

A comparison step of comparing the data stored in the read data register with the data stored in the comparison data register step.

After the predetermined data in the memory and the predetermined data are written in the comparison data register, the predetermined data is read from the read data register, and in the comparison step, the read data register is read. The present invention is to perform a write / read confirmation process for collating the predetermined data in the data with the predetermined data in the comparison data register. A thirty-fifth aspect of the present invention (corresponding to claim 35) is the memory control device according to the first aspect of the present invention, wherein the clock generation circuit generates a clock. The computer functions as all or a part of a delay adjustment circuit that performs delay adjustment processing for delaying and outputs as a capture clock, and a read data register that reads and stores data recorded in a memory based on the capture clock. It is a program for

The 36th invention (corresponding to claim 36) is a 30th invention of the present invention. A clock generation step of generating a clock in the memory control method, a delay adjustment step of performing a delay adjustment process of delaying the clock with a variable delay value, and outputting the captured clock.

Based on the capture clock, the computer executes all or part of a read data register storage step of reading data recorded in a memory and storing the data in a read data register. It is a program.

A thirty-seventh aspect of the present invention (corresponding to claim 37) is the memory control device according to the first aspect of the present invention, wherein the clock generation circuit generates a clock, and the clock is delayed by a variable delay value. A delay adjustment circuit that performs delay adjustment processing to output the data as a capture clock, and a read data register that reads and stores data recorded in a memory based on the capture clock. A medium that carries a program for causing a computer to function, and is a medium that can be processed by a computer. ·

Further, a thirty-eighth aspect of the present invention (corresponding to claim 38) is a memory control method according to a thirtieth aspect of the present invention, wherein the clock generating step of generating a clock; A delay adjustment step of performing delay adjustment processing for delaying the data and outputting it as a capture clock; and a read data register for reading data recorded in a memory based on the capture clock and storing the data in a read data register. A medium that carries a program for causing a computer to execute all or a part of the storage process, and is a medium that can be processed by a computer. BRIEF DESCRIPTION OF THE FIGURES

Figure 1 is a block diagram of a memory control apparatus according to the first embodiment of the present invention _c FIG. 2 is a timing chart for storing read data from the DRAM.

FIG. 3 is a configuration diagram of a memory control device according to Embodiment 2 of the present invention. FIG. 4 is a configuration diagram of a memory control device according to Embodiment 3 of the present invention. FIG. 5 is a configuration diagram of a memory control device according to Embodiment 4 of the present invention. FIG. 6 is a configuration diagram of a memory control device according to the fifth embodiment of the present invention. FIG. 7 is a configuration diagram of a memory control device according to Embodiment 6 of the present invention. FIG. 8 is a configuration diagram of a memory control device according to Embodiment 7 of the present invention. FIG. 9 is a configuration diagram of a memory control device according to Embodiment 8 of the present invention. FIG. 10 is a configuration diagram of a memory control device according to Embodiment 9 of the present invention.

FIG. 11 is a configuration diagram of a memory control device in which the embodiments of the present invention are collectively configured.

FIG. 12 is a configuration diagram of a memory control device according to a conventional technique.

Figure 13 is a timing chart for storing read data from the DRAM of the prior art.

FIG. 14 (a) is a diagram for describing an example of the write Z-read process according to the second embodiment of the present invention. '

FIG. 14B is a diagram for explaining an example of the write / read processing according to the second embodiment of the present invention.

Explanation of reference numerals

1 Memory controller

1 1 Capture clock generation circuit

1 2 Delay adjustment circuit

1 3 Register for storing read data 14 Register for storing comparison data

1 5 Comparison circuit.

1 6 Timer

1 7 Temperature monitor

18 Power supply zero pressure monitor ''

1 9 Register rewritable from outside

20 counter

21 Arbitration circuit

31 DRAM

32 block A

33 Error detection block

34 error correction block

1 00, 1 01 Enable signal generator

1 01 Conventional memory controller

1 10, 1 22 Data bus

1 12 Delay circuit

1 13 Read data storage register

121 Best Mode for Carrying Out the Invention

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)

The memory control device according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a configuration diagram of a memory control device according to a first embodiment of the present invention. In the drawing, 1 is a memory control device, and 1 is a capture clock. A generation circuit, 12 is a delay adjustment circuit, 13 is a read data register, and 31 is a DRAM. 100 is an rice signal generator, and 110 is a data path. FIG. 2 is a diagram showing the timing of storing data read from the DRAM 31 in the read data register 13.

The operation of the memory control device according to the first embodiment of the present invention having the above-described configuration will be described below, and thereby an embodiment of the memory control method of the present invention will be described.

The time during which the data read from the DRAM 31 is determined on the data bus 110 (t_data) is determined by the period of the enable signal output from the enable signal generator 100, and the time The read data must be loaded into the read data register 13.

Therefore, upon receiving the input from the capture clock generation circuit 11, the delay adjustment circuit 12 adjusts the delay time and outputs the adjusted capture clock to the read data register 13. As a result, the read data can be stored in the read data register 13 even if the time during which the read data is determined on the data bus 110 fluctuates due to wiring delay or the like. At this time, the setting of the delay value in the delay adjustment circuit 12 is performed as follows. In advance, determine an appropriate delay value from the specifications of the DRAM 31 and the wiring delay of the read data, enable signal, etc. from the DRAM 31 and set it at approximately the center of the fixed time of the read data on the output data bus 110. Set the value so that the capture clock comes, and set this as the initial value. Thus, if the time that the read data is determined on the data path 110 fluctuates for some reason, the delay value in the delay adjustment circuit 12 is reset according to that, and the read data is read. You can adjust the amount of delay in the capture window so that it is time to capture it reliably.

As described above, according to the present invention, the read data is always stored on the data bus 110. The data can be surely taken into the read data register 13 at the time determined above.

As the configuration of the delay adjustment circuit 12, a plurality of delay elements may be provided, and the number of delay elements that pass through the intake port may be changed according to a desired delay value. Means for changing the delay value according to the control of an external CPU or the like may be used. .

(Embodiment 2)

The memory control device according to the second embodiment of the present invention includes a circuit necessary for confirming whether or not the write / read operation can be normally performed on the DRAM 31. This will be described below with reference to FIG.

FIG. 3 is a configuration diagram of a memory control device according to Embodiment 2 of the present invention. In the figure, the same or corresponding parts as those in FIG. Reference numeral 14 denotes a comparison data register, reference numeral 15 denotes a comparison circuit, reference numeral 19 denotes a register, and reference numeral 32 denotes a block A. The description of the enable signal generation circuit 100 is omitted because the same configuration and operation as those of the first embodiment are performed.

The operation of the memory control device according to the second embodiment of the present invention having the above-described configuration will be described below, and an embodiment of the memory control method of the present invention will be described.

When data is written from the block A32 to the DRAM31, the comparison data register stores the same data from the block A32. Next, as in the first embodiment, when the read data register 13 acquires and stores the read data from the DRAM 31, the comparison circuit 15 compares the read data with the data stored in the read data register 13. And compare it with the data stored in the data register 14.

If the comparison result of comparison circuit 15 is the same, it was written to DRAM 31 If the capture clock is set within the time that the data is read data is determined, and there is a discrepancy in the comparison result, the capture clock is shifted, so the delay adjustment circuit 12 resets the delay value. It is possible to confirm that it is necessary to carry out.

Here, the data written in the DRAM 31 and the address in the DRAM 31 can be specified by setting the register 19 which can be rewritten from the outside. As described above, once the same data is written to the DRAM 31 and the comparison data register 14, the data read to the read data register 13 and the data in the comparison data register 14 are Is referred to as a write Z read process. It should be noted that the delay value data in the delay adjustment circuit 12 may be set in the register 19, or the fetched clock input to the delay adjustment circuit 12 may be inverted, and Alternatively, data such as inversion control data for adjustment by the delay adjustment circuit 12 1 may be set and used for the write / read processing. Here, FIG. 14 shows an example of the inversion control data. As shown in Fig. 14 (a), if the capture clock is set at a timing when the read data is not determined, the write / read signal is inverted by the inversion control data as shown in Fig. 14 (b). Inverts the capture clock during read processing. Thus, the capture clock can be set at the timing when the read data is determined.

On the other hand, in the above operation, it can be confirmed that the read data from the DRAM 31 is set within the range determined on the data path 110 and the read data is set. It is not known at which timing in the range where the data is fixed the capture timer is set. In this case, a small delay may cause the capture clock to shift to the time domain where the read data is not determined. In such a case, write an arbitrary value to the DRAM 31 and make sure that the value can be read. \ Set a predetermined delay value in the delay adjustment circuit 12 and check with the method described above. I do. Next, the delay value in the delay adjusting circuit 12 is set to a value different from the predetermined value, and the write / read processing is performed again. At this time, the delay value may be set to the front or the back of the time arbitrarily. For example, by alternately setting the front and the back, it is possible to determine the direction of the delay value shift. Become.

By repeating the write Z read process while changing the delay value, it can be confirmed that the value written to the DRAM 31 can be read within the specified range from the set delay value to a certain value . The delay adjusting circuit 12 sets the center value of the delay value having the predetermined range as the final delay value.

As described above, according to the memory control device of the present embodiment, it is possible to set the capture clock at a timing at which the data of DRAM 31 can be reliably read.

(Embodiment 3)

The memory control device according to the third embodiment of the present invention is such that the delay adjustment processing is performed when an external signal is input. This will be described below with reference to FIG.

FIG. 4 is a configuration diagram of a memory control device according to Embodiment 3 of the present invention. In the figure, the same or corresponding parts as those in FIG. 21 is an arbitration circuit. Description of the enable signal generation circuit 100 is omitted because it performs the same configuration and operation as in the first embodiment.

The operation of the memory control device according to Embodiment 3 of the present invention having the above-described configuration will be described below. An embodiment of the memory control method will be described.

'The signal input to the memory control device 1 as an external signal includes a signal indicating a power-on, a reset signal, and a signal indicating a return from a sleep state of the power supply.

In the memory control circuit according to the present embodiment, the delay adjustment circuit 12 performs the delay adjustment processing when an external signal is input, thereby setting before the block A32 accesses the DRAM 31. Thus, the read data from the DRAM 31 can be surely taken into the read data register 13.

Further, it is confirmed that the arbitration circuit 21 block A 32 is not accessing the DRAM 31, and during that time, the delay adjustment circuit 12 performs delay adjustment processing.

As described above, according to the present invention, the time when the DRAM 31 is not accessed can be effectively used without interrupting the access to the DRAM 31 of the block A32, and the data of the DRAM 31 can always be read reliably. It becomes possible to do.

Although the present embodiment has been described assuming that the arbitration circuit 21 is mounted on the configuration of the second embodiment, the arbitration circuit may be added to the configuration of the first embodiment. Can obtain the same effect as that of the present embodiment _c (Embodiment 4).

FIG. 5 is a configuration diagram of a memory control device according to Embodiment 4 of the present invention. In the drawings, the same or corresponding parts as in FIGS. 1 to 4 are denoted by the same reference numerals, and description thereof will be omitted. Also, 16 is a timer, and 20 is a counter. Further, the enable signal generation circuit 100 has the same configuration and operation as the first embodiment, so that the description is omitted.

Memory control according to Embodiment 4 of the present invention having the above configuration Hereinafter, the operation of the device will be described, and an embodiment of the memory control method according to the present invention will be described. However, portions common to Embodiments 2 to 4 are omitted, and only differences are described.

While the memory control device 1 is operating, the wiring length changes to the data bus 110 due to a change in temperature, power supply voltage, or the like, and there is a possibility that read data cannot be taken. In such a case, the time is set by the timer 16 and the delay adjusting circuit 12 performs the delay adjusting process at a fixed time interval, which is an example of the predetermined time of the present invention, set in the timer 16. To This makes it possible to set the optimal delay value periodically. At this time, as shown in FIG. 5, the fixed time interval may be set by an external register 19 to be adjustable, or may be a fixed value held by the delay adjustment circuit 12. Good. Of course, the register 19 may be omitted.

In the above operation, the arbitration circuit 21 permits access to the DRA 31 of the block A 32, and if the access is being made, the arbitration circuit 21 gives priority to the access to the DRA 31 and delay adjustment processing is performed. Is not performed, or the delay adjustment processing a is performed after the access of the block A32 to the DRAM 31 is completed.

When the access to the DRAM 31 of the block A32 continues, the counter 20 counts the number of times that the access of the block A32 has priority, and the count value is incremented to a certain number. If it has, the priority of block A32 is lowered and the delay adjustment circuit 12 performs delay adjustment processing.

As described above, according to the memory control device of the present embodiment, it is possible to always reliably read the data of DRAM 31 by adjusting the delay value periodically.

(Embodiment 5) FIG. 6 is a configuration diagram of a memory control device according to Embodiment 5 of the present invention. In the drawings, the same or corresponding parts as in FIGS. 1 to 4 are denoted by the same reference numerals, and description thereof will be omitted. 17 is a temperature monitor. The enable signal generation circuit 100 has the same configuration and operation as in the first embodiment, so that the description is omitted. '

The operation of the memory control device having the above-described configuration according to the fifth embodiment of the present invention will be described below, and thereby, one embodiment of the memory control method of the present invention will be described. However, parts common to Embodiments 2 to 4 are omitted, and only differences are described.

While the memory control device 1 is operating, the wiring delay to the data bus 110 changes due to a change in temperature or the like, and there is a possibility that read data cannot be taken. In such a case, the temperature monitor 17 monitors the temperatures of the DRAM 31 and the memory controller 1, and if there is a change from the temperature when the block A 32 previously accessed the DRAM 31, the delay adjustment circuit 1 2 performs delay adjustment processing. This makes it possible to set the optimum delay value according to the temperature change during operation. As shown in FIG. 6, the temperature at which the delay adjustment circuit 12 performs the delay adjustment is not limited to the temperature of the previous DRAM 31 and the memory controller 1 but may be a value that can be externally set by the register 19. You may. Of course, the register 19 may be omitted. In the above operation, if the arbitration circuit 21 permits access to the DRAM 31 of the block A32 and the access is being made, the arbitration circuit 21 gives priority to that access and does not perform the delay adjustment processing. Alternatively, the delay adjustment processing is performed after the access to the DRAM 31 of the block A32 is completed.

If access to DRAM 31 in block A32 continues, counter 20 counts the number of times block A32 has been given priority in access. When the count value reaches a certain number, the priority of block A32 is lowered, and the delay adjustment circuit 12 performs delay adjustment processing.

As described above, according to the memory control device of the present embodiment, even if a wiring delay occurs due to an unpredicted temperature change, the delay value is adjusted, so that the DRAM 31 data can always be read reliably. It is possible to do.

(Embodiment 6)

FIG. 7 is a configuration diagram of a memory control device according to Embodiment 6 of the present invention. In the drawings, the same or corresponding parts as in FIGS. 1 to 4 are denoted by the same reference numerals, and description thereof will be omitted. Reference numeral 18 denotes a power supply voltage monitor. The description of the enable signal generation circuit 100 is omitted because the same configuration and operation as in the first embodiment are performed.

The operation of the memory control device according to Embodiment 5 of the present invention having the above-described configuration will be described below, and an embodiment of the memory control method of the present invention will be described. However, parts common to Embodiments 2 to 5 are omitted, and only differences are described.

During the operation of the memory controller 1, the wiring delay changes to the data path 110 due to a change in the power supply voltage or the like, and there is a possibility that the read data cannot be taken. In such a case, the power supply voltage monitor 18 monitors the power supply voltage of the memory controller 1 and delays if there is a change from the voltage when block A 32 previously accessed the DRAM 31. Adjustment circuit 12 performs delay adjustment processing. This makes it possible to set the optimum delay value according to the voltage change during operation. In addition, as shown in FIG. 7, the voltage at which the delay adjustment circuit 12 performs the delay adjustment is not limited to the voltage at which the block A 32 previously accessed the DRAM 31 but may be externally applied to the register. It may be a value that can be set according to 19. Of course, the register 19 may be omitted. In the above operation, the arbitration circuit 21 permits access to the DRAM 31 of the block A 32, and when the access is being made, the arbitration circuit 21 gives priority to the access, and the delay adjustment processing is performed. Should not be performed, or delay adjustment processing will be performed after the access of block A32 to DRAM 31 is completed. "

If access to DRAM 31 of block A 32 continues, counter 20 counts the number of times that block A 32 has priority over access, and the count value reaches a certain number. In this case, the priority of the block A32 is lowered, and the delay adjustment circuit 12 performs the delay adjustment processing.

As described above, according to the memory control device of the present embodiment, even if a wiring delay occurs due to an unexpected power supply voltage change, the delay value is adjusted, so that the data of the DRAM 31 is always reliably read. It is possible to do.

Note that the power supply voltage monitor of the present embodiment is an example of the voltage monitor of the present invention, and the voltage monitor of the present invention is not limited to the operation of the above embodiment, and may be a predetermined portion of the memory control device 內, or The voltage of the block performing data access may be monitored.

(Embodiment 7).

FIG. 8 is a configuration diagram of a memory control device according to Embodiment 7 of the present invention. In the drawings, the same or corresponding parts as in FIGS. 1 to 4 are denoted by the same reference numerals, and description thereof will be omitted. 33 is an error detection block. The description of the enable signal generation circuit 10 is omitted in order to perform the same configuration and operation as in the first embodiment.

The operation of the memory control device according to the seventh embodiment of the present invention having the above-described configuration will be described below, and thereby an embodiment of the memory control method of the present invention will be described. However, the implementation Parts common to modes 2 to 4 are omitted, and only differences are described.

If an error is detected as a result of error detection performed by the error detection block 33 accessing the DRAM 31, there is a possibility that the data recorded in the DRAM 31 cannot be reliably captured in addition to the actual error. Is also conceivable. '.

In such a case, the counter 20 counts the number of error detections per specific number of codewords to be detected, and when the number of times exceeds a certain number, the delay adjusting circuit 12 adjusts the delay. Perform processing. At this time, a fixed number of error detection times may be set in an externally rewritable register 19 or may be stored in the DRAM 31 as a constant in advance. When the data is stored in the DRAM 31, the register 19 may be omitted.

In the above operation, the arbitration circuit 21 permits access to the DR A M31 of the block A32, and if access is being made, the arbitration circuit 21 gives priority to the access and does not perform the delay adjustment processing. Or, after the access to the DRAM 31 of the block A 32 is completed, the delay adjustment processing a is performed.

When the access to the DRAM 31 of the block A32 continues, the counter 20 counts the number of times that the access of the block A32 is prioritized, and when the count value reaches a certain number, the block counts. Lower the priority of A32 so that the delay adjustment circuit 12 performs delay adjustment processing.

As described above, according to the memory control device of the present embodiment, it is possible to prevent an increase in the number of error detections due to incorrect reading of the DRAM 31.

(Embodiment 8). FIG. 9 is a configuration diagram of a memory control device according to the eighth embodiment of the present invention. In the drawings, the same or corresponding parts as in FIGS. 1 to 4 are denoted by the same reference numerals, and description thereof will be omitted. Reference numeral 34 denotes an error correction block. The description of the enable signal generation circuit 100 is omitted because it performs the same configuration and operation as in the first embodiment. '

The operation of the memory control device according to the eighth embodiment of the present invention having the above-described configuration will be described below, and thereby an embodiment of the memory control method of the present invention will be described. However, portions common to Embodiments 2 to 4 are omitted, and only differences are described.

If the error correction block 34 makes an error correction by accessing the DRAM 31, if the error occurs, the data recorded in the DRAM 31 as well as the data that actually contains the error will be confirmed. There is a possibility that they cannot be imported to the Internet.

In such a case, the number of error corrections is counted by the counter 20, and when the number of corrections becomes larger than a certain number, the delay adjusting circuit 12 performs a delay adjusting process. At this time, the fixed number of error correction times may be set to the number set in the externally rewritable register 19, or may be stored in the DRAM 31 as a constant in advance. When the data is held in DRAM 31, the register 19 may be omitted.

In the above operation, the arbitration circuit 21 permits access to the DRAM 31 of the block A 32, and when the access is being performed, the arbitration circuit 21 gives priority to the access, and the delay adjustment processing is performed. Either this is not performed, or delay adjustment processing is performed after access to DRAM 31 of block A 32 is completed. '

Also, if access to DRAM 31 of block A 32 continues, In this case, the counter 20 counts the number of times that the block A32 has been given priority for access, and when the count value reaches a certain number, the priority of the block A32 is lowered, and the delay adjustment circuit 12 performs the delay adjustment processing. Try to do it. The number of times at this time may be retained in the DRAM 31 with the force set in the register 19. '

As described above, according to the memory control device of the present embodiment, it is possible to prevent an increase in the number of uncorrectable errors due to incorrect reading of the DRAM 31.

(Embodiment 9)

FIG. 10 is a configuration diagram of a memory control device according to Embodiment 9 of the present invention. In the drawings, the same or corresponding parts as in FIGS. 1 to 4 are denoted by the same reference numerals, and description thereof will be omitted. However, description of the enable signal generation circuit 100 is omitted because the same configuration and operation as those in the first embodiment are performed.

The operation of the memory control device according to the ninth embodiment of the present invention having the above configuration will be described below, and thereby, one embodiment of the memory control method of the present invention will be described. . However, portions common to Embodiments 2 to 4 are omitted, and only differences are described.

The memory control device according to the present embodiment performs delay adjustment processing in accordance with the number of times of writing of the block A3'2, and counts the number of times that the block A32 has written to the DR A31 by the counter 20, and When the number of times of writing becomes larger than a certain number, the delay adjusting circuit 12 performs a delay adjusting process. At this time, a fixed number of write times may be set in the externally rewritable register 19, or may be stored in the DRAM 31 as a constant in advance. When the data is stored in the DRAM 31, the register 19 may be omitted.

As described above, according to the memory control device of the present embodiment, the DRA By adjusting the delay value every time the number of writes to M31 reaches a specific number, it is possible to always read the data of DRAM31 reliably.

Note that the memory control device according to each embodiment of the present invention may be realized in one memory control device as shown in FIG. 11, and in this case, the environment surrounding the memory control device, the data access The optimal data capture timing can be obtained according to various conditions, such as the situation and the number of times.

Further, the memory of the present invention is a DRAM in each embodiment, but may be an SRAM in other embodiments. In this case, the same effect as described above can be obtained.

Further, although the embodiments of the present invention have been described as a configuration in which the DRAM outputs read data to the data path 110 by outputting an enable signal, the present invention provides a memory such as an SDRAM. The operation may be implemented as a memory control device for a memory whose operations are all synchronized with a clock, output data without using an enable signal, and can be determined on a data bus. That is, the present invention is implemented as a memory control device having no enable signal generation unit 100 or means equivalent thereto. In each of the above embodiments, the delay value of the delay adjustment circuit 12 is determined by the temperature monitor 17. The voltage may be changed based on the temperature measured by the power supply or the voltage measured by the power supply voltage monitor 18. Further, it may be changed based on a predetermined cycle set by the timer 16 and the counter 20.

In the above description, the memory control device according to the embodiment of the present invention has been described. However, the present invention relates to all or a part of the memory control device of the present invention described above (or the device). , Elements, circuits, sections, etc.) by a computer. It may be a program that operates in cooperation with a computer.

Further, the present invention is a program for causing a computer to execute all or some of the steps (or steps, operations, actions, etc.) of the above-described memory control method of the present invention. May be a program that works

The present invention is a medium which carries a program for causing a computer to execute all or a part of the functions of all or part of the memory control device of the present invention described above. The read program may be a medium that executes the function in cooperation with the computer.

The present invention is a medium that carries a program for causing a computer to execute all or a part of the operations of all or some of the above-described memory control methods of the present invention. The read program may be a medium that executes the operation in cooperation with the computer.

Note that some means (or devices, elements, circuits, units, and the like) of the present invention and some steps (or steps, operations, functions, and the like) of the present invention refer to a plurality of these means or steps. Means several means or steps within, or means some function or part of one means or step.

Further, some devices (or elements, circuits, units, and the like) of the present invention mean several devices among a plurality of devices, or one device among one device. It means a unit means (or an element, a circuit, a unit, or the like), or means a part of functions of a group of three means.

Further, a computer-readable recording medium that records the program of the present invention is also included in the present invention. One use form of the program of the present invention may be a form in which the program is recorded on a computer-readable recording medium and operates in cooperation with the computer.

Further, one usage form of the program of the present invention may be a mode in which the program is transmitted through a transmission medium, read by a computer, and operates in cooperation with a π computer. .

Further, the data structure of the present invention includes a database, a data format, a data table, a data list, a data type, and the like.

The recording medium includes ROM and the like, and the transmission medium includes a transmission medium such as the Internet, light, radio waves, and sound waves.

The computer of the present invention described above is not limited to pure hardware such as a CPU, but may include a firmware, an OS, and peripheral devices.

As described above, the configuration of the present invention may be implemented in a software manner or in hardware. INDUSTRIAL APPLICABILITY As is clear from the above description, according to the present invention, it is possible to adjust the timing at which the read data is captured, and to surely recover the read data even in various situations. Data can be captured.

Claims

The scope of the claims

1. A clock generation circuit for generating a clock,

A delay adjustment circuit that performs a delay adjustment process of delaying the clock by a variable delay value, and outputs the captured clock.

A memory control device comprising: a read data register for reading and storing data recorded in a memory based on the take-in clock.

2. The memory control device according to claim 1, wherein the delay adjustment circuit starts the delay adjustment process based on an environmental change around the memory control device.

3. The memory control device according to claim 1, wherein the delay adjustment circuit starts the delay adjustment processing at a predetermined cycle.

4. The memory control device according to claim 1, wherein the delay adjustment circuit starts delay adjustment processing based on an error detection or error correction operation for the memory.

5. The memory control device according to claim 1, wherein the delay adjustment circuit changes the delay value based on an environmental change around the memory control device. '-

6. The memory control device according to claim 1, wherein the delay adjustment circuit changes the delay value based on a predetermined cycle.

7. The memory according to claim 1, wherein the delay adjustment circuit has one or a plurality of delay elements, and performs the quick delay processing by passing the clock through a predetermined number of the delay elements. Control device.

8. The memory control device according to claim 1, wherein the delay adjustment circuit can adjust a delay amount in the delay adjustment process by external control.

9. A comparison data register for storing the same data as the data to be recorded in the memory;

A comparison circuit for comparing the data stored in the read data register with the data stored in the comparison data register, wherein a predetermined address in the memory and predetermined data in the comparison data register are provided. After the data is written, the read data register reads the predetermined data, and the comparison circuit reads the predetermined data in the read data register and the predetermined data in the comparison data register. The memory control device according to any one of claims 1 to 8, wherein the memory control device performs a write / read confirmation process for collating with a memory.

10. The memory control device according to claim 9, further comprising a register whose contents can be rewritten externally, wherein the comparison circuit performs the write / read confirmation processing using data set in the register. .

11. The memory control device according to claim 9, wherein at least the predetermined address of the memory is set in the register.

12. The delay adjustment circuit performs the delay adjustment processing after the end of the write / read confirmation processing.

After the delay adjustment processing is performed, the comparison circuit performs the write Z read repetition confirmation processing for performing the write Z read confirmation processing again, and performs the write / read confirmation processing or the write Z ′ read. 10. The memory control device according to claim 9, wherein the delay value is optimized by a confirmation process and the write / read repetition confirmation process.

13. The memory control according to claim 1, wherein the delay adjustment circuit performs the delay adjustment processing when a control signal is input from the outside.

14. The memory control device according to claim 13, wherein the external signal is a signal indicating power-on of the memory control device.

15. The memory control device according to claim 13, wherein the external signal is a signal indicating initialization or reset of the memory control device.

16. The memory control device according to claim 13, wherein the external signal is a signal indicating a return from the sleep state of the memory control device.

1 7. Access to blocks that have access to the memory

And further comprising an arbitration circuit for determining the priority of access to the block,

10. The memory control device according to claim 9, wherein the arbitration circuit performs the delay adjustment processing when at least confirming that the block does not access the memory.

18. The memory control device according to claim 17, wherein the arbitration circuit does not perform the delay adjustment processing when the arbitration circuit confirms that the block is accessing the memory.

1 9. A counter for counting a predetermined number of times that can be set externally or by the register,

If the arbitration circuit confirms that the block is accessing the memory, the delay adjustment circuit does not perform the delay adjustment processing, increments the value of the counter, and sets the value of the counter to a predetermined value. 10. The memory control device according to claim 9, wherein the delay adjustment processing is performed when the value of the memory control value becomes:

20. Further equipped with a timer to measure time,

The memory control device according to claim 19, wherein the delay adjustment circuit performs the delay adjustment process at predetermined time intervals based on the time measurement of the timer.

21. The memory control device according to claim 21, wherein the predetermined time can be set in the register.

2 2. It is further equipped with a temperature monitor that measures the temperature.

10. The memory control according to claim 9, wherein the delay adjustment circuit performs the delay adjustment processing based on a temperature change of the block having an access right to the memory. 11. apparatus. ,

23. A predetermined temperature can be set in the register,

23. The memory control device according to claim 22, wherein the delay adjustment process is performed when the temperature monitor detects the predetermined temperature. '

2 4. A voltage monitor for measuring voltage is further provided.

10. The delay adjustment circuit according to claim 9, wherein the delay adjustment circuit performs the delay adjustment processing based on a block having an access right to the memory or a voltage change of the memory control device. 11. Memory control device. .

25. A predetermined voltage can be set in the register,

25. The memory control device according to claim 24, wherein when the voltage monitor detects a voltage equal to or higher than the predetermined voltage, the delay adjustment process is performed.

26. When an error detection block having an access right to the memory performs error detection by accessing the memory, the number of error detections per specific number of codewords subject to error detection is: 10. The memory control device _{c27 according} to any one of claims 9, 10, and 19, wherein when the number of times exceeds a predetermined number, the delay adjustment circuit performs the delay adjustment processing. If the error correction block having access right performs error correction by accessing the memory, and if the number of error corrections is greater than a predetermined number, the delay adjustment circuit performs the delay adjustment processing. Any of claims 9, 10, or 19 to be made 3. The memory control device according to 1.

28. The delay adjusting circuit performs the delay adjusting process when the number of times that the block having an access right to the memory writes data to the memory reaches a predetermined number. , 10, or 19.

29. The memory control device according to claim 26, wherein the predetermined number of times can be set in the register.

30. A clock generation step of generating a clock,

A delay adjusting step of performing a delay adjusting process for delaying the mouthpiece with a variable delay value and outputting the captured clock.

A read data register storing step of reading data recorded in a memory and storing the read data in a read data register based on the capture clock. '

31. The memory control method according to claim 30, wherein the delay adjustment step starts the delay adjustment processing based on an environmental change around the memory control device. .

32. The memory control method according to claim 30, wherein the delay adjustment step starts the delay adjustment processing at a predetermined cycle. '

33. The memory control step according to claim 30, wherein the delay adjustment step starts delay adjustment processing based on an error detection or error correction operation for the memory.

3 4. A comparison data register storing step of storing the same data as the data to be recorded in the memory in the comparison data register; and the data stored in the read data register and the comparison data register. A comparison step of comparing the data stored in the data register step with the data stored in the data register step. After the predetermined data in the memory and the predetermined data are written in the comparison data register, the predetermined data is read from the read data register. 30. The memory control method according to claim 30, wherein a write Z read confirmation process is performed for comparing the predetermined data in the comparison data with the predetermined data in the comparison data register. ,

35. The memory control device according to claim 1, wherein the clock generation circuit generates a clock, and the clock adjustment circuit performs delay adjustment processing for delaying the clock with a variable delay value and outputs the clock as a fetched clock. A program for causing a computer to function as all or part of a circuit and a read data register that reads and stores data recorded in a memory based on the capture clock.

36. The memory control method according to claim 30, wherein a clock generation step of generating a clock;

Performing a delay adjustment process of delaying with a variable delay value on the mouthpiece; a delay adjustment step of outputting as a capture clock;

A program for causing a computer to execute all or part of a read data register storage step of reading data recorded in a memory and storing the data in a read data register based on the capture clock.

37. The memory control device according to claim 1, wherein the clock generation circuit generates a clock, and performs delay adjustment processing for delaying the clock with a variable delay value, and outputs a delay as a capture clock. A medium carrying a program for causing a computer to function as all or part of a circuit and a read data register that reads and stores data recorded in a memory based on the fetch clock. A medium characterized by being processable by a computer.

38. The memory control method according to claim 30, wherein: a clock generation step of generating a clock; and a delay adjustment processing of performing a delay adjustment process of delaying the clock with a variable delay value and outputting the clock as a capture clock. And causing the computer to execute all or part of a read data register storing step of reading data recorded in a memory and storing the data in a read data register based on the capture clock. A medium carrying a program, which can be processed by a computer.