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WO2002000969A1 - Procede de fabrication d'une tranche de silicium et d'une tranche epitaxiale ;tranche epitaxiale - Google Patents

Procede de fabrication d'une tranche de silicium et d'une tranche epitaxiale ;tranche epitaxiale Download PDF

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Publication number
WO2002000969A1
WO2002000969A1 PCT/JP2001/005360 JP0105360W WO0200969A1 WO 2002000969 A1 WO2002000969 A1 WO 2002000969A1 JP 0105360 W JP0105360 W JP 0105360W WO 0200969 A1 WO0200969 A1 WO 0200969A1
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
silicon
single crystal
epitaxy
nitrogen
Prior art date
Application number
PCT/JP2001/005360
Other languages
English (en)
Japanese (ja)
Inventor
Makoto Iida
Yoshinori Hayamizu
Akihiro Kimura
Original Assignee
Shin-Etsu Handotai Co., Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin-Etsu Handotai Co., Ltd filed Critical Shin-Etsu Handotai Co., Ltd
Priority to JP2002506275A priority Critical patent/JP4102988B2/ja
Publication of WO2002000969A1 publication Critical patent/WO2002000969A1/fr

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Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
    • C30B15/20—Controlling or regulating
    • C30B15/203—Controlling or regulating the relationship of pull rate (v) to axial thermal gradient (G)

Definitions

  • CZ method Czochralski method
  • the nitrogen concentration must be 1 ⁇ 10 14 / cm 3 or less to suppress the generation of epi defects and heat treatment at 800 ° C for 4 hours and at 100 ° C for 16 hours after epitaxial growth
  • the VG during single crystal growth is set to a sufficiently high value so that the BMD generated at the same time becomes a predetermined density
  • the BMD for generating the BMD density that can obtain a sufficient gettering effect in the device process It turned out that a nucleus could be obtained.
  • the V / G variation can be in the range of ⁇ 0.015 mm 2 / K ⁇ min in the radial direction of the silicon single crystal to be grown.
  • an epitaxy wafer having an extremely high IG capability and having an epi layer free of epi defects produced by the production method.
  • Ru can and child to the nitrogen concentration in the silicon Konueha and 1 XI 0 13 ⁇ 1 XI 0 14 pieces / cm 3.
  • a silicon wafer having a dislocation loop density of 20 cm 2 or less on the surface of the silicon wafer serving as a substrate is provided. Since an epitaxy wafer having a layer formed thereon is provided, an epitaxy wafer with few epi defects can be reliably obtained.
  • an annular solid-liquid interface heat insulator 8 is provided on the periphery of the solid-liquid interface of the crystal, Upper surrounding insulation 9 is arranged.
  • the solid-liquid interface insulation 8 has a gap 10 to 5 cm between its lower end and the surface of the silicon melt 2. Is installed.
  • the upper surrounding insulation 9 may not be used depending on the conditions.
  • a cylindrical cooling device 36 for spraying a cooling gas or cooling the single crystal by blocking radiant heat may be provided.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

Cette invention concerne un procédé de fabrication d'une tranche de silicium à partir d'un monocristal de silicium tiré par la méthode CZ (Czochralski) et dopé à l'azote, caractérisé en ce que l'azote est dopé en concentrations de 1 X 1014 éléments/cm3 ou moins et, lors de la croissance du monocristal de silicium, le rapport (V/G) entre le taux de croissance (V) et le gradient de température de l'interface solide-liquide (G) est ajusté pour que l'on obtienne la densité de microdéfauts volumiques (BMD) requise après formation d'une couche épitaxiale sur la tranche de silicium produite. L'invention concerne également un procédé d'obtention d'une tranche épitaxiale consistant à former une couche épitaxiale sur la tranche de silicium produite selon cette méthode, ainsi qu'une tranche épitaxiale ainsi obtenue. Ces procédés peuvent s'utiliser pour former un substrat pour couche épitaxiale qui est éliminé lors la formation de défauts cristallins pendant la croissance d'une tranche de monocristal de silicium dopé à l'azote, tiré par la méthode CZ, et qui présente par ailleurs une remarquable capacité IG, ainsi que pour la fabrication d'une tranche épitaxiale au moyen du substrat.
PCT/JP2001/005360 2000-06-26 2001-06-22 Procede de fabrication d'une tranche de silicium et d'une tranche epitaxiale ;tranche epitaxiale WO2002000969A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002506275A JP4102988B2 (ja) 2000-06-26 2001-06-22 シリコンウエーハおよびエピタキシャルウエーハの製造方法ならびにエピタキシャルウエーハ

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2000-191047 2000-06-26
JP2000191047 2000-06-26
JP2001-16696 2001-01-25
JP2001016696 2001-01-25

Publications (1)

Publication Number Publication Date
WO2002000969A1 true WO2002000969A1 (fr) 2002-01-03

Family

ID=26594668

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2001/005360 WO2002000969A1 (fr) 2000-06-26 2001-06-22 Procede de fabrication d'une tranche de silicium et d'une tranche epitaxiale ;tranche epitaxiale

Country Status (3)

Country Link
JP (1) JP4102988B2 (fr)
TW (1) TW575696B (fr)
WO (1) WO2002000969A1 (fr)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002076007A (ja) * 2000-08-31 2002-03-15 Mitsubishi Materials Silicon Corp エピタキシャルウェーハの製造方法及びその方法により製造されたエピタキシャルウェーハ
JP2003002786A (ja) * 2001-06-25 2003-01-08 Shin Etsu Handotai Co Ltd シリコン単結晶基板、エピタキシャルウエーハおよびこれらの製造方法
JP2003286094A (ja) * 2002-03-27 2003-10-07 Sumitomo Mitsubishi Silicon Corp 半導体シリコン基板の製造方法
JP2004304095A (ja) * 2003-04-01 2004-10-28 Sumitomo Mitsubishi Silicon Corp シリコンウェーハおよびその製造方法
JP2013147407A (ja) * 2012-01-23 2013-08-01 Shin Etsu Handotai Co Ltd シリコン単結晶ウエーハ、その酸素析出量の面内均一性評価方法、シリコン単結晶の製造方法
WO2016019051A1 (fr) * 2014-07-31 2016-02-04 Sunedison Semiconductor Limited Lingot de silicium dopé par de l'azote et dominé par des lacunes et tranche thermiquement traitée formée à partir de ce dernier ayant une densité et une taille de précipités avec de l'oxygène radialement uniformément distribuées
JP2017050490A (ja) * 2015-09-04 2017-03-09 株式会社Sumco エピタキシャルシリコンウェーハ
KR20190135913A (ko) 2018-05-29 2019-12-09 신에쯔 한도타이 가부시키가이샤 실리콘 단결정의 제조방법, 에피택셜 실리콘 웨이퍼 및 실리콘 단결정 기판
CN115404539A (zh) * 2022-08-30 2022-11-29 西安奕斯伟材料科技有限公司 直拉法拉制单晶硅棒的方法、单晶硅棒、硅片及外延硅片

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6447351B2 (ja) 2015-05-08 2019-01-09 株式会社Sumco シリコンエピタキシャルウェーハの製造方法およびシリコンエピタキシャルウェーハ

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11189493A (ja) * 1997-12-25 1999-07-13 Sumitomo Metal Ind Ltd シリコン単結晶およびエピタキシャルウェーハ
WO1999057344A1 (fr) * 1998-05-01 1999-11-11 Nippon Steel Corporation Plaquette de semi-conducteur en silicium et son procede de fabrication

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1179889A (ja) * 1997-07-09 1999-03-23 Shin Etsu Handotai Co Ltd 結晶欠陥が少ないシリコン単結晶の製造方法、製造装置並びにこの方法、装置で製造されたシリコン単結晶とシリコンウエーハ
JP3771737B2 (ja) * 1998-03-09 2006-04-26 信越半導体株式会社 シリコン単結晶ウエーハの製造方法
JP4084902B2 (ja) * 1998-05-01 2008-04-30 シルトロニック・ジャパン株式会社 シリコン半導体基板及びその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11189493A (ja) * 1997-12-25 1999-07-13 Sumitomo Metal Ind Ltd シリコン単結晶およびエピタキシャルウェーハ
WO1999057344A1 (fr) * 1998-05-01 1999-11-11 Nippon Steel Corporation Plaquette de semi-conducteur en silicium et son procede de fabrication

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002076007A (ja) * 2000-08-31 2002-03-15 Mitsubishi Materials Silicon Corp エピタキシャルウェーハの製造方法及びその方法により製造されたエピタキシャルウェーハ
JP2003002786A (ja) * 2001-06-25 2003-01-08 Shin Etsu Handotai Co Ltd シリコン単結晶基板、エピタキシャルウエーハおよびこれらの製造方法
JP2003286094A (ja) * 2002-03-27 2003-10-07 Sumitomo Mitsubishi Silicon Corp 半導体シリコン基板の製造方法
JP2004304095A (ja) * 2003-04-01 2004-10-28 Sumitomo Mitsubishi Silicon Corp シリコンウェーハおよびその製造方法
JP4670224B2 (ja) * 2003-04-01 2011-04-13 株式会社Ｓｕｍｃｏ シリコンウェーハの製造方法
JP2013147407A (ja) * 2012-01-23 2013-08-01 Shin Etsu Handotai Co Ltd シリコン単結晶ウエーハ、その酸素析出量の面内均一性評価方法、シリコン単結晶の製造方法
KR20170038017A (ko) * 2014-07-31 2017-04-05 썬에디슨 세미컨덕터 리미티드 질소 도핑 및 공공 지배 실리콘 잉곳 및 그로부터 형성된, 반경방향으로 균일하게 분포된 산소 석출 밀도 및 크기를 갖는 열 처리 웨이퍼
WO2016019051A1 (fr) * 2014-07-31 2016-02-04 Sunedison Semiconductor Limited Lingot de silicium dopé par de l'azote et dominé par des lacunes et tranche thermiquement traitée formée à partir de ce dernier ayant une densité et une taille de précipités avec de l'oxygène radialement uniformément distribuées
JP2017528404A (ja) * 2014-07-31 2017-09-28 サンエディソン・セミコンダクター・リミテッドＳｕｎＥｄｉｓｏｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｌｉｍｉｔｅｄ 窒素ドープされた空孔優勢であるシリコンインゴット、およびそれから形成された半径方向に均一に分布した酸素析出の密度およびサイズを有する熱処理されたウエハ
US20180266016A1 (en) * 2014-07-31 2018-09-20 SunEdison Semiconductor Limited (UEN20133416H) Nitrogen Doped and Vacancy Dominated Silicon Ingot and Thermally Treated Wafer Formed Therefrom Having Radially Uniformly Distributed Oxygen Precipitation Density and Size
JP2020079195A (ja) * 2014-07-31 2020-05-28 グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． 窒素ドープされた空孔優勢であるシリコンインゴット、およびそれから形成された半径方向に均一に分布した酸素析出の密度およびサイズを有する熱処理されたウエハ
KR102175689B1 (ko) 2014-07-31 2020-11-09 글로벌웨이퍼스 씨오., 엘티디. 질소 도핑 및 공공 지배 실리콘 잉곳 및 그로부터 형성된, 반경방향으로 균일하게 분포된 산소 석출 밀도 및 크기를 갖는 열 처리 웨이퍼
US10988859B2 (en) 2014-07-31 2021-04-27 Globalwafers Co., Ltd. Nitrogen doped and vacancy dominated silicon ingot and thermally treated wafer formed therefrom having radially uniformly distributed oxygen precipitation density and size
US11111602B2 (en) 2014-07-31 2021-09-07 Globalwafers Co., Ltd. Nitrogen doped and vacancy dominated silicon ingot and thermally treated wafer formed therefrom having radially uniformly distributed oxygen precipitation density and size
US11753741B2 (en) 2014-07-31 2023-09-12 Globalwafers Co., Ltd. Nitrogen doped and vacancy dominated silicon ingot and thermally treated wafer formed therefrom having radially uniformly distributed oxygen precipitation density and size
JP2017050490A (ja) * 2015-09-04 2017-03-09 株式会社Sumco エピタキシャルシリコンウェーハ
KR20190135913A (ko) 2018-05-29 2019-12-09 신에쯔 한도타이 가부시키가이샤 실리콘 단결정의 제조방법, 에피택셜 실리콘 웨이퍼 및 실리콘 단결정 기판
CN115404539A (zh) * 2022-08-30 2022-11-29 西安奕斯伟材料科技有限公司 直拉法拉制单晶硅棒的方法、单晶硅棒、硅片及外延硅片

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TW575696B (en) 2004-02-11
JP4102988B2 (ja) 2008-06-18

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