WO2002049089A1

WO2002049089A1 - Method of etching porous insulating film, dual damascene process, and semiconductor device

Info

Publication number: WO2002049089A1
Application number: PCT/JP2001/010933
Authority: WO
Inventors: Li-Hung Chen; Koichiro Inazawa; Tomoki Suemasa
Original assignee: Tokyo Electron Limited
Priority date: 2000-12-14
Filing date: 2001-12-13
Publication date: 2002-06-20
Also published as: AU2002222632A1; JPWO2002049089A1; TWI223341B

Abstract

A method of etching a porous insulating film with a plasma which comprises using as a treating gas a gas mixture comprising a fluorocarbon gas, e.g., CF4, and an inert gas, e.g., argon, and regulating the pressure to a value of 150 to 300 mTorr to thereby inhibit spike generation during the etching. The RF power density is preferably 0.25 to 0.50 W/cm2.

Description

Method for etching porous insulating film, dual damascene process and semi-etching method

Technical field

The present invention relates to a method for etching a porous insulating film, and a dual damascene process.

And semiconductor devices.

Field background technology

With the recent increase in the density of semiconductor integrated circuits, interconnect propagation delay is becoming an important factor in determining the operating speed. For this reason, a low-dielectric-constant film is used as an interlayer insulating film to suppress propagation delay.

As a method of lowering the relative dielectric constant of the interlayer insulating film, there is a method of making the interlayer insulating film porous. When a porous insulating film is employed in a semiconductor manufacturing process, it is necessary to etch the porous insulating film in order to form a via hole or the like.

In this method of etching a porous insulating film, C ₄ F ₈ / A r is used to efficiently perform etching of the porous insulating film while ensuring a certain selectivity between the porous insulating film and the photoresist. System gas, CF ₄ / Ar system gas, etc. were used. Also, in order to improve the etching rate and to cope with etching with a high aspect ratio, O ₂ , CO or N ₂ is mixed with these gases.

In addition, during the festival in which these etching gases are turned into plasma to perform etching, the mean free path of the ions is lengthened to make it easier for ions to enter the contact holes and to maintain in-plane uniformity during etching. Low Etching was performed with high pressure and high output.

However, mixing the 0 ₂ gas in the etching gas, the etching is performed porous insulating film at a low pressure and the conditions of high output, spike there is a problem that occurs in the porous insulating film. In particular, the occurrence of this spike became a more serious problem in the dual damascene process. Note that the spike is the unevenness on the bottom surface of the etched porous insulating film.

FIG. 8 is a cross-sectional view showing a conventional dual damascene process using a porous insulating film. In FIG. 8 (a), a porous insulating film 42 and a silicon nitride film 43 are formed on the lower region 41, and the opening corresponding to the via hole B2 is formed by using a photolithography technique and an etching technique. A portion H 3 is formed on the silicon nitride film 43. The lower region 41 is a silicon substrate or a lower wiring layer such as Cu or A1.

Next, a porous insulating film 44 is formed on the silicon nitride film 43, and a photoresist film 45 is formed on the entire surface. Then, an opening H4 corresponding to the wiring groove T2 is formed in the photoresist film 45 by using photolithography technology.

Next, as shown in FIG. 8 (b), by using this photoresist film 45 as a mask, etching E3 such as RIE is performed to form a wiring groove T2 in the porous insulating film 44. Here, as an etch Ngugasu in etching E 3, in order to ensure the selectivity of the porous insulating film 4 4 and the silicon nitride film 4 3, C ₄ F ₈ based gas is used. In addition, the pressure is set to a low pressure of less than 5 ° mTorr and the RF power density is set to 0.5 W in order to increase the etching rate and maintain in-plane uniformity during etching.

It is set to a high output exceeding / cm ^2.

When the etching E3 of the porous insulating film 44 is performed under these conditions, a spike SP occurs in the porous insulating film 44. For this reason, etching E 3 If the etching is stopped during the etching of the insulating film 44, the spike SP remains on the step D2 of the wiring groove T2.

Next, as shown in FIG. 8C, the etching E 3 is further continued using the silicon nitride film 43 as a mask, and a via hole B 2 is formed in the porous insulating film 42. Here, on the step D 2 of the silicon nitride film 4 3, the porous insulating film 4

4 is performed to remove the spike SP on the step D2. Also, spikes generated in the porous insulating film 42 when forming the via hole B2 can be removed by over-etching the porous insulating film 42.

Next, as shown in FIG. 8D, the photoresist 45 is removed, and a conductive material such as Cu or A1 is deposited on the entire surface. Then, the vias 46 and the wirings 47 are formed simultaneously by flattening the surface of the conductive material by CMP (chemical mechanical polishing) or the like.

As described above, in the conventional dual damascene process, since the silicon nitride film 43 serving as the superposition is provided between the porous insulating films 42 and 44, the porous insulating film 44 is over-etched. By this spike

SP can be removed.

However, in the dual damascene process, the porous insulating film 4

When the silicon nitride film 43 is provided between the layers 2 and 44, there is a problem that the overall relative dielectric constant increases and the propagation delay of the wiring 47 increases. Disclosure of the invention

Therefore, an object of the present invention is to provide a method for etching a porous insulating film, which can suppress generation of spikes during etching. Another object of the present invention is to provide a dual damascene pump capable of lowering the dielectric constant of an interlayer insulating film while suppressing the occurrence of spikes during etching. Process and a semiconductor device.

In order to solve the above-mentioned problem, the method for etching a porous insulating film of the present invention is characterized in that a processing gas during plasma etching is a mixed gas containing a fluorocarbon-based gas and an inert gas, and the pressure is 15 OmTorr or more. It is characterized by being at most 300 mTorr.

By increasing the pressure to some extent, it is possible to suppress high-energy ions from directly colliding with the etched surface of the porous insulating film, and to suppress physical erosion by high-energy ions. And Further, by setting the pressure within the above range, it is possible to suppress the spike of the porous insulating film within a practical level while suppressing an adverse effect on the CD shift amount and the micro opening when the pressure is increased. It is possible. The CD shift amount is represented by the change in the finished width with respect to the pattern width before etching, and the microloading is (narrow trench etching rate) / (wide trench etching rate) x 100%. expressed.

The etching method of porous insulation film of the present invention, in the above-mentioned method, RF power density, characterized in that 0.2 5 / ^/ 0! 11 ² or more 0.5 is 0 WZ c ni ² below .

In the case of a porous insulating film, the film quality is softer than that of a non-porous insulating film, so that even when the RF power density is reduced, the progress of etching is not extremely hindered. For this reason, spikes in the porous insulating film can be suppressed while preventing the etching characteristics of the porous insulating film from being significantly impaired.

Further, in the method for etching a porous insulating film of the present invention, in the above method, the fluorocarbon-based gas is CF ₄ , and the inert gas is Ar. By using a gas with a high F / C ratio, the porous insulating film can be etched while suppressing the deposition of the carbon-based polymer that causes a decrease in the etching rate, and the RF power density has been reduced. Even in this case, it is possible to secure an etching rate.

The etching method of porous insulation film of the present invention, in the above-mentioned method, wherein the flow rate ratio relative to the Furuoroka one carbon-containing gas further comprises a 0. 2 5 following 0 ₂ gas.

By decreasing the flow rate ratio of 〇 ₂ gas, even when carbon-containing Murrell the porous insulating film, to suppress that the carbon reacts with 0 ₂ gas, carbon is extracted from the porous insulating film This makes it possible to suppress spikes during the etching of the porous insulating film.

Further, the semiconductor device of the present invention is a semiconductor device in which a wiring groove and a via hole are formed by a dual damascene process, wherein the porous insulating film in which the wiring groove is formed and the porous insulating film in which the via hole is formed. The porous insulating film is formed without any intervening stopper layer, and is substantially free of spikes during etching of the porous insulating film.

According to the semiconductor device of the present invention, even when a stopper layer having a high relative dielectric constant is not formed between the porous insulating films, it is possible to suppress the occurrence of spikes in the wiring grooves of the porous insulating film. Thus, it is possible to suppress the propagation delay of the wiring, and to improve the reliability of the wiring embedded in the wiring groove.

Further, the dual damascene process of the present invention includes a step of forming a first photoresist film on which a pattern corresponding to a via hole is formed on a porous insulating film;

Etching the porous insulating film using the first photoresist film as a mask. Forming a via hole in the porous insulating film by performing

Removing the first photoresist film;

Forming a second photoresist film having a pattern corresponding to the wiring groove on the porous insulating film,

0 RF power density is 0. ² 5 W / cm 2 or more. 5 0 W / cm ² or less, the pressure at 1 5 0 mTorr or 3 0 0 mTorr following conditions, the said second photoresist film as a mask Forming a wiring groove in the porous insulating film by partially etching the porous insulating film;

Removing the second photoresist film;

Embedding a conductive material in the via hole and the wiring groove.

According to the dual damascene process of the present invention, it is possible to form a via hole and a wiring groove in a porous insulating film without using a stopper film such as a silicon nitride film, and it is also possible to form a porous insulating film at the time of etching. Spikes can be suppressed, and the dual damascene process can be simplified.

Further, the dual damascene process of the present invention is characterized in that a mixed gas containing a fluorocarbon-based gas and an inert gas is used as a processing gas in the step of forming a wiring groove in the porous insulating film, It is characterized in that the fluorocarbon gas is CF ₄ and the inert gas is Ar.

According to the dual damascene process of the present invention, since there is no scan stopper film such as a silicon nitride film, the selectivity to the scan stopper film and the porous insulating film since it is not necessary to consider, in the C ₄ F ₈ based gas It can be etched porous insulating film with a size not CF ₄ based gas more F / C ratio in place with Do Ri, improving the etching rate for etching the porous insulating film It becomes possible. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a cross-sectional view showing a schematic configuration of an etching apparatus according to one embodiment of the present invention.

FIG. 2 is a sectional view showing a result of etching according to one embodiment of the present invention in comparison with a conventional example.

FIG. 3 is a diagram showing the pressure dependence of the etching characteristic according to one embodiment of the present invention.

FIG. 4 is a diagram showing the RF power density dependency of the etching characteristics according to one embodiment of the present invention.

FIG. 5 is a diagram showing the dependence of the etching characteristics on the 02 flow rate according to one embodiment of the present invention.

FIG. 6 is a diagram showing the bottom temperature dependence of the etching characteristic according to one embodiment of the present invention.

FIG. 7 is a sectional view showing a dual damascene process according to one embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a conventional dual damascene process. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an etching method according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view showing a schematic configuration of an etching apparatus according to one embodiment of the present invention. In this embodiment, a case will be described in which a mixed gas of CF ₄ and A ₄ is used as an etching gas.

In FIG. 1, an upper electrode 2 and a susceptor 3 are provided in a processing chamber 1. This susceptor 3 also serves as the lower electrode. The upper electrode 2 is provided with a gas outlet 2 a for introducing an etching gas into the processing chamber 1. In addition, the susceptor 3 is supported on a susceptor support 4, and the susceptor support 4 is held in the processing chamber 1 via an insulating plate 5. A high-frequency power supply 11 is connected to the susceptor 3 to convert the etching gas introduced into the processing chamber 1 into plasma.

The susceptor support 4 is provided with a refrigerant chamber 10, and a refrigerant such as liquid nitrogen circulates in the refrigerant chamber 10 via the refrigerant supply pipe 10a and the refrigerant discharge pipe 10b. Then, the wafer W can be cooled by transferring the cold generated therefrom to the wafer W via the susceptor support 4 and the susceptor 3.

An electrostatic chuck 6 is provided on the susceptor 3, and the electrostatic chuck 6 has a configuration in which a conductive layer 7 is sandwiched between polyimide films 8a and 8b. Here, a DC high-voltage power supply 12 is connected to the conductive layer 7, and a DC high voltage is applied to the conductive layer 7 to apply a cron force to the wafer W to fix the wafer W on the susceptor 3. can do.

Further, a gas passage 9 for introducing He gas is provided in the susceptor 3 and the electrostatic chuck 6, and He gas is ejected to the back surface of the wafer W through the gas passage 9, thereby forming a susceptor. The wafer W placed on the evening 3 can be cooled. Here, the gas passage 9 is connected to a He gas supply source 16 via a flow control valve 16a and an opening / closing valve 16b, and controls the pressure of the He gas on the back surface of the wafer W. be able to.

The processing chamber 1 is provided with a gas supply pipe 1a and an exhaust pipe 1b. Gas supply pipe 1 a via the flow regulating valve 1 4 a, 1 5 a and the opening and closing valve 1 4 b, 1 5 b, is connected to the CF ₄ gas supply source 1 4 and A r gas source 1 5 I have. The exhaust pipe 1b is connected to a vacuum pump. this By evacuating the inside of the processing chamber 1 with a vacuum pump, the pressure in the processing chamber 1 can be adjusted. A horizontal magnetic field forming magnet 13 is provided around the processing chamber 1, and by applying a magnetic field to the processing chamber 1, the density of plasma can be increased and etching can be performed efficiently.

When etching the porous insulating film, the wafer W on which the porous insulating film is formed is placed on the susceptor 3 and fixed by the electrostatic chuck 6.

Next, the processing chamber 1 is evacuated, the pressure in the processing chamber 1 is adjusted, and the opening and closing valves 14 b and 15 b are opened to introduce CF ₄ gas and Ar gas into the processing chamber 1. The flow ratio between CF ₄ gas and Ar gas can be adjusted by the flow control valves 14 a and 15 a.

Next, the RF power from the high-frequency power supply 11 is applied to the susceptor 3, and the etching gas is turned into plasma to etch the porous insulating film. At this time, the wafer W can be cooled by opening the opening / closing valve 16 b to introduce He gas into the gas passage 9 and ejecting the He gas from the gas passage 9. Further, the cooling temperature of the wafer W can be controlled by adjusting the pressure of the He gas using the flow control valve 16a.

Conditions for etching the porous insulating film are as follows: RF power density is 0.25 to 0.50 W / cm2, and pressure in the processing chamber 1 is 150 to 300 mTorr. Thus, the porous insulating film can be etched to an arbitrary depth while suppressing the generation of spikes.

Incidentally, the porous insulating film, for example, port one Las HSQ (hydrogen silsesquioxane) yarns, port one lath MSQ ^ methyl silsesauioxane) yarns, Porous organic material or a porous S i 0 _2,, density 1. ³ gZcm 3 below Means

Further, in the above-described embodiment, a method of performing etching using a magnetron RIE apparatus has been described. Sound may be applied to plasma etching equipment, HEP (helicon wave excited plasma) etching equipment, ICP (inductively coupled plasma) etching equipment, TCP (transfer coupled plasma) etching equipment, and the like. Hereinafter, examples of the present invention will be described with reference to experimental data. In the following examples, etching was performed using the sample of FIG. 2A and the etching apparatus of FIG. In FIG. 2A, a silicon nitride film 21, a porous MSQ film 22, and an antireflection film 23 are sequentially laminated, and a photo resist film having lines and spaces is formed on the antireflection film 23. 24 are stacked. The thickness of the silicon nitride film 21 was 300 nm, the thickness of the porous MS Q film 22 was 600 nm, the thickness of the antireflection film 23 was 75 nm, and the thickness of the photoresist film 24 was 540 nm. .

2 (b) to 2 (d) are cross-sectional views showing etching results according to one embodiment of the present invention in comparison with a conventional example. Here, as the etching condition of Conventional Example 1, a mixed gas of C ₄ F ₈ , N ₂ , CO and Ar was used at a flow rate ratio of 10/50/200/200 sccm. In addition, the RF power is 1500 W, the pressure is 35 mTorr, the He pressure on the back of the wafer W is 7 Torr at the center, 40 Torr at the edge, the top & wall temperature is 60 ° C, and the bottom temperature is 40 ° C. And etched for 20 seconds. The distance between the electrodes was 37 mm and the diameter of the force source was 260 mm.

In this case, when the line & space is 0.25 m / 0.25 m, the porous MSQ film 22 is etched by 395.8 nm in the depth direction, and the line & space is 0.2. In the pattern of 25 urn / 1.25 zm, the porous MS Q film 22 was etched by 458.3 nm in the depth direction. The etching rate at this time is 1 187. AnmZ seconds for a pattern with a line & space of 0.25 urn 0.25.m, and 1 for a pattern with a line & space of 0.25〃mZl. 25 / m. 3 7 5 nm / Seconds. In addition, as shown in FIG. 2 (b), spikes are generated on the etched surface in any of the lines and spaces.

Further, as the etching conditions in the conventional example 2, using mixed-gas of CF ₄ and A r and 0 ₂ at a flow ratio of 8 0/1 6 0/2 0 SC cm. In addition, the RF power is 500 W, the pressure is 40 mTorr, the He pressure on the back side of the wafer W is 7 Torr at sunset, the edge is 40 Torr, the top and wall temperature is 60 ° C, and the bottom is The temperature was set at 40 ° C. and etching was performed for 20 seconds.

In this case, the porous MSQ film 22 is etched by 270.8 nm in the depth direction in the case where the line & space is 0.25 m / 0.25 m, In the pattern with the line & space of 0.25 urn / 1.25 / m, the porous MSQ film 22 was etched by 302 nm in the depth direction. The etching rate at this time is 8 12.4 nm / sec for a pattern with a line & space of 0.25〃m / 0.25〃m, and a rate of 0.25 p./1.2 for a line & space. For a 5 μm pattern, it was 906 nm / sec. In addition, as shown in Fig. 2 (c), spikes occur on the etched surface in any line and space.

On the other hand, as the etching conditions in this example, a mixed gas of CF ₄ and Ar was used at a flow rate ratio of 80/160 sccm. The RF power is 500 W, the pressure is 150 mTorr, the He pressure on the backside of the wafer W is 7 Torr at the center, 40 Torr at the age, the top and wall temperature is 60 ° C, and the bottom temperature is The temperature was set at 40 ° C. and the etching was performed for 35 seconds.

In this case, in a pattern with a line & space of 0.25〃m / 0.25〃m, the porous MSQ film 22 is etched by 270.8 nm in the depth direction, and the line & space In the pattern with a space of 0.25 rn / 1.0 μm, the porous MSQ film 22 was etched by 281.3 nm in the length direction. The etching rate at this time is 0.25〃 for line & space. m / 0.25 m pattern: 46.2 nm / sec; line & space: 0.25 m / l. nm / sec. In addition, as shown in Fig. 2 (d), spikes on the etched surface were suppressed in all lines and spaces.

Thus, when etching the port one lath MS Q membrane 2 2, to remove the 0 ₂ gas from Etsuchin Gugasu, by increasing the pressure, while preventing the Edzuchingureto drops below the practical level, Etsu Spikes on the chining surface could be suppressed. When the size of the spike is quantitatively expressed, it can be obtained by (top height-bottom height) / (etching depth).

FIG. 3 is a diagram showing the pressure dependence of the etching characteristic according to one embodiment of the present invention. In this example, the pressure was changed to 50, 150, and 30 OmTorr, and the other conditions were the same as those in FIG. 2 (c).

In Fig. 3 (a), as the pressure increases, the amount of CD shift increases, but the spike decreases. On the other hand, in Fig. 3 (b), as the pressure increases, the microloading deteriorates. However, even if the pressure rises, in the case of the porous MS Q, the line & space is either 0.25〃m / 0.25〃m or 0.25j / 0.75〃m. Even in the pattern, the etching rate hardly changes.

Therefore, by increasing the pressure, spikes on the etched surface can be reduced while suppressing a decrease in the etching rate. Here, from the viewpoint of suppressing spikes, the pressure is preferably 50 mTorr or more, and more preferably higher.

If the pressure is 500 mTorr or more, the etching shape becomes a bowing shape, which is not preferable.

In addition, consider the negative impact on CD shift volume and micro-mouthing Then, the pressure is preferably in the range of 150 to 300 mTorr. It should be noted that the spikes decrease as the pressure increases because the mean free path of the ion decreases as the pressure increases and the energy acquired by the ions decreases. it is conceivable that.

FIG. 4 is a diagram showing RF power density dependence of etching characteristics according to one embodiment of the present invention. In this example, the RF power density was changed to 0.15, 0.50, 0.75 W / cm ^2, and the other conditions were the same as those in FIG. 2 (c). The diameter of the cathode is 260 mm.

In Fig. 4 (a), as the power density decreases, spikes decrease, but have little effect on the amount of CD shift. Therefore, it is possible to reduce the spikes on the etched surface by reducing the RF power density. ₍ On the other hand, in FIG. 4 (b), when the RF power density decreases, the line & space becomes 0.25 jum / The etching rate is reduced in both the patterns of 0.25 / m and 0.25 jum / 0.75 / m.

Here, from the viewpoint of suppressing spikes, it is preferable that the RF power density is 0.50 W / cm2 or less, but in consideration of a decrease in the etching rate, the RF power density is 0.25 to 0.55 W / cm2. It is preferably in the range of 0.5 W / cm ² .

The reason why the spikes decrease when the RF power density decreases is thought to be that when the RF power density decreases, the energy acquired by the ions decreases and the sputter power of the ions decreases.

Figure 5 is a diagram showing the 0 ₂ flow rate dependency of the etching characteristics according to an embodiment of the present invention. In this example, 0 ₂ flow to 0, 1 0, 2 0, 4 0 sccm and varied were the same as the conditions of FIG. 2 and other relevant conditions (c). In FIG. 5 (a), 0 if ₂ flow rate decreases, reduces any of the CD shift amount and spike. On the other hand, in FIG. 5 (b), 0 ₂ of contaminating ne In comparison with the case where 0 ₂ is mixed in, the line & space of 0.25 m / 0.25〃111 ぉ and 0.25〃m / 0.75 m Although the etching rate is reduced, the micro-pitting is improved.

Therefore, by lowering the 0 ₂ flow rate, while maintaining the degree extent that the etching rate, it is possible to reduce the spike of the etched surface. Here, from the viewpoint of spike suppression, preferably 0 ₂ flow rate is 0, by the 02 flow rate to zero, can be improved CD shift amount and the micro-loading. However, 0 ₂ necessarily必short without to 0 flow rate, 0 ₂ be somewhat mixed, it is possible to suppress the spike no practical problem. Here, 0 _{if 2} incorporating the 0 ₂ gas flow rate ratio of for CF ₄ gas preferred to a 0.25 or less arbitrarily. Further, 0 ₂ gas flow rate ratio of may be set for the total gas flow rate, in this case, arbitrary preferred that the flow ratio of 0 ₂ gas 0.08 or less.

Incidentally, 0 ₂ when the flow rate is增加, the spike increases, port one lath M SQ is, '- 0- S i-0-' organic group on the side chain to the main chain of the (mainly 'single CH ₃ ') is considered to be linked. That is, if 0 ₂ gas is present in the etching gas, a high bonding energy by reacting with carbon 0 ₂ gas contained in the organic group 'C-0, is generated, because the carbon is withdrawn from the porous MS Q it is conceivable that.

FIG. 6 is a diagram showing bottom temperature dependence of etching characteristics according to one embodiment of the present invention. In this example, the bottom temperature of the wafer W was changed to 0, 40, and 80 ° C., and the other conditions were the same as those in FIG. 2 (c). In Fig. 6 (a), when the bottom temperature increases, the CD shift amount increases, but the spike is hardly affected. On the other hand, Fig. 6 (b) Bottom temperature has little effect on microloading and etch rates.

For this reason, from the viewpoint of suppressing spikes, the bottom temperature may be set anywhere, but from the viewpoint of suppressing the amount of CD shift, a lower bottom temperature is preferable. In this case, the bottom temperature is preferably 40 ° C or less.

In the embodiment described above, description has been given of the case using a CF ₄ based gas, well whatever Furuorokabon based gas, for example, C ₂ F ₆ based gas, C ₃ F ₆ based gas, C ₄ F ₆ based gas, C ₄ F ₈ based gas, C ₅ F ₈ based gas may be used CHF ₃ series gas or CH ₂ F ₂ based gas. Further, C 0 or N ₂ may be mixed with these gases. Further, instead of Ar, other good _c example be an inert gas such as H e, C ₄ F ₈ gas, A r and N ₂ 5: 1000: mixing a flow rate ratio of 0.99, RF power density from 0.25 to 0.50 0! 11 ^2, by a 1 50~30 OmTorr the pressures, it was possible to suppress the spike of the porous insulating film.

FIG. 7 is a sectional view showing a dual damascene process according to one embodiment of the present invention. In FIG. 7 (a), a porous insulating film 32 and a photoresist film 33 are formed on a lower region 31 and the opening H1 corresponding to the via hole B1 is formed by photolithography. The resist film 33 is formed. The lower region 31 is a silicon substrate or a lower wiring layer such as Cu or A1.

Next, as shown in FIG. 7 (b), using the photoresist film 33 as a mask, etching E1 such as RIE is performed to form a via hole B1 opening to the surface of the lower region 31 with a porous insulating film. Formed on film 32. Next, as shown in FIG. 7C, the photoresist film 33 is removed, A photoresist film 34 is applied over the entire surface. Then, an opening H2 corresponding to the wiring groove T1 is formed in the photoresist film 34 by using photolithography technology.

Next, as shown in FIG. 7 (d), using the photoresist film 34 as a mask, etching E 2 such as RIE is performed halfway through the porous insulating film 32 to form the porous insulating film 3. 2, a wiring groove T1 is formed.

Here, as the etching conditions in the etching E 2, using a mixed gas of CF ₄ gas and A r gas, 0 an RF power density. 2 5~ 0. 5 0 W / cm 2, the pressure 1 5 0-3 Set to 0 0 mTorr. Thereby, even when the etching E2 is completed in the middle of the porous insulating film 32, it is possible to prevent the occurrence of a spike in the step D1.

Next, the photoresist 34 is removed, and a conductive material such as Cu or A1 is deposited on the entire surface. Then, the surface of the conductive material is flattened by CMP (chemical mechanical polishing) or the like, thereby simultaneously forming vias and wiring. Here, since there is no spike on the step D1, it is possible to increase the adhesion of the wiring formed on the step D1, and to suppress particles generated from the spike.

As described above, according to the above-described dual damascene process, even when the stopper film such as the silicon nitride film is removed, the spikes during the etching of the porous insulating film 32 are suppressed and the via hole B 1 is connected to the wiring. The groove T 1 can be formed in the porous insulating film 32. For this reason, the relative dielectric constant of the porous insulating film 32 can be reduced, and the propagation delay of the wiring can be suppressed. In addition, since a stopper film such as a silicon nitride film does not exist between the porous insulating films 32, when the porous insulating film 32 is etched, a choice between the stopper film and the porous insulating film 32 is made. There is no need to consider the ratio. For this reason, instead of C 4 F ₈ gas, a CF 4 gas with a higher F / C ratio is The insulating film 32 can be etched, and the etching rate at the time of etching the porous insulating film 32 can be improved. As described above, according to the present invention, it is possible to suppress the occurrence of spikes in the porous insulating film. Industrial applicability

The method for etching a porous insulating film, the dual damascene process, and the semiconductor device according to the present invention can be used in a semiconductor manufacturing industry that manufactures semiconductor devices. Therefore, industrial availability

• ff 3

Claims

The scope of the claims

1. The processing gas during plasma etching is a mixed gas containing a fluorocarbon-based gas and an inert gas,

A method for etching a porous insulating film, wherein the pressure is not less than 15 O mTorr and not more than 300 mTorr.

2. The method for etching a porous insulating film according to claim 1,

The RF power density is not less than 0.25 W / cm ^{2 and not} more than 0.5 W / cm ² .

3. The method for etching a porous insulating film according to claim 1, wherein the fluorcarbon-based gas is CF ₄ , and the inert gas is Ar.

4. In claim 1, 2 or 3 etching method of a porous insulating film according to, characterized in that the flow rate ratio relative to the Furuoroka one carbon-containing gas further comprises a 0. 2 5 following 0 ₂ gas.

5. In a semiconductor device with wiring trenches and via holes formed by a dual damascene process,

The porous insulating film in which the wiring groove is formed and the porous insulating film in which the via hole is formed are formed without passing through a stopper layer, and a spike is substantially present when etching the porous insulating film. A semiconductor device characterized by not being performed.

6. forming a first photoresist film having a pattern corresponding to the via hole on the porous insulating film;

Forming a via hole in the porous insulating film by etching the porous insulating film using the first photoresist film as a mask; Removing the first photoresist film;

Forming a second photoresist film having a pattern corresponding to the wiring groove on the porous insulating film;

RF power density is 0. ² 5 W / cm 2 or more 0. 5 0 W / cm ² or less, a pressure is 1 5 O mTorr or 3 0 0 mTorr following conditions, the second photo registry film as a mask Forming a wiring groove in the porous insulating film by partially etching the porous insulating film;

Removing the second photoresist film;

A step of burying a conductive material in the via hole and the wiring groove.

7. In the dual damascene process according to claim 6,

A mixed gas containing a fluorocarbon-based gas and an inert gas is used as a processing gas in the step of forming a wiring groove in the porous insulating film.

8. In the dual damascene process of claim 7,

The fluorocarbon-based gas is CF ₄ , and the inert gas is Ar.