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WO1999000974A1 - Systeme de commutation et procede de commutation d'entree-sortie - Google Patents

Systeme de commutation et procede de commutation d'entree-sortie Download PDF

Info

Publication number
WO1999000974A1
WO1999000974A1 PCT/JP1998/002928 JP9802928W WO9900974A1 WO 1999000974 A1 WO1999000974 A1 WO 1999000974A1 JP 9802928 W JP9802928 W JP 9802928W WO 9900974 A1 WO9900974 A1 WO 9900974A1
Authority
WO
WIPO (PCT)
Prior art keywords
input
output
line
switching
switcher
Prior art date
Application number
PCT/JP1998/002928
Other languages
English (en)
Japanese (ja)
Inventor
Kimiyasu Satoh
Original Assignee
Sony Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corporation filed Critical Sony Corporation
Priority to US09/242,954 priority Critical patent/US6351258B1/en
Priority to GB9902666A priority patent/GB2331427B/en
Publication of WO1999000974A1 publication Critical patent/WO1999000974A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/64—Distributing or queueing
    • H04Q3/68—Grouping or interlacing selector groups or stages
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H60/00—Arrangements for broadcast applications with a direct linking to broadcast information or broadcast space-time; Broadcast-related systems
    • H04H60/02—Arrangements for generating broadcast information; Arrangements for generating broadcast-related information with a direct linking to broadcast information or to broadcast space-time; Arrangements for simultaneous generation of broadcast information and broadcast-related information
    • H04H60/04—Studio equipment; Interconnection of studios
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/222—Studio circuitry; Studio devices; Studio equipment
    • H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/268—Signal distribution or switching

Definitions

  • a switch is newly provided by setting a new matrix range for switching the input / output path of a new signal from an unused matrix range of the switcher. Even if there is no signal, a switcher device that can control the switching of the input / output path for each type as long as the type of signal is an integer multiple or more of the number of switchers can be realized. Further, in the present invention, a plurality of input lines and a plurality of output lines in a matrix-like switcher comprising a set of a plurality of cross points where a plurality of input lines and a plurality of output lines intersect.
  • an input / output switching method capable of controlling input / output switching for each type can be realized.
  • a switcher device for switching a signal path of a signal input from one or more input lines from a single or a plurality of output lines to a desired output line An input / output range setting section that sets the use range of the output line, and also sets the use range of the input color whose use is restricted for the use range of the output line, and the input line for the use range of the output line.
  • FIG. 9 is a schematic diagram for explaining the range setting of the input line and the output line.
  • FIG. 10 is a schematic diagram showing a control panel.
  • the CPU 12 controls the RAM 13 and the flash R ⁇ Ml4 with the control signal SC, and also controls the RAM 13 and the flash R0M14 with the address data AD. Specify the address.
  • the area of the matrix range B is located at a position where the number of input / output lines is offset by two with respect to the area of the matrix range A.
  • the input lines IN1, IN2 and the output lines OUT1, O2 of the matrix range A are connected to IN3, IN4 and OUT3, OUT4 of the matrix range B.
  • the conversion is performed using the offset value “2” to correspond to UT2.
  • the switcher device 1 controls the input / output route of all the signals at levels 1 to 16 by specifying the cross point of [IN 1, 0 UT 1], for example.
  • the remote control unit 6 receives the route setting data D1 from the unit 2, the remote control unit 6 is designated at the control levels 1 to 8. It is only necessary to switch the input / output route to the cross point of [IN 1, 0 UT 1]. However, in expansion levels 9 to 16, the area of matrix range B is used. Therefore, the offset value “2” is added to each of the specified [IN 1, 0 UT 1] cross points, and the [IN 3, 0 UT 3] cross points are added. Switch the input / output route to the point.
  • step SP 6 the CPU 12 sets the input point “IN 3” and the output line “0 UT 3” to which the offset value “2” has been added in steps SP 4 and 5 described above. Switch the signal input / output route, and move to step SP 7 to end the process.
  • step SP12 if a positive result is obtained in step SP12, this indicates that the displayed level is the extended level of levels 9 to 16, and the CPU 12 then proceeds to step SP13. Move on.
  • step SP 15 the CPU 12 switches the input / output route of the signal in the matrix range B of level 4 based on the route setting data D 1, and the switched output line “ Check the signal type of the input line (IN 4 in this case) connected to “UT 4” and proceed to step SP 16.
  • the CPU 12 of the remote control unit 106 sets the desired output from a plurality of output lines by the user on the character display section 18 of the control panel 20.
  • the range setting data D10 stored in the flash ROM 14 is read out to RAMI3, and the range of use of the selected output line is checked based on this. .
  • the 16 selection buttons provided on the control panel 25, such as "KEY input line number”, are displayed.
  • the signal type “I ⁇ ” and the line number unique to each input color ( 0 0 1 to 0 8, 10 1 to 10 8) to specify the input line for each selection button 17 ⁇ ⁇ 0 0 1 to ⁇ ⁇ 0 0 8, INI 0 Set 1 to IN 108
  • control part 2 is the same as the one set in the control port terminal 2A. -When the route setting is switched based on the port setting data D 0, if the output line OUT 0 0 1 is included in the switching request data S 1, the output line OUT 1 0 0 and A request to switch to input line IN 100 is also made at the same time.
  • step SP 22 the CPU 12 expands the route setting data D 20 read from the flash R 0 M 14 on the RAM 13, and checks it in step SP 21. It checks whether or not the combination of the input line and the output line has been set using the extended input line IN100 based on the route setting data D20.
  • the switcher device 200 is connected to the extension routing switcher 204B from the extension input line IN100 of the main unit routing switcher 204A via the output signal line UTL1. I do.

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Studio Circuits (AREA)

Abstract

On décrit un système de commutation qui s'utilise pour commuter la voie d'entrée-sortie de chaque signal sans augmenter le nombre de commutateurs même lorsque les types de signaux ont augmenté en nombre. Le système comprend des commutateurs matricielles qui comprennent un ensemble de points de contact dans laquelle une série de lignes d'entrée et de lignes de sortie s'entrecroisent pour commuter la voie d'entrée-sortie de signal par commutation du raccordement des points de contact à l'intérieur d'une plage matricielle spécifiée constituée de lignes d'entrée et de lignes de sortie spécifiées extraites des lignes d'entrée et des lignes de sortie. Le système comprend également un moyen de stockage de données de plage matricielle non utilisées correspondant à des lignes d'entrée et à des lignes de sortie non utilisées extraites des lignes d'entrée et des lignes de sortie à l'exclusion de la plage matricielle spécifiée, ainsi que des données de plage matricielle sélectionnées correspondant à des lignes d'entrée et à des lignes de sortie choisies à partir d'une plage matricielle non utilisée. Le système comprend enfin un moyen de commande permettant de créer une nouvelle plage matricielle à partir de la plage matricielle non utilisée sur la base des données de plage matricielle non utilisées et des données de plage matricielle sélectionnées.
PCT/JP1998/002928 1997-06-30 1998-06-30 Systeme de commutation et procede de commutation d'entree-sortie WO1999000974A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US09/242,954 US6351258B1 (en) 1997-06-30 1998-06-30 Switcher system and I/O switching method
GB9902666A GB2331427B (en) 1997-06-30 1998-06-30 Switcher system and input/output switching method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP17483297 1997-06-30
JP9/174832 1997-06-30

Publications (1)

Publication Number Publication Date
WO1999000974A1 true WO1999000974A1 (fr) 1999-01-07

Family

ID=15985445

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1998/002928 WO1999000974A1 (fr) 1997-06-30 1998-06-30 Systeme de commutation et procede de commutation d'entree-sortie

Country Status (3)

Country Link
KR (1) KR20000068153A (fr)
GB (1) GB2331427B (fr)
WO (1) WO1999000974A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7821932B2 (en) * 2008-06-25 2010-10-26 Disney Enterprises, Inc. System and method for intelligent signal routing in a television production studio

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07264474A (ja) * 1994-03-19 1995-10-13 Sony Corp 入出力切換制御装置
JPH07312723A (ja) * 1994-03-19 1995-11-28 Sony Corp 入出力切換装置及びマトリクススイツチヤ制御装置
JPH09107567A (ja) * 1995-10-06 1997-04-22 Fujitsu General Ltd マトリクススイッチ装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1758375B1 (fr) * 1996-04-17 2012-12-26 Sony Corporation Commutateur de matrices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07264474A (ja) * 1994-03-19 1995-10-13 Sony Corp 入出力切換制御装置
JPH07312723A (ja) * 1994-03-19 1995-11-28 Sony Corp 入出力切換装置及びマトリクススイツチヤ制御装置
JPH09107567A (ja) * 1995-10-06 1997-04-22 Fujitsu General Ltd マトリクススイッチ装置

Also Published As

Publication number Publication date
GB2331427A (en) 1999-05-19
GB9902666D0 (en) 1999-03-31
KR20000068153A (ko) 2000-11-25
GB2331427B (en) 2002-02-13

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