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WO1999065076A1 - Dispositif a semiconducteur et procede de fabrication - Google Patents

Dispositif a semiconducteur et procede de fabrication Download PDF

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Publication number
WO1999065076A1
WO1999065076A1 PCT/JP1998/002506 JP9802506W WO9965076A1 WO 1999065076 A1 WO1999065076 A1 WO 1999065076A1 JP 9802506 W JP9802506 W JP 9802506W WO 9965076 A1 WO9965076 A1 WO 9965076A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
wirings
groove
semiconductor chip
manufacturing
Prior art date
Application number
PCT/JP1998/002506
Other languages
English (en)
Japanese (ja)
Inventor
Kouji Tsuchiya
Noriyuki Takahashi
Keisuke Takahashi
Original Assignee
Hitachi, Ltd.
Hitachi Yonezawa Electronics Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd., Hitachi Yonezawa Electronics Co., Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1998/002506 priority Critical patent/WO1999065076A1/fr
Publication of WO1999065076A1 publication Critical patent/WO1999065076A1/fr

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    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Definitions

  • the present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique which is effective when applied to a chip size package (CSP) type semiconductor device.
  • CSP chip size package
  • CSPs whose package dimensions are almost the same as or slightly larger than those of semiconductor chips, are capable of high-density packaging equivalent to bare-chip packaging, and are relatively inexpensive to manufacture.
  • Demand in the field of small and light electronic devices such as digital cameras and notebook computers is increasing rapidly.
  • the above CSPs come in a variety of package forms.
  • ball grids are used in which solder bumps are attached to one surface of a package substrate on which chips are mounted, and the solder bumps are reflow soldered to the surface of the printed wiring board.
  • An array (gall Grid Array; BGA) structure is adopted.
  • BGA gallium Grid Array
  • TCP lape carrier package
  • tape BGA tape BGA
  • the package substrate on which the chip is mounted is made of insulating tape such as polyimide
  • Japanese Patent Application Laid-Open No. 8-293510 discloses another embodiment of a CSP having a BGA structure and a method of manufacturing the same.
  • a flat molded product made of epoxy resin with a concave groove for chip mounting in the center of one surface is molded by transfer molding, and at the same time, The wiring member, which has been bent so as to correspond to the wall surface, is integrally formed with the flat molded product to form a package substrate.
  • the chip is mounted (with a pellet) inside the above-mentioned groove, and the chip and the wiring fixed to the wall surface of the groove are connected with a wire, and then the potting resin is filled inside the groove and the chip is filled. Is sealed.
  • the package base A CSP is completed by applying solder resist on one side of the board, opening a part of it, exposing a part of the wiring, and joining solder bumps to it.
  • ⁇ 3 8 adopting the 80 structure means that thermal stress such as temperature cycling caused by the difference in thermal expansion coefficient between the package board and the printed wiring board after mounting, There is also a problem that the reliability after mounting on the board is inferior to QFP due to the structure that allows easy concentration.
  • an underfill resin is used in the gap between the package substrate and the printed wiring board to relieve stress (eg, April 1990, Transactions of the Institute of Electronics, Information and Communication Engineers, Cll Vol. J73-C-II No. 9 p516- 524) is also used, but in this case, an increase in the number of manufacturing processes and an increase in manufacturing costs are inevitable in exchange for improved reliability.
  • An object of the present invention is to provide a technique for realizing a CSP with low cost and high reliability.
  • a semiconductor chip is mounted inside a concave groove provided on a first surface of a package substrate, and each of a plurality of wirings formed on the first surface around the concave groove is provided.
  • One end of the semiconductor chip is electrically connected to the semiconductor chip via a wire, the semiconductor chip is sealed with a resin filled in the concave groove, and a part of each of the plurality of wirings is provided.
  • Bump electrode is connected to the surface of the land formed A surface of one end of each of the plurality of wirings to which the wires are connected, a surface of the plurality of wirings excluding the surface of the land portion, and the first surface of the package substrate.
  • An insulating layer is applied to each of the second surfaces.
  • the semiconductor chip is sealed with the resin, the bump electrode is connected to a surface of the land formed on a part of each of the plurality of wires, and the plurality of wires connected to the wires
  • the insulating layer is provided on the surface of one end of each of the plurality of wirings, the surface of the plurality of wirings excluding the surface of the land portion, and the surface of a second surface of the package substrate opposite to the first surface.
  • the manufacturing cost is minimized by simplifying the package substrate.
  • FIG. 1 is a plan view of a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 2 is a plan view showing a state in which the potting resin has been removed from the semiconductor device according to the first embodiment of the present invention.
  • FIG. 3 is a cross-sectional view taken along the line III-III of FIG.
  • FIG. 4 is an enlarged cross-sectional view of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 5A is an overall plan view of a matrix substrate used for manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 5B is a cross-sectional view taken along line BB of FIG. It is a figure.
  • FIG. 6 is a plan view of a main part of a matrix substrate used for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 7 is a cross-sectional view of a main part of a matrix substrate used for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 8 is a plan view of a main part of a glass-epoxy single-layer plate showing a method of manufacturing a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 9 is an enlarged cross-sectional view of a glass-epoxy single-layer plate showing a method of manufacturing a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 10 is a plan view of a main part of a glass epoxy single-layer plate showing a method of manufacturing a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 11 is a fragmentary cross-sectional view of a glass-epoxy single-layer plate showing a method of manufacturing a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 12 is a plan view of a main portion of a glass epoxy single-layer plate showing a method of manufacturing a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 13 is a fragmentary cross-sectional view of a glass-epoxy single-layer plate showing a method of manufacturing a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 14 to FIG. 16 are plan views of a main part of a glass-epoxy single-layer plate showing a method of manufacturing a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 17 is a cross-sectional view of a main part of a single-layer glass epoxy plate illustrating a method of manufacturing a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 18 is a plan view of relevant parts of a matrix substrate, illustrating a method for manufacturing a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 19 is a fragmentary cross-sectional view of the matrix substrate, illustrating the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 20 is a plan view of a main part of a matrix substrate showing a method for manufacturing a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 21 is a fragmentary cross-sectional view of the matrix substrate, illustrating the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIGS. 22A and 22B are explanatory diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 23 is a cross-sectional view of a main part of a matrix substrate, illustrating the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIGS. 24 (a), (b), and (c) are explanatory views of a sealing method using a potting resin.
  • FIG. 25 is an explanatory diagram of a method of connecting solder bumps.
  • FIG. 26 to FIG. 30 are explanatory diagrams of the dicing method of the matrix substrate.
  • FIG. 31 is a cross-sectional view showing a state where the semiconductor device according to the first embodiment of the present invention is mounted on a printed wiring board.
  • FIG. 32 and FIG. 33 are cross-sectional views of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 34 is a cross-sectional view of a semiconductor device according to Embodiment 3 of the present invention.
  • FIG. 35 is a sectional view of a multi-chip module in which semiconductor devices according to the third embodiment of the present invention are stacked.
  • FIG. 1 is a plan view showing the CSP of the present embodiment with its board mounting surface facing upward
  • FIG. 2 is a plan view showing the CSP with a potting resin removed
  • FIG. FIG. 1 is a sectional view taken along the line m-m of FIG.
  • the CSP of the present embodiment includes a rectangular package substrate 2 made of synthetic resin having a plurality of wirings 1 formed on one surface (substrate mounting surface).
  • a square groove 3 is formed in the center of the surface of the package substrate 2 where the wiring 1 is formed (substrate mounting surface), and a semiconductor chip 4 on which LSIs such as microcomputers and ASICs are formed. Is mounted with its element formation surface facing up.
  • the semiconductor chip 4 is fixed to the bottom surface of the concave groove 3 by an adhesive 5 such as Ag paste, and is hermetically sealed by a potting resin 6 filled in the concave groove 3.
  • each of the plurality of wirings 1 formed on the package substrate 2 extends to an intermediate portion of the side wall of the concave groove 3, and a wire 7 having one end bonded thereto is interposed therebetween. 4 is electrically connected to the bonding pad BP. Further, the other end of each of the plurality of wirings 1 extends to the periphery of the package substrate 2 on which the solder resist 8, which is an insulating layer for protecting the wirings 1, is applied. At the periphery, lands 1 A are formed by removing a part of solder resist 8 to expose wiring 1, and external connection terminals of CSP are formed on the surface of each land 1 A.
  • the constituent solder bumps 9 are connected. In the CSP of the present embodiment, for example, 136 solder bumps 9 are arranged in two rows along the outer periphery of the concave groove 3.
  • the other surface of the package substrate 2 facing the surface on which the wiring 1 and the concave groove 2 are formed is a flat surface, and a solder resist 8 is applied to the surface. That is, the CSP of the present embodiment covers the surface of the wiring 1 formed on one surface (substrate mounting surface) of the package substrate 2 with the solder resist 8 and also solders the other surface on which the wiring 1 is not formed. Coated with resist 8.
  • FIG. 4 is an enlarged sectional view showing a part of the package substrate 2.
  • a step-like step is provided on the side wall of the concave groove 3, and the upper part thereof is tapered in order.
  • the inclined surface (s), and the lower part has a surface substantially perpendicular to the bottom surface of the groove 3.
  • One end of each of the plurality of wirings 1 extends to the upper surface of the lower portion, and is electrically connected to the wire 7 in this region. Further, the solder resist 8 covering the surface of the wiring 1 is terminated at a middle part of the inclined surface (s).
  • the package substrate 2 is made of a well-known resin substrate material, such as glass epoxy resin, BT resin, polyimide resin, and the like.
  • the CSP of the present embodiment is an inexpensive substrate material for the package substrate 2. It is composed of a single layer glass / epoxy resin.
  • the wiring 1 is formed by etching the electrolytic copper foil (or rolled copper foil) attached to the surface of the single-layer plate.
  • the package substrate 2 has a simple structure in which one layer of wiring 1 is formed on the surface of a glass / epoxy single layer plate, so that the manufacturing cost can be minimized.
  • FIG. 5 (a) is an overall plan view of the matrix substrate 20 used for manufacturing the CSP
  • FIG. 5 (b) is a cross-sectional view along the line BB of FIG. 5 (a).
  • the matrix substrate 20 is, for example, composed of a glass-epoxy single-layer plate having a height of 0.5 and a width of 50 x XI and a thickness of 0.6 to 0.8.
  • the wiring 1 is formed on one surface of the matrix substrate 20, and the solder resist 8 is coated on the surface on which the wiring 1 is formed and the other surface. Is being worn.
  • the solder resist 8 is applied to both surfaces of the matrix substrate 20, heat treatment in the CSP manufacturing process described later, or a difference in thermal expansion coefficient between both surfaces of the substrate due to filling of potting resin, etc. Glass or epoxy single-layer plate with a thickness of less than 1 mm may warp or deform. This makes it possible to prevent the inconvenience and to ensure flatness.
  • the upper limit of the outer dimensions of the matrix substrate 20 is mainly determined by the area of the bonding stage of the wire bonding apparatus. Therefore, when a wire bonding apparatus having a large stage area is used, a matrix substrate having a size larger than the above-mentioned dimensions, for example, a matrix having a length of about 10 mm and a width of about 10 Omm x 110. It is also possible to use 0. Also in this case, warping and deformation can be prevented by using a structure in which the solder resist 8 is applied to both surfaces of the glass / epoxy single-layer plate.
  • Fig. 6 is a plan view of the main part of the matrix substrate 20 showing an area of 3 to about one (the area surrounded by a circle in Fig. 5 (a)), and Fig. 7 is a cross-sectional view of the same main part. is there.
  • a plurality of wirings 1 having one end extending to an intermediate portion of the side wall of the concave groove 3 are formed around each concave groove 3 formed on one surface of the matrix substrate 20. .
  • the other ends of these wires 1 are connected to a power supply line 21 for electrolytic plating formed along the outer periphery of the concave groove 3.
  • the power supply line 21 extends along the long side direction and the short side direction of the matrix substrate 20 and is formed so as to surround the periphery of each concave groove 3, so that the power supply line 21 is formed on one surface of the matrix substrate 20. It is possible to apply plating such as Ni (nickel) and Au (gold) to all of the wirings 1 that have been made. Further, a land portion 1A is formed at one end of each wiring 1 and at a halfway between the power supply line 21 and the wiring 1 is exposed by removing a part of the solder resist 8.
  • the inclined surface (s) having a forward taper shape is provided on the side wall of the groove 3A, and the angle between the one surface of the glass single-layer plate 2OA and the side wall of the groove 3A is 90 °.
  • the groove is formed by pressing with a large obtuse angle.
  • the lower step portion of the groove 3 is formed on the bottom surface of the groove 3A.
  • a concave groove 3B corresponding to (see FIG. 4) is formed.
  • the four corners of the concave groove 3B are cut into an arc shape in the zigzag processing using a router.
  • the four corners of the concave groove 3B are further cut. Chip and increase the diameter of the arc.
  • the number of types of the semiconductor chips 4 mounted in the four grooves 3 can be increased. Also, by providing the above-described large arc-shaped notches 10 at the four corners of the concave groove 3B, it is possible to prevent a problem in which thermal stress or mechanical stress is concentrated on the four corners of the concave groove 3. In monkey.
  • solder resist 8 made of an epoxy resin having a thickness of about 20 ⁇ is applied to both surfaces of the glass single-layer epoxy board 2OA.
  • the inside of the concave groove 3 and the middle part of the wiring 1 are masked so that the solder resist 2 is not applied to this area.
  • one end of the solder resist 8 is terminated at an intermediate portion of the inclined surface (s) provided on the side wall of the concave groove 3.
  • the pitch of the land portion 1A to which the solder bump 9 is connected in a later step is, for example, 0.5 thigh, but other pitches (for example, 0.8 mm, 1.0 mm, 1.27 mm) Etc.).
  • insulating layers made of, for example, a photosensitive resin may be applied to both surfaces of the glass / epoxy single layer plate 20A.
  • the other surface of the glass / epoxy single-layer plate 2OA is masked with an area (not shown) that forms an index mark (mark indicating the reference position of the pin arrangement) of about one diameter in diameter, and covers the remaining entire surface.
  • a solder resist 8 is applied. Since this surface becomes the upper surface when the completed CSP is mounted on the printed wiring board, the mark such as the product number is written by the screen printing method using silver ink or the laser marking method. Therefore, in order to secure the visibility of the mark, the solder The resist 8 is desirably colored so as to be black or a color close thereto.
  • the surface of the wiring 1 (one end and the land 1A extending inside the concave groove 3) in a region not covered with the solder resist 8 is subjected to plating of Ni and Au, thereby obtaining the matrix substrate. 20 is completed.
  • This plating process can also be performed by a forceless electroplating method performed by an electrolytic plating method using the power supply line 21 formed integrally with the wiring 1.
  • the semiconductor chip 4 is bonded to the inside of each concave groove 3 formed on the matrix substrate 20 using an adhesive 5 such as Ag paste. Mount.
  • each wiring 1 and the bonding pad BP of the semiconductor chip 4 are connected by a wire 7 such as Au.
  • a wire 7 such as Au.
  • the bonding of the wire 7 is performed, for example, by using a known wire bonder using both ultrasonic vibration and thermocompression bonding, and bonding the matrix substrate onto a bonding stage heated to about 170 to 180 ° C. Perform by positioning 20.
  • the depth (d) of the concave groove 3B is larger than the total thickness (t) of the thickness of the semiconductor chip 4 and the thickness of the adhesive 5 in advance ( d> t)
  • the height of the wiring 1 on the second bonding side is higher than the position of the bonding pad BP on the first bonding side.
  • the bottom surface of the concave groove 3A where one end of the wiring 1 is formed has an inclination angle ( ⁇ ) that is closer to the semiconductor chip 4 and higher than the far side. Since the wire 7 is crimped onto the wiring 1 at the tip of the sash 22 during the second bonding, the tensile strength of the wire 7 bonded on the wiring 1 is improved.
  • ⁇ inclination angle
  • the inclination angle ( ⁇ ) is at most about 2 °.
  • a liquid potting resin 6 made of, for example, an epoxy resin is filled into the concave groove 3 in which the semiconductor chip 4 is mounted, and then the potting resin 6 is removed.
  • the semiconductor chip 4 is hermetically sealed by heating and curing at about 150 ° C.
  • the potting resin 6 is filled using a dispenser (not shown) equipped with a single nozzle or a multi-nozzle.
  • the potting resin 6 is dropped while moving the dispenser along a locus as shown in, for example, FIG. 24 (a) or FIG. 24 (b).
  • the potting resin 6 is simultaneously dropped, for example, at a location as shown in FIG.
  • the potting resin 6 can easily flow outward from the center side of the concave groove 3A. Further, by terminating one end of the solder resist 8 at an intermediate portion of the inclined surface (s) formed on the side wall of the groove 3, the flow of the potting resin 6 stops at an intermediate portion of the inclined surface, and the groove 3 Hard to crawl outside By these measures, the surface of the potting resin 6 after curing can be flattened, and the film thickness can be reduced to about 150 / m or less.
  • solder bumps 9 are connected to the surfaces of the lands 1 A formed in the middle of each wiring 1.
  • a plurality of solder bumps 9 previously formed into a ball shape are vacuum-sucked using a suction tool 23 as shown in FIG. Tank (fig.
  • the solder bumps 9 are immersed in (not shown) and a flux is applied to the surfaces thereof, and then the respective solder bumps 9 are temporarily attached to the corresponding land portions 1A at the same time using the adhesive force of the flatness.
  • the solder bump 9 is made of, for example, an Sn (63%) / Pb (37%) alloy and has a diameter of 0.3 thigh.
  • the connection of the solder bumps 9 may be performed for one CSP (136 pieces) at the same time. However, in order to improve the throughput of the bump connection process, multiple CSPs are connected at the same time. It is desirable to do it. In this case, a large area suction tool 23 is used.Therefore, if the matrix substrate 20 is warped or deformed, some solder bumps 9 are not connected to the land portion 1A. Occurs.
  • solder bumps 9 are heated and reflowed at a temperature of about 220 ° C. to fix the solder bumps 9 to the lands 1 A. Then, the flux residue remaining on the surface of the matrix substrate 20 is removed using a neutral detergent or the like. This completes the bump connection process.
  • the matrix substrate 20 is cut and divided into a plurality of package substrates 2, whereby the CSP of the present embodiment shown in FIGS. 1 to 3 is obtained.
  • the package substrate 2 is cut using the die sinter blade 26.
  • the power supply line 21 formed on the surface of the matrix substrate 20 is used as a dicing line, and if the width of the dicing blade 26 is narrow, it is cut twice (see FIG. 28). 28 (a), (b)). If the width is large, cut once (Fig. 28 (c), (d)).
  • the obtained CSP is sucked by one collet 27, and the dicing tape 2 is pushed up using the push-up pins 28.
  • the dicing tape 2 is pushed up using the push-up pins 28.
  • store them one by one in tray 29 as shown in Fig. 30.
  • a cutting die may be used to divide the matrix substrate 20 into a plurality of package substrates 2, but in this case, due to structural limitations such as a cutting punch and a pedestal, one CSP Since the matrix substrate 20 having a certain gap between the region and the region for one adjacent CSP must be prepared, the utilization efficiency of the substrate material is reduced. On the other hand, in the above dicing method, the gap can be reduced to about 0.5 thigh, and the amount of discarded substrate material can be minimized. It has the advantage of high efficiency.
  • the CSP manufactured as described above is subjected to inspection by a burn-in tester and appearance inspection to be sorted into non-defective and non-defective products, and then packed and shipped.
  • the semiconductor chip 4 is mounted inside the concave groove 3 and then the solder bump 9 is connected to the land 1A.
  • the matrix substrate having the solder bump 9 connected to the land 1A in advance is used.
  • FIG. 31 is a cross-sectional view showing a state where the CSP of the present embodiment is mounted on printed wiring board 30.
  • a flux is applied to the surface of the solder pump 9, and each solder bump 9 is applied to the corresponding electrode 3 1 After the temporary attachment to the surface of the solder bumps 9, the solder bumps 9 may be reflowed in a heating furnace.
  • the mounting height of the CSP of this embodiment when mounted on a board is as thin as about lmm, the mounting height is almost the same as TQFP (Thin Quad Flat Package), and the external dimensions in the vertical and horizontal directions are TQFP Since it is much smaller than, it is possible to realize much higher-density mounting than a peripheral terminal type resin package represented by QFP.
  • TQFP Thin Quad Flat Package
  • the package substrate 2 is formed using the same material (glass “epoxy resin”) as the normally used printed wiring board 30.
  • the stress applied to the solder bumps 9 due to the difference in thermal expansion coefficient from the package substrate 2 is small, and there is an advantage that the reliability after mounting the substrate is higher than that of the existing CSP.
  • the CSP of the present embodiment employs a fan-out structure in which solder bumps 9 are arranged on the periphery of the package substrate 2 remote from the semiconductor chip 4. Therefore, compared to a fan-in structure in which the solder bumps 9 are arranged near the semiconductor chip 4, the semiconductor chip 4 is less affected by heat and the reliability of the CSP alone is high.
  • the CSP of the present embodiment has a simple structure in which the package substrate 2 has a single layer of wiring 1 formed on the surface of a glass-epoxy single-layer plate, thereby minimizing the manufacturing cost, and reducing the manufacturing cost of the matrix substrate 20. The manufacturing cost has been reduced by adopting a batch processing process using multiple pieces used.
  • the sealing method using the potting resin 6 adopted in the present embodiment and the cutting method of the matrix substrate 20 by dicing can convert existing package manufacturing equipment. Only a little related to assembly jigs.
  • the concave groove 3 of the package substrate 2 is formed in two steps of press processing and counterboring processing has been described, but the concave groove 3 having a desired depth is formed by one press processing.
  • the concave groove 3 may be formed only by pressing.
  • the wiring 1 is formed when the concave groove 3 is formed. Disconnection at the corners can be prevented.
  • the concave groove 3 of the package substrate 2 is formed in two steps of pressing and counterboring, the concave groove formed by the counterboring
  • a CSP with low thermal resistance can be realized.
  • a metal heat radiating fin (not shown) can be attached to one surface of the heat radiating plate 40, so that a CSP with even lower thermal resistance can be realized.
  • the land 1A is provided in the middle of the wiring 1 formed on one surface of the package substrate 2 and the solder bump 9 is connected to the surface is described.
  • the land 1A was formed on the surface where the wiring 1 was not formed, and the wiring 1 and the land 1A were electrically connected to each other through the through holes 41 formed in the package substrate 2. May be connected.
  • the above structure has an advantage that when the CSP is mounted on the printed wiring board, the wiring 1 and the semiconductor chip 4 are located on the upper surface side of the package board 2, so that the electrical inspection after the board mounting can be easily performed.
  • the above structure in which the through hole 41 is formed in the package substrate 2 allows the land portions 1A to be formed on both surfaces of the package substrate 2; for example, as shown in FIG.
  • the above structure in which the through hole 41 is formed in the package substrate 2 allows the land portions 1A to be formed on both surfaces of the package substrate 2; for example, as shown in FIG.
  • the CSP of the present invention is inexpensive and has high reliability, it can be widely applied to mounting on small and light electronic devices such as portable information devices, digital cameras, and notebook computers.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

On forme un sillon en retrait (3) sur une surface de substrat de boîtier (2) en résine verre/époxy enduit de résist de soudure (8) des deux côtés, et une puce de semiconducteur (4) encapsulée dans une résine d'enrobage (6) est placée dans le sillon (3). Plusieurs câblages (1) reliés chacun à la puce de semiconducteur (4) via un câble (7) sur un côté sont constitués autour du sillon (3), et des bosses de soudure (9) représentant les bornes de connexion externes d'un boîtier de circuit intégré sont reliées aux surfaces de zones de dépôt conducteur (1A) formées dans les parties médianes des câblages respectifs (1).
PCT/JP1998/002506 1998-06-05 1998-06-05 Dispositif a semiconducteur et procede de fabrication WO1999065076A1 (fr)

Priority Applications (1)

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PCT/JP1998/002506 WO1999065076A1 (fr) 1998-06-05 1998-06-05 Dispositif a semiconducteur et procede de fabrication

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Application Number Priority Date Filing Date Title
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1498948A3 (fr) * 2003-07-17 2006-10-18 Cookson Electronics, Inc. Interface reconnectable pour des puces et boîtier asssociée
US9012144B2 (en) 2003-11-12 2015-04-21 Fluidigm Corporation Short cycle methods for sequencing polynucleotides
JP2019029427A (ja) * 2017-07-27 2019-02-21 京セラ株式会社 電子部品搭載基板、電子装置および電子部品搭載基板の製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07135270A (ja) * 1993-11-11 1995-05-23 Hitachi Ltd 半導体集積回路装置の製造方法
JPH0897315A (ja) * 1994-09-28 1996-04-12 Dainippon Printing Co Ltd 表面実装型半導体装置
JPH0945812A (ja) * 1995-07-28 1997-02-14 Mitsui High Tec Inc 半導体装置
JPH1041430A (ja) * 1996-07-19 1998-02-13 Nhk Spring Co Ltd 半導体パッケージ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07135270A (ja) * 1993-11-11 1995-05-23 Hitachi Ltd 半導体集積回路装置の製造方法
JPH0897315A (ja) * 1994-09-28 1996-04-12 Dainippon Printing Co Ltd 表面実装型半導体装置
JPH0945812A (ja) * 1995-07-28 1997-02-14 Mitsui High Tec Inc 半導体装置
JPH1041430A (ja) * 1996-07-19 1998-02-13 Nhk Spring Co Ltd 半導体パッケージ

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1498948A3 (fr) * 2003-07-17 2006-10-18 Cookson Electronics, Inc. Interface reconnectable pour des puces et boîtier asssociée
US9012144B2 (en) 2003-11-12 2015-04-21 Fluidigm Corporation Short cycle methods for sequencing polynucleotides
JP2019029427A (ja) * 2017-07-27 2019-02-21 京セラ株式会社 電子部品搭載基板、電子装置および電子部品搭載基板の製造方法

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