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WO1998037576A1 - Procede de production d'un dispositif a semi-conducteur et son systeme - Google Patents

Procede de production d'un dispositif a semi-conducteur et son systeme Download PDF

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Publication number
WO1998037576A1
WO1998037576A1 PCT/JP1998/000669 JP9800669W WO9837576A1 WO 1998037576 A1 WO1998037576 A1 WO 1998037576A1 JP 9800669 W JP9800669 W JP 9800669W WO 9837576 A1 WO9837576 A1 WO 9837576A1
Authority
WO
WIPO (PCT)
Prior art keywords
polishing
semiconductor
semiconductor device
defect
manufacturing
Prior art date
Application number
PCT/JP1998/000669
Other languages
English (en)
Japanese (ja)
Inventor
Minori Noguchi
Takenori Hirose
Yukio Kenbo
Takanori Ninomiya
Masayoshi Serizawa
Yoichi Takahara
Takeshi Kimura
Shinichiro Mitani
Yoshikazu Tanabe
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Publication of WO1998037576A1 publication Critical patent/WO1998037576A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step

Definitions

  • the present invention relates to a method and a system for manufacturing a semiconductor device by repeating film formation, exposure, and etching on a substrate by a manufacturing line, and in particular, to flatten the surface after film formation by chemical and mechanical polishing.
  • the present invention relates to a method and a system for manufacturing a semiconductor device having a process and an apparatus for forming a semiconductor device.
  • a semiconductor device repeats film formation, exposure, and etching on a substrate to manufacture the semiconductor device on the substrate. At this time, the semiconductor device is manufactured using a finer pattern in order to achieve a higher density. Further, in order to realize a more complicated circuit, a step is generated because a multilayer wiring pattern is used, and the step is a cause of a pattern defect when a pattern is formed on the step. Therefore, conventionally, a flat film is formed on a pattern having a step, and the next pattern is formed on the flat film.
  • a pattern such as a wiring pattern is placed below the film to be planarized. Since the influence of this pattern was not sufficiently considered in the above-mentioned conventional technology, it was not possible to measure the residual film with sufficient sensitivity and high accuracy.
  • An object of the present invention is to solve the above-mentioned problems of the prior art, reduce the influence of a pattern present below a material to be flattened, enable highly accurate measurement of the remaining film thickness, and provide a highly accurate chemical
  • Another object of the present invention is to provide a method of manufacturing a semiconductor device which realizes mechanical polishing and can manufacture a semiconductor device (semiconductor element) at a high yield.
  • Another object of the present invention is to realize a high-throughput and high-precision chemical and mechanical polishing so that a semiconductor device (semiconductor element) can be manufactured at a high throughput and at a high yield. It is an object of the present invention to provide a method for manufacturing a semiconductor device.
  • Another object of the present invention is to reduce defects and surface roughness such as scratches and foreign substances generated when a material to be planarized is chemically and mechanically polished. It is an object of the present invention to provide a method of manufacturing a semiconductor device which can manufacture (semiconductor element) with a high yield.
  • Another object of the present invention is to provide a method of manufacturing a semiconductor device and a system therefor in which it is possible to determine whether or not a defect is caused by a defect such as a scratch or a foreign substance, and to take measures against the defect. Is to do.
  • Another object of the present invention is to provide a method for inspecting defects in a defect inspection process or its means. It is an object of the present invention to provide a method of manufacturing a semiconductor device and a system thereof that can improve the reliability of inspection and manufacture a semiconductor device with a high yield.
  • the present invention relates to a semiconductor device manufacturing method for manufacturing a semiconductor device by subjecting a material to be polished formed on a substrate to chemical and mechanical polishing and flattening the material.
  • the remaining film thickness of the polishing target material is measured, and according to the measured remaining film thickness of the polishing target material, And a method of manufacturing a semiconductor device, characterized by controlling mechanical polishing.
  • the present invention provides a method of manufacturing a semiconductor device, in which a material to be polished formed on a semiconductor substrate is chemically and mechanically polished and planarized to manufacture a semiconductor device.
  • a material to be polished formed on a semiconductor substrate is chemically and mechanically polished and planarized to manufacture a semiconductor device.
  • the chemical and mechanical polishing is performed, the remaining film thickness of the material to be polished is measured. According to the measured remaining film thickness of the material to be polished, the chemical and mechanical high-speed polishing is performed.
  • This is a method for manufacturing a semiconductor device, characterized by performing switching control to low-speed polishing.
  • the present invention is characterized in that, in the method of manufacturing a semiconductor device, the remaining film thickness of the material to be polished is measured from a spectral intensity distribution of light reflected from the material to be polished (planarized film).
  • the present invention also provides the method of manufacturing a semiconductor device, wherein a remaining film thickness of the polished material is measured from a change in the wavelength of the characteristic peak from a spectral intensity distribution of light reflected from the polished material (planarized film). It is characterized by doing.
  • the present invention also provides the method of manufacturing a semiconductor device, wherein the transparent substrate is polished in the same manner as the material to be polished, and the intensity of the interference light reflected from the polished surface of the transparent substrate and the surface on the opposite side is changed. It is characterized by measuring the polishing rate of the abrasive. Further, according to the present invention, in the method of manufacturing a semiconductor device, the transparent substrate is polished in the same manner as the material to be polished, and a polishing rate of the material to be polished is measured from a movement amount of interference fringes generated from a polished surface of the transparent substrate. It is characterized by the following.
  • the present invention provides a polishing stopper layer forming step of forming a thin polishing stopper layer on a semiconductor substrate, an etching step of digging a recess for element isolation in the semiconductor substrate including the polishing stopper layer, An insulating film forming step of forming a film so as to fill a concave portion dug by the etching step with an insulating film; and chemically and mechanically forming the insulating film formed in the insulating film forming step.
  • An oxidation step of oxidizing a surface of the semiconductor substrate to form an oxide layer, wherein an element isolation structure is formed with respect to the semiconductor substrate.
  • the present invention provides an insulating film pattern forming step of forming an insulating film pattern on a substrate, and forming a film so as to bury a metal material for wiring in a gap of the insulating film pattern formed in the insulating film pattern forming step. And a polishing step of performing chemical and mechanical polishing on the metal material formed in the film forming step to flatten the metal material, thereby forming a gap between the insulating film patterns.
  • a method for manufacturing a semiconductor device comprising forming a wiring pattern.
  • the present invention provides a polishing step of performing chemical and mechanical polishing on a material to be polished formed on a substrate to flatten the same, and a surface generated on the polished surface flattened by the polishing step.
  • An inspection step of inspecting the state of occurrence of roughness or defect, wherein the state of occurrence of surface roughness or defect on the polished surface inspected in the inspection step is fed back to the polishing step, and polishing conditions Semiconductor device manufacturing method characterized by controlling Is the law.
  • the present invention provides a polishing step of performing a chemical and mechanical polishing on a material to be polished formed on a substrate to flatten the same, and a cleaning step of cleaning the polished surface flattened by the polishing step. And an inspection step for inspecting an occurrence state of surface roughness or a defect generated on the polished surface cleaned in the cleaning step.
  • a method of manufacturing a semiconductor device characterized in that the state of occurrence of the defects is fed back to the polishing step to control the polishing conditions so as to optimize the conditions.
  • the present invention provides a polishing step of performing a chemical and mechanical polishing on a material to be polished formed on a substrate to flatten the same, and a cleaning step of cleaning the polished surface flattened by the polishing step. And an inspection step for inspecting the state of occurrence of surface roughness or defects occurring on the polished surface before and after the cleaning step.
  • a method of manufacturing a semiconductor device characterized in that the state of occurrence of defects is fed back to the polishing step to control the polishing conditions so as to optimize the conditions.
  • the present invention provides a polishing step of performing chemical and mechanical polishing on a material to be polished formed on a substrate to flatten the same, and a surface generated on the polished surface flattened by the polishing step.
  • a plurality of semiconductor substrates manufactured in a predetermined manufacturing process of a manufacturing line may be extracted in lots.
  • a defect inspection step of inspecting a defect occurrence state of each semiconductor device An electrical characteristic inspection step of performing an electrical characteristic inspection on each of the semiconductor devices obtained from the semiconductor substrates over the plurality of semiconductor substrates to determine a non-defective product or a defective product; The correlation between the state of generation of foreign matter for each semiconductor device on the plurality of semiconductor substrates and the result of a non-defective product or a defective product of each semiconductor device over the plurality of semiconductor substrates determined in the electrical characteristic inspection step.
  • a defect occurrence investigation process for investigating whether or not the defect origination is caused by a defect, and taking measures against the defect occurrence investigation identified in the defect occurrence investigation process. 6 shows a method for manufacturing a semiconductor device.
  • a plurality of semiconductor substrates manufactured in a predetermined manufacturing process of a manufacturing line may be extracted in lots.
  • the cause of the defect is determined by the defect.
  • a plurality of semiconductor substrates manufactured in a predetermined manufacturing process of a manufacturing line may be extracted in lots.
  • a defect inspection process for inspecting the state of occurrence of defects for each semiconductor device An electrical characteristic inspection step of performing an electrical characteristic inspection on each of the semiconductor devices obtained from the semiconductor substrates over a number of semiconductor substrates to determine a non-defective product or a defective product; Between the result of the non-defective product or defective product of each semiconductor device over the plurality of semiconductor substrates obtained and the state of occurrence of defects for each semiconductor device on the plurality of semiconductor substrates inspected in the defect inspection process.
  • the present invention provides a defect inspection means for inspecting a state of occurrence of a defect of each semiconductor device on a semiconductor substrate over a plurality of semiconductor substrates produced by a predetermined production apparatus of a production line; An electrical characteristic inspection unit that performs an electrical characteristic inspection on each of the semiconductor devices obtained from the semiconductor substrates over a plurality of manufactured semiconductor substrates to determine a non-defective product or a defective product; and an inspection performed by the defect inspection unit. Between the occurrence state of foreign matter for each semiconductor device on the plurality of semiconductor substrates and the result of non-defective or defective product of each semiconductor device across the plurality of semiconductor substrates determined by the electrical characteristic inspection means. Means for determining whether the cause of the failure is due to a defect based on the defect, and the defect determined by the means for determining the cause of the failure.
  • Raw cause a manufacturing system wherein a and Fi one Dobakku child to prescribed manufacturing apparatus.
  • the present invention provides a defect inspection means for inspecting a state of occurrence of a defect of each semiconductor device on a semiconductor substrate over a plurality of semiconductor substrates produced by a predetermined production apparatus of a production line;
  • the non-defective / defective product ratio is determined by conducting an electrical characteristic test on each semiconductor device obtained from the semiconductor substrate over a plurality of manufactured semiconductor substrates to determine a non-defective product or a defective product.
  • an electrical characteristic inspection unit for calculating a defective product ratio, a foreign matter generation state of each semiconductor device on the plurality of semiconductor substrates inspected by the defect inspection unit, and a plurality of electrical characteristics calculated by the electrical characteristic inspection unit.
  • a failure occurrence cause finding means for determining whether or not a failure occurrence is due to a defect based on a correlation with a non-defective rate or a defective rate of each semiconductor device over the entire semiconductor substrate.
  • a semiconductor device manufacturing system characterized in that the fault occurrence cause determined by the fault occurrence cause determining means is fed back to a predetermined manufacturing apparatus.
  • the present invention provides a defect inspection means for inspecting a state of occurrence of a defect of each semiconductor device on a semiconductor substrate over a plurality of semiconductor substrates produced by a predetermined production device of a production line, Electrical characteristic inspection means for performing electrical characteristic inspection on each of the semiconductor devices obtained from the semiconductor substrates over the plurality of semiconductor substrates thus determined to determine a non-defective product or a defective product, and the electrical characteristics.
  • the present invention detects a defect such as a foreign matter attached to a plurality of semiconductor devices (semiconductor elements) on a substrate in an arbitrary manufacturing process, and detects a defect such as a foreign material obtained from an electrical inspection result of the semiconductor device.
  • the detected defect rate (non-defective rate) of the semiconductor device is compared with the defective rate (non-defective rate) of the semiconductor device in which no defect such as a foreign substance is detected, and the comparison result is fed back to the defect inspection apparatus to increase the detection sensitivity.
  • Adjusting (controlling) semiconductor device manufacturing method Is the law.
  • a semiconductor device (semiconductor element) is manufactured with high throughput and high yield by realizing high-throughput, high-precision chemical and mechanical polishing. be able to.
  • a semiconductor device semiconductor element
  • semiconductor element semiconductor element
  • reducing defects and surface roughness such as scratches and foreign substances generated when a material to be planarized is chemically and mechanically polished. It can be manufactured with high yield.
  • an element isolation structure can be formed on a semiconductor substrate by using chemical and mechanical polishing without causing defects.
  • FIG. 1 is a diagram showing a cross-sectional structure of a semiconductor wafer for manufacturing a semiconductor device (semiconductor element) according to the present invention
  • FIG. 2 is a diagram which is generated when an insulating film according to the present invention is subjected to CMP. Scratch formed a wiring pattern on it
  • FIG. 3 is a cross-sectional view illustrating each step for explaining a method of forming a wiring pattern on a substrate by a technique called damascene according to the present invention.
  • FIG. 4 is a perspective view showing a polished surface for explaining that a scratch generated when performing CMP by a method called a damascene according to the present invention may cut the wiring;
  • FIG. 1 is a diagram showing a cross-sectional structure of a semiconductor wafer for manufacturing a semiconductor device (semiconductor element) according to the present invention
  • FIG. 2 is a diagram which is generated when an insulating film according to the present invention is subjected to CMP. Scratch formed
  • FIG. 5 is a sectional view showing each step for explaining a method for forming an element isolation structure on a semiconductor substrate according to the present invention.
  • FIG. 6 is a sectional view showing an element isolation structure on a semiconductor substrate according to the present invention.
  • FIG. 7 is a diagram for explaining that a scratch generated when performing CMP to form a semiconductor substrate enters a semiconductor substrate and loses the function of an active element.
  • FIG. 7 is a diagram illustrating a management system in a CMP process according to the present invention. It is a configuration diagram showing a stem,
  • FIG. 8 is a view showing a schematic configuration of a CMP apparatus and a residual film thickness detecting apparatus according to the present invention.
  • FIG. 9 is a perspective view showing the CMP apparatus shown in FIG. FIG.
  • FIG. 11 is a configuration diagram showing a first embodiment of a residual film thickness detection head shown in FIG. 8, and FIG. 11 is a diagram showing a spectral intensity distribution detected by the detector shown in FIG.
  • FIG. 12 is a diagram showing a signal waveform
  • FIG. 12 is a diagram showing a signal waveform obtained by converting the horizontal axis of the signal waveform shown in FIG. 11 to 1
  • FIG. FIG. 14 is a diagram showing the principle of detection in the residual film thickness detecting device shown in FIG. 14.
  • FIG. 14 shows the material to be polished (from the variation in the wavelength of the characteristic peak of the spectral intensity distribution detected by the detector shown in FIG. 10).
  • FIG. 15 is a diagram for explaining the measurement of the remaining film thickness of the flattening film).
  • FIG. 15 is a configuration diagram showing a second embodiment of the remaining film thickness detection head shown in FIG. so FIG. 16 is a block diagram showing a third embodiment of the remaining film thickness detection head shown in FIG. 8, and FIG. 17 is a diagram showing the remaining film thickness detection head shown in FIG.
  • FIG. 18 is a configuration diagram showing a fourth embodiment of the present invention.
  • FIG. 18 is a diagram showing an intensity distribution of a diffraction image detected in the fourth embodiment shown in FIG.
  • FIG. 19 is based on the intensity distribution of the diffraction image detected in the fourth embodiment shown in FIG.
  • FIG. 20 is a diagram showing signal waveforms.
  • FIG. 20 is a block diagram showing another embodiment for measuring the remaining film thickness.
  • FIG. 21 is a diagram showing the signal detected by the detector shown in FIG. FIG.
  • FIG. 22 is a diagram showing interference fringes and their signal waveforms.
  • FIG. 22 is a configuration diagram showing still another embodiment for measuring a remaining film thickness.
  • FIG. 23 is a diagram showing a polished surface according to the present invention.
  • FIG. 24 is a block diagram showing an embodiment of a defect inspection apparatus for inspecting defects such as scratches and foreign substances on the polished surface in the apparatus shown in FIG. 23.
  • FIG. 25 is an explanatory diagram for performing discrimination processing and detection from signals obtained by the apparatus and the foreign matter.
  • FIG. 26 is a view for explaining scratches and foreign matter generated on the polished surface in the apparatus shown in FIG. 23 from a plurality of directions.
  • FIG. 27 is a diagram schematically illustrating a case where bright light is obliquely irradiated.
  • FIG. 27 is a configuration diagram illustrating a method of illuminating from all directions in the apparatus illustrated in FIG. 23, and FIG. FIG. 29 is a schematic configuration diagram showing one embodiment of a defect inspection apparatus for inspecting a defect such as a scratch or a foreign substance on a polished surface in a liquid according to the present invention.
  • FIG. 30 is a diagram showing a state of detection of a foreign object or a scratch when total reflection occurs in the apparatus shown in FIG. 30.
  • FIG. 30 shows an irradiation angle between the P-polarized illumination light and the S-polarized illumination light shown in FIG.
  • FIG. 31 is a diagram showing reflectivity on the surface according to FIG. 31.
  • FIG. 31 is a schematic configuration diagram showing an embodiment different from FIG. 28, and FIG.
  • FIG. 32 is a manufacturing line of a semiconductor device according to the present invention.
  • FIG. 33 is a configuration diagram illustrating an example of a management system that manages a device.
  • FIG. 33 illustrates a predetermined manufacturing apparatus (a predetermined manufacturing process).
  • FIG. 34 is a diagram for explaining the principle of detecting foreign matter generated by the method. It is a figure which shows the 1st case of distribution over several wafers with the yield of a chip,
  • FIG. 35 shows the difference with respect to the number of the chip with the foreign substance in a wafer unit in a predetermined manufacturing process. It is a figure which shows the 2nd case of distribution over the several wafer of the yield of a chip without a thing, and the yield of a chip with a foreign substance, and FIG.
  • FIG. 36 shows in a predetermined manufacturing process
  • FIG. 37 is a diagram showing a third case of the distribution over a plurality of wafers of the yield of a chip without foreign matter and the yield of a chip with foreign matter with respect to the number of chips having foreign matter in wafer units
  • FIG. 39 In the given manufacturing process, the results of calculating the relationship between the number of chips with foreign particles in each wafer, the yield of chips with no foreign particles, and the yield of chips with foreign particles in each unit are shown.
  • FIG. 38 is a diagram showing the relationship between the number of foreign substances in a chip and the number of chips in which this chip is a good product and a defective product in a predetermined manufacturing process.
  • FIG. 39 is a diagram showing the manufacturing process. In order, the yield of chips without foreign matter and the yield of chips with foreign matter FIG. BEST MODE FOR CARRYING OUT THE INVENTION
  • a semiconductor device (semiconductor element) comprising an LSI or the like according to the present invention is manufactured by repeatedly forming, exposing, and etching a substrate.
  • the semiconductor device (semiconductor element) 300 shown in FIG. 1 is manufactured using a finer pattern in order to realize a higher density.
  • it is necessary to use a multilayer wiring pattern (first-layer wiring pattern 305, second-layer wiring pattern 301, third-layer wiring pattern 302, etc.). For example, even if the third-layer wiring pattern 302 is formed on the second-layer wiring pattern 301 via the interlayer insulating film 303, the surface of the interlayer insulating layer 303 is formed.
  • 304 is the third layer wiring This is an interlayer insulating film or a protective film that covers the pattern. That is, a fourth-layer wiring pattern may be formed on the third-layer wiring pattern 302 in some cases.
  • Reference numeral 2005 denotes a first-layer wiring pattern.
  • Reference numeral 36 denotes a gate wiring.
  • Reference numeral 327 denotes an element isolation structure made of an insulating material.
  • Reference numeral 328 denotes an active element portion such as a MOS structure.
  • a wiring pattern made of a metal material such as copper, silver, gold, or platinum, which is a material having a low wiring resistance, which is a material that is extremely difficult to form a wiring pattern by etching is manufactured using, for example, a damascene method. Will do.
  • the damascene will be described with reference to FIG.
  • FIGS. 3 (a) to 3 (c) an insulating film pattern (negative wiring pattern) 315 of the wiring pattern is formed on the substrate 311. Then, FIG. As shown in (d), a metal material for wiring pattern is buried in the gap between the insulating film patterns 315 by spattering, plating, etc., and then formed as shown in FIG. 3 (e).
  • the metal wiring pattern 317 is formed by polishing to the height of the film pattern 315.
  • the purpose of this damascene is to create wiring patterns from materials that are difficult to etch (metal materials such as copper, silver, gold, and platinum, which have low wiring resistance).
  • metal materials such as copper, silver, gold, and platinum, which have low wiring resistance.
  • FIG. 3 (a) the SiO 2 -based film forming step, An insulating film (SiO 2 -based film) 312 is formed on the substrate 311 by a resist coating process, and a resist 313 is coated thereon.
  • FIG. 3 (b) by exposure and development step, a registry pattern 3 1 4 on the insulating film (S i 0 2 based film) 3 1 2.
  • FIG. 3 (a) the SiO 2 -based film forming step
  • An insulating film (SiO 2 -based film) 312 is formed on the substrate 311 by a resist coating process, and a resist 313 is coated thereon.
  • FIG. 3 (c) to shows, the etching process, and the resist removal process, the insulating film (S i 0 2 based film) 3 1 2 Etsu quenching as described registry pattern 3 1 4 against alms insulating film pattern (S i 0 2 based film pattern) 3 1 5 is formed, to remove the registry pattern 3 1 thereon.
  • a metal material for the wiring pattern (copper, silver, gold, white, which is a material having a low wiring resistance) is formed in the gap between the insulating film patterns 315 by a metal material film forming step. A metal material such as gold) is embedded and formed into a film.
  • the metal wiring pattern 317 is formed by polishing to the height of the insulating film pattern 315 by a polishing step.
  • a metal material for the wiring pattern (a material having a low wiring resistance) is formed by filling the gap between the insulating film patterns 3 1 5.
  • a certain metal material such as copper, silver, gold, and platinum
  • an element isolation structure 327 for isolating an active element portion 328 such as a transistor having a MOS structure
  • a SiO 2 -based oxide insulation is required.
  • the film needs to be polished and planarized.
  • a method of manufacturing an element isolation structure 327 for isolating an active element portion 328 such as a transistor having a MOS structure will be described with reference to FIG.
  • the Si 3 N 4 layer forming step and the resist coating step are performed in a nitrogen atmosphere on the Si substrate 321, so that 0.1 to 0. .
  • a Si 3 N 4 layer 3 22 with excellent thermal shock resistance consisting of a thin film layer of about 2 m is formed, and a resist 3 23 is applied thereon.
  • a resist pattern 324 is formed by an exposure and development process.
  • the Si 3 N 4 film 32 2 and the Si substrate 32 1 are etched according to the resist pattern 324 by an etching step and a resist removing step. Then, a groove 325 for element isolation is formed, and the resist pattern 32 thereon is removed.
  • deposition film of S i 0 2 system by CVD or the like so as to fill the groove 3 2 5 for element isolation 3 26 is deposited.
  • the formed SiO 2 -based deposition film 326 was formed by a polishing process to increase the height of the Si 3 N 4 layer 32 2 having excellent thermal shock resistance. Polish to the end. Since the Si 3 N 4 layer 322 having excellent thermal shock resistance is provided, it is possible to prevent the Si 3 N 4 layer 322 from directly contacting the Si substrate 3 21 during polishing and flattening.
  • the S i 3 N 4 layer removal step Subsequently, as shown in FIG. 5 (f), removing the S i 3 N 4 layer 3 2 2.
  • the Si 3 N 4 layer 3 22 may be any material that can withstand polishing and can be removed from the Si substrate 3 21 thereafter.
  • the element c can be separated by the film 327, that is, an element isolation structure 327 in which the active element part 328 is separated by a SiO 2 -based insulating film can be obtained.
  • the film to be planarized is the interlayer insulating film 303
  • the film is transparent to light
  • the wiring pattern 301 exists below.
  • the polished semiconductor substrate is stored in a liquid until cleaning, thereby preventing the abrasive grains from firmly adhering to the polished surface without being exposed to the air. Even in this case, it is necessary to realize the measurement of the remaining film thickness and the inspection of foreign matter and scratches with high accuracy.
  • the present invention is to reduce the influence of the underlying pattern and realize highly accurate remaining film thickness measurement. Specifically, by detecting the waveform of the film thickness measurement in a pattern in which the remaining film thickness is known in advance on a wafer on which a good pattern exists, and comparing the result with the detection result from the object to be measured. The influence of the underlayer pattern is removed, and the remaining film thickness with high accuracy is measured.
  • FIG. 2 (b) is a side sectional view of FIG. 2 (a).
  • the metal film for the third-layer wiring pattern will not be formed at the place of the foreign matter when the metal film is formed. This causes disconnection of the layer wiring pattern.
  • there is an electrically conductive foreign substance on the flattening film made of the interlayer insulating film 303 it may cause a short circuit between the third-layer wiring patterns.
  • the semiconductor device may be damaged. Further on the planarization film made of S i 0 2 based film 3 1 5 and the metal wiring patterns 3 1 7 for, when foreign matter or scratches present on the co Ntaku isolation portion of the upper wiring pattern, and causes of contactor bets poor In addition, the presence of electrically conductive foreign substances on the flattening film causes a short circuit between the metal wiring patterns 317.
  • the thickness of the Si 3 N 4 layer 322 forming the active element 328 is 0.05 to 0.3 ⁇ m. It is formed to a very small extent, and if any more foreign matter or flaws 329 exist on the polished surface as shown in Fig. 6 (a) and (b), it can easily be placed on the Si side.
  • the active element 3 288 does not operate normally.
  • FIG. 6 (a) is a plan view showing the planarized film surface (polished surface) shown in FIG. 5 (e), and FIG. 6 (b) is a side sectional view of FIG. 6 (a). is there. Therefore, there is no defect such as a scratch or foreign matter on the planarized film surface (polished surface) shown in FIG. By inspecting and monitoring whether or not this is the case, it is possible to obtain a polished surface on which the active element operates normally for the first time.
  • the function as a semiconductor element can be obtained.
  • a semiconductor device having high reliability can be realized. That is, since the object to be inspected for the presence of a defect such as a scratch or a foreign matter is a polished surface, the detection signal component from the surface polished by the surface polishing is made sufficiently small so that the surface polished by the polishing is reduced. It is possible to inspect with high sensitivity (high resolution) whether or not there is a defect such as a scratch or a foreign substance by reducing the influence of the defect.
  • FIG. 7 is a diagram showing a schematic configuration of the entire system.
  • the CMP device 200 supplies a polishing platen 210 called a platen on which a polishing cloth is adhered, and a supply of a suspension of polishing abrasive grains called a slurry onto the polishing cloth of the polishing platen 201.
  • Means 203-The semiconductor wafer 1 which is the material to be polished is supported, and revolving and rotating between the polishing platen 201 and the polishing platen 201 while flowing a suspension of abrasive grains called slurry.
  • a control device 20 for controlling the driving rotation speed of a rotary drive device for rotating the polishing head 200 and revolving and rotating, the polishing pressure applied by the polishing pressure applying means, and the polishing time. Be composed.
  • the control device 204 controls the polishing conditions (type of water suspension of polishing abrasive grains, polishing head 200) according to the type of semiconductor wafer 1 that is the material to be polished to be input into the CMP device 200. 0 rotation and rotation speed, polishing pressure, polishing time, etc.) are set. Then, only the polishing time calculated from the rough polishing speed previously determined according to the type of the semiconductor wafer 1 to be polished into the CMP device 200 by the control device 204 (when the time is slightly shorter). After polishing by the CMP device, the polishing head 202 rises to the position of 202 'and pure water is applied to the semiconductor wafer 1 to polish the semiconductor wafer 1 The surface is cleaned.
  • polishing conditions type of water suspension of polishing abrasive grains, polishing head 200
  • the remaining film thickness detection head 211 is installed so as to face the polished surface of the semiconductor wafer 1.
  • the remaining film thickness detecting device 210 for measuring the remaining film thickness of the film to be polished on the surface of the semiconductor wafer 1 includes the remaining film thickness detecting head 211 and the remaining film thickness detecting head 2 1 1 And a processing means 2 12 composed of a microcomputer or the like that processes the signal detected by the microcomputer.
  • the remaining film thickness data of the film to be polished on the surface of the semiconductor wafer 1 calculated by the processing means 2 12 of the remaining film thickness detecting device 210 is fed back to the control device 204 of the CMP device, and the control device Based on the remaining film thickness data fed back, 204 controls the transition from, for example, high-speed polishing to low-speed, high-definition polishing, controls the polishing time, and executes planarization with a desired film thickness.
  • the remaining film thickness of the film to be polished on the surface of the semiconductor wafer 1 can be monitored by the remaining film thickness detecting device 210, a high-throughput polishing method with a high throughput, Immediately before the end of polishing, it is possible to perform multi-stage polishing using a low-speed and high-definition polishing method that has a low throughput but has almost no defects such as scratches and foreign matter, and improves the polishing throughput. Defects such as scratches and foreign substances can be eliminated.
  • the semiconductor wafer 1 When the polishing of the surface of the semiconductor wafer 1 is completed as described above, the semiconductor wafer 1 is removed from the polishing head 202, and is cleaned until it is cleaned by the cleaning device 230. It will be stored in the liquid. The reason is that when stored in air, the abrasive grains that have adhered to the semiconductor wafer 1 due to the chemical reaction between water and oxygen in the air, etc., will adhere strongly to the wafer surface, and subsequent cleaning This is because it will no longer be possible. In addition, when inspecting whether or not there is a defect such as a scratch or a foreign substance on the polished surface after the polishing of the semiconductor wafer, it is necessary to perform the inspection while distinguishing from the fine roughness of the surface due to polishing.
  • the polished semiconductor wafer 1 is stored in a liquid and optically inspected for defects such as scratches and foreign matter on the polished surface by using a scratch / foreign matter inspection device 220, In addition, it is possible to prevent the abrasive grains from firmly adhering to the wafer surface, and to easily set the conditions for total reflection on the polished surface so that light from the underlying wiring pattern cannot be obtained. Obtainable.
  • the scratch / foreign matter inspection device 220 stores an immersion liquid for the semiconductor wafer 1 having a polished polished surface, and an illumination window for irradiating the polished surface of the semiconductor wafer 1 with light under the condition of total reflection. 1 and a tank 3 having a detection window 35 for detecting scattered reflected light from the polished surface, and an objective lens 31 for condensing scattered reflected light from the polished surface obtained through the detection window 35.
  • a detector 34 composed of a linear image sensor that receives the light condensed by the objective lens 31 and converts it into a signal; It comprises processing means 221 composed of a microcomputer or the like for processing a detected pixel signal to detect a defect such as a scratch or a foreign matter on the polished surface.
  • the polished surface is in a state before being cleaned, and there is a high possibility that the abrasive grains are attached. Therefore, the scratch / foreign matter inspection device 220 is capable of detecting defects such as scratches and foreign matter present on the polished surface. It is necessary to discriminate and inspect abrasive grains. Therefore, it is not necessary to inspect the polished surface of the semiconductor wafer 1 for defects such as scratches and foreign substances while being immersed in the liquid in the tank 3.
  • the cleaning device 230 cleans the semiconductor wafer 1 polished by the CMP device 200 and removes the abrasive wafer and the like attached to the polished surface.
  • the scratch / foreign matter inspection device 240 inspects defects such as scratches and foreign matter present on the polished surface of the semiconductor wafer 1 cleaned by the cleaning device 230 ⁇
  • Reference numeral 40 denotes the final inspection of the polished surface of the semiconductor wafer 1 cleaned by the cleaning device 230, so that, for example, the same optical system as the remaining film thickness detection head 210 is installed and polished. You may comprise so that the film thickness of a surface may be measured.
  • the scratch / foreign matter inspection device 240 includes a stage system 70 on which the semiconductor wafer 1 cleaned by the cleaning device 230 is placed, and an illumination system 10 for irradiating the polished surface of the semiconductor wafer with light.
  • a detection optical system 30 having a detector 3 for detecting scattered light from scratches and foreign matter on the polished surface; and processing of pixel signals obtained from the detector 34 to detect defects such as scratches and foreign matter on the polished surface. It comprises processing means 21 comprising a microcomputer or the like for detecting.
  • the computer 250 controls production of the polished surface of the semiconductor wafer 1.
  • the processing means 222 of the inspection device 220 and the processing means 241 of the scratch / foreign matter inspection device 240 are connected via a network.
  • the computer 250 is a control device 204 of the CMP device 200.
  • Conditions set in accordance with the type of the semiconductor wafer 1 to be polished, which is to be polished into the CMP apparatus 200 (the type of the aqueous suspension of the abrasive grains, the revolution of the polishing head 200). And rotation speed of rotation, polishing pressure, polishing time, etc.), and the residual film thickness measurement result corresponding to the type of the semiconductor wafer 1 can be obtained from the processing means 2 12 of the residual film thickness detecting device 210.
  • From the processing means 222 of the scratch / foreign matter inspection device 220 information on defects such as scratches and foreign materials present on the polished surface before cleaning (including information on the position where the defect has occurred) can be obtained.
  • reference numeral 255 denotes a display means composed of a display or the like.
  • Reference numeral 253 denotes an input means composed of a keyboard, a recording medium, and the like.
  • Reference numeral 254 denotes an output unit composed of a printing machine, a recording medium, and the like.
  • the computer 250 can provide information on the defect such as a scratch or a foreign substance present on the final polished surface inspected by the scratch / foreign substance inspection device 240 and the polishing conditions at that time in units of the semiconductor wafer 1.
  • Data related to the type of suspension of polishing abrasive grains, the rotational speed of the polishing head 200 and its rotation, the polishing pressure and the polishing time are read out from the storage device 25 1 in association with each other.
  • the administrator estimates the polishing condition, which is the cause of the defect, while viewing the information displayed on the display means 25, and inputs the polishing condition, the estimated cause, to the input means 25, 53.
  • the computer 250 analyzes whether or not the polishing condition estimated from the correspondence between the past defect information and the polishing condition is correct, and when it is determined to be correct, the polishing condition is transmitted to the controller 204. give feedback.
  • the control device 204 issues a command to change the polishing condition to the CMP device 200 so as to change the polishing condition, and the polishing is performed on the semiconductor wafer 1 which is input under the corrected polishing condition. .
  • polishing can be performed without causing many defect defects.
  • the administrator estimates the polishing conditions, which are the causes of the defects, while looking at the information displayed on the display means 250, but the estimated algorithm is stored in the memory in the computer 250. If this is input and stored in advance, the computer 250 estimates the polishing condition that is the cause of the defect based on the estimation algorithm, and determines whether the estimated polishing condition is appropriate. It can be determined based on past career information.
  • FIG. 8 is a front view showing the CMP apparatus 200 and the remaining film thickness detecting apparatus 210
  • FIG. 9 is a perspective view showing the CMP apparatus 200.
  • a CMP (chemical mechanical polishing) device 200 is composed of a polishing platen 210, called a platen, to which a polishing pad 204 is attached, and a suspension of abrasive grains called a slurry on the surface.
  • a water suspension liquid supply means 203 for polishing abrasive grains and a semiconductor wafer as a material to be polished are supported, and are disposed at 120 ° intervals so that revolving and rotation are performed.
  • three polishing heads 202 are provided.
  • Each semiconductor head 1 is supported by each polishing head 202 while a suspension of polishing abrasive grains, called a slurry, is flown onto the surface of the polishing cloth 204 attached to the surface of the polishing platen 201. While applying polishing pressure, the polishing platen 201 revolves and the polishing head 202 rotates. By performing such rotation, the surface of the semiconductor wafer 1 is polished in multiple stages. Based on the control signal from the control device 204, high-speed polishing is first performed, and when the polishing is approaching the end, the polishing is switched to low-speed high-definition polishing and the process is shifted. As a result, polishing can be performed at a high throughput, and the occurrence of defects such as scratches and foreign substances on the surface at the end of polishing can be minimized.
  • a suspension of polishing abrasive grains called a slurry
  • polishing head 202 is rotated at high speed during polishing (specifically, for example, The rotation speed is greater than 60 rpm, and the pressure between the material to be polished and the polishing pad (polishing pad) is increased (specifically, for example, a pressure greater than 100 g / cm 2 ).
  • polishing head 202 In low-speed polishing, small abrasive grains (specifically, for example, smaller than 50 nm) are used, and the polishing head 202 is rotated at a low speed during polishing (specifically, for example, (Rotation speed less than 60 rpm), and reduce the pressure between the workpiece and the polishing pad (polishing pad) (specifically, for example, a pressure less than 100 g Z cm 2 ).
  • a low speed during polishing specifically, for example, (Rotation speed less than 60 rpm)
  • polishing pad specifically, for example, a pressure less than 100 g Z cm 2
  • the polishing was performed only for the polishing time calculated from the rough polishing speed previously obtained by the CMP device 200 (only a slightly smaller polishing time). Then, the polishing head 202 is raised to the position 202 ', pure water is applied to the semiconductor wafer 1 supported by the polishing head 202 to wash the polished surface, and the remaining film amount described later.
  • the detection head 211 is inserted, and the remaining film thickness of the film to be polished on the wafer surface is measured by the remaining film thickness detecting device 210.
  • the remaining film thickness measured by the remaining film thickness detecting device 210 has reached a predetermined amount, the polishing is finished, and if not, the processing means 212 detects the remaining film thickness.
  • the control device 204 calculates the subsequent polishing time from the remaining film thickness, and the calculated polishing time is calculated.
  • the polishing is further performed by the calculated polishing time. As a result, the amount of polishing at the end point does not greatly deviate.
  • FIG. 10 is a configuration diagram showing a first embodiment of the remaining film thickness detection head 2 11.
  • the remaining film thickness detection head 211 is a light source 261 composed of a halogen lamp or the like, a pinhole 262 forming a point light source, and light emitted from the pinhole 262 being substantially parallel.
  • An illumination optical system consisting of a condenser lens 263 that converts the light into light 265 and irradiates the polished surface of the semiconductor wafer 1 with a half mirror 264, a diffraction grating 271, an imaging lens 272 And a detector 33.
  • the image of the point light source by the pinhole 262 is formed through the condenser lens 263, the polished surface of the semiconductor wafer 1 (film to be planarized), the half mirror 264, and the diffraction lens 271.
  • An image is formed on the detector 2 7 3 by 2 7 2.
  • the diffraction angle of the diffraction grating 332 differs for each wavelength of the light source, it is imaged as a spectral image on the detector 3334, and the waveform shown in FIG. 11 is detected.
  • FIG. 11 shows a detection waveform with respect to a wavelength detected by spectroscopy on the detector 273.
  • FIG. 12 shows a detection waveform for one wavelength that is spectrally detected on the detector 273. In the case of FIG.
  • the horizontal axis is the wavelength, and in the case of FIG. 12, the horizontal axis is 1 / wavelength ⁇ .
  • the longer the wavelength ⁇ the longer the pitch of the peak position of the waveform.
  • the pitches of the waveform peak positions are arranged at equal intervals at all positions. Therefore, the remaining film thickness d can be calculated by the following (Equation 1).
  • Equation 1 N / (2 ⁇ ⁇ ( ⁇ / ⁇ ,- ⁇ / ⁇ 2 )) (Equation 1) where ⁇ is the peak from the peak position (1 /) to the peak position (1 Z ⁇ 2 ) It is the number. Peaks can be maximum or minimum Les ,. n is the refractive index of the insulating film to be polished.
  • the pinhole 262 may be a one-dimensional pinhole, that is, a slit.
  • the light source be formed by a point light source or a slit light source and be able to irradiate the polished surface with substantially parallel light.
  • FIG. 13 shows a cross-sectional view of the object for measuring the remaining film thickness.
  • the remaining film thickness measurement target semiconductor wafer
  • a wiring pattern 13 2 (301) is formed on a base pattern 13 1, and the gap is further filled.
  • the light 265 applied to the surface of the insulating film 133 (303) planarized by the polishing is flat because the insulating film (film to be planarized) 133 is transparent.
  • the light is reflected at three points on the surface of the oxide film 13 3, the top (upper surface) of the wiring pattern 13 2, and the bottom of the wiring pattern 13 2, and reaches the detector 2 73.
  • the underlying pattern itself is complicated, and furthermore, light reaches the ground and forms a more complicated wavefront.
  • the three light beams interfere with each other, and the waveform shown in FIG. 11 is detected. Therefore, this detection waveform is such that interference light generated from three optical path differences of dl, d2, and d3 is superimposed. Therefore, it is necessary to separate (decompose) these three interference lights in order to realize more accurate measurement.
  • the frequency analysis of the detected waveform shown in Fig. 12 is effective.
  • This frequency analysis may be a Fourier analysis such as an FFT or a predictive frequency analysis such as a maximum entrance peak method.
  • the frequency analysis is performed by the processing means 2 12 and separated (decomposed), and the remaining film thickness d can be measured from the separated one based on the above (Equation 1).
  • the remaining film thickness can be measured with high accuracy. In rough cases, accuracy may decrease. In order to maintain the accuracy even in such a case, attention may be paid to a specific peak as shown in FIG. 14 and the lateral fluctuation ⁇ of the peak may be detected (monitored). This allows for more accurate detection. In this case, the peak shift ⁇ may not always change linearly with the remaining film thickness. Therefore, for more accurate detection, it is preferable to use a table showing the relationship between the amount of movement measured in advance and the amount of remaining film thickness. This conversion is automatically performed on the processing means 2 12 such as a microcomputer.
  • FIG. 15 is a configuration diagram showing a second embodiment of the remaining film thickness detection head 2 11. That is, when the interlayer insulating film 133 (303) is polished and flattened on the semiconductor wafer 1, the wiring pattern 133 (300) is provided below the interlayer insulating film 133 (303). 1) is regularly formed. Therefore, when the polished inter-layer insulating film 13 3 (30 3) is irradiated with the illumination light 265, the regularly arranged wiring patterns 13 2 (30 1) form the diffraction grating. As a function, the reflected light separated from the interlayer insulating film 133 (303) is obtained, and the separated light is received by the detector 273, as shown in FIG. Signal can be detected.
  • the remaining film thickness can be calculated based on (Equation 1) by converting the signals into the signals shown in FIG. 12 by the processing means 2 12.
  • Equation 1 the remaining film thickness
  • FIG. 16 is a configuration diagram showing a third embodiment of the head 211 for detecting the remaining film thickness.
  • the third embodiment is basically the same as the second embodiment shown in FIG. That is, when the interlayer insulating film 133 (303) is polished and flattened in the semiconductor wafer 1, the wiring pattern 133 (303) is provided below the interlayer insulating film 133 (303). ) Are regularly formed. Head for detecting remaining film thickness
  • a light source 261 which is constituted by a halogen lamp, etc.
  • a pinhole 262 forming a point light source, and light emitted from the pinhole 262 are converted into substantially parallel light 265.
  • an illumination optical system comprising a condensing lens 263 for irradiating the illumination light 2665 to the polished interlayer insulating film 133 (303) of the semiconductor wafer 1 from an oblique direction.
  • An imaging optical system including an imaging lens 272 and a detector 273 for detecting an image that has been split and formed. Therefore, when the polished interlayer insulating film 1 3 3 (3 0 3) is irradiated with the illumination light 2 65, the regularly arranged wiring patterns 1 3 2
  • the processing means 2 12 functions as a diffraction grating, and the reflected light that is spectrally separated from the interlayer insulating film 133 (303) is obtained.
  • the spectrally separated light is converted by the imaging lens 272.
  • the detector 273 By forming an image and receiving the formed spectral image by the detector 273, a signal as shown in FIG. 11 can be detected. Therefore, by converting the signals into the signals shown in FIG. 12 by the processing means 2 12,
  • the remaining film thickness can be calculated based on (Equation 1).
  • equation 1 the remaining film thickness
  • FIG. 17 is a configuration diagram showing a fourth embodiment of the remaining film thickness detection head 2 11. That is, the remaining film thickness detection head 211 is formed of a white light source 331, a half mirror 3333, and a semiconductor wafer 1 which condenses the white light emitted from the white light source 3311.
  • a condenser lens (imaging lens) 332 that forms an image on the detector 3334 by irradiating the polished surface of the semiconductor wafer 1 with the diffracted light obtained from the polished surface (film to be planarized) of the semiconductor wafer 1;
  • a detector 334 for receiving the formed diffraction image and converting it into a diffraction image signal.
  • FIG. 1 is a configuration diagram showing a fourth embodiment of the remaining film thickness detection head 2 11. That is, the remaining film thickness detection head 211 is formed of a white light source 331, a half mirror 3333, and a semiconductor wafer 1 which condenses the white light emitted from the white light source 3311.
  • Fig. 18 shows the intensity distribution of the diffraction image 146 on the diffraction image surface 144 detected by the detector 334.
  • Fig. 19 shows the change of the remaining film thickness in the u-direction (radius method) on the diffraction image plane.
  • 14 shows changes in the intensity distribution of the diffraction image according to the transformation. Therefore, by measuring and storing in advance the intensity distribution of the diffraction image corresponding to a plurality of remaining film thicknesses in the memory in the processing means 2 12, the processing means 2 12 The remaining film thickness can be calculated by interpolating the intensity distribution of the diffraction image corresponding to the plurality of remaining film thicknesses stored in the memory from the intensity distribution of the diffraction image detected in step (1).
  • FIG. 20 is a block diagram showing another embodiment for measuring the remaining film thickness.
  • This embodiment is provided with a small polishing head 202a for supporting a sample 281, which is made of a tapered transparent substrate for measuring the remaining film thickness, and uses the original polishing head 202.
  • the sample 281 is configured to be polished with a polishing platen 201 on which a polishing cloth 204 is adhered. That is, similarly to the polishing head 202, the polishing head 202a is rotationally driven so as to rotate by applying a polishing pressure.
  • the polishing amount for the semiconductor wafer 1 and the polishing amount for the sample 281 can be matched. In any case, it is necessary to determine in advance the correlation between the polishing amount for the semiconductor wafer 1 and the polishing amount for the sample 28 1. Since the correlation between the amount of polishing for the semiconductor wafer 1 and the amount of polishing for the sample 28 1 has been grasped in this manner, the remaining film thickness for the semiconductor wafer 1 is measured by measuring the remaining film thickness for the sample 28 1. Can be calculated.
  • a polishing head 202 a a coherent light source 282 such as a laser, a half mirror 283 and a detector 284 are provided, and a polishing head 202 a is provided.
  • the supported sample (tapered transparent substrate) 281 was irradiated with coherent light from the back through window 285 from behind, and the tapered transparent substrate was exposed.
  • An interference optical system is formed in which an interference fringe image (shown in FIG. 21 (a)) from the bright substrate 281 is detected by a detector 284.
  • the coherent light source 282 does not necessarily need to be a laser, but may use a white light source such as a halogen lamp to form a coherent state in the entire optical system.
  • the detector 284 receives the interference fringe image 286 shown in FIG. 21 (a) and receives the interference fringe image 286 shown in FIG. 21 (b) according to the remaining film thickness of the sample 281. Signals 287 and 288 are obtained. Therefore, by calculating the shift amount 51 of the signals 287 and 288 in the processing means 211 with i O, the remaining film thickness of the sample 281 can be obtained.
  • the remaining film thickness for the semiconductor wafer 1 can be calculated from the correlation between the polishing amount for the wafer 1 and the polishing amount for the sample 28 1. In the case of this embodiment, the remaining film thickness can be calculated at any time during polishing. During polishing, the sample 2
  • the illumination optical system and the detection optical system composed of the 20-color 2831 and the detector 2884 are provided. May be installed. In this case, in order to measure the remaining film thickness of the sample 281 supported on the polishing head 202a, as shown in FIG. 8, the polishing head 202a was used. Raise to position 2 0 2 '.
  • the polished sample (taper For the polishing head 202a supporting the 281, the remaining film thickness of the sample 281, as with the remaining film thickness detection head 211 shown in FIG.
  • the quantity can be measured.
  • FIG. 22 is a block diagram showing another embodiment different from FIG. 20 for measuring the remaining film thickness.
  • This example has a small polishing head 202a supporting a sample 291, which is a parallel transparent substrate for measuring the remaining film thickness, and has a semiconductor polishing method using the original polishing head 202.
  • the sample 291 is polished with the polishing platen 201 on which the polishing cloth 20 is adhered. That is, similarly to the polishing head 202, the polishing head 202a is also driven to rotate by applying a polishing pressure and rotating.
  • the material to be polished for the semiconductor wafer 1 is the insulating film 303, 326, the material of the insulating film 303, 326 and the material of the sample 291.
  • the amount of polishing for the semiconductor wafer 1 and the amount of polishing for the sample 29 1 can be matched.
  • the coherent light such as a laser is applied to the polishing head 202 a from an oblique direction symmetrically with respect to the detection optical axis 294 so as to substantially overlap the polished surface of the sample 29 1.
  • Specimen parallel transparent substrate supported by a polishing head 202a, comprising an irradiation optical system for irradiating 293b and 293b, an imaging lens 292, and a detector 284
  • the coherent light beams 293 a and 293 b are obliquely symmetrical with respect to the detection optical axis 294 through the window 285 from the back side of the sample 291 so that they almost overlap each other on the polished surface of the sample 291.
  • the detector 284 receives the interference fringe image 286 shown in FIG. 21 (a) and receives the interference fringe image 286 shown in FIG. 21 (b) according to the remaining film thickness of the sample 291. Signals 287 and 288 are obtained.
  • the remaining film thickness of the sample 291 can be obtained by calculating the shift amount 51 of the signals 287 and 288 in the processing means 2 12, and as a result, the semiconductor wafer 1
  • the remaining film thickness for the semiconductor wafer 1 can be calculated from the correlation between the polishing amount for the semiconductor wafer 1 and the polishing amount for the sample 29 1.
  • the remaining film thickness can be calculated at any time during polishing.
  • a water suspension of abrasive grains is interposed between the polished surface of the sample 291 and the polishing cloth 204.
  • the interference fringes shown in Fig. 21 (a) can be detected without being greatly affected by the water suspension.
  • the polishing speed (polishing rate) can be monitored in real time during polishing, the film thickness must be measured in advance. The amount of residual film thickness can be monitored, and the switching from high-speed polishing to high-precision low-speed polishing can be delayed until the time when defects such as scratches and foreign matter do not finally occur is reached. As a result, a flattened polished surface free of defects such as scratches and foreign substances can be manufactured at a high throughput with respect to the semiconductor wafer 1.
  • the metal film 3 16 is applied to the CMP device 20 as shown in FIG. Even when polishing at 0, it is necessary to predict or detect the point in time when the lower SiO 2 -based insulating film pattern 3 15 is exposed as the remaining film thickness. Therefore, the cross-sectional structure shown in Fig. 3 (d) A semiconductor wafer 1 having a structure is supported on a polishing head 202, and a metal film 3 16 on the surface of the semiconductor nano 1 is connected to a polishing cloth 204 adhered to a polishing platen 201.
  • the head 202 is raised to the position 202 ', and the semiconductor wafer 1 supported by the polishing head 202 is washed with pure water to wash the polished surface of the semiconductor wafer 1.
  • the thickness of the wiring pattern with the exposed insulating film pattern 3 15 can be optically measured by optical interference using the remaining film thickness detecting head 2 1 1, which is appropriate for the end point of polishing. Or not. In other words, when only the metal film 316 is formed on the surface, no interference occurs, so that a flat detection waveform is detected.
  • the insulating film pattern 315 below the metal film 316 When the insulating film pattern 315 below the metal film 316 is exposed, the insulating film is formed. Reflected light from the lower surface of 315 (only a small amount of reflected light is obtained from the lower surface of the insulating film 315 when the surface of the substrate 315 is formed of an insulating film) and metal wiring By detecting a waveform due to interference with the pattern 317 or the light reflected from the surface of the insulating film 315, it can be determined whether or not the polishing end point is appropriate. In particular, when the third embodiment shown in FIG. 16 is used as the remaining film thickness detection head 211, the configuration is simple and appropriate. Next, the defect inspection apparatus 240 for scratches / foreign matter will be specifically described with reference to FIGS. 23 to 26. FIG.
  • FIG. 23 is a configuration diagram showing a first embodiment of the defect inspection apparatus 240 for flaws and foreign matter according to the present invention.
  • an argon laser 1 a beam expander 12, a half-wave plate 13, a polarizing element 14, a polarizing element rotating mechanism 15 for changing the polarization direction of the polarizing element 14,
  • An illumination system 1 consisting of a condenser lens 16 such as a cylindrical lens and a variable incident angle mechanism 17 and an objective lens 31, a polarizing element 32, a spatial filter 33, and a detector 34.
  • the detection optical system 30 formed, the binarization circuit 51, the coordinate generation circuit 52, the detection result memory 54, the computer 53, and the detection result display means 55
  • a loading / unloading means 7 an xyz stage 71, an automatic focus detection system 73, a z stage controller 75, and an xy stage controller 72.
  • the computer 53 constituting the data processing system (processing means) 24 1 is connected to the management computer 250 via a network.
  • the semiconductor wafer 1 polished by the CMP device 200 and washed by at least the cleaning device 230 is transported from the cleaning device 230 to a loading position using a transporting device, and is loaded by the loading device 74. It is placed on the xyz stage 71 with the polished surface facing upward.
  • Inspection range data input and set in advance to the computer 53 is provided to the xy stage controller 72, and the xy stage 71 is changed to xy based on the control of the xy stage controller 72.
  • the output of the xy stage controller 72 is led to a coordinate generation circuit 52, which is used to create the coordinates of the inspection position.
  • the automatic focus detection system 73 detects the focus position based on the amount of defocus by projecting a stripe pattern. It may be one that detects the position, or one that measures the z position with a capacitance type sensor.
  • the light emitted from the argon laser 11 has its beam diameter expanded by the beam expander 12, is converted into circular or elliptically polarized light through the half-wave plate 13, and is S-polarized or polarized by the polarizing element 14.
  • the light is converted into P-polarized light, condensed in a narrow band shape by a condensing lens 16 such as a cylindrical lens, and is irradiated onto the flattened polished surface on the semiconductor wafer 1.
  • the polished surface of the semiconductor wafer 1 is condensed by the detection lens 31 and is detected by the detector 34 through the polarizing element 32 or the filter and the spatial filter 33. That is, the polished surface of the semiconductor wafer 1 is irradiated with condensed laser light from an oblique direction, the xy stage 71 is scanned, and the scattered diffraction light from the polished surface of the semiconductor wafer 1 is applied to the objective lens 31.
  • the polished surface of the semiconductor wafer 1 is, for example, the interlayer insulating film 303
  • the wiring pattern 301 underneath causes scattering scattering from the regularly arranged wiring pattern 301.
  • the emitted light is shielded by a polarizing element 32 or a spatial filter 33, and an image due to scattered diffraction light generated from the polished surface of the semiconductor wafer 1 is received by a detector 34 constituted by, for example, a linear sensor (CCD), and a detection signal is received. 3 7 is output.
  • the detection signal 37 is converted into a binarized signal by a binarization circuit 51 at a desired threshold, and a defect such as a scratch or a foreign substance present on the polished surface exceeding the desired threshold in the binarized signal.
  • the detection result memory 54 stores the positions of the occurrence positions of the scratches and the foreign matters by discriminating them from each other.
  • the computer 53 Since the target is stored for each semiconductor wafer in correspondence with each other, the computer 53 reads out the stored data to read the stored data for each semiconductor wafer, for a plurality of semiconductor wafers, or for each lot.
  • the distribution of flaws and foreign matter generated on the semiconductor wafer can be collected as a map, which can be displayed on the display means 55 and provided to the management computer 250 for storage.
  • the information can be stored in the device 25 1 or displayed on the display means 25 2.
  • the computer 53 can collect changes (fluctuations) in the number of scratches or foreign substances generated on the semiconductor wafer for each semiconductor wafer or for each lot, and display them on the display means 55. It can also be provided to the management computer 250 and stored in the storage device 251, or displayed on the display means 252.
  • FIGS. 24 (a) and (b) show a light beam 10 ° applied to the surface (polished surface) of the semiconductor wafer 1.
  • FIG. Fig. 24 (a) shows the case where the surface (polished surface) is rough after film formation and after the CMP treatment
  • Fig. 24 (b) shows the case where the surface is not rough and foreign matter 41 is present.
  • FIGS. 24 (c) and (d) show the detection signal waveforms 109 and 110 obtained by receiving the scattered light with the detector 34 in each case. By the way, the signal waveform 109 based on the surface roughness shown in FIG.
  • the size of the detection pixel needs to be 7 ⁇ m square on the surface (polished surface). If the pixel size of the CCD itself is, for example, 13 square, the imaging magnification by the objective lens 31 may be about 1.9 times.
  • the value of the detection pixel size should be selected according to the purpose in relation to these other parameters. If you want to have sufficient detection sensitivity, convert to ⁇ ! ⁇ 2; It is desirable to make it about m square.
  • the threshold value may be set to the threshold value 112 shown in FIG. 24 (c). That is, when information on surface roughness is required when setting polishing conditions in the CMP apparatus 200, the defect inspection apparatus 2
  • the binarization circuit 51 is for erasing a rough surface signal, and need not necessarily be a binarization circuit. That is, the signal detected by the detector 34 is converted into image data quantized by a multi-valued threshold, and the image data is correlated with the position coordinates on the surface (polished surface), and the detection result memory is stored.
  • the computer 53 reads out the data stored in the detection result memory 54 and performs a classification process according to the size of the flaw generated on the surface (polished surface) of the semiconductor wafer 1 to determine whether the quality is good or bad. This has the effect of making a determination. Also, out of multiple thresholds By using either (or more than one) as the threshold for detecting surface roughness, the level of surface roughness, or distribution of surface roughness, can be measured, and the results can be used for management. By performing feed-packing to the CMP apparatus 200 via the computer 250, the polishing conditions in the CMP apparatus 200 can be optimized.
  • the computer 53 obtains the detection results (quantized image data from which surface roughness has been removed) for each semiconductor wafer 1 stored in the detection result memory 5 as shown in FIG. 25 (a). Scratches 40 usually appear in multiple continuous (or intermittently continuous) forms, and as shown in Fig. 25 (b), the foreign matter 41 usually appears in an isolated form. Are classified into flaws and foreign substances by shape recognition processing based on basic knowledge. Then, for each semiconductor wafer 1, the computer 53 groups adjacent flaws into one continuous flaw with respect to the image data classified as flaws, and counts the number of the grouped flaws. The number of flaws for each semiconductor wafer 1 can be calculated and stored in the detection result memory 5, and the number of flaws for each semiconductor wafer 1 can be managed.
  • this grouping process is not always useful, and it is clear that the grouping process is not necessary when managing the area of the scratches on each semiconductor wafer 1 (over the entire surface). It is.
  • This grouping process is performed using a labeling algorithm known as a normal image processing algorithm. Further, it has been described that this processing is performed softly by the computer 53, but it may be realized by dedicated hardware (circuit).
  • the process of assigning the same label to continuous or very close image patterns and grouping them can be used for classification of scratches and foreign matter. This is because wounds usually appear in multiple continuous (or intermittent) forms, and foreign bodies usually appear in an isolated form. Furthermore, the face By grouping the signals from which the roughness has been eliminated by hardware, the capacity of the detection result memory 54 can be saved.
  • the computer 53 reads out the binarized image data stored in the detection result memory 54 for each semiconductor wafer, and recognizes the shape by image processing as shown in FIG. It is determined whether the scratch is a stretch 40 or a particle-like foreign matter 41, and when the scratch 40 is determined, the area S s of the scratch 40 is determined from the binarized image data indicating the scratch. And the maximum length L is determined, the pass / fail judgment is made by comparing it with the scratch judgment criteria, and the result is stored in the detection result memory 54 in correspondence with the coordinates of the occurrence position.
  • the area S f of the foreign substance 4 1 is obtained from the binarized image data indicating the foreign substance, is compared with the foreign substance determination standard, and the quality is determined, and the result is detected. And store. Recognizing whether a defect generated on the polished surface is a scratch or a foreign substance is because the criteria for quality are different and the polishing conditions for generating the scratch and the polishing conditions for generating the foreign substance are different. .
  • the CMP apparatus 200 corrects the CMP conditions based on a command or control from the control unit 204 so that the polishing surface of the semiconductor wafer 1 is free from scratches and foreign matter. Yield can be improved. Also, if the CMP apparatus 200 also needs surface roughness information of the polished surface to set the polishing conditions, the control unit 204 will send the information from the processing means 21 of the inspection apparatus 240 for scratches and foreign matter. Provision may be made via the management computer 250.
  • the planarized polished surface on the semiconductor wafer 1 includes a case where an insulating film 303 is formed on a wiring pattern 301 and a case where As shown in Fig. 3 (e) and Fig. 4, the substrate (the surface may be formed of an insulating film) 3 11
  • the insulating film pattern 3 15 and the wiring pattern 3 17 are formed on 1 1 and if it is, FIG. 5 (e) and sixth when the pattern 3 2 2 S i 0 2 based insulating film pattern 3 2 5 and S i 3 N 4 is formed as shown in FIG. There is.
  • the flattened polished surface on the semiconductor wafer 1 is slightly roughened by polishing.
  • the insulating film pattern 315 and the wiring pattern 317 exist on the polished surface.
  • the insulating film pattern 315 and the wiring pattern 317 have different surface reflectivities. Therefore, a signal waveform obtained by the detector 34 receiving the scattered diffracted light generated from the surface of the insulating film pattern 3 15 due to the surface roughness, and a signal waveform generated from the surface of the wiring pattern 3 17 due to the surface mark The intensity is different from the signal waveform obtained by the detector 34 receiving the scattered diffraction light.
  • the computer 53 determines the area of the insulating film pattern 315 and the area of the wiring pattern 317 from the signal 37 obtained from the detector 34, and determines the area of the wiring pattern 317 from the area of the wiring pattern 317.
  • a high threshold is set for the binarization circuit 51, and for the signal obtained by the detector 34 from the region of the insulating film pattern 3 15, the binarization circuit 5 is set.
  • a low threshold for 1 Can be erased.
  • the image signal obtained from the detector 34 is stored for a predetermined time until the computer 53 determines the area of the insulating film pattern 315 and the area of the wiring pattern 317. Need to be done.
  • the intensity of scattered light generated from scratches generated on the surface of the insulating film pattern 315 is weaker than the intensity of scattered light generated from scratches generated on the surface of the wiring pattern 317.
  • the problem with the semiconductor element is the damage on the surface of the wiring pattern 317, and the sensitivity of the damage on the surface of the insulating film pattern 315 decreases. It doesn't matter if you don't recognize it correctly. Regarding foreign matter, no problem occurs because the same scattered light intensity can be obtained for the insulating film pattern 315 and the wiring pattern 317.
  • the threshold value is changed between the region of the insulating film pattern 3 15 and the region of the wiring pattern 3 17 in order to erase a signal caused by surface roughness. If it is not necessary to be able to recognize the scratches generated on the surface, it is sufficient to set a high threshold that can eliminate the surface roughness generated on the surface of the wiring pattern 317 regardless of the area. This eliminates the need for the computer 53 to determine the region of the insulating film pattern 315 and the region of the wiring pattern 317 and change the threshold. As described above, in the cases shown in FIGS. 3 (e) and 4, it is possible to inspect for foreign substances and scratches generated on the polished surface.
  • the insulating film pattern 325 and the Si 3 N 4 layer 3222 exist on the polished surface.
  • both the insulating film pattern 325 and the Si 3 N 4 layer 322 show similar characteristics to the illumination light, and as shown in FIGS. 24 (c) and (d),
  • the threshold value 1 1 1 eliminates the signal generated by the surface roughness, and as a result, it becomes possible to inspect the polished surface for foreign substances and scratches.
  • the sensitivity such as the threshold may be set.
  • the light source of the illumination light in the defect inspection apparatus 240 for scratches and foreign matter shown in FIG. 23 does not need to be an argon laser 11 but a laser light source of another wavelength, for example, a helium neon laser, It may be a red semiconductor laser (gallium aluminum arsenide compound semiconductor laser), a light source using SHG (second harmonic), a discharge tube light source such as a xenon lamp or a mercury lamp, or a filament lamp such as a halogen lamp.
  • a red semiconductor laser gallium aluminum arsenide compound semiconductor laser
  • SHG second harmonic
  • discharge tube light source such as a xenon lamp or a mercury lamp
  • a filament lamp such as a halogen lamp.
  • the spatial filter 33, the half-wave plate 13 and the polarizing elements 14 and 32 are not necessarily required. These filters are used to classify the shape of a flaw, and to classify uneven shapes such as foreign matter or defects. Specifically, by using S-polarized light (light flux whose electric field vector is perpendicular to the incident surface) as irradiation light, surface roughness of the surface (polished surface) of the semiconductor wafer 1 is reduced, and foreign matter, scratches and scratches are reduced. Detection sensitivity can be improved. Conversely, by using P-polarized light (a light beam whose electric field vector is parallel to the plane of incidence), surface roughness can be detected with high sensitivity. These modes are selected according to the object to be evaluated.
  • S-polarized light light flux whose electric field vector is perpendicular to the incident surface
  • P-polarized light a light beam whose electric field vector is parallel to the plane of incidence
  • FIG. 26 schematically shows a case where the illumination is two-way illumination in the defect inspection apparatus 240 for scratches and foreign matter shown in FIG.
  • the illumination is two-way illumination in the defect inspection apparatus 240 for scratches and foreign matter shown in FIG.
  • FIG. 23 a flaw having a direction close to the direction perpendicular to the plane of incidence of the illumination is emphasized and detected. Therefore, as shown in FIG. 26, this directivity can be reduced by obliquely illuminating from directions 101, 102, 103, 104 perpendicular to each other.
  • two perpendicular directions 101 and 102 may be used.
  • four directions 103, 105, 106, and 104 including directions that are not right angles, may be used.
  • two or four perpendicular directions shown above are used.
  • FIG. 27 shows a method of illuminating from all directions in the defect inspection apparatus 240 for flaws and foreign matter shown in FIG.
  • an illumination optical system composed of a light source 1 I, beam expanders 18 and 19, a mirror 38 penetrating the center, an objective lens 31, an imaging lens 37, and a detector 3 4 and a stage optical system 70 shown in FIG. 23 and a data processing system 24 1.
  • one point on the surface (polished surface) of the semiconductor wafer 1 is illuminated from all directions by the illumination optical system.
  • the light reflected from the surface of the semiconductor wafer 1 is shielded from the 0th-order reflected light by the mirror 38 penetrating the center, and only the scattered light from defects such as scratches or foreign matter passes through the mirror 38 to form an image.
  • the image is formed on the detector 34 by the lens 37 and detected.
  • the illuminating light beam spirals with respect to the surface of the semiconductor wafer 1 by scanning the X stage while rotating the stage. Scanning is efficient. Therefore, the X z S stage system is used for the stage system.
  • stage system is also of course c not an essential problem even shown to X yz stage to the second 3 figures, configurations such as the data processing system 2 1 is equivalent to that of the second 3 Figure is there.
  • the directivity is further reduced by detecting a flaw or the like as compared with the method shown in FIG.
  • FIG. 28 An embodiment of the defect inspection apparatus 220 for scratches / foreign matter will be specifically described with reference to FIGS. 28 to 31.
  • FIG. 28 An embodiment of the defect inspection apparatus 220 for scratches / foreign matter will be specifically described with reference to FIGS. 28 to 31.
  • This embodiment utilizes the fact that a semiconductor wafer 1 polished by a CMP apparatus 200 is stored in a liquid until it is cleaned by a cleaning apparatus 230, so that scratches on the polished surface in the liquid can be prevented. This is to inspect for defects such as foreign matter.
  • FIG. 1 is a schematic configuration diagram showing an embodiment of a defect inspection apparatus 220 for an object or the like.
  • This embodiment has substantially the same configuration as that of FIG.
  • a stage 71 for placing the semiconductor wafer 1 in the liquid in the tank 3 is provided.
  • the illumination system 10 is provided outside the tank 3, and the detection system 30 is housed in the casing 36.
  • the processing means 24 1 is the same as in FIG. Therefore, the illumination light from the illumination system 10 irradiates the surface (polished surface) of the semiconductor wafer 1 in the liquid through the illumination window 18 and the scattered light from the surface of the semiconductor wafer 1 in the liquid is detected. Through 35, detection is performed by the detection optical system 30. Since the semiconductor wafer 1 exists in the liquid, the stage on which the wafer is placed is fixed, and it is desirable that the illumination optical system 10 and the detection optical system 30 scan the stationary semiconductor wafer 1. Of course, a configuration for scanning the stage may be used.
  • the illumination window 18 and the detection window 35 are provided to prevent the illumination and detection light from being distorted due to fluctuations in the liquid surface when light enters the liquid.
  • This method has an effect that the polished semiconductor wafer 1 is stored in a liquid, so that the inspection can be performed during the storage.
  • the flattening film is made of quartz with a refractive index of 1.462
  • liquids such as aniline with a refractive index of 1.586, glycerin with a refractive index of 1.473, and a refractive index of 1 460 carbon tetrachloride, refraction index 1.73 7 jade methane, refraction index 1.516 seda oil, refraction index 1.48 paraffin oil, refraction index 1.66 ⁇ —Bromonaphthalene, benzene with a refractive index of 1.5012, etc. are considered.
  • Fig. 29 shows how foreign matter or scratches are detected when total reflection occurs.
  • FIG. 30 shows the reflectance at the surface shown in FIG. 29. The values for P-polarized light 47 and S-polarized light 48 are shown, respectively.
  • FIG. 31 shows another embodiment.
  • light is irradiated onto the entire surface or a part of the surface of the semiconductor wafer 1 through an illumination window 18, and an area illuminated through a detection window 35 is formed on an imaging lens 34 on a two-dimensional detector 34.
  • the image is re-imaged by 3 1.
  • This embodiment also uses the above conditions for total reflection. By using the condition of the total reflection, the influence of the underlying pattern can be eliminated, so that the pixel size of the detection can be increased. Even with such a two-dimensional sensor 34, a wide area can be inspected at a time. For example, using a 1000 ⁇ 100 pixel CCD camera, a 7 micron pixel can inspect a 7 mm ⁇ 7 mm area.
  • the inspection area needs to be increased, the pixel size may be increased, or the inspection area may be enlarged by step-and-repeat. Further, the detection sensitivity may be increased by reducing the pixel size at the expense of the inspection area.
  • the defect inspection data of the scratches / foreign matter obtained from the processing means 2 41 of the defect inspection apparatus 240 for flaws / foreign matter and the processing means 25 1 of the completed tester 250 obtained from the processing means 25 1 The production management of the production line 400 of the semiconductor wafer 1 by the management computer 250 based on the electrical characteristic data of the semiconductor element will be described with reference to FIGS. 32 to 39.
  • FIG. 32 shows a production line 400 of the semiconductor wafer 1 according to the present invention.
  • 1 is a diagram showing an overall configuration of production management by all management computers 250.
  • FIG. FIG. 7 shows a similar configuration.
  • the production line 400 of the semiconductor wafer 1 typically includes a metal film forming process such as sputtering, a resist pattern forming process (a resist coating process, an exposure process, a developing process, etc.), and an etching process (resist pattern).
  • an insulating film forming step 402 for forming an insulating film 303 on the wiring pattern 301 by a CVD apparatus or the like.
  • a sputtering device in the wiring pattern forming step 401 and the wiring pattern forming step 404, a sputtering device, a resist coating device, an exposure device, an etching device and the like are used.
  • a CVD apparatus or the like is used in the insulating film forming step 402 and the insulating film forming step 405.
  • Reference numerals 411, 412, 413 (204), 414, and 415 denote control devices for controlling devices provided in each process. Therefore, the control devices 411, 12, 13 (204), 414, and 415 form the film formation, etching, exposure, polishing, etc. for each semiconductor wafer 1 to be input.
  • the defect inspection device 240 for obtaining scratches, foreign matter, etc. which can obtain the manufacturing conditions, can be used in the desired process (may be within the process) in the manufacturing line 400 of the semiconductor wafer 1.
  • the semiconductor wafer 1 that needs to be inspected for defects such as scratches and foreign matter is inspected for defects such as damage and foreign matter.
  • the defect inspection device 24 ⁇ for scratches / contaminants, etc. is polished by the CMP device 200 and the surface of the semiconductor wafer 1 cleaned by the cleaning device 230 is subjected to defects such as scratches / contaminations.
  • the defect inspection device 240 for scratches, foreign matter, etc. may be installed between required steps in the production line 400. In this case, although the number of the defect inspection devices 240 such as scratches / foreign matter increases, the defect such as scratches / foreign matter generated on the surface of the semiconductor wafer 1 can be regularly inspected.
  • Reference numeral 430 denotes a tester for inspecting electrical characteristics of a substantially completed semiconductor device capable of performing an operation test.
  • Reference numeral 431 denotes processing means constituted by a computer or the like for performing an inspection process of the electrical characteristics in the tester 430. Therefore, the processing means 431 of the tester 430 can obtain the results of the electrical characteristics of the semiconductor elements (semiconductor chips) for each semiconductor wafer 1.
  • the management computer 250 includes processing means 24 1 for the defect inspection device 240 for scratches and foreign matter, processing means 43 1 for the tester 430, and control devices 4 1 1, 4 1 2 and 4 1 3 for the manufacturing equipment ( 204), 414, 415 and network 409. Therefore, the management computer 250 obtains the electrical characteristic results of the semiconductor elements (semiconductor chips) for each semiconductor wafer 1 from the processing means 431 of the tester 43, and the yield per semiconductor wafer. Can be calculated. Further, the management computer 250 is damaged. From the processing means 21 of the defect inspection apparatus 240 for objects and the like, it is possible to discriminate scratches and foreign substances generated on the surface of each semiconductor wafer 1 in each manufacturing process and obtain the coordinates including the coordinates of the generated positions.
  • the one detected at the same position coordinate is judged to be the scratch or foreign matter generated in the previous process or all the previous processes before input, and erased.
  • These determination processes may be performed by the processing means 241 of the defect inspection device 240 for flaws and foreign matter.
  • the management computer 250 includes the coordinates of the position of occurrence on the surface of each semiconductor wafer 1 for each manufacturing process obtained from the processing means 241 of the defect inspection device 240 for scratches and foreign matter.
  • the information on the foreign matter that has been generated and the information on the electrical characteristics of the semiconductor elements (semiconductor chips) for each semiconductor wafer 1 obtained from the processing means 431 of the tester 4340 are used.
  • ⁇ Yield for each of the chip having no foreign matter and the chip having foreign matter can be calculated with respect to the number of chips having foreign matter on a wafer basis as shown in Fig. 36.
  • FIGS. 34 to 36 shows, in a certain manufacturing process, the yield and the foreign matter of a chip without foreign matter in the number of chips having foreign matter per wafer over a predetermined number of semiconductor wafers. This shows the relationship with the yield of the existing chips.
  • Non-defective chip rate different All non-product chips are handled as good products.
  • the non-defective rate is a high and constant value. That is, when the data shown in Fig. 34 is obtained from a certain manufacturing process, it can be understood that the foreign matter is normally detected, and the foreign matter can be determined as the main cause of the defect, and the result is displayed. It can also be displayed in means 25 2.
  • Fig. 35 Indicates that there is not. Therefore, if the data shown in Fig. 35 is obtained from a certain manufacturing process, it can be understood that foreign matter has not been detected normally, and foreign matter can be determined as the main cause of failure, and the result is displayed. It can also be displayed in means 25 2.
  • the management computer 250 obtains the results shown in Fig. 35, feed it into the processing means 241 of the defect inspection device 240 for scratches and foreign matter, and adjust the sensitivity so that inspection can be performed without oversight. You need to do something like that. Alternatively, it is necessary to use a more sensitive foreign substance inspection device. Specifically, measures such as prolonging the inspection time or using a light or SEM type visual inspection device can be considered.
  • the chips with foreign matter exist in wafer units. As the number (the number of foreign chips) increases, the yield of foreign chips decreases, and even if the number of foreign chips (the number of foreign chips) increases, the yield of foreign chips does not increase. It shows a low and almost constant value, similar to the yield of chips with foreign matter. In other words, the yield of chips without foreign matter is not related to the number of chips with foreign matter (the number of chips with foreign matter), but the yield is lowered. It indicates that there are other factors (for example, process factors). If the yield of foreign particles is constant irrespective of the number of chips with foreign particles (the number of foreign particles), it can be understood that the cause of the decrease in yield is other than foreign particles. Therefore, if the data shown in Fig. 36 is obtained from a certain manufacturing process, it can be determined that the cause of the defect that reduces the yield is other than foreign matter (for example, process factors), and as a result, Can be displayed on the display means 25 2.
  • the management computer 250 is provided with a foreign substance including coordinates of a generation position generated on the surface of each semiconductor wafer in each manufacturing process obtained from the processing means 241 of the defect inspection apparatus 240 such as a scratch and a foreign substance.
  • the information of the electrical characteristics of the semiconductor elements (semiconductor chips) for each semiconductor wafer 1 obtained from the processing means 431 of the tester 4330 is shown in FIG. Calculate the change in the number of chips with foreign particles (the number of chips with foreign particles), the change in yield for chips with no foreign particles, and the change in yield for chips with foreign particles in lot units as shown in the figure. Can be.
  • the yield of chips with foreign particles should have a correlation with the number of chips with foreign particles.
  • the yield of foreign chips increases, and if the number of foreign chips increases, the yield of foreign chips must decrease.
  • the yield for chips without foreign matter should not be correlated with the number of chips with foreign matter. Therefore, if it is assumed that foreign matter can be reliably inspected, If the yield of a chip without a substance cannot be correlated with the number of chips with a foreign substance, it is determined that the cause of the decrease in the yield of a chip without a foreign substance is other than a foreign substance (for example, a process factor). be able to.
  • the management computer 250 is provided with a foreign substance including coordinates of a generation position generated on the surface of each semiconductor wafer in each manufacturing process obtained from the processing means 241 of the defect inspection apparatus 240 such as a scratch and a foreign substance.
  • the information of the electrical characteristics of the semiconductor elements (semiconductor chips) for each semiconductor wafer 1 obtained from the processing means 431 of the tester 4330 are shown in FIG.
  • the number of foreign substances present in one chip in a semiconductor wafer unit or a plurality of semiconductor wafers, and the non-defective product of the chip (a non-defective product includes a completely non-defective product and a non-defective product obtained by bit rescue). ), The relationship with the number of defective products can be calculated.
  • the probability that the chip becomes defective should increase.
  • the probability of a defective product (the number of defective products and the number of non-defective products) should increase. If this relationship is established, it can be determined that the main cause of the failure is due to foreign matter, and if this relationship is not established, the main cause of the failure is a process factor other than the foreign matter. Can be determined.
  • the management computer 250 is capable of detecting the foreign matter including the coordinates of the occurrence position generated on the surface of each semiconductor wafer in each manufacturing process obtained from the processing means 21 of the defect inspection device 240 for scratches and foreign matter. From the information and the information on the electrical characteristics of the semiconductor elements (semiconductor chips) for each semiconductor wafer 1 obtained from the processing means 431 of the tester 43, the same semiconductor as shown in FIG. It is possible to calculate the transition between the yield of a chip without foreign matter and the yield of a chip with foreign matter in the order of the manufacturing process of the body wafer.
  • the management computer 250 includes at least the manufacturing conditions for each lot from the control devices 411, 412, 413 (204), 4114 and 415 of the manufacturing equipment. (Including information on maintenance, cleaning, etc.) is input and stored in the storage device 251, together with the inspection data, corresponding to the manufactured semiconductor wafer. Therefore, the management computer 250 investigates the cause of the occurrence of foreign matter, scratches, etc. in each manufacturing process, and the result is used as the control device 411, 412, 413 (204), Feedback can be made to 414 and 415, and it can also be displayed on the display means 252 and output.
  • the management computer 250 determines that the cause of the decrease in the yield as a semiconductor element is a process factor in a predetermined manufacturing process
  • the management computer 250 stores the predetermined manufacturing data stored in the storage device 251. It is possible to select the manufacturing conditions to be adjusted from the transition of the past manufacturing conditions in the process and feed back the result to the control device of the manufacturing equipment that constitutes the specified manufacturing process, and display it on the display means 252. Can also be output.
  • the control devices 4 1 1, 4 1 2, 4 1 3 (2 04) and 4 1. 4 1 5 of each manufacturing device are based on the information fed back from the management computer 250, and By controlling the It can be manufactured at high yields. Industrial applicability
  • the end point of polishing can be detected when the semiconductor wafer is polished and planarized, so that defects such as excessive and insufficient polishing can be prevented, and as a result, This has the effect that the device can be manufactured with a high yield and a high throughput.
  • the present invention when a semiconductor wafer is polished and flattened, defects such as scratches, foreign matter, surface roughness and the like at the time of flattening are inspected, and the result is fed back to the polishing process, whereby defects are reduced.
  • the effect of reducing fabrication is that semiconductor elements can be manufactured at a high yield.
  • the present invention when polishing and flattening a semiconductor wafer, the amount of remaining film is monitored in real time, and switching between high-speed polishing with a high polishing rate and low-speed polishing with high accuracy can be controlled. As a result, it is possible to prevent the occurrence of defects such as scratches, foreign matter, surface roughness, etc. due to polishing, and to produce an effect that a semiconductor device can be manufactured with a high yield and with a high throughput.
  • the cause of the failure can be removed at an early stage. It has the effect that it can be manufactured by stopping.
  • a semiconductor device semiconductor element
  • reduces defects and surface roughness such as scratches and foreign substances generated when a material to be planarized is subjected to chemical and mechanical polishing. That can be manufactured with high yield To play.
  • an element isolation structure can be formed on a semiconductor substrate without causing defects by using chemical and mechanical polishing.
  • a wiring pattern can be formed on a substrate by using chemical and mechanical polishing with a metal material which is difficult to etch without causing defects.
  • the present invention it is possible to determine whether or not the cause of the defect is due to a defect such as a scratch or a foreign substance, and to take measures against the defect.
  • the present invention it is possible to improve the reliability of the defect inspection in the defect inspection step or its means, and to produce a semiconductor device with a high yield.
  • the present invention is suitable for a method for manufacturing a semiconductor device.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un procédé de production d'un dispositif à semi-conducteur par polissage chimique et mécanique d'un matériau cible formé sur un substrat à semi-conducteur afin de l'aplanir, de manière à produire un dispositif à semi-conducteur (élément à semi-conducteur) avec une capacité et un rendement élevés tout en réalisant un polissage chimique et mécanique très précis. Dans ce procédé de production, on mesure l'épaisseur d'une couche mince résiduelle de l'objet de polissage lorsqu'un polissage chimique et mécanique est effectué sur l'objet du polissage, et on fait passer l'opération de polissage chimique et mécanique d'un polissage rapide à un polissage lent selon l'épaisseur mesurée de la couche mince résiduelle de l'objet de polissage. Le procédé de production comprend une étape de polissage consistant en un polissage chimique et mécanique d'un matériau cible formé sur un substrat afin d'aplanir l'objet du polissage, et une étape d'inspection consistant en l'inspection de l'état général regroupant les défauts et les particules de poussière, séparément du dégrossissage de surface, générés sur une surface polie aplanie à l'étape de polissage, de sorte que l'état de production de défauts et de particules de poussière sur la surface polie et inspectée à l'étape d'inspection soit rapporté à l'étape de polissage afin de gérer les états de polissage, réduisant ainsi les défauts et les particules de poussière générés sur la surface polie.
PCT/JP1998/000669 1997-02-19 1998-02-18 Procede de production d'un dispositif a semi-conducteur et son systeme WO1998037576A1 (fr)

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JP3448997A JPH10233374A (ja) 1997-02-19 1997-02-19 半導体装置の製造方法およびそのシステム
JP9/34489 1997-02-19

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JPH05326690A (ja) * 1992-05-14 1993-12-10 Sony Corp 素子分離領域形成方法及び半導体装置の製造方法並びに半導体装置
JPH06295892A (ja) * 1992-10-15 1994-10-21 Nec Corp ポリッシング方法及び金属配線の形成方法
JPH07221055A (ja) * 1994-02-02 1995-08-18 Sumitomo Metal Ind Ltd 配線の形成方法
JPH0825194A (ja) * 1994-07-12 1996-01-30 Mitsubishi Materials Shilicon Corp 半導体ウェーハの研磨方法および研磨装置

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* Cited by examiner, † Cited by third party
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WO2004038327A1 (fr) * 2002-10-24 2004-05-06 Hitachi, Ltd. Procede d'inspection de l'epaisseur d'un film sur un dispositif a film mince et procede de production d'un dispositif a film mince

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