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WO1998037576A1 - Method for manufacturing semiconductor device and system therefor - Google Patents

Method for manufacturing semiconductor device and system therefor Download PDF

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Publication number
WO1998037576A1
WO1998037576A1 PCT/JP1998/000669 JP9800669W WO9837576A1 WO 1998037576 A1 WO1998037576 A1 WO 1998037576A1 JP 9800669 W JP9800669 W JP 9800669W WO 9837576 A1 WO9837576 A1 WO 9837576A1
Authority
WO
WIPO (PCT)
Prior art keywords
polishing
semiconductor
semiconductor device
defect
manufacturing
Prior art date
Application number
PCT/JP1998/000669
Other languages
French (fr)
Japanese (ja)
Inventor
Minori Noguchi
Takenori Hirose
Yukio Kenbo
Takanori Ninomiya
Masayoshi Serizawa
Yoichi Takahara
Takeshi Kimura
Shinichiro Mitani
Yoshikazu Tanabe
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Publication of WO1998037576A1 publication Critical patent/WO1998037576A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step

Definitions

  • the present invention relates to a method and a system for manufacturing a semiconductor device by repeating film formation, exposure, and etching on a substrate by a manufacturing line, and in particular, to flatten the surface after film formation by chemical and mechanical polishing.
  • the present invention relates to a method and a system for manufacturing a semiconductor device having a process and an apparatus for forming a semiconductor device.
  • a semiconductor device repeats film formation, exposure, and etching on a substrate to manufacture the semiconductor device on the substrate. At this time, the semiconductor device is manufactured using a finer pattern in order to achieve a higher density. Further, in order to realize a more complicated circuit, a step is generated because a multilayer wiring pattern is used, and the step is a cause of a pattern defect when a pattern is formed on the step. Therefore, conventionally, a flat film is formed on a pattern having a step, and the next pattern is formed on the flat film.
  • a pattern such as a wiring pattern is placed below the film to be planarized. Since the influence of this pattern was not sufficiently considered in the above-mentioned conventional technology, it was not possible to measure the residual film with sufficient sensitivity and high accuracy.
  • An object of the present invention is to solve the above-mentioned problems of the prior art, reduce the influence of a pattern present below a material to be flattened, enable highly accurate measurement of the remaining film thickness, and provide a highly accurate chemical
  • Another object of the present invention is to provide a method of manufacturing a semiconductor device which realizes mechanical polishing and can manufacture a semiconductor device (semiconductor element) at a high yield.
  • Another object of the present invention is to realize a high-throughput and high-precision chemical and mechanical polishing so that a semiconductor device (semiconductor element) can be manufactured at a high throughput and at a high yield. It is an object of the present invention to provide a method for manufacturing a semiconductor device.
  • Another object of the present invention is to reduce defects and surface roughness such as scratches and foreign substances generated when a material to be planarized is chemically and mechanically polished. It is an object of the present invention to provide a method of manufacturing a semiconductor device which can manufacture (semiconductor element) with a high yield.
  • Another object of the present invention is to provide a method of manufacturing a semiconductor device and a system therefor in which it is possible to determine whether or not a defect is caused by a defect such as a scratch or a foreign substance, and to take measures against the defect. Is to do.
  • Another object of the present invention is to provide a method for inspecting defects in a defect inspection process or its means. It is an object of the present invention to provide a method of manufacturing a semiconductor device and a system thereof that can improve the reliability of inspection and manufacture a semiconductor device with a high yield.
  • the present invention relates to a semiconductor device manufacturing method for manufacturing a semiconductor device by subjecting a material to be polished formed on a substrate to chemical and mechanical polishing and flattening the material.
  • the remaining film thickness of the polishing target material is measured, and according to the measured remaining film thickness of the polishing target material, And a method of manufacturing a semiconductor device, characterized by controlling mechanical polishing.
  • the present invention provides a method of manufacturing a semiconductor device, in which a material to be polished formed on a semiconductor substrate is chemically and mechanically polished and planarized to manufacture a semiconductor device.
  • a material to be polished formed on a semiconductor substrate is chemically and mechanically polished and planarized to manufacture a semiconductor device.
  • the chemical and mechanical polishing is performed, the remaining film thickness of the material to be polished is measured. According to the measured remaining film thickness of the material to be polished, the chemical and mechanical high-speed polishing is performed.
  • This is a method for manufacturing a semiconductor device, characterized by performing switching control to low-speed polishing.
  • the present invention is characterized in that, in the method of manufacturing a semiconductor device, the remaining film thickness of the material to be polished is measured from a spectral intensity distribution of light reflected from the material to be polished (planarized film).
  • the present invention also provides the method of manufacturing a semiconductor device, wherein a remaining film thickness of the polished material is measured from a change in the wavelength of the characteristic peak from a spectral intensity distribution of light reflected from the polished material (planarized film). It is characterized by doing.
  • the present invention also provides the method of manufacturing a semiconductor device, wherein the transparent substrate is polished in the same manner as the material to be polished, and the intensity of the interference light reflected from the polished surface of the transparent substrate and the surface on the opposite side is changed. It is characterized by measuring the polishing rate of the abrasive. Further, according to the present invention, in the method of manufacturing a semiconductor device, the transparent substrate is polished in the same manner as the material to be polished, and a polishing rate of the material to be polished is measured from a movement amount of interference fringes generated from a polished surface of the transparent substrate. It is characterized by the following.
  • the present invention provides a polishing stopper layer forming step of forming a thin polishing stopper layer on a semiconductor substrate, an etching step of digging a recess for element isolation in the semiconductor substrate including the polishing stopper layer, An insulating film forming step of forming a film so as to fill a concave portion dug by the etching step with an insulating film; and chemically and mechanically forming the insulating film formed in the insulating film forming step.
  • An oxidation step of oxidizing a surface of the semiconductor substrate to form an oxide layer, wherein an element isolation structure is formed with respect to the semiconductor substrate.
  • the present invention provides an insulating film pattern forming step of forming an insulating film pattern on a substrate, and forming a film so as to bury a metal material for wiring in a gap of the insulating film pattern formed in the insulating film pattern forming step. And a polishing step of performing chemical and mechanical polishing on the metal material formed in the film forming step to flatten the metal material, thereby forming a gap between the insulating film patterns.
  • a method for manufacturing a semiconductor device comprising forming a wiring pattern.
  • the present invention provides a polishing step of performing chemical and mechanical polishing on a material to be polished formed on a substrate to flatten the same, and a surface generated on the polished surface flattened by the polishing step.
  • An inspection step of inspecting the state of occurrence of roughness or defect, wherein the state of occurrence of surface roughness or defect on the polished surface inspected in the inspection step is fed back to the polishing step, and polishing conditions Semiconductor device manufacturing method characterized by controlling Is the law.
  • the present invention provides a polishing step of performing a chemical and mechanical polishing on a material to be polished formed on a substrate to flatten the same, and a cleaning step of cleaning the polished surface flattened by the polishing step. And an inspection step for inspecting an occurrence state of surface roughness or a defect generated on the polished surface cleaned in the cleaning step.
  • a method of manufacturing a semiconductor device characterized in that the state of occurrence of the defects is fed back to the polishing step to control the polishing conditions so as to optimize the conditions.
  • the present invention provides a polishing step of performing a chemical and mechanical polishing on a material to be polished formed on a substrate to flatten the same, and a cleaning step of cleaning the polished surface flattened by the polishing step. And an inspection step for inspecting the state of occurrence of surface roughness or defects occurring on the polished surface before and after the cleaning step.
  • a method of manufacturing a semiconductor device characterized in that the state of occurrence of defects is fed back to the polishing step to control the polishing conditions so as to optimize the conditions.
  • the present invention provides a polishing step of performing chemical and mechanical polishing on a material to be polished formed on a substrate to flatten the same, and a surface generated on the polished surface flattened by the polishing step.
  • a plurality of semiconductor substrates manufactured in a predetermined manufacturing process of a manufacturing line may be extracted in lots.
  • a defect inspection step of inspecting a defect occurrence state of each semiconductor device An electrical characteristic inspection step of performing an electrical characteristic inspection on each of the semiconductor devices obtained from the semiconductor substrates over the plurality of semiconductor substrates to determine a non-defective product or a defective product; The correlation between the state of generation of foreign matter for each semiconductor device on the plurality of semiconductor substrates and the result of a non-defective product or a defective product of each semiconductor device over the plurality of semiconductor substrates determined in the electrical characteristic inspection step.
  • a defect occurrence investigation process for investigating whether or not the defect origination is caused by a defect, and taking measures against the defect occurrence investigation identified in the defect occurrence investigation process. 6 shows a method for manufacturing a semiconductor device.
  • a plurality of semiconductor substrates manufactured in a predetermined manufacturing process of a manufacturing line may be extracted in lots.
  • the cause of the defect is determined by the defect.
  • a plurality of semiconductor substrates manufactured in a predetermined manufacturing process of a manufacturing line may be extracted in lots.
  • a defect inspection process for inspecting the state of occurrence of defects for each semiconductor device An electrical characteristic inspection step of performing an electrical characteristic inspection on each of the semiconductor devices obtained from the semiconductor substrates over a number of semiconductor substrates to determine a non-defective product or a defective product; Between the result of the non-defective product or defective product of each semiconductor device over the plurality of semiconductor substrates obtained and the state of occurrence of defects for each semiconductor device on the plurality of semiconductor substrates inspected in the defect inspection process.
  • the present invention provides a defect inspection means for inspecting a state of occurrence of a defect of each semiconductor device on a semiconductor substrate over a plurality of semiconductor substrates produced by a predetermined production apparatus of a production line; An electrical characteristic inspection unit that performs an electrical characteristic inspection on each of the semiconductor devices obtained from the semiconductor substrates over a plurality of manufactured semiconductor substrates to determine a non-defective product or a defective product; and an inspection performed by the defect inspection unit. Between the occurrence state of foreign matter for each semiconductor device on the plurality of semiconductor substrates and the result of non-defective or defective product of each semiconductor device across the plurality of semiconductor substrates determined by the electrical characteristic inspection means. Means for determining whether the cause of the failure is due to a defect based on the defect, and the defect determined by the means for determining the cause of the failure.
  • Raw cause a manufacturing system wherein a and Fi one Dobakku child to prescribed manufacturing apparatus.
  • the present invention provides a defect inspection means for inspecting a state of occurrence of a defect of each semiconductor device on a semiconductor substrate over a plurality of semiconductor substrates produced by a predetermined production apparatus of a production line;
  • the non-defective / defective product ratio is determined by conducting an electrical characteristic test on each semiconductor device obtained from the semiconductor substrate over a plurality of manufactured semiconductor substrates to determine a non-defective product or a defective product.
  • an electrical characteristic inspection unit for calculating a defective product ratio, a foreign matter generation state of each semiconductor device on the plurality of semiconductor substrates inspected by the defect inspection unit, and a plurality of electrical characteristics calculated by the electrical characteristic inspection unit.
  • a failure occurrence cause finding means for determining whether or not a failure occurrence is due to a defect based on a correlation with a non-defective rate or a defective rate of each semiconductor device over the entire semiconductor substrate.
  • a semiconductor device manufacturing system characterized in that the fault occurrence cause determined by the fault occurrence cause determining means is fed back to a predetermined manufacturing apparatus.
  • the present invention provides a defect inspection means for inspecting a state of occurrence of a defect of each semiconductor device on a semiconductor substrate over a plurality of semiconductor substrates produced by a predetermined production device of a production line, Electrical characteristic inspection means for performing electrical characteristic inspection on each of the semiconductor devices obtained from the semiconductor substrates over the plurality of semiconductor substrates thus determined to determine a non-defective product or a defective product, and the electrical characteristics.
  • the present invention detects a defect such as a foreign matter attached to a plurality of semiconductor devices (semiconductor elements) on a substrate in an arbitrary manufacturing process, and detects a defect such as a foreign material obtained from an electrical inspection result of the semiconductor device.
  • the detected defect rate (non-defective rate) of the semiconductor device is compared with the defective rate (non-defective rate) of the semiconductor device in which no defect such as a foreign substance is detected, and the comparison result is fed back to the defect inspection apparatus to increase the detection sensitivity.
  • Adjusting (controlling) semiconductor device manufacturing method Is the law.
  • a semiconductor device (semiconductor element) is manufactured with high throughput and high yield by realizing high-throughput, high-precision chemical and mechanical polishing. be able to.
  • a semiconductor device semiconductor element
  • semiconductor element semiconductor element
  • reducing defects and surface roughness such as scratches and foreign substances generated when a material to be planarized is chemically and mechanically polished. It can be manufactured with high yield.
  • an element isolation structure can be formed on a semiconductor substrate by using chemical and mechanical polishing without causing defects.
  • FIG. 1 is a diagram showing a cross-sectional structure of a semiconductor wafer for manufacturing a semiconductor device (semiconductor element) according to the present invention
  • FIG. 2 is a diagram which is generated when an insulating film according to the present invention is subjected to CMP. Scratch formed a wiring pattern on it
  • FIG. 3 is a cross-sectional view illustrating each step for explaining a method of forming a wiring pattern on a substrate by a technique called damascene according to the present invention.
  • FIG. 4 is a perspective view showing a polished surface for explaining that a scratch generated when performing CMP by a method called a damascene according to the present invention may cut the wiring;
  • FIG. 1 is a diagram showing a cross-sectional structure of a semiconductor wafer for manufacturing a semiconductor device (semiconductor element) according to the present invention
  • FIG. 2 is a diagram which is generated when an insulating film according to the present invention is subjected to CMP. Scratch formed
  • FIG. 5 is a sectional view showing each step for explaining a method for forming an element isolation structure on a semiconductor substrate according to the present invention.
  • FIG. 6 is a sectional view showing an element isolation structure on a semiconductor substrate according to the present invention.
  • FIG. 7 is a diagram for explaining that a scratch generated when performing CMP to form a semiconductor substrate enters a semiconductor substrate and loses the function of an active element.
  • FIG. 7 is a diagram illustrating a management system in a CMP process according to the present invention. It is a configuration diagram showing a stem,
  • FIG. 8 is a view showing a schematic configuration of a CMP apparatus and a residual film thickness detecting apparatus according to the present invention.
  • FIG. 9 is a perspective view showing the CMP apparatus shown in FIG. FIG.
  • FIG. 11 is a configuration diagram showing a first embodiment of a residual film thickness detection head shown in FIG. 8, and FIG. 11 is a diagram showing a spectral intensity distribution detected by the detector shown in FIG.
  • FIG. 12 is a diagram showing a signal waveform
  • FIG. 12 is a diagram showing a signal waveform obtained by converting the horizontal axis of the signal waveform shown in FIG. 11 to 1
  • FIG. FIG. 14 is a diagram showing the principle of detection in the residual film thickness detecting device shown in FIG. 14.
  • FIG. 14 shows the material to be polished (from the variation in the wavelength of the characteristic peak of the spectral intensity distribution detected by the detector shown in FIG. 10).
  • FIG. 15 is a diagram for explaining the measurement of the remaining film thickness of the flattening film).
  • FIG. 15 is a configuration diagram showing a second embodiment of the remaining film thickness detection head shown in FIG. so FIG. 16 is a block diagram showing a third embodiment of the remaining film thickness detection head shown in FIG. 8, and FIG. 17 is a diagram showing the remaining film thickness detection head shown in FIG.
  • FIG. 18 is a configuration diagram showing a fourth embodiment of the present invention.
  • FIG. 18 is a diagram showing an intensity distribution of a diffraction image detected in the fourth embodiment shown in FIG.
  • FIG. 19 is based on the intensity distribution of the diffraction image detected in the fourth embodiment shown in FIG.
  • FIG. 20 is a diagram showing signal waveforms.
  • FIG. 20 is a block diagram showing another embodiment for measuring the remaining film thickness.
  • FIG. 21 is a diagram showing the signal detected by the detector shown in FIG. FIG.
  • FIG. 22 is a diagram showing interference fringes and their signal waveforms.
  • FIG. 22 is a configuration diagram showing still another embodiment for measuring a remaining film thickness.
  • FIG. 23 is a diagram showing a polished surface according to the present invention.
  • FIG. 24 is a block diagram showing an embodiment of a defect inspection apparatus for inspecting defects such as scratches and foreign substances on the polished surface in the apparatus shown in FIG. 23.
  • FIG. 25 is an explanatory diagram for performing discrimination processing and detection from signals obtained by the apparatus and the foreign matter.
  • FIG. 26 is a view for explaining scratches and foreign matter generated on the polished surface in the apparatus shown in FIG. 23 from a plurality of directions.
  • FIG. 27 is a diagram schematically illustrating a case where bright light is obliquely irradiated.
  • FIG. 27 is a configuration diagram illustrating a method of illuminating from all directions in the apparatus illustrated in FIG. 23, and FIG. FIG. 29 is a schematic configuration diagram showing one embodiment of a defect inspection apparatus for inspecting a defect such as a scratch or a foreign substance on a polished surface in a liquid according to the present invention.
  • FIG. 30 is a diagram showing a state of detection of a foreign object or a scratch when total reflection occurs in the apparatus shown in FIG. 30.
  • FIG. 30 shows an irradiation angle between the P-polarized illumination light and the S-polarized illumination light shown in FIG.
  • FIG. 31 is a diagram showing reflectivity on the surface according to FIG. 31.
  • FIG. 31 is a schematic configuration diagram showing an embodiment different from FIG. 28, and FIG.
  • FIG. 32 is a manufacturing line of a semiconductor device according to the present invention.
  • FIG. 33 is a configuration diagram illustrating an example of a management system that manages a device.
  • FIG. 33 illustrates a predetermined manufacturing apparatus (a predetermined manufacturing process).
  • FIG. 34 is a diagram for explaining the principle of detecting foreign matter generated by the method. It is a figure which shows the 1st case of distribution over several wafers with the yield of a chip,
  • FIG. 35 shows the difference with respect to the number of the chip with the foreign substance in a wafer unit in a predetermined manufacturing process. It is a figure which shows the 2nd case of distribution over the several wafer of the yield of a chip without a thing, and the yield of a chip with a foreign substance, and FIG.
  • FIG. 36 shows in a predetermined manufacturing process
  • FIG. 37 is a diagram showing a third case of the distribution over a plurality of wafers of the yield of a chip without foreign matter and the yield of a chip with foreign matter with respect to the number of chips having foreign matter in wafer units
  • FIG. 39 In the given manufacturing process, the results of calculating the relationship between the number of chips with foreign particles in each wafer, the yield of chips with no foreign particles, and the yield of chips with foreign particles in each unit are shown.
  • FIG. 38 is a diagram showing the relationship between the number of foreign substances in a chip and the number of chips in which this chip is a good product and a defective product in a predetermined manufacturing process.
  • FIG. 39 is a diagram showing the manufacturing process. In order, the yield of chips without foreign matter and the yield of chips with foreign matter FIG. BEST MODE FOR CARRYING OUT THE INVENTION
  • a semiconductor device (semiconductor element) comprising an LSI or the like according to the present invention is manufactured by repeatedly forming, exposing, and etching a substrate.
  • the semiconductor device (semiconductor element) 300 shown in FIG. 1 is manufactured using a finer pattern in order to realize a higher density.
  • it is necessary to use a multilayer wiring pattern (first-layer wiring pattern 305, second-layer wiring pattern 301, third-layer wiring pattern 302, etc.). For example, even if the third-layer wiring pattern 302 is formed on the second-layer wiring pattern 301 via the interlayer insulating film 303, the surface of the interlayer insulating layer 303 is formed.
  • 304 is the third layer wiring This is an interlayer insulating film or a protective film that covers the pattern. That is, a fourth-layer wiring pattern may be formed on the third-layer wiring pattern 302 in some cases.
  • Reference numeral 2005 denotes a first-layer wiring pattern.
  • Reference numeral 36 denotes a gate wiring.
  • Reference numeral 327 denotes an element isolation structure made of an insulating material.
  • Reference numeral 328 denotes an active element portion such as a MOS structure.
  • a wiring pattern made of a metal material such as copper, silver, gold, or platinum, which is a material having a low wiring resistance, which is a material that is extremely difficult to form a wiring pattern by etching is manufactured using, for example, a damascene method. Will do.
  • the damascene will be described with reference to FIG.
  • FIGS. 3 (a) to 3 (c) an insulating film pattern (negative wiring pattern) 315 of the wiring pattern is formed on the substrate 311. Then, FIG. As shown in (d), a metal material for wiring pattern is buried in the gap between the insulating film patterns 315 by spattering, plating, etc., and then formed as shown in FIG. 3 (e).
  • the metal wiring pattern 317 is formed by polishing to the height of the film pattern 315.
  • the purpose of this damascene is to create wiring patterns from materials that are difficult to etch (metal materials such as copper, silver, gold, and platinum, which have low wiring resistance).
  • metal materials such as copper, silver, gold, and platinum, which have low wiring resistance.
  • FIG. 3 (a) the SiO 2 -based film forming step, An insulating film (SiO 2 -based film) 312 is formed on the substrate 311 by a resist coating process, and a resist 313 is coated thereon.
  • FIG. 3 (b) by exposure and development step, a registry pattern 3 1 4 on the insulating film (S i 0 2 based film) 3 1 2.
  • FIG. 3 (a) the SiO 2 -based film forming step
  • An insulating film (SiO 2 -based film) 312 is formed on the substrate 311 by a resist coating process, and a resist 313 is coated thereon.
  • FIG. 3 (c) to shows, the etching process, and the resist removal process, the insulating film (S i 0 2 based film) 3 1 2 Etsu quenching as described registry pattern 3 1 4 against alms insulating film pattern (S i 0 2 based film pattern) 3 1 5 is formed, to remove the registry pattern 3 1 thereon.
  • a metal material for the wiring pattern (copper, silver, gold, white, which is a material having a low wiring resistance) is formed in the gap between the insulating film patterns 315 by a metal material film forming step. A metal material such as gold) is embedded and formed into a film.
  • the metal wiring pattern 317 is formed by polishing to the height of the insulating film pattern 315 by a polishing step.
  • a metal material for the wiring pattern (a material having a low wiring resistance) is formed by filling the gap between the insulating film patterns 3 1 5.
  • a certain metal material such as copper, silver, gold, and platinum
  • an element isolation structure 327 for isolating an active element portion 328 such as a transistor having a MOS structure
  • a SiO 2 -based oxide insulation is required.
  • the film needs to be polished and planarized.
  • a method of manufacturing an element isolation structure 327 for isolating an active element portion 328 such as a transistor having a MOS structure will be described with reference to FIG.
  • the Si 3 N 4 layer forming step and the resist coating step are performed in a nitrogen atmosphere on the Si substrate 321, so that 0.1 to 0. .
  • a Si 3 N 4 layer 3 22 with excellent thermal shock resistance consisting of a thin film layer of about 2 m is formed, and a resist 3 23 is applied thereon.
  • a resist pattern 324 is formed by an exposure and development process.
  • the Si 3 N 4 film 32 2 and the Si substrate 32 1 are etched according to the resist pattern 324 by an etching step and a resist removing step. Then, a groove 325 for element isolation is formed, and the resist pattern 32 thereon is removed.
  • deposition film of S i 0 2 system by CVD or the like so as to fill the groove 3 2 5 for element isolation 3 26 is deposited.
  • the formed SiO 2 -based deposition film 326 was formed by a polishing process to increase the height of the Si 3 N 4 layer 32 2 having excellent thermal shock resistance. Polish to the end. Since the Si 3 N 4 layer 322 having excellent thermal shock resistance is provided, it is possible to prevent the Si 3 N 4 layer 322 from directly contacting the Si substrate 3 21 during polishing and flattening.
  • the S i 3 N 4 layer removal step Subsequently, as shown in FIG. 5 (f), removing the S i 3 N 4 layer 3 2 2.
  • the Si 3 N 4 layer 3 22 may be any material that can withstand polishing and can be removed from the Si substrate 3 21 thereafter.
  • the element c can be separated by the film 327, that is, an element isolation structure 327 in which the active element part 328 is separated by a SiO 2 -based insulating film can be obtained.
  • the film to be planarized is the interlayer insulating film 303
  • the film is transparent to light
  • the wiring pattern 301 exists below.
  • the polished semiconductor substrate is stored in a liquid until cleaning, thereby preventing the abrasive grains from firmly adhering to the polished surface without being exposed to the air. Even in this case, it is necessary to realize the measurement of the remaining film thickness and the inspection of foreign matter and scratches with high accuracy.
  • the present invention is to reduce the influence of the underlying pattern and realize highly accurate remaining film thickness measurement. Specifically, by detecting the waveform of the film thickness measurement in a pattern in which the remaining film thickness is known in advance on a wafer on which a good pattern exists, and comparing the result with the detection result from the object to be measured. The influence of the underlayer pattern is removed, and the remaining film thickness with high accuracy is measured.
  • FIG. 2 (b) is a side sectional view of FIG. 2 (a).
  • the metal film for the third-layer wiring pattern will not be formed at the place of the foreign matter when the metal film is formed. This causes disconnection of the layer wiring pattern.
  • there is an electrically conductive foreign substance on the flattening film made of the interlayer insulating film 303 it may cause a short circuit between the third-layer wiring patterns.
  • the semiconductor device may be damaged. Further on the planarization film made of S i 0 2 based film 3 1 5 and the metal wiring patterns 3 1 7 for, when foreign matter or scratches present on the co Ntaku isolation portion of the upper wiring pattern, and causes of contactor bets poor In addition, the presence of electrically conductive foreign substances on the flattening film causes a short circuit between the metal wiring patterns 317.
  • the thickness of the Si 3 N 4 layer 322 forming the active element 328 is 0.05 to 0.3 ⁇ m. It is formed to a very small extent, and if any more foreign matter or flaws 329 exist on the polished surface as shown in Fig. 6 (a) and (b), it can easily be placed on the Si side.
  • the active element 3 288 does not operate normally.
  • FIG. 6 (a) is a plan view showing the planarized film surface (polished surface) shown in FIG. 5 (e), and FIG. 6 (b) is a side sectional view of FIG. 6 (a). is there. Therefore, there is no defect such as a scratch or foreign matter on the planarized film surface (polished surface) shown in FIG. By inspecting and monitoring whether or not this is the case, it is possible to obtain a polished surface on which the active element operates normally for the first time.
  • the function as a semiconductor element can be obtained.
  • a semiconductor device having high reliability can be realized. That is, since the object to be inspected for the presence of a defect such as a scratch or a foreign matter is a polished surface, the detection signal component from the surface polished by the surface polishing is made sufficiently small so that the surface polished by the polishing is reduced. It is possible to inspect with high sensitivity (high resolution) whether or not there is a defect such as a scratch or a foreign substance by reducing the influence of the defect.
  • FIG. 7 is a diagram showing a schematic configuration of the entire system.
  • the CMP device 200 supplies a polishing platen 210 called a platen on which a polishing cloth is adhered, and a supply of a suspension of polishing abrasive grains called a slurry onto the polishing cloth of the polishing platen 201.
  • Means 203-The semiconductor wafer 1 which is the material to be polished is supported, and revolving and rotating between the polishing platen 201 and the polishing platen 201 while flowing a suspension of abrasive grains called slurry.
  • a control device 20 for controlling the driving rotation speed of a rotary drive device for rotating the polishing head 200 and revolving and rotating, the polishing pressure applied by the polishing pressure applying means, and the polishing time. Be composed.
  • the control device 204 controls the polishing conditions (type of water suspension of polishing abrasive grains, polishing head 200) according to the type of semiconductor wafer 1 that is the material to be polished to be input into the CMP device 200. 0 rotation and rotation speed, polishing pressure, polishing time, etc.) are set. Then, only the polishing time calculated from the rough polishing speed previously determined according to the type of the semiconductor wafer 1 to be polished into the CMP device 200 by the control device 204 (when the time is slightly shorter). After polishing by the CMP device, the polishing head 202 rises to the position of 202 'and pure water is applied to the semiconductor wafer 1 to polish the semiconductor wafer 1 The surface is cleaned.
  • polishing conditions type of water suspension of polishing abrasive grains, polishing head 200
  • the remaining film thickness detection head 211 is installed so as to face the polished surface of the semiconductor wafer 1.
  • the remaining film thickness detecting device 210 for measuring the remaining film thickness of the film to be polished on the surface of the semiconductor wafer 1 includes the remaining film thickness detecting head 211 and the remaining film thickness detecting head 2 1 1 And a processing means 2 12 composed of a microcomputer or the like that processes the signal detected by the microcomputer.
  • the remaining film thickness data of the film to be polished on the surface of the semiconductor wafer 1 calculated by the processing means 2 12 of the remaining film thickness detecting device 210 is fed back to the control device 204 of the CMP device, and the control device Based on the remaining film thickness data fed back, 204 controls the transition from, for example, high-speed polishing to low-speed, high-definition polishing, controls the polishing time, and executes planarization with a desired film thickness.
  • the remaining film thickness of the film to be polished on the surface of the semiconductor wafer 1 can be monitored by the remaining film thickness detecting device 210, a high-throughput polishing method with a high throughput, Immediately before the end of polishing, it is possible to perform multi-stage polishing using a low-speed and high-definition polishing method that has a low throughput but has almost no defects such as scratches and foreign matter, and improves the polishing throughput. Defects such as scratches and foreign substances can be eliminated.
  • the semiconductor wafer 1 When the polishing of the surface of the semiconductor wafer 1 is completed as described above, the semiconductor wafer 1 is removed from the polishing head 202, and is cleaned until it is cleaned by the cleaning device 230. It will be stored in the liquid. The reason is that when stored in air, the abrasive grains that have adhered to the semiconductor wafer 1 due to the chemical reaction between water and oxygen in the air, etc., will adhere strongly to the wafer surface, and subsequent cleaning This is because it will no longer be possible. In addition, when inspecting whether or not there is a defect such as a scratch or a foreign substance on the polished surface after the polishing of the semiconductor wafer, it is necessary to perform the inspection while distinguishing from the fine roughness of the surface due to polishing.
  • the polished semiconductor wafer 1 is stored in a liquid and optically inspected for defects such as scratches and foreign matter on the polished surface by using a scratch / foreign matter inspection device 220, In addition, it is possible to prevent the abrasive grains from firmly adhering to the wafer surface, and to easily set the conditions for total reflection on the polished surface so that light from the underlying wiring pattern cannot be obtained. Obtainable.
  • the scratch / foreign matter inspection device 220 stores an immersion liquid for the semiconductor wafer 1 having a polished polished surface, and an illumination window for irradiating the polished surface of the semiconductor wafer 1 with light under the condition of total reflection. 1 and a tank 3 having a detection window 35 for detecting scattered reflected light from the polished surface, and an objective lens 31 for condensing scattered reflected light from the polished surface obtained through the detection window 35.
  • a detector 34 composed of a linear image sensor that receives the light condensed by the objective lens 31 and converts it into a signal; It comprises processing means 221 composed of a microcomputer or the like for processing a detected pixel signal to detect a defect such as a scratch or a foreign matter on the polished surface.
  • the polished surface is in a state before being cleaned, and there is a high possibility that the abrasive grains are attached. Therefore, the scratch / foreign matter inspection device 220 is capable of detecting defects such as scratches and foreign matter present on the polished surface. It is necessary to discriminate and inspect abrasive grains. Therefore, it is not necessary to inspect the polished surface of the semiconductor wafer 1 for defects such as scratches and foreign substances while being immersed in the liquid in the tank 3.
  • the cleaning device 230 cleans the semiconductor wafer 1 polished by the CMP device 200 and removes the abrasive wafer and the like attached to the polished surface.
  • the scratch / foreign matter inspection device 240 inspects defects such as scratches and foreign matter present on the polished surface of the semiconductor wafer 1 cleaned by the cleaning device 230 ⁇
  • Reference numeral 40 denotes the final inspection of the polished surface of the semiconductor wafer 1 cleaned by the cleaning device 230, so that, for example, the same optical system as the remaining film thickness detection head 210 is installed and polished. You may comprise so that the film thickness of a surface may be measured.
  • the scratch / foreign matter inspection device 240 includes a stage system 70 on which the semiconductor wafer 1 cleaned by the cleaning device 230 is placed, and an illumination system 10 for irradiating the polished surface of the semiconductor wafer with light.
  • a detection optical system 30 having a detector 3 for detecting scattered light from scratches and foreign matter on the polished surface; and processing of pixel signals obtained from the detector 34 to detect defects such as scratches and foreign matter on the polished surface. It comprises processing means 21 comprising a microcomputer or the like for detecting.
  • the computer 250 controls production of the polished surface of the semiconductor wafer 1.
  • the processing means 222 of the inspection device 220 and the processing means 241 of the scratch / foreign matter inspection device 240 are connected via a network.
  • the computer 250 is a control device 204 of the CMP device 200.
  • Conditions set in accordance with the type of the semiconductor wafer 1 to be polished, which is to be polished into the CMP apparatus 200 (the type of the aqueous suspension of the abrasive grains, the revolution of the polishing head 200). And rotation speed of rotation, polishing pressure, polishing time, etc.), and the residual film thickness measurement result corresponding to the type of the semiconductor wafer 1 can be obtained from the processing means 2 12 of the residual film thickness detecting device 210.
  • From the processing means 222 of the scratch / foreign matter inspection device 220 information on defects such as scratches and foreign materials present on the polished surface before cleaning (including information on the position where the defect has occurred) can be obtained.
  • reference numeral 255 denotes a display means composed of a display or the like.
  • Reference numeral 253 denotes an input means composed of a keyboard, a recording medium, and the like.
  • Reference numeral 254 denotes an output unit composed of a printing machine, a recording medium, and the like.
  • the computer 250 can provide information on the defect such as a scratch or a foreign substance present on the final polished surface inspected by the scratch / foreign substance inspection device 240 and the polishing conditions at that time in units of the semiconductor wafer 1.
  • Data related to the type of suspension of polishing abrasive grains, the rotational speed of the polishing head 200 and its rotation, the polishing pressure and the polishing time are read out from the storage device 25 1 in association with each other.
  • the administrator estimates the polishing condition, which is the cause of the defect, while viewing the information displayed on the display means 25, and inputs the polishing condition, the estimated cause, to the input means 25, 53.
  • the computer 250 analyzes whether or not the polishing condition estimated from the correspondence between the past defect information and the polishing condition is correct, and when it is determined to be correct, the polishing condition is transmitted to the controller 204. give feedback.
  • the control device 204 issues a command to change the polishing condition to the CMP device 200 so as to change the polishing condition, and the polishing is performed on the semiconductor wafer 1 which is input under the corrected polishing condition. .
  • polishing can be performed without causing many defect defects.
  • the administrator estimates the polishing conditions, which are the causes of the defects, while looking at the information displayed on the display means 250, but the estimated algorithm is stored in the memory in the computer 250. If this is input and stored in advance, the computer 250 estimates the polishing condition that is the cause of the defect based on the estimation algorithm, and determines whether the estimated polishing condition is appropriate. It can be determined based on past career information.
  • FIG. 8 is a front view showing the CMP apparatus 200 and the remaining film thickness detecting apparatus 210
  • FIG. 9 is a perspective view showing the CMP apparatus 200.
  • a CMP (chemical mechanical polishing) device 200 is composed of a polishing platen 210, called a platen, to which a polishing pad 204 is attached, and a suspension of abrasive grains called a slurry on the surface.
  • a water suspension liquid supply means 203 for polishing abrasive grains and a semiconductor wafer as a material to be polished are supported, and are disposed at 120 ° intervals so that revolving and rotation are performed.
  • three polishing heads 202 are provided.
  • Each semiconductor head 1 is supported by each polishing head 202 while a suspension of polishing abrasive grains, called a slurry, is flown onto the surface of the polishing cloth 204 attached to the surface of the polishing platen 201. While applying polishing pressure, the polishing platen 201 revolves and the polishing head 202 rotates. By performing such rotation, the surface of the semiconductor wafer 1 is polished in multiple stages. Based on the control signal from the control device 204, high-speed polishing is first performed, and when the polishing is approaching the end, the polishing is switched to low-speed high-definition polishing and the process is shifted. As a result, polishing can be performed at a high throughput, and the occurrence of defects such as scratches and foreign substances on the surface at the end of polishing can be minimized.
  • a suspension of polishing abrasive grains called a slurry
  • polishing head 202 is rotated at high speed during polishing (specifically, for example, The rotation speed is greater than 60 rpm, and the pressure between the material to be polished and the polishing pad (polishing pad) is increased (specifically, for example, a pressure greater than 100 g / cm 2 ).
  • polishing head 202 In low-speed polishing, small abrasive grains (specifically, for example, smaller than 50 nm) are used, and the polishing head 202 is rotated at a low speed during polishing (specifically, for example, (Rotation speed less than 60 rpm), and reduce the pressure between the workpiece and the polishing pad (polishing pad) (specifically, for example, a pressure less than 100 g Z cm 2 ).
  • a low speed during polishing specifically, for example, (Rotation speed less than 60 rpm)
  • polishing pad specifically, for example, a pressure less than 100 g Z cm 2
  • the polishing was performed only for the polishing time calculated from the rough polishing speed previously obtained by the CMP device 200 (only a slightly smaller polishing time). Then, the polishing head 202 is raised to the position 202 ', pure water is applied to the semiconductor wafer 1 supported by the polishing head 202 to wash the polished surface, and the remaining film amount described later.
  • the detection head 211 is inserted, and the remaining film thickness of the film to be polished on the wafer surface is measured by the remaining film thickness detecting device 210.
  • the remaining film thickness measured by the remaining film thickness detecting device 210 has reached a predetermined amount, the polishing is finished, and if not, the processing means 212 detects the remaining film thickness.
  • the control device 204 calculates the subsequent polishing time from the remaining film thickness, and the calculated polishing time is calculated.
  • the polishing is further performed by the calculated polishing time. As a result, the amount of polishing at the end point does not greatly deviate.
  • FIG. 10 is a configuration diagram showing a first embodiment of the remaining film thickness detection head 2 11.
  • the remaining film thickness detection head 211 is a light source 261 composed of a halogen lamp or the like, a pinhole 262 forming a point light source, and light emitted from the pinhole 262 being substantially parallel.
  • An illumination optical system consisting of a condenser lens 263 that converts the light into light 265 and irradiates the polished surface of the semiconductor wafer 1 with a half mirror 264, a diffraction grating 271, an imaging lens 272 And a detector 33.
  • the image of the point light source by the pinhole 262 is formed through the condenser lens 263, the polished surface of the semiconductor wafer 1 (film to be planarized), the half mirror 264, and the diffraction lens 271.
  • An image is formed on the detector 2 7 3 by 2 7 2.
  • the diffraction angle of the diffraction grating 332 differs for each wavelength of the light source, it is imaged as a spectral image on the detector 3334, and the waveform shown in FIG. 11 is detected.
  • FIG. 11 shows a detection waveform with respect to a wavelength detected by spectroscopy on the detector 273.
  • FIG. 12 shows a detection waveform for one wavelength that is spectrally detected on the detector 273. In the case of FIG.
  • the horizontal axis is the wavelength, and in the case of FIG. 12, the horizontal axis is 1 / wavelength ⁇ .
  • the longer the wavelength ⁇ the longer the pitch of the peak position of the waveform.
  • the pitches of the waveform peak positions are arranged at equal intervals at all positions. Therefore, the remaining film thickness d can be calculated by the following (Equation 1).
  • Equation 1 N / (2 ⁇ ⁇ ( ⁇ / ⁇ ,- ⁇ / ⁇ 2 )) (Equation 1) where ⁇ is the peak from the peak position (1 /) to the peak position (1 Z ⁇ 2 ) It is the number. Peaks can be maximum or minimum Les ,. n is the refractive index of the insulating film to be polished.
  • the pinhole 262 may be a one-dimensional pinhole, that is, a slit.
  • the light source be formed by a point light source or a slit light source and be able to irradiate the polished surface with substantially parallel light.
  • FIG. 13 shows a cross-sectional view of the object for measuring the remaining film thickness.
  • the remaining film thickness measurement target semiconductor wafer
  • a wiring pattern 13 2 (301) is formed on a base pattern 13 1, and the gap is further filled.
  • the light 265 applied to the surface of the insulating film 133 (303) planarized by the polishing is flat because the insulating film (film to be planarized) 133 is transparent.
  • the light is reflected at three points on the surface of the oxide film 13 3, the top (upper surface) of the wiring pattern 13 2, and the bottom of the wiring pattern 13 2, and reaches the detector 2 73.
  • the underlying pattern itself is complicated, and furthermore, light reaches the ground and forms a more complicated wavefront.
  • the three light beams interfere with each other, and the waveform shown in FIG. 11 is detected. Therefore, this detection waveform is such that interference light generated from three optical path differences of dl, d2, and d3 is superimposed. Therefore, it is necessary to separate (decompose) these three interference lights in order to realize more accurate measurement.
  • the frequency analysis of the detected waveform shown in Fig. 12 is effective.
  • This frequency analysis may be a Fourier analysis such as an FFT or a predictive frequency analysis such as a maximum entrance peak method.
  • the frequency analysis is performed by the processing means 2 12 and separated (decomposed), and the remaining film thickness d can be measured from the separated one based on the above (Equation 1).
  • the remaining film thickness can be measured with high accuracy. In rough cases, accuracy may decrease. In order to maintain the accuracy even in such a case, attention may be paid to a specific peak as shown in FIG. 14 and the lateral fluctuation ⁇ of the peak may be detected (monitored). This allows for more accurate detection. In this case, the peak shift ⁇ may not always change linearly with the remaining film thickness. Therefore, for more accurate detection, it is preferable to use a table showing the relationship between the amount of movement measured in advance and the amount of remaining film thickness. This conversion is automatically performed on the processing means 2 12 such as a microcomputer.
  • FIG. 15 is a configuration diagram showing a second embodiment of the remaining film thickness detection head 2 11. That is, when the interlayer insulating film 133 (303) is polished and flattened on the semiconductor wafer 1, the wiring pattern 133 (300) is provided below the interlayer insulating film 133 (303). 1) is regularly formed. Therefore, when the polished inter-layer insulating film 13 3 (30 3) is irradiated with the illumination light 265, the regularly arranged wiring patterns 13 2 (30 1) form the diffraction grating. As a function, the reflected light separated from the interlayer insulating film 133 (303) is obtained, and the separated light is received by the detector 273, as shown in FIG. Signal can be detected.
  • the remaining film thickness can be calculated based on (Equation 1) by converting the signals into the signals shown in FIG. 12 by the processing means 2 12.
  • Equation 1 the remaining film thickness
  • FIG. 16 is a configuration diagram showing a third embodiment of the head 211 for detecting the remaining film thickness.
  • the third embodiment is basically the same as the second embodiment shown in FIG. That is, when the interlayer insulating film 133 (303) is polished and flattened in the semiconductor wafer 1, the wiring pattern 133 (303) is provided below the interlayer insulating film 133 (303). ) Are regularly formed. Head for detecting remaining film thickness
  • a light source 261 which is constituted by a halogen lamp, etc.
  • a pinhole 262 forming a point light source, and light emitted from the pinhole 262 are converted into substantially parallel light 265.
  • an illumination optical system comprising a condensing lens 263 for irradiating the illumination light 2665 to the polished interlayer insulating film 133 (303) of the semiconductor wafer 1 from an oblique direction.
  • An imaging optical system including an imaging lens 272 and a detector 273 for detecting an image that has been split and formed. Therefore, when the polished interlayer insulating film 1 3 3 (3 0 3) is irradiated with the illumination light 2 65, the regularly arranged wiring patterns 1 3 2
  • the processing means 2 12 functions as a diffraction grating, and the reflected light that is spectrally separated from the interlayer insulating film 133 (303) is obtained.
  • the spectrally separated light is converted by the imaging lens 272.
  • the detector 273 By forming an image and receiving the formed spectral image by the detector 273, a signal as shown in FIG. 11 can be detected. Therefore, by converting the signals into the signals shown in FIG. 12 by the processing means 2 12,
  • the remaining film thickness can be calculated based on (Equation 1).
  • equation 1 the remaining film thickness
  • FIG. 17 is a configuration diagram showing a fourth embodiment of the remaining film thickness detection head 2 11. That is, the remaining film thickness detection head 211 is formed of a white light source 331, a half mirror 3333, and a semiconductor wafer 1 which condenses the white light emitted from the white light source 3311.
  • a condenser lens (imaging lens) 332 that forms an image on the detector 3334 by irradiating the polished surface of the semiconductor wafer 1 with the diffracted light obtained from the polished surface (film to be planarized) of the semiconductor wafer 1;
  • a detector 334 for receiving the formed diffraction image and converting it into a diffraction image signal.
  • FIG. 1 is a configuration diagram showing a fourth embodiment of the remaining film thickness detection head 2 11. That is, the remaining film thickness detection head 211 is formed of a white light source 331, a half mirror 3333, and a semiconductor wafer 1 which condenses the white light emitted from the white light source 3311.
  • Fig. 18 shows the intensity distribution of the diffraction image 146 on the diffraction image surface 144 detected by the detector 334.
  • Fig. 19 shows the change of the remaining film thickness in the u-direction (radius method) on the diffraction image plane.
  • 14 shows changes in the intensity distribution of the diffraction image according to the transformation. Therefore, by measuring and storing in advance the intensity distribution of the diffraction image corresponding to a plurality of remaining film thicknesses in the memory in the processing means 2 12, the processing means 2 12 The remaining film thickness can be calculated by interpolating the intensity distribution of the diffraction image corresponding to the plurality of remaining film thicknesses stored in the memory from the intensity distribution of the diffraction image detected in step (1).
  • FIG. 20 is a block diagram showing another embodiment for measuring the remaining film thickness.
  • This embodiment is provided with a small polishing head 202a for supporting a sample 281, which is made of a tapered transparent substrate for measuring the remaining film thickness, and uses the original polishing head 202.
  • the sample 281 is configured to be polished with a polishing platen 201 on which a polishing cloth 204 is adhered. That is, similarly to the polishing head 202, the polishing head 202a is rotationally driven so as to rotate by applying a polishing pressure.
  • the polishing amount for the semiconductor wafer 1 and the polishing amount for the sample 281 can be matched. In any case, it is necessary to determine in advance the correlation between the polishing amount for the semiconductor wafer 1 and the polishing amount for the sample 28 1. Since the correlation between the amount of polishing for the semiconductor wafer 1 and the amount of polishing for the sample 28 1 has been grasped in this manner, the remaining film thickness for the semiconductor wafer 1 is measured by measuring the remaining film thickness for the sample 28 1. Can be calculated.
  • a polishing head 202 a a coherent light source 282 such as a laser, a half mirror 283 and a detector 284 are provided, and a polishing head 202 a is provided.
  • the supported sample (tapered transparent substrate) 281 was irradiated with coherent light from the back through window 285 from behind, and the tapered transparent substrate was exposed.
  • An interference optical system is formed in which an interference fringe image (shown in FIG. 21 (a)) from the bright substrate 281 is detected by a detector 284.
  • the coherent light source 282 does not necessarily need to be a laser, but may use a white light source such as a halogen lamp to form a coherent state in the entire optical system.
  • the detector 284 receives the interference fringe image 286 shown in FIG. 21 (a) and receives the interference fringe image 286 shown in FIG. 21 (b) according to the remaining film thickness of the sample 281. Signals 287 and 288 are obtained. Therefore, by calculating the shift amount 51 of the signals 287 and 288 in the processing means 211 with i O, the remaining film thickness of the sample 281 can be obtained.
  • the remaining film thickness for the semiconductor wafer 1 can be calculated from the correlation between the polishing amount for the wafer 1 and the polishing amount for the sample 28 1. In the case of this embodiment, the remaining film thickness can be calculated at any time during polishing. During polishing, the sample 2
  • the illumination optical system and the detection optical system composed of the 20-color 2831 and the detector 2884 are provided. May be installed. In this case, in order to measure the remaining film thickness of the sample 281 supported on the polishing head 202a, as shown in FIG. 8, the polishing head 202a was used. Raise to position 2 0 2 '.
  • the polished sample (taper For the polishing head 202a supporting the 281, the remaining film thickness of the sample 281, as with the remaining film thickness detection head 211 shown in FIG.
  • the quantity can be measured.
  • FIG. 22 is a block diagram showing another embodiment different from FIG. 20 for measuring the remaining film thickness.
  • This example has a small polishing head 202a supporting a sample 291, which is a parallel transparent substrate for measuring the remaining film thickness, and has a semiconductor polishing method using the original polishing head 202.
  • the sample 291 is polished with the polishing platen 201 on which the polishing cloth 20 is adhered. That is, similarly to the polishing head 202, the polishing head 202a is also driven to rotate by applying a polishing pressure and rotating.
  • the material to be polished for the semiconductor wafer 1 is the insulating film 303, 326, the material of the insulating film 303, 326 and the material of the sample 291.
  • the amount of polishing for the semiconductor wafer 1 and the amount of polishing for the sample 29 1 can be matched.
  • the coherent light such as a laser is applied to the polishing head 202 a from an oblique direction symmetrically with respect to the detection optical axis 294 so as to substantially overlap the polished surface of the sample 29 1.
  • Specimen parallel transparent substrate supported by a polishing head 202a, comprising an irradiation optical system for irradiating 293b and 293b, an imaging lens 292, and a detector 284
  • the coherent light beams 293 a and 293 b are obliquely symmetrical with respect to the detection optical axis 294 through the window 285 from the back side of the sample 291 so that they almost overlap each other on the polished surface of the sample 291.
  • the detector 284 receives the interference fringe image 286 shown in FIG. 21 (a) and receives the interference fringe image 286 shown in FIG. 21 (b) according to the remaining film thickness of the sample 291. Signals 287 and 288 are obtained.
  • the remaining film thickness of the sample 291 can be obtained by calculating the shift amount 51 of the signals 287 and 288 in the processing means 2 12, and as a result, the semiconductor wafer 1
  • the remaining film thickness for the semiconductor wafer 1 can be calculated from the correlation between the polishing amount for the semiconductor wafer 1 and the polishing amount for the sample 29 1.
  • the remaining film thickness can be calculated at any time during polishing.
  • a water suspension of abrasive grains is interposed between the polished surface of the sample 291 and the polishing cloth 204.
  • the interference fringes shown in Fig. 21 (a) can be detected without being greatly affected by the water suspension.
  • the polishing speed (polishing rate) can be monitored in real time during polishing, the film thickness must be measured in advance. The amount of residual film thickness can be monitored, and the switching from high-speed polishing to high-precision low-speed polishing can be delayed until the time when defects such as scratches and foreign matter do not finally occur is reached. As a result, a flattened polished surface free of defects such as scratches and foreign substances can be manufactured at a high throughput with respect to the semiconductor wafer 1.
  • the metal film 3 16 is applied to the CMP device 20 as shown in FIG. Even when polishing at 0, it is necessary to predict or detect the point in time when the lower SiO 2 -based insulating film pattern 3 15 is exposed as the remaining film thickness. Therefore, the cross-sectional structure shown in Fig. 3 (d) A semiconductor wafer 1 having a structure is supported on a polishing head 202, and a metal film 3 16 on the surface of the semiconductor nano 1 is connected to a polishing cloth 204 adhered to a polishing platen 201.
  • the head 202 is raised to the position 202 ', and the semiconductor wafer 1 supported by the polishing head 202 is washed with pure water to wash the polished surface of the semiconductor wafer 1.
  • the thickness of the wiring pattern with the exposed insulating film pattern 3 15 can be optically measured by optical interference using the remaining film thickness detecting head 2 1 1, which is appropriate for the end point of polishing. Or not. In other words, when only the metal film 316 is formed on the surface, no interference occurs, so that a flat detection waveform is detected.
  • the insulating film pattern 315 below the metal film 316 When the insulating film pattern 315 below the metal film 316 is exposed, the insulating film is formed. Reflected light from the lower surface of 315 (only a small amount of reflected light is obtained from the lower surface of the insulating film 315 when the surface of the substrate 315 is formed of an insulating film) and metal wiring By detecting a waveform due to interference with the pattern 317 or the light reflected from the surface of the insulating film 315, it can be determined whether or not the polishing end point is appropriate. In particular, when the third embodiment shown in FIG. 16 is used as the remaining film thickness detection head 211, the configuration is simple and appropriate. Next, the defect inspection apparatus 240 for scratches / foreign matter will be specifically described with reference to FIGS. 23 to 26. FIG.
  • FIG. 23 is a configuration diagram showing a first embodiment of the defect inspection apparatus 240 for flaws and foreign matter according to the present invention.
  • an argon laser 1 a beam expander 12, a half-wave plate 13, a polarizing element 14, a polarizing element rotating mechanism 15 for changing the polarization direction of the polarizing element 14,
  • An illumination system 1 consisting of a condenser lens 16 such as a cylindrical lens and a variable incident angle mechanism 17 and an objective lens 31, a polarizing element 32, a spatial filter 33, and a detector 34.
  • the detection optical system 30 formed, the binarization circuit 51, the coordinate generation circuit 52, the detection result memory 54, the computer 53, and the detection result display means 55
  • a loading / unloading means 7 an xyz stage 71, an automatic focus detection system 73, a z stage controller 75, and an xy stage controller 72.
  • the computer 53 constituting the data processing system (processing means) 24 1 is connected to the management computer 250 via a network.
  • the semiconductor wafer 1 polished by the CMP device 200 and washed by at least the cleaning device 230 is transported from the cleaning device 230 to a loading position using a transporting device, and is loaded by the loading device 74. It is placed on the xyz stage 71 with the polished surface facing upward.
  • Inspection range data input and set in advance to the computer 53 is provided to the xy stage controller 72, and the xy stage 71 is changed to xy based on the control of the xy stage controller 72.
  • the output of the xy stage controller 72 is led to a coordinate generation circuit 52, which is used to create the coordinates of the inspection position.
  • the automatic focus detection system 73 detects the focus position based on the amount of defocus by projecting a stripe pattern. It may be one that detects the position, or one that measures the z position with a capacitance type sensor.
  • the light emitted from the argon laser 11 has its beam diameter expanded by the beam expander 12, is converted into circular or elliptically polarized light through the half-wave plate 13, and is S-polarized or polarized by the polarizing element 14.
  • the light is converted into P-polarized light, condensed in a narrow band shape by a condensing lens 16 such as a cylindrical lens, and is irradiated onto the flattened polished surface on the semiconductor wafer 1.
  • the polished surface of the semiconductor wafer 1 is condensed by the detection lens 31 and is detected by the detector 34 through the polarizing element 32 or the filter and the spatial filter 33. That is, the polished surface of the semiconductor wafer 1 is irradiated with condensed laser light from an oblique direction, the xy stage 71 is scanned, and the scattered diffraction light from the polished surface of the semiconductor wafer 1 is applied to the objective lens 31.
  • the polished surface of the semiconductor wafer 1 is, for example, the interlayer insulating film 303
  • the wiring pattern 301 underneath causes scattering scattering from the regularly arranged wiring pattern 301.
  • the emitted light is shielded by a polarizing element 32 or a spatial filter 33, and an image due to scattered diffraction light generated from the polished surface of the semiconductor wafer 1 is received by a detector 34 constituted by, for example, a linear sensor (CCD), and a detection signal is received. 3 7 is output.
  • the detection signal 37 is converted into a binarized signal by a binarization circuit 51 at a desired threshold, and a defect such as a scratch or a foreign substance present on the polished surface exceeding the desired threshold in the binarized signal.
  • the detection result memory 54 stores the positions of the occurrence positions of the scratches and the foreign matters by discriminating them from each other.
  • the computer 53 Since the target is stored for each semiconductor wafer in correspondence with each other, the computer 53 reads out the stored data to read the stored data for each semiconductor wafer, for a plurality of semiconductor wafers, or for each lot.
  • the distribution of flaws and foreign matter generated on the semiconductor wafer can be collected as a map, which can be displayed on the display means 55 and provided to the management computer 250 for storage.
  • the information can be stored in the device 25 1 or displayed on the display means 25 2.
  • the computer 53 can collect changes (fluctuations) in the number of scratches or foreign substances generated on the semiconductor wafer for each semiconductor wafer or for each lot, and display them on the display means 55. It can also be provided to the management computer 250 and stored in the storage device 251, or displayed on the display means 252.
  • FIGS. 24 (a) and (b) show a light beam 10 ° applied to the surface (polished surface) of the semiconductor wafer 1.
  • FIG. Fig. 24 (a) shows the case where the surface (polished surface) is rough after film formation and after the CMP treatment
  • Fig. 24 (b) shows the case where the surface is not rough and foreign matter 41 is present.
  • FIGS. 24 (c) and (d) show the detection signal waveforms 109 and 110 obtained by receiving the scattered light with the detector 34 in each case. By the way, the signal waveform 109 based on the surface roughness shown in FIG.
  • the size of the detection pixel needs to be 7 ⁇ m square on the surface (polished surface). If the pixel size of the CCD itself is, for example, 13 square, the imaging magnification by the objective lens 31 may be about 1.9 times.
  • the value of the detection pixel size should be selected according to the purpose in relation to these other parameters. If you want to have sufficient detection sensitivity, convert to ⁇ ! ⁇ 2; It is desirable to make it about m square.
  • the threshold value may be set to the threshold value 112 shown in FIG. 24 (c). That is, when information on surface roughness is required when setting polishing conditions in the CMP apparatus 200, the defect inspection apparatus 2
  • the binarization circuit 51 is for erasing a rough surface signal, and need not necessarily be a binarization circuit. That is, the signal detected by the detector 34 is converted into image data quantized by a multi-valued threshold, and the image data is correlated with the position coordinates on the surface (polished surface), and the detection result memory is stored.
  • the computer 53 reads out the data stored in the detection result memory 54 and performs a classification process according to the size of the flaw generated on the surface (polished surface) of the semiconductor wafer 1 to determine whether the quality is good or bad. This has the effect of making a determination. Also, out of multiple thresholds By using either (or more than one) as the threshold for detecting surface roughness, the level of surface roughness, or distribution of surface roughness, can be measured, and the results can be used for management. By performing feed-packing to the CMP apparatus 200 via the computer 250, the polishing conditions in the CMP apparatus 200 can be optimized.
  • the computer 53 obtains the detection results (quantized image data from which surface roughness has been removed) for each semiconductor wafer 1 stored in the detection result memory 5 as shown in FIG. 25 (a). Scratches 40 usually appear in multiple continuous (or intermittently continuous) forms, and as shown in Fig. 25 (b), the foreign matter 41 usually appears in an isolated form. Are classified into flaws and foreign substances by shape recognition processing based on basic knowledge. Then, for each semiconductor wafer 1, the computer 53 groups adjacent flaws into one continuous flaw with respect to the image data classified as flaws, and counts the number of the grouped flaws. The number of flaws for each semiconductor wafer 1 can be calculated and stored in the detection result memory 5, and the number of flaws for each semiconductor wafer 1 can be managed.
  • this grouping process is not always useful, and it is clear that the grouping process is not necessary when managing the area of the scratches on each semiconductor wafer 1 (over the entire surface). It is.
  • This grouping process is performed using a labeling algorithm known as a normal image processing algorithm. Further, it has been described that this processing is performed softly by the computer 53, but it may be realized by dedicated hardware (circuit).
  • the process of assigning the same label to continuous or very close image patterns and grouping them can be used for classification of scratches and foreign matter. This is because wounds usually appear in multiple continuous (or intermittent) forms, and foreign bodies usually appear in an isolated form. Furthermore, the face By grouping the signals from which the roughness has been eliminated by hardware, the capacity of the detection result memory 54 can be saved.
  • the computer 53 reads out the binarized image data stored in the detection result memory 54 for each semiconductor wafer, and recognizes the shape by image processing as shown in FIG. It is determined whether the scratch is a stretch 40 or a particle-like foreign matter 41, and when the scratch 40 is determined, the area S s of the scratch 40 is determined from the binarized image data indicating the scratch. And the maximum length L is determined, the pass / fail judgment is made by comparing it with the scratch judgment criteria, and the result is stored in the detection result memory 54 in correspondence with the coordinates of the occurrence position.
  • the area S f of the foreign substance 4 1 is obtained from the binarized image data indicating the foreign substance, is compared with the foreign substance determination standard, and the quality is determined, and the result is detected. And store. Recognizing whether a defect generated on the polished surface is a scratch or a foreign substance is because the criteria for quality are different and the polishing conditions for generating the scratch and the polishing conditions for generating the foreign substance are different. .
  • the CMP apparatus 200 corrects the CMP conditions based on a command or control from the control unit 204 so that the polishing surface of the semiconductor wafer 1 is free from scratches and foreign matter. Yield can be improved. Also, if the CMP apparatus 200 also needs surface roughness information of the polished surface to set the polishing conditions, the control unit 204 will send the information from the processing means 21 of the inspection apparatus 240 for scratches and foreign matter. Provision may be made via the management computer 250.
  • the planarized polished surface on the semiconductor wafer 1 includes a case where an insulating film 303 is formed on a wiring pattern 301 and a case where As shown in Fig. 3 (e) and Fig. 4, the substrate (the surface may be formed of an insulating film) 3 11
  • the insulating film pattern 3 15 and the wiring pattern 3 17 are formed on 1 1 and if it is, FIG. 5 (e) and sixth when the pattern 3 2 2 S i 0 2 based insulating film pattern 3 2 5 and S i 3 N 4 is formed as shown in FIG. There is.
  • the flattened polished surface on the semiconductor wafer 1 is slightly roughened by polishing.
  • the insulating film pattern 315 and the wiring pattern 317 exist on the polished surface.
  • the insulating film pattern 315 and the wiring pattern 317 have different surface reflectivities. Therefore, a signal waveform obtained by the detector 34 receiving the scattered diffracted light generated from the surface of the insulating film pattern 3 15 due to the surface roughness, and a signal waveform generated from the surface of the wiring pattern 3 17 due to the surface mark The intensity is different from the signal waveform obtained by the detector 34 receiving the scattered diffraction light.
  • the computer 53 determines the area of the insulating film pattern 315 and the area of the wiring pattern 317 from the signal 37 obtained from the detector 34, and determines the area of the wiring pattern 317 from the area of the wiring pattern 317.
  • a high threshold is set for the binarization circuit 51, and for the signal obtained by the detector 34 from the region of the insulating film pattern 3 15, the binarization circuit 5 is set.
  • a low threshold for 1 Can be erased.
  • the image signal obtained from the detector 34 is stored for a predetermined time until the computer 53 determines the area of the insulating film pattern 315 and the area of the wiring pattern 317. Need to be done.
  • the intensity of scattered light generated from scratches generated on the surface of the insulating film pattern 315 is weaker than the intensity of scattered light generated from scratches generated on the surface of the wiring pattern 317.
  • the problem with the semiconductor element is the damage on the surface of the wiring pattern 317, and the sensitivity of the damage on the surface of the insulating film pattern 315 decreases. It doesn't matter if you don't recognize it correctly. Regarding foreign matter, no problem occurs because the same scattered light intensity can be obtained for the insulating film pattern 315 and the wiring pattern 317.
  • the threshold value is changed between the region of the insulating film pattern 3 15 and the region of the wiring pattern 3 17 in order to erase a signal caused by surface roughness. If it is not necessary to be able to recognize the scratches generated on the surface, it is sufficient to set a high threshold that can eliminate the surface roughness generated on the surface of the wiring pattern 317 regardless of the area. This eliminates the need for the computer 53 to determine the region of the insulating film pattern 315 and the region of the wiring pattern 317 and change the threshold. As described above, in the cases shown in FIGS. 3 (e) and 4, it is possible to inspect for foreign substances and scratches generated on the polished surface.
  • the insulating film pattern 325 and the Si 3 N 4 layer 3222 exist on the polished surface.
  • both the insulating film pattern 325 and the Si 3 N 4 layer 322 show similar characteristics to the illumination light, and as shown in FIGS. 24 (c) and (d),
  • the threshold value 1 1 1 eliminates the signal generated by the surface roughness, and as a result, it becomes possible to inspect the polished surface for foreign substances and scratches.
  • the sensitivity such as the threshold may be set.
  • the light source of the illumination light in the defect inspection apparatus 240 for scratches and foreign matter shown in FIG. 23 does not need to be an argon laser 11 but a laser light source of another wavelength, for example, a helium neon laser, It may be a red semiconductor laser (gallium aluminum arsenide compound semiconductor laser), a light source using SHG (second harmonic), a discharge tube light source such as a xenon lamp or a mercury lamp, or a filament lamp such as a halogen lamp.
  • a red semiconductor laser gallium aluminum arsenide compound semiconductor laser
  • SHG second harmonic
  • discharge tube light source such as a xenon lamp or a mercury lamp
  • a filament lamp such as a halogen lamp.
  • the spatial filter 33, the half-wave plate 13 and the polarizing elements 14 and 32 are not necessarily required. These filters are used to classify the shape of a flaw, and to classify uneven shapes such as foreign matter or defects. Specifically, by using S-polarized light (light flux whose electric field vector is perpendicular to the incident surface) as irradiation light, surface roughness of the surface (polished surface) of the semiconductor wafer 1 is reduced, and foreign matter, scratches and scratches are reduced. Detection sensitivity can be improved. Conversely, by using P-polarized light (a light beam whose electric field vector is parallel to the plane of incidence), surface roughness can be detected with high sensitivity. These modes are selected according to the object to be evaluated.
  • S-polarized light light flux whose electric field vector is perpendicular to the incident surface
  • P-polarized light a light beam whose electric field vector is parallel to the plane of incidence
  • FIG. 26 schematically shows a case where the illumination is two-way illumination in the defect inspection apparatus 240 for scratches and foreign matter shown in FIG.
  • the illumination is two-way illumination in the defect inspection apparatus 240 for scratches and foreign matter shown in FIG.
  • FIG. 23 a flaw having a direction close to the direction perpendicular to the plane of incidence of the illumination is emphasized and detected. Therefore, as shown in FIG. 26, this directivity can be reduced by obliquely illuminating from directions 101, 102, 103, 104 perpendicular to each other.
  • two perpendicular directions 101 and 102 may be used.
  • four directions 103, 105, 106, and 104 including directions that are not right angles, may be used.
  • two or four perpendicular directions shown above are used.
  • FIG. 27 shows a method of illuminating from all directions in the defect inspection apparatus 240 for flaws and foreign matter shown in FIG.
  • an illumination optical system composed of a light source 1 I, beam expanders 18 and 19, a mirror 38 penetrating the center, an objective lens 31, an imaging lens 37, and a detector 3 4 and a stage optical system 70 shown in FIG. 23 and a data processing system 24 1.
  • one point on the surface (polished surface) of the semiconductor wafer 1 is illuminated from all directions by the illumination optical system.
  • the light reflected from the surface of the semiconductor wafer 1 is shielded from the 0th-order reflected light by the mirror 38 penetrating the center, and only the scattered light from defects such as scratches or foreign matter passes through the mirror 38 to form an image.
  • the image is formed on the detector 34 by the lens 37 and detected.
  • the illuminating light beam spirals with respect to the surface of the semiconductor wafer 1 by scanning the X stage while rotating the stage. Scanning is efficient. Therefore, the X z S stage system is used for the stage system.
  • stage system is also of course c not an essential problem even shown to X yz stage to the second 3 figures, configurations such as the data processing system 2 1 is equivalent to that of the second 3 Figure is there.
  • the directivity is further reduced by detecting a flaw or the like as compared with the method shown in FIG.
  • FIG. 28 An embodiment of the defect inspection apparatus 220 for scratches / foreign matter will be specifically described with reference to FIGS. 28 to 31.
  • FIG. 28 An embodiment of the defect inspection apparatus 220 for scratches / foreign matter will be specifically described with reference to FIGS. 28 to 31.
  • This embodiment utilizes the fact that a semiconductor wafer 1 polished by a CMP apparatus 200 is stored in a liquid until it is cleaned by a cleaning apparatus 230, so that scratches on the polished surface in the liquid can be prevented. This is to inspect for defects such as foreign matter.
  • FIG. 1 is a schematic configuration diagram showing an embodiment of a defect inspection apparatus 220 for an object or the like.
  • This embodiment has substantially the same configuration as that of FIG.
  • a stage 71 for placing the semiconductor wafer 1 in the liquid in the tank 3 is provided.
  • the illumination system 10 is provided outside the tank 3, and the detection system 30 is housed in the casing 36.
  • the processing means 24 1 is the same as in FIG. Therefore, the illumination light from the illumination system 10 irradiates the surface (polished surface) of the semiconductor wafer 1 in the liquid through the illumination window 18 and the scattered light from the surface of the semiconductor wafer 1 in the liquid is detected. Through 35, detection is performed by the detection optical system 30. Since the semiconductor wafer 1 exists in the liquid, the stage on which the wafer is placed is fixed, and it is desirable that the illumination optical system 10 and the detection optical system 30 scan the stationary semiconductor wafer 1. Of course, a configuration for scanning the stage may be used.
  • the illumination window 18 and the detection window 35 are provided to prevent the illumination and detection light from being distorted due to fluctuations in the liquid surface when light enters the liquid.
  • This method has an effect that the polished semiconductor wafer 1 is stored in a liquid, so that the inspection can be performed during the storage.
  • the flattening film is made of quartz with a refractive index of 1.462
  • liquids such as aniline with a refractive index of 1.586, glycerin with a refractive index of 1.473, and a refractive index of 1 460 carbon tetrachloride, refraction index 1.73 7 jade methane, refraction index 1.516 seda oil, refraction index 1.48 paraffin oil, refraction index 1.66 ⁇ —Bromonaphthalene, benzene with a refractive index of 1.5012, etc. are considered.
  • Fig. 29 shows how foreign matter or scratches are detected when total reflection occurs.
  • FIG. 30 shows the reflectance at the surface shown in FIG. 29. The values for P-polarized light 47 and S-polarized light 48 are shown, respectively.
  • FIG. 31 shows another embodiment.
  • light is irradiated onto the entire surface or a part of the surface of the semiconductor wafer 1 through an illumination window 18, and an area illuminated through a detection window 35 is formed on an imaging lens 34 on a two-dimensional detector 34.
  • the image is re-imaged by 3 1.
  • This embodiment also uses the above conditions for total reflection. By using the condition of the total reflection, the influence of the underlying pattern can be eliminated, so that the pixel size of the detection can be increased. Even with such a two-dimensional sensor 34, a wide area can be inspected at a time. For example, using a 1000 ⁇ 100 pixel CCD camera, a 7 micron pixel can inspect a 7 mm ⁇ 7 mm area.
  • the inspection area needs to be increased, the pixel size may be increased, or the inspection area may be enlarged by step-and-repeat. Further, the detection sensitivity may be increased by reducing the pixel size at the expense of the inspection area.
  • the defect inspection data of the scratches / foreign matter obtained from the processing means 2 41 of the defect inspection apparatus 240 for flaws / foreign matter and the processing means 25 1 of the completed tester 250 obtained from the processing means 25 1 The production management of the production line 400 of the semiconductor wafer 1 by the management computer 250 based on the electrical characteristic data of the semiconductor element will be described with reference to FIGS. 32 to 39.
  • FIG. 32 shows a production line 400 of the semiconductor wafer 1 according to the present invention.
  • 1 is a diagram showing an overall configuration of production management by all management computers 250.
  • FIG. FIG. 7 shows a similar configuration.
  • the production line 400 of the semiconductor wafer 1 typically includes a metal film forming process such as sputtering, a resist pattern forming process (a resist coating process, an exposure process, a developing process, etc.), and an etching process (resist pattern).
  • an insulating film forming step 402 for forming an insulating film 303 on the wiring pattern 301 by a CVD apparatus or the like.
  • a sputtering device in the wiring pattern forming step 401 and the wiring pattern forming step 404, a sputtering device, a resist coating device, an exposure device, an etching device and the like are used.
  • a CVD apparatus or the like is used in the insulating film forming step 402 and the insulating film forming step 405.
  • Reference numerals 411, 412, 413 (204), 414, and 415 denote control devices for controlling devices provided in each process. Therefore, the control devices 411, 12, 13 (204), 414, and 415 form the film formation, etching, exposure, polishing, etc. for each semiconductor wafer 1 to be input.
  • the defect inspection device 240 for obtaining scratches, foreign matter, etc. which can obtain the manufacturing conditions, can be used in the desired process (may be within the process) in the manufacturing line 400 of the semiconductor wafer 1.
  • the semiconductor wafer 1 that needs to be inspected for defects such as scratches and foreign matter is inspected for defects such as damage and foreign matter.
  • the defect inspection device 24 ⁇ for scratches / contaminants, etc. is polished by the CMP device 200 and the surface of the semiconductor wafer 1 cleaned by the cleaning device 230 is subjected to defects such as scratches / contaminations.
  • the defect inspection device 240 for scratches, foreign matter, etc. may be installed between required steps in the production line 400. In this case, although the number of the defect inspection devices 240 such as scratches / foreign matter increases, the defect such as scratches / foreign matter generated on the surface of the semiconductor wafer 1 can be regularly inspected.
  • Reference numeral 430 denotes a tester for inspecting electrical characteristics of a substantially completed semiconductor device capable of performing an operation test.
  • Reference numeral 431 denotes processing means constituted by a computer or the like for performing an inspection process of the electrical characteristics in the tester 430. Therefore, the processing means 431 of the tester 430 can obtain the results of the electrical characteristics of the semiconductor elements (semiconductor chips) for each semiconductor wafer 1.
  • the management computer 250 includes processing means 24 1 for the defect inspection device 240 for scratches and foreign matter, processing means 43 1 for the tester 430, and control devices 4 1 1, 4 1 2 and 4 1 3 for the manufacturing equipment ( 204), 414, 415 and network 409. Therefore, the management computer 250 obtains the electrical characteristic results of the semiconductor elements (semiconductor chips) for each semiconductor wafer 1 from the processing means 431 of the tester 43, and the yield per semiconductor wafer. Can be calculated. Further, the management computer 250 is damaged. From the processing means 21 of the defect inspection apparatus 240 for objects and the like, it is possible to discriminate scratches and foreign substances generated on the surface of each semiconductor wafer 1 in each manufacturing process and obtain the coordinates including the coordinates of the generated positions.
  • the one detected at the same position coordinate is judged to be the scratch or foreign matter generated in the previous process or all the previous processes before input, and erased.
  • These determination processes may be performed by the processing means 241 of the defect inspection device 240 for flaws and foreign matter.
  • the management computer 250 includes the coordinates of the position of occurrence on the surface of each semiconductor wafer 1 for each manufacturing process obtained from the processing means 241 of the defect inspection device 240 for scratches and foreign matter.
  • the information on the foreign matter that has been generated and the information on the electrical characteristics of the semiconductor elements (semiconductor chips) for each semiconductor wafer 1 obtained from the processing means 431 of the tester 4340 are used.
  • ⁇ Yield for each of the chip having no foreign matter and the chip having foreign matter can be calculated with respect to the number of chips having foreign matter on a wafer basis as shown in Fig. 36.
  • FIGS. 34 to 36 shows, in a certain manufacturing process, the yield and the foreign matter of a chip without foreign matter in the number of chips having foreign matter per wafer over a predetermined number of semiconductor wafers. This shows the relationship with the yield of the existing chips.
  • Non-defective chip rate different All non-product chips are handled as good products.
  • the non-defective rate is a high and constant value. That is, when the data shown in Fig. 34 is obtained from a certain manufacturing process, it can be understood that the foreign matter is normally detected, and the foreign matter can be determined as the main cause of the defect, and the result is displayed. It can also be displayed in means 25 2.
  • Fig. 35 Indicates that there is not. Therefore, if the data shown in Fig. 35 is obtained from a certain manufacturing process, it can be understood that foreign matter has not been detected normally, and foreign matter can be determined as the main cause of failure, and the result is displayed. It can also be displayed in means 25 2.
  • the management computer 250 obtains the results shown in Fig. 35, feed it into the processing means 241 of the defect inspection device 240 for scratches and foreign matter, and adjust the sensitivity so that inspection can be performed without oversight. You need to do something like that. Alternatively, it is necessary to use a more sensitive foreign substance inspection device. Specifically, measures such as prolonging the inspection time or using a light or SEM type visual inspection device can be considered.
  • the chips with foreign matter exist in wafer units. As the number (the number of foreign chips) increases, the yield of foreign chips decreases, and even if the number of foreign chips (the number of foreign chips) increases, the yield of foreign chips does not increase. It shows a low and almost constant value, similar to the yield of chips with foreign matter. In other words, the yield of chips without foreign matter is not related to the number of chips with foreign matter (the number of chips with foreign matter), but the yield is lowered. It indicates that there are other factors (for example, process factors). If the yield of foreign particles is constant irrespective of the number of chips with foreign particles (the number of foreign particles), it can be understood that the cause of the decrease in yield is other than foreign particles. Therefore, if the data shown in Fig. 36 is obtained from a certain manufacturing process, it can be determined that the cause of the defect that reduces the yield is other than foreign matter (for example, process factors), and as a result, Can be displayed on the display means 25 2.
  • the management computer 250 is provided with a foreign substance including coordinates of a generation position generated on the surface of each semiconductor wafer in each manufacturing process obtained from the processing means 241 of the defect inspection apparatus 240 such as a scratch and a foreign substance.
  • the information of the electrical characteristics of the semiconductor elements (semiconductor chips) for each semiconductor wafer 1 obtained from the processing means 431 of the tester 4330 is shown in FIG. Calculate the change in the number of chips with foreign particles (the number of chips with foreign particles), the change in yield for chips with no foreign particles, and the change in yield for chips with foreign particles in lot units as shown in the figure. Can be.
  • the yield of chips with foreign particles should have a correlation with the number of chips with foreign particles.
  • the yield of foreign chips increases, and if the number of foreign chips increases, the yield of foreign chips must decrease.
  • the yield for chips without foreign matter should not be correlated with the number of chips with foreign matter. Therefore, if it is assumed that foreign matter can be reliably inspected, If the yield of a chip without a substance cannot be correlated with the number of chips with a foreign substance, it is determined that the cause of the decrease in the yield of a chip without a foreign substance is other than a foreign substance (for example, a process factor). be able to.
  • the management computer 250 is provided with a foreign substance including coordinates of a generation position generated on the surface of each semiconductor wafer in each manufacturing process obtained from the processing means 241 of the defect inspection apparatus 240 such as a scratch and a foreign substance.
  • the information of the electrical characteristics of the semiconductor elements (semiconductor chips) for each semiconductor wafer 1 obtained from the processing means 431 of the tester 4330 are shown in FIG.
  • the number of foreign substances present in one chip in a semiconductor wafer unit or a plurality of semiconductor wafers, and the non-defective product of the chip (a non-defective product includes a completely non-defective product and a non-defective product obtained by bit rescue). ), The relationship with the number of defective products can be calculated.
  • the probability that the chip becomes defective should increase.
  • the probability of a defective product (the number of defective products and the number of non-defective products) should increase. If this relationship is established, it can be determined that the main cause of the failure is due to foreign matter, and if this relationship is not established, the main cause of the failure is a process factor other than the foreign matter. Can be determined.
  • the management computer 250 is capable of detecting the foreign matter including the coordinates of the occurrence position generated on the surface of each semiconductor wafer in each manufacturing process obtained from the processing means 21 of the defect inspection device 240 for scratches and foreign matter. From the information and the information on the electrical characteristics of the semiconductor elements (semiconductor chips) for each semiconductor wafer 1 obtained from the processing means 431 of the tester 43, the same semiconductor as shown in FIG. It is possible to calculate the transition between the yield of a chip without foreign matter and the yield of a chip with foreign matter in the order of the manufacturing process of the body wafer.
  • the management computer 250 includes at least the manufacturing conditions for each lot from the control devices 411, 412, 413 (204), 4114 and 415 of the manufacturing equipment. (Including information on maintenance, cleaning, etc.) is input and stored in the storage device 251, together with the inspection data, corresponding to the manufactured semiconductor wafer. Therefore, the management computer 250 investigates the cause of the occurrence of foreign matter, scratches, etc. in each manufacturing process, and the result is used as the control device 411, 412, 413 (204), Feedback can be made to 414 and 415, and it can also be displayed on the display means 252 and output.
  • the management computer 250 determines that the cause of the decrease in the yield as a semiconductor element is a process factor in a predetermined manufacturing process
  • the management computer 250 stores the predetermined manufacturing data stored in the storage device 251. It is possible to select the manufacturing conditions to be adjusted from the transition of the past manufacturing conditions in the process and feed back the result to the control device of the manufacturing equipment that constitutes the specified manufacturing process, and display it on the display means 252. Can also be output.
  • the control devices 4 1 1, 4 1 2, 4 1 3 (2 04) and 4 1. 4 1 5 of each manufacturing device are based on the information fed back from the management computer 250, and By controlling the It can be manufactured at high yields. Industrial applicability
  • the end point of polishing can be detected when the semiconductor wafer is polished and planarized, so that defects such as excessive and insufficient polishing can be prevented, and as a result, This has the effect that the device can be manufactured with a high yield and a high throughput.
  • the present invention when a semiconductor wafer is polished and flattened, defects such as scratches, foreign matter, surface roughness and the like at the time of flattening are inspected, and the result is fed back to the polishing process, whereby defects are reduced.
  • the effect of reducing fabrication is that semiconductor elements can be manufactured at a high yield.
  • the present invention when polishing and flattening a semiconductor wafer, the amount of remaining film is monitored in real time, and switching between high-speed polishing with a high polishing rate and low-speed polishing with high accuracy can be controlled. As a result, it is possible to prevent the occurrence of defects such as scratches, foreign matter, surface roughness, etc. due to polishing, and to produce an effect that a semiconductor device can be manufactured with a high yield and with a high throughput.
  • the cause of the failure can be removed at an early stage. It has the effect that it can be manufactured by stopping.
  • a semiconductor device semiconductor element
  • reduces defects and surface roughness such as scratches and foreign substances generated when a material to be planarized is subjected to chemical and mechanical polishing. That can be manufactured with high yield To play.
  • an element isolation structure can be formed on a semiconductor substrate without causing defects by using chemical and mechanical polishing.
  • a wiring pattern can be formed on a substrate by using chemical and mechanical polishing with a metal material which is difficult to etch without causing defects.
  • the present invention it is possible to determine whether or not the cause of the defect is due to a defect such as a scratch or a foreign substance, and to take measures against the defect.
  • the present invention it is possible to improve the reliability of the defect inspection in the defect inspection step or its means, and to produce a semiconductor device with a high yield.
  • the present invention is suitable for a method for manufacturing a semiconductor device.

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Abstract

A method for manufacturing a semiconductor device by chemically and mechanically polishing an objective material formed on a semiconductor substrate to planarize it, in order to manufacture a semiconductor device (semiconductor element) with high throughput and high yield while realizing highly precise chemical and mechanical polishing. In this manufacturing method, the thickness of a residual film of the polishing object is measured when chemical and mechanical polishing is carried out on the polishing object, and the chemical and mechanical polishing is switched from high-speed polishing to low-speed polishing in accordance with the measured thickness of the residual film of the polishing object. The manufacturing method includes a polishing step of chemically and mechanically polishing an objective material formed on a substrate so as to planarize the polishing object, and an inspection step of inspecting the generation state of flaws and dust particles apart from surface roughening generated on a polished surface planarized by the polishing step, so that the generation state of flaws and dust particles on the polished surface inspected by the inspection step is fed back to the polishing step so as to control polishing conditions, thereby reducing flaws and dust particles generated on the polished surface.

Description

明 細 書 半導体装置の製造方法およびそのシステム 技術分野  Description: Semiconductor device manufacturing method and system therefor
この発明は、 製造ラインにより基板上に成膜、 露光、 エッチングを繰 リ返し、 半導体装置を製造する方法及びシステムに関し、 特に成膜後の 表面を化学的、 且つ機械的な研磨によリ平坦化する工程および装置を有 する半導体装置の製造方法及びそのシステムに関する。  The present invention relates to a method and a system for manufacturing a semiconductor device by repeating film formation, exposure, and etching on a substrate by a manufacturing line, and in particular, to flatten the surface after film formation by chemical and mechanical polishing. The present invention relates to a method and a system for manufacturing a semiconductor device having a process and an apparatus for forming a semiconductor device.
背景技術 Background art
半導体装置は、 基板上に成膜、 露光、 エッチングを繰り返し、 基板上 に半導体装置を製造する。 この際、 半導体装置はその高密度化を達成す るために、 より微細なパターンを用いて製造される。 また、 より複雑な 回路を実現するために、 多層の配線パターンを用いるため段差が生じ、 段差上にパターンを形成する際に段差がパターン欠陥の原因となってい た。 そこで、 従来より、 段差が生じたパターン上に平坦な膜を形成し、 この平坦膜上に次のパターンを形成するようにしている。  A semiconductor device repeats film formation, exposure, and etching on a substrate to manufacture the semiconductor device on the substrate. At this time, the semiconductor device is manufactured using a finer pattern in order to achieve a higher density. Further, in order to realize a more complicated circuit, a step is generated because a multilayer wiring pattern is used, and the step is a cause of a pattern defect when a pattern is formed on the step. Therefore, conventionally, a flat film is formed on a pattern having a step, and the next pattern is formed on the flat film.
上記、 平坦化プロセスでは、 平坦化の際に残膜厚さを設計値通りに製 造することが極めて困難であった。 そこで、 特開平 8 _ 1 7 7 6 8号公 報には、 膜厚測定装置を研磨装置に装着し、 研磨後、 装着した膜厚測定 装置により残膜厚を測定し、 基準値に満たない場合、 再研磨する構成の 製造方法が開示されている。 さらに、 特開平 7— 2 8 3 1 7 8号公報、 特開平 7 - 2 8 5 0 5 0号公報、 特開平 8 - 5 1 0 9 0号公報にも、 同 様の平坦化時の終点検出法が開示されている。  In the above-mentioned planarization process, it was extremely difficult to manufacture the remaining film thickness according to the design value during the planarization. Therefore, in the publication of Japanese Patent Application Laid-Open No. 8-177768, a film thickness measuring device was attached to a polishing device, and after polishing, the remaining film thickness was measured by the attached film thickness measuring device, and the remaining film thickness was less than a reference value. In such a case, a manufacturing method in which re-polishing is performed is disclosed. Further, Japanese Patent Application Laid-Open Nos. Hei 7-2831178, Hei 7-25050, and Hei 8-51090 also disclose the same end point in flattening. A detection method is disclosed.
平坦化プロセスでは、 被平坦化膜の下部に配線パターン等のパターン が形成されており、 このパターンの影響について、 上記従来技術では十 分考慮されていなかったため、 十分な感度で、 高精度の残膜測定ができ なかった。 In the planarization process, a pattern such as a wiring pattern is placed below the film to be planarized. Since the influence of this pattern was not sufficiently considered in the above-mentioned conventional technology, it was not possible to measure the residual film with sufficient sensitivity and high accuracy.
本発明の目的は、 上記従来技術の課題を解決すべく、 平坦化すべき被 研磨材の下部に存在するパターンの影響を低減して高精度の残膜厚測定 を可能にし、 高精度の化学的、 且つ機械的な研磨を実現して半導体装置 (半導体素子） を高歩留ま りで製造できるようにした半導体装置の製造 方法を提供することにある。  An object of the present invention is to solve the above-mentioned problems of the prior art, reduce the influence of a pattern present below a material to be flattened, enable highly accurate measurement of the remaining film thickness, and provide a highly accurate chemical Another object of the present invention is to provide a method of manufacturing a semiconductor device which realizes mechanical polishing and can manufacture a semiconductor device (semiconductor element) at a high yield.
また本発明の他の目的は、 高スループッ トで、 且つ高精度の化学的、 且つ機械的な研磨を実現して半導体装置 （半導体素子） を高スループッ 卜で、 しかも高歩留まりで製造できるようにした半導体装置の製造方法 を提供することにある。  Another object of the present invention is to realize a high-throughput and high-precision chemical and mechanical polishing so that a semiconductor device (semiconductor element) can be manufactured at a high throughput and at a high yield. It is an object of the present invention to provide a method for manufacturing a semiconductor device.
また本発明の他の目的は、 平坦化すべき被研磨材に対して、 化学的、 且つ機械的な研磨を施した際に発生する傷や異物等の欠陥および面荒れ を低減して、 半導体装置 （半導体素子） を高歩留ま りで製造できるよう にした半導体装置の製造方法を提供することにある。  Another object of the present invention is to reduce defects and surface roughness such as scratches and foreign substances generated when a material to be planarized is chemically and mechanically polished. It is an object of the present invention to provide a method of manufacturing a semiconductor device which can manufacture (semiconductor element) with a high yield.
また本発明の他の目的は、 化学的、 且つ機械的な研磨を用いて半導体 基板上に素子分離構造を形成できるようにした半導体装置の製造方法を 提供することにある。  It is another object of the present invention to provide a method of manufacturing a semiconductor device in which an element isolation structure can be formed on a semiconductor substrate by using chemical and mechanical polishing.
また本発明の他の目的は、 化学的、 且つ機械的な研磨を用いて基板上 にエツチングが難しい金属材料で配線パターンを形成できるようにした 半導体装置の製造方法を提供することにある。  It is another object of the present invention to provide a method of manufacturing a semiconductor device in which a wiring pattern can be formed on a substrate using a metal material that is difficult to etch by using chemical and mechanical polishing.
また本発明の他の目的は、 不良の発生原因が傷や異物等の欠陥による ものであるか否かについて究明できるようにして、 その対策を可能にし た半導体装置の製造方法およびそのシステムを提供することにある。 また本発明の他の目的は、 欠陥検査工程またはその手段における欠陥 検査の信頼度を向上して、 高歩留ま りで半導体装置を製造できるように した半導体装置の製造方法およびそのシステムを提供することにある。 Another object of the present invention is to provide a method of manufacturing a semiconductor device and a system therefor in which it is possible to determine whether or not a defect is caused by a defect such as a scratch or a foreign substance, and to take measures against the defect. Is to do. Another object of the present invention is to provide a method for inspecting defects in a defect inspection process or its means. It is an object of the present invention to provide a method of manufacturing a semiconductor device and a system thereof that can improve the reliability of inspection and manufacture a semiconductor device with a high yield.
発明の開示 Disclosure of the invention
上記目的を達成するために、 本発明は、 基板上に形成された被研磨材 に対して化学的、 且つ機械的な研磨を施して平坦化して半導体装置を製 造する半導体装置の製造方法において、 前記被研磨材に対して化学的、 且つ機械的な研磨を施す際該被研磨材の残膜厚を測定し、 この測定され た被研磨材の残膜厚に応じて、 前記化学的、 且つ機械的な研磨を制御す ることを特徴とする半導体装置の製造方法である。  In order to achieve the above object, the present invention relates to a semiconductor device manufacturing method for manufacturing a semiconductor device by subjecting a material to be polished formed on a substrate to chemical and mechanical polishing and flattening the material. When performing chemical and mechanical polishing on the polishing target material, the remaining film thickness of the polishing target material is measured, and according to the measured remaining film thickness of the polishing target material, And a method of manufacturing a semiconductor device, characterized by controlling mechanical polishing.
また本発明は、 半導体基板上に形成された被研磨材に対して化学的、 且つ機械的な研磨を施して平坦化して半導体装置を製造する半導体装置 の製造方法において、 前記被研磨材に対して化学的、 且つ機械的な研磨 を施す際該被研磨材の残膜厚を測定し、 この測定された被研磨材の残膜 厚に応じて、 前記化学的、 且つ機械的な高速研磨から低速研磨に切リ換 え制御することを特徴とする半導体装置の製造方法である。  Further, the present invention provides a method of manufacturing a semiconductor device, in which a material to be polished formed on a semiconductor substrate is chemically and mechanically polished and planarized to manufacture a semiconductor device. When the chemical and mechanical polishing is performed, the remaining film thickness of the material to be polished is measured. According to the measured remaining film thickness of the material to be polished, the chemical and mechanical high-speed polishing is performed. This is a method for manufacturing a semiconductor device, characterized by performing switching control to low-speed polishing.
また本発明は、 前記半導体装置の製造方法において、 被研磨材 （被平 坦化膜） から反射する光の分光強度分布から被研磨材の残膜厚を測定す ることを特徴とする。  Further, the present invention is characterized in that, in the method of manufacturing a semiconductor device, the remaining film thickness of the material to be polished is measured from a spectral intensity distribution of light reflected from the material to be polished (planarized film).
また本発明は、 前記半導体装置の製造方法において、 被研磨材 （被平 坦化膜） から反射する光の分光強度分布からこの特徴的ピークの波長の 変動から被研磨材の残膜厚を測定することを特徴とする。  The present invention also provides the method of manufacturing a semiconductor device, wherein a remaining film thickness of the polished material is measured from a change in the wavelength of the characteristic peak from a spectral intensity distribution of light reflected from the polished material (planarized film). It is characterized by doing.
また本発明は、 前記半導体装置の製造方法において、 前記被研磨材と 同様に透明基板を研磨させ、 該透明基板の研磨面とその反対側の面とか ら反射する干渉光強度変化から、 前記被研磨材の研磨速度を計測するこ とを特徴とする。 また本発明は、 前記半導体装置の製造方法において、 前記被研磨材と 同様に透明基板を研磨させ、 該透明基板の研磨面から生じる干渉縞の移 動量から前記被研磨材の研磨速度を計測することを特徴とする。 The present invention also provides the method of manufacturing a semiconductor device, wherein the transparent substrate is polished in the same manner as the material to be polished, and the intensity of the interference light reflected from the polished surface of the transparent substrate and the surface on the opposite side is changed. It is characterized by measuring the polishing rate of the abrasive. Further, according to the present invention, in the method of manufacturing a semiconductor device, the transparent substrate is polished in the same manner as the material to be polished, and a polishing rate of the material to be polished is measured from a movement amount of interference fringes generated from a polished surface of the transparent substrate. It is characterized by the following.
また本発明は、 半導体基板上に薄い研磨ストツバ層を形成する研磨ス トツパ層形成工程と、 該研磨ス トツバ層も含めて前記半導体基板に対し て素子分離用の凹部を堀込むエッチング工程と、 該エッチング工程によ つて堀込まれた凹部を絶縁膜で埋めるように成膜する絶縁膜成膜工程と、 該絶縁膜成膜工程で成膜された絶縁膜に対して化学的、 且つ機械的な研 磨を施して平坦化して前記研磨ストツバ層の表面を露出する研磨工程と、 該研磨工程で露出した研磨ストツパ層を取り除く研磨ストツパ除去工程 と、 該研磨ストツバ除去工程で研磨ストツバ層が取り除かれた半導体基 板の表面を酸化して酸化層を形成する酸化工程とを有し、 前記半導体基 板に対して素子分離構造を形成することを特徴とする半導体装置の製造 方法である。  Further, the present invention provides a polishing stopper layer forming step of forming a thin polishing stopper layer on a semiconductor substrate, an etching step of digging a recess for element isolation in the semiconductor substrate including the polishing stopper layer, An insulating film forming step of forming a film so as to fill a concave portion dug by the etching step with an insulating film; and chemically and mechanically forming the insulating film formed in the insulating film forming step. A polishing step of polishing and flattening to expose the surface of the polishing stopper layer, a polishing stopper removing step of removing the polishing stopper layer exposed in the polishing step, and a polishing stopper layer being removed in the polishing stopper removing step. An oxidation step of oxidizing a surface of the semiconductor substrate to form an oxide layer, wherein an element isolation structure is formed with respect to the semiconductor substrate.
また本発明は、 基板上に絶縁膜パターンを形成する絶縁膜パターン形 成工程と、 該絶縁膜パターン形成工程で形成された絶縁膜パターンの隙 間に配線用の金属材料を埋め込むように成膜する成膜工程と、 該成膜ェ 程で成膜された金属材料に対して化学的、 且つ機械的な研磨を施して平 坦化する研磨工程とを有し、 前記絶縁膜パターンの隙間に配線パターン を形成することを特徴とする半導体装置の製造方法である。  Further, the present invention provides an insulating film pattern forming step of forming an insulating film pattern on a substrate, and forming a film so as to bury a metal material for wiring in a gap of the insulating film pattern formed in the insulating film pattern forming step. And a polishing step of performing chemical and mechanical polishing on the metal material formed in the film forming step to flatten the metal material, thereby forming a gap between the insulating film patterns. A method for manufacturing a semiconductor device, comprising forming a wiring pattern.
また本発明は、 基板上に形成された被研磨材に対して化学的、 且つ機 械的な研磨を施して平坦化する研磨工程と、 該研磨工程によって平坦化 された研磨面に発生する面荒れまたは欠陥についての発生状態を検査す る検査工程とを有し、 該検査工程で検査された研磨面における面荒れま たは欠陥についての発生状態を前記研磨工程にフィードバック して、 研 磨条件を制御して適正化をはかることを特徴とする半導体装置の製造方 法である。 Further, the present invention provides a polishing step of performing chemical and mechanical polishing on a material to be polished formed on a substrate to flatten the same, and a surface generated on the polished surface flattened by the polishing step. An inspection step of inspecting the state of occurrence of roughness or defect, wherein the state of occurrence of surface roughness or defect on the polished surface inspected in the inspection step is fed back to the polishing step, and polishing conditions Semiconductor device manufacturing method characterized by controlling Is the law.
また本発明は、 基板上に形成された被研磨材に対して化学的、 且つ機 械的な研磨を施して平坦化する研磨工程と、 該研磨工程によって平坦化 された研磨面を洗浄する洗浄工程と、 該洗浄工程によって洗浄された研 磨面に発生する面荒れまたは欠陥についての発生状態を検査する検査ェ 程とを有し、 該検査工程で検査された研磨面における面荒れまたは欠陥 についての発生状態を前記研磨工程にフイードバック して研磨条件を制 御して適正化をはかることを特徴とする半導体装置の製造方法である。  Further, the present invention provides a polishing step of performing a chemical and mechanical polishing on a material to be polished formed on a substrate to flatten the same, and a cleaning step of cleaning the polished surface flattened by the polishing step. And an inspection step for inspecting an occurrence state of surface roughness or a defect generated on the polished surface cleaned in the cleaning step. A method of manufacturing a semiconductor device, characterized in that the state of occurrence of the defects is fed back to the polishing step to control the polishing conditions so as to optimize the conditions.
また本発明は、 基板上に形成された被研磨材に対して化学的、 且つ機 械的な研磨を施して平坦化する研磨工程と、 該研磨工程によって平坦化 された研磨面を洗浄する洗浄工程と、 該洗浄工程の前と後とにおいて研 磨面に発生する面荒れまたは欠陥についての発生状態を検査する検査ェ 程とを有し、 該検査工程で検査された研磨面における面荒れまたは欠陥 についての発生状態を前記研磨工程にフィ一ドバック して研磨条件を制 御して適正化をはかることを特徴とする半導体装置の製造方法である。  Further, the present invention provides a polishing step of performing a chemical and mechanical polishing on a material to be polished formed on a substrate to flatten the same, and a cleaning step of cleaning the polished surface flattened by the polishing step. And an inspection step for inspecting the state of occurrence of surface roughness or defects occurring on the polished surface before and after the cleaning step. A method of manufacturing a semiconductor device, characterized in that the state of occurrence of defects is fed back to the polishing step to control the polishing conditions so as to optimize the conditions.
また本発明は、 基板上に形成された被研磨材に対して化学的、 且つ機 械的な研磨を施して平坦化する研磨工程と、 該研磨工程によって平坦化 された研磨面に発生する面荒れと区別して傷や異物についての発生状態 を検査する検査工程とを有し、 該検査工程で検査された研磨面における 傷や異物についての発生状態を前記研磨工程にフィ一ドバックして研磨 条件を制御して研磨面に発生する傷や異物を低減することを特徴とする 半導体装置の製造方法である。  Further, the present invention provides a polishing step of performing chemical and mechanical polishing on a material to be polished formed on a substrate to flatten the same, and a surface generated on the polished surface flattened by the polishing step. An inspection step of inspecting the state of occurrence of scratches and foreign matter in distinction from roughening, wherein the state of occurrence of scratches and foreign matter on the polished surface inspected in the inspection step is fed back to the above-mentioned polishing step to obtain polishing conditions. And reducing scratches and foreign matter generated on the polished surface.
また本発明は、 製造ラインの所定の製造工程において製造された複数 の半導体基板に亘つての （連続していなくてもよい。 即ちロッ ト単位で 抜き取られたものでも良い。 ） 半導体基板上の各半導体装置毎の欠陥の 発生状態を検査する欠陥検査工程と、 前記製造ラインによって製造され た複数の半導体基板に亘つての半導体基板から得られる各半導体装置に ついての電気的特性検査を行なって良品または不良品の判定を行なう電 気的特性検査工程と、 前記欠陥検査工程で検査された複数の半導体基板 上の各半導体装置毎の異物の発生状態と前記電気的特性検査工程で判定 された複数の半導体基板に亘つての各半導体装置の良品または不良品の 結果との相関関係に基いて、 不良の発生原因が欠陥によるものであるか 否かについて究明する不良発生原因究明工程とを有し、 該不良発生原因 究明工程で究明された不良発生原因について対策することを特徴とする 半導体装置の製造方法である。 Further, according to the present invention, a plurality of semiconductor substrates manufactured in a predetermined manufacturing process of a manufacturing line (they need not be continuous, that is, may be extracted in lots). A defect inspection step of inspecting a defect occurrence state of each semiconductor device; An electrical characteristic inspection step of performing an electrical characteristic inspection on each of the semiconductor devices obtained from the semiconductor substrates over the plurality of semiconductor substrates to determine a non-defective product or a defective product; The correlation between the state of generation of foreign matter for each semiconductor device on the plurality of semiconductor substrates and the result of a non-defective product or a defective product of each semiconductor device over the plurality of semiconductor substrates determined in the electrical characteristic inspection step. A defect occurrence investigation process for investigating whether or not the defect origination is caused by a defect, and taking measures against the defect occurrence investigation identified in the defect occurrence investigation process. 6 shows a method for manufacturing a semiconductor device.
また本発明は、 製造ラインの所定の製造工程において製造された複数 の半導体基板に亘つての （連続していなくてもよい。 即ちロッ ト単位で 抜き取られたものでも良い。 ） 半導体基板上の各半導体装置毎の欠陥の 発生状態を検査する欠陥検査工程と、 前記製造ラインによって製造され た複数の半導体基板に亘つての半導体基板から得られる各半導体装置に ついての電気的特性検査を行なって良品または不良品の判定を行なって 良品率または不良品率を算出する電気的特性検査工程と、 前記欠陥検査 工程で検査された複数の半導体基板上の各半導体装置毎の異物の発生状 態と前記電気的特性検査工程で算出された複数の半導体基板に亘つての 各半導体装置の良品率または不良品率との相関関係に基いて、 不良の発 生原因が欠陥によるものであるか否かについて究明する不良発生原因究 明工程とを有し、 該不良発生原因究明工程で究明された不良発生原因に ついて対策することを特徴とする半導体装置の製造方法である。  Further, according to the present invention, a plurality of semiconductor substrates manufactured in a predetermined manufacturing process of a manufacturing line (they need not be continuous, that is, may be extracted in lots). A defect inspection step of inspecting a state of occurrence of a defect in each semiconductor device, and an electrical characteristic inspection of each semiconductor device obtained from the semiconductor substrates over a plurality of semiconductor substrates manufactured by the manufacturing line. An electrical characteristic inspection step of calculating a non-defective or defective product to calculate a non-defective or defective rate; and a state of occurrence of foreign matter for each semiconductor device on the plurality of semiconductor substrates inspected in the defect inspection step. Based on the correlation between the non-defective product rate or the defective product rate of each semiconductor device over the plurality of semiconductor substrates calculated in the electrical characteristic inspection process, the cause of the defect is determined by the defect. A method for investigating a cause of failure to determine whether the defect is caused or not, and a countermeasure against the cause of failure identified in the step of investigating the cause of failure. .
また本発明は、 製造ラインの所定の製造工程において製造された複数 の半導体基板に亘つての （連続していなくてもよい。 即ちロッ ト単位で 抜き取られたものでも良い。 ） 半導体基板上の各半導体装置毎の欠陥の 発生状態を検査する欠陥検査工程と、 製造ラインによって製造された複 数の半導体基板に亘つての半導体基板から得られる各半導体装置につい ての電気的特性検査を行なって良品または不良品の判定を行なう電気的 特性検査工程と、 前記前記電気的特性検査工程で判定された複数の半導 体基板に亘つての各半導体装置の良品または不良品の結果と前記欠陥検 査工程で検査された複数の半導体基板上の各半導体装置毎の欠陥の発生 状態との相関関係に基いて、 前記欠陥検査工程における不良品となる欠 陥の発生状態を検査できているか否かを評価し、 この評価結果を前記欠 陥検査工程にフィ一ドバックする欠陥検査評価工程とを有することを特 徴とする半導体装置の製造方法である。 Further, according to the present invention, a plurality of semiconductor substrates manufactured in a predetermined manufacturing process of a manufacturing line (they need not be continuous, that is, may be extracted in lots). A defect inspection process for inspecting the state of occurrence of defects for each semiconductor device; An electrical characteristic inspection step of performing an electrical characteristic inspection on each of the semiconductor devices obtained from the semiconductor substrates over a number of semiconductor substrates to determine a non-defective product or a defective product; Between the result of the non-defective product or defective product of each semiconductor device over the plurality of semiconductor substrates obtained and the state of occurrence of defects for each semiconductor device on the plurality of semiconductor substrates inspected in the defect inspection process. A defect inspection step of evaluating whether or not the occurrence state of a defect that is a defective product in the defect inspection step has been inspected based on the relationship; and feeding back the evaluation result to the defect inspection step. This is a method for manufacturing a semiconductor device characterized by having
また本発明は、 製造ラインの所定の製造装置において製造された複数 の半導体基板に亘つての半導体基板上の各半導体装置毎の欠陥の発生状 態を検査する欠陥検査手段と、 前記製造ラインによって製造された複数 の半導体基板に亘つての半導体基板から得られる各半導体装置について の電気的特性検査を行なって良品または不良品の判定を行なう電気的特 性検査手段と、 前記欠陥検査手段で検査された複数の半導体基板上の各 半導体装置毎の異物の発生状態と前記電気的特性検査手段で判定された 複数の半導体基板に亘つての各半導体装置の良品または不良品の結果と の相関関係に基いて、 不良の発生原因が欠陥によるものであるか否かに ついて究明する不良発生原因究明手段とを有し、 該不良発生原因究明手 段で究明された不良発生原因を所定の製造装置にフィ一ドバックするこ とを特徴とする半導体装置の製造システムである。  Further, the present invention provides a defect inspection means for inspecting a state of occurrence of a defect of each semiconductor device on a semiconductor substrate over a plurality of semiconductor substrates produced by a predetermined production apparatus of a production line; An electrical characteristic inspection unit that performs an electrical characteristic inspection on each of the semiconductor devices obtained from the semiconductor substrates over a plurality of manufactured semiconductor substrates to determine a non-defective product or a defective product; and an inspection performed by the defect inspection unit. Between the occurrence state of foreign matter for each semiconductor device on the plurality of semiconductor substrates and the result of non-defective or defective product of each semiconductor device across the plurality of semiconductor substrates determined by the electrical characteristic inspection means. Means for determining whether the cause of the failure is due to a defect based on the defect, and the defect determined by the means for determining the cause of the failure. Raw cause a manufacturing system wherein a and Fi one Dobakku child to prescribed manufacturing apparatus.
また本発明は、 製造ラインの所定の製造装置において製造された複数 の半導体基板に亘つての半導体基板上の各半導体装置毎の欠陥の発生状 態を検査する欠陥検査手段と、 前記製造ラインによって製造された複数 の半導体基板に亘つての半導体基板から得られる各半導体装置について の電気的特性検査を行なって良品または不良品の判定を行なって良品率 または不良品率を算出する電気的特性検査手段と、 前記欠陥検査手段で 検査された複数の半導体基板上の各半導体装置毎の異物の発生状態と前 記電気的特性検査手段で算出された複数の半導体基板に亘つての各半導 体装置の良品率または不良品率との相関関係に基いて、 不良の発生原因 が欠陥によるものであるか否かについて究明する不良発生原因究明手段 とを有し、 該不良発生原因究明手段で究明された不良発生原因を所定の 製造装置にフィ一ドバックすることを特徴とする半導体装置の製造シス テムである。 Further, the present invention provides a defect inspection means for inspecting a state of occurrence of a defect of each semiconductor device on a semiconductor substrate over a plurality of semiconductor substrates produced by a predetermined production apparatus of a production line; The non-defective / defective product ratio is determined by conducting an electrical characteristic test on each semiconductor device obtained from the semiconductor substrate over a plurality of manufactured semiconductor substrates to determine a non-defective product or a defective product. Or, an electrical characteristic inspection unit for calculating a defective product ratio, a foreign matter generation state of each semiconductor device on the plurality of semiconductor substrates inspected by the defect inspection unit, and a plurality of electrical characteristics calculated by the electrical characteristic inspection unit. A failure occurrence cause finding means for determining whether or not a failure occurrence is due to a defect based on a correlation with a non-defective rate or a defective rate of each semiconductor device over the entire semiconductor substrate. A semiconductor device manufacturing system characterized in that the fault occurrence cause determined by the fault occurrence cause determining means is fed back to a predetermined manufacturing apparatus.
また本発明は、 製造ラインの所定の製造装置において製造された複数 の半導体基板に亘つての半導体基板上の各半導体装置毎の欠陥の発生状 態を検査する欠陥検査手段と、 製造ラインによって製造された複数の半 導体基板に亘つての半導体基板から得られる各半導体装置についての電 気的特性検査を行なって良品または不良品の判定を行なう電気的特性検 査手段と、 前記前記電気的特性検査手段で判定された複数の半導体基板 に亘つての各半導体装置の良品または不良品の結果と前記欠陥検査工程 で検査された複数の半導体基板上の各半導体装置毎の欠陥の発生状態と の相関関係に基いて、 前記欠陥検査手段における不良品となる欠陥の発 生状態を検査できているか否かを評価し、 この評価結果を前記欠陥検査 手段にフィ一ドバックする欠陥検査評価手段とを有することを特徴とす る半導体装置の製造システムである。 また本発明は、 任意の製造工程において基板上の複数の半導体装置 (半導体素子） 上に付着した異物等の欠陥を検出し、 該半導体装置の電 気的検査結果から得られる異物等の欠陥が検出された半導体装置の不良 率 （良品率） と異物等の欠陥が検出されなかった半導体装置の不良率 (良品率） とを比較し、 その比較結果を欠陥検査装置にフィードバック して検出感度を調整 （制御） することを特徴とする半導体装置の製造方 法である。 Further, the present invention provides a defect inspection means for inspecting a state of occurrence of a defect of each semiconductor device on a semiconductor substrate over a plurality of semiconductor substrates produced by a predetermined production device of a production line, Electrical characteristic inspection means for performing electrical characteristic inspection on each of the semiconductor devices obtained from the semiconductor substrates over the plurality of semiconductor substrates thus determined to determine a non-defective product or a defective product, and the electrical characteristics. The result of the non-defective or defective product of each semiconductor device over the plurality of semiconductor substrates determined by the inspection means and the state of occurrence of a defect for each semiconductor device on the plurality of semiconductor substrates inspected in the defect inspection step. Based on the correlation, it is evaluated whether the defect inspection means has inspected the state of occurrence of a defective defect, and the evaluation result is fed back to the defect inspection means. A manufacturing system for a semiconductor device you; and a defect inspection evaluating means for. Further, the present invention detects a defect such as a foreign matter attached to a plurality of semiconductor devices (semiconductor elements) on a substrate in an arbitrary manufacturing process, and detects a defect such as a foreign material obtained from an electrical inspection result of the semiconductor device. The detected defect rate (non-defective rate) of the semiconductor device is compared with the defective rate (non-defective rate) of the semiconductor device in which no defect such as a foreign substance is detected, and the comparison result is fed back to the defect inspection apparatus to increase the detection sensitivity. Adjusting (controlling) semiconductor device manufacturing method Is the law.
以上説明したように、 前記構成によれば、 平坦化すべき被研磨材の下 部に存在するパターンの影響を低減して高精度の残膜厚測定を可能にし、 高精度の化学的、 且つ機械的な研磨を実現して半導体装置 （半導体素子） を高歩留ま リで製造することができる。  As described above, according to the above configuration, it is possible to reduce the influence of the pattern present below the workpiece to be planarized, thereby enabling high-precision measurement of the remaining film thickness, and achieving high-precision chemical and mechanical Semiconductor devices (semiconductor elements) can be manufactured with high yield by realizing efficient polishing.
また前記構成によれば、 高スループッ トで、 且つ高精度の化学的、 且 つ機械的な研磨を実現して半導体装置 （半導体素子） を高スループッ ト で、 しかも高歩留ま りで製造することができる。  Further, according to the above configuration, a semiconductor device (semiconductor element) is manufactured with high throughput and high yield by realizing high-throughput, high-precision chemical and mechanical polishing. be able to.
また前記構成によれば、 平坦化すべき被研磨材に対して化学的、 且つ 機械的な研磨を施した際発生する傷や異物等の欠陥および面荒れを低減 して半導体装置 （半導体素子） を高歩留ま りで製造することができる。 また前記構成によれば、 化学的、 且つ機械的な研磨を用いて半導体基 板上に素子分離構造を欠陥を生じることなく形成することができる。  Further, according to the above configuration, a semiconductor device (semiconductor element) can be manufactured by reducing defects and surface roughness such as scratches and foreign substances generated when a material to be planarized is chemically and mechanically polished. It can be manufactured with high yield. Further, according to the above configuration, an element isolation structure can be formed on a semiconductor substrate by using chemical and mechanical polishing without causing defects.
また前記構成によれば、 化学的、 且つ機械的な研磨を用いて基板上に エッチングが難しい金属材料で配線パターンを欠陥を生じることなく形 成することができる。  Further, according to the above configuration, it is possible to form a wiring pattern on a substrate by using chemical and mechanical polishing with a metal material which is difficult to be etched without causing defects.
また前記構成によれば、 不良の発生原因が傷や異物等の欠陥によるも のであるか否かについて究明できるようにしてその対策を施すことがで きる。  Further, according to the above configuration, it is possible to determine whether or not the cause of the failure is due to a defect such as a scratch or a foreign substance, and to take measures against the defect.
また前記構成によれば、 欠陥検査工程またはその手段における欠陥検 査の信頼度を向上して高歩留ま リで半導体装置を製造することができる。 図面の簡単な説明  Further, according to the above configuration, it is possible to improve the reliability of the defect inspection in the defect inspection step or its means, and to manufacture a semiconductor device with a high yield. BRIEF DESCRIPTION OF THE FIGURES
第 1図は、 本発明に係る半導体装置 （半導体素子） を製造するための 半導体ウェハの断面構造を示す図であり、 第 2図は、 本発明に係る絶縁 膜を C M Pを施した際に発生した傷がその上に配線パターンを形成した 際短絡が生じることを説明するための断面図であり、 第 3図は、 本発明 に係るダマシンと称する手法によって基板上に配線パターンを形成する 方法を説明するための各工程を示す断面図であり、 第 4図は、 本発明に 係るダマシンと称する手法によって C M Pを施した際に発生した傷が配 線を切断する可能性があることを説明するための研磨面を示す斜視図で あり、 第 5図は、 本発明に係る半導体基板上に素子分離構造を形成する 方法を説明するための各工程を示す断面図であり、 第 6図は、 本発明に 係る半導体基板上に素子分離構造を形成するために C M Pを施した際に 発生した傷が半導体基板に入り込んで能動素子機能を失うことを説明す るための図であり、 第 7図は、 本発明に係る C M P工程における管理シ ステムを示す構成図であり、 第 8図は、 本発明に係る C M P装置と残膜 厚検出装置との概略構成を示す図であり、 第 9図は、 第 8図に示す C M P装置を示す斜視図であり、 第 1 0図は、 第 8図に示す残膜厚検出へッ ドの第 1の実施例を示す構成図であり、 第 1 1図は、 第 1 0図に示す検 出器によって検出される分光強度分布の信号波形を示した図であり、 第 1 2図は、 第 1 1図に示す信号波形の横軸えを 1 に変換した信号波 形を示す図であり、 第 I 3図は、 第 8図に示す残膜厚検出装置における 検出原理を示す図であり、 第 1 4図は、 第 1 0図に示す検出器によって 検出される分光強度分布の特徴的ピークの波長の変動から被研磨材 （被 平坦化膜） の残膜厚を測定することを説明するための図であり、 第 1 5 図は、 第 8図に示す残膜厚検出へッ ドの第 2の実施例を示す構成図であ り、 第 1 6図は、 第 8図に示す残膜厚検出へッ ドの第 3の実施例を示す 構成図であり、 第 1 7図は、 第 8図に示す残膜厚検出へッ ドの第 4の実 施例を示す構成図であり、 第 1 8図は、 第 1 7図に示す第 4の実施例に おいて検出される回折像の強度分布を示す図であり、 第 1 9図は、 第 1 7図に示す第 4の実施例において検出される回折像の強度分布に基づく 信号波形を示す図であり.、 第 2 0図は、 残膜厚測定のための他の実施例 を示す構成図であり、 第 2 1図は、 第 2 0図に示す検出器で検出される 干渉縞とその信号波形を示す図であり、 第 2 2図は、 残膜厚測定のため の更に他の実施例を示す構成図であり、 第 2 3図は、 本発明に係る研磨 面の傷や異物等の欠陥を検査する傷 ·異物等の欠陥検査装置の一実施例 を示す構成図であり、 第 2 4図は、 第 2 3図に示す装置において研磨面 に発生した面荒れと異物とによって得られる信号から弁別処理して検出 するための説明図であり、 第 2 5図は、 第 2 3図に示す装置において研 磨面に発生した傷と異物とを弁別処理することを説明するための図であ リ、 第 2 6図は、 第 2 3図に示す装置において研磨面に発生した傷、 異 物に対して複数方向から照明光を斜方照射する場合を模式的に示した図 であり、 第 2 7図は、 第 2 3図に示す装置において全方向から照明する 手法を示した構成図であり、 第 2 8図は、 本発明に係る液中において研 磨面の傷や異物等の欠陥を検査する傷 * 異物等の欠陥検査装置の一実施 例を示す概略構成図であり、 第 2 9図は、 第 2 8図に示す装置において 全反射が生じている際の異物あるいは傷の検出様子を示す図であり、 第 3 0図は、 第 2 9図に示す P偏光照明光と S偏光照明光との照射角度に よって表面での反射率を示す図であり、 第 3 1図は、 第 2 8図と異なる 実施例を示す概略構成図であり、 第 3 2図は、 本発明に係る半導体装置 の製造ラインについて管理する管理システムの一実施例を示す構成図で あり、 第 3 3図は、 所定の製造装置 （所定の製造工程） によって発生し た異物を検出する原理を説明するための図であり、 第 3 4図は、 所定の 製造工程において、 ウェハ単位における異物の存在するチップ数に対す る異物無チップの歩留まりと異物有チップの歩留まりとの複数のウェハ に亘つての分布の第 1の場合を示す図であり、 第 3 5図は、 所定の製造 工程において、 ウェハ単位における異物の存在するチップ数に対する異 物無チップの歩留ま りと異物有チップの歩留ま リとの複数のウェハに亘 つての分布の第 2の場合を示す図であり、 第 3 6図は、 所定の製造工程 において、 ウェハ単位における異物の存在するチップ数に対する異物無 チップの歩留まりと異物有チップの歩留ま リとの複数のウェハに亘つて の分布の第 3の場合を示す図であり、 第 3 7図は、 所定の製造工程にお いて、 ウェハ単位における異物の存在するチップ数と異物無チップの歩 留ま りと異物有チップの歩留ま りとの関係を口ッ ト毎に算出した結果を 示す図であり、 第 3 8図は、 所定の製造工程において、 チップ内異物数 とこのチップが良品および不良品となるチップ数との関係を示した図で あり、 第 3 9図は、 製造工程順に異物無チップの歩留ま りと異物有チッ プの歩留ま りとの関係を示した図である。 発明を実施するための最良の形態 FIG. 1 is a diagram showing a cross-sectional structure of a semiconductor wafer for manufacturing a semiconductor device (semiconductor element) according to the present invention, and FIG. 2 is a diagram which is generated when an insulating film according to the present invention is subjected to CMP. Scratch formed a wiring pattern on it FIG. 3 is a cross-sectional view illustrating each step for explaining a method of forming a wiring pattern on a substrate by a technique called damascene according to the present invention. FIG. 4 is a perspective view showing a polished surface for explaining that a scratch generated when performing CMP by a method called a damascene according to the present invention may cut the wiring; FIG. 5 is a sectional view showing each step for explaining a method for forming an element isolation structure on a semiconductor substrate according to the present invention. FIG. 6 is a sectional view showing an element isolation structure on a semiconductor substrate according to the present invention. FIG. 7 is a diagram for explaining that a scratch generated when performing CMP to form a semiconductor substrate enters a semiconductor substrate and loses the function of an active element. FIG. 7 is a diagram illustrating a management system in a CMP process according to the present invention. It is a configuration diagram showing a stem, FIG. 8 is a view showing a schematic configuration of a CMP apparatus and a residual film thickness detecting apparatus according to the present invention. FIG. 9 is a perspective view showing the CMP apparatus shown in FIG. FIG. 11 is a configuration diagram showing a first embodiment of a residual film thickness detection head shown in FIG. 8, and FIG. 11 is a diagram showing a spectral intensity distribution detected by the detector shown in FIG. FIG. 12 is a diagram showing a signal waveform, FIG. 12 is a diagram showing a signal waveform obtained by converting the horizontal axis of the signal waveform shown in FIG. 11 to 1, and FIG. FIG. 14 is a diagram showing the principle of detection in the residual film thickness detecting device shown in FIG. 14. FIG. 14 shows the material to be polished (from the variation in the wavelength of the characteristic peak of the spectral intensity distribution detected by the detector shown in FIG. 10). FIG. 15 is a diagram for explaining the measurement of the remaining film thickness of the flattening film). FIG. 15 is a configuration diagram showing a second embodiment of the remaining film thickness detection head shown in FIG. so FIG. 16 is a block diagram showing a third embodiment of the remaining film thickness detection head shown in FIG. 8, and FIG. 17 is a diagram showing the remaining film thickness detection head shown in FIG. FIG. 18 is a configuration diagram showing a fourth embodiment of the present invention. FIG. 18 is a diagram showing an intensity distribution of a diffraction image detected in the fourth embodiment shown in FIG. FIG. 19 is based on the intensity distribution of the diffraction image detected in the fourth embodiment shown in FIG. FIG. 20 is a diagram showing signal waveforms. FIG. 20 is a block diagram showing another embodiment for measuring the remaining film thickness. FIG. 21 is a diagram showing the signal detected by the detector shown in FIG. FIG. 22 is a diagram showing interference fringes and their signal waveforms. FIG. 22 is a configuration diagram showing still another embodiment for measuring a remaining film thickness. FIG. 23 is a diagram showing a polished surface according to the present invention. FIG. 24 is a block diagram showing an embodiment of a defect inspection apparatus for inspecting defects such as scratches and foreign substances on the polished surface in the apparatus shown in FIG. 23. FIG. 25 is an explanatory diagram for performing discrimination processing and detection from signals obtained by the apparatus and the foreign matter. FIG. 26 is a view for explaining scratches and foreign matter generated on the polished surface in the apparatus shown in FIG. 23 from a plurality of directions. FIG. 27 is a diagram schematically illustrating a case where bright light is obliquely irradiated. FIG. 27 is a configuration diagram illustrating a method of illuminating from all directions in the apparatus illustrated in FIG. 23, and FIG. FIG. 29 is a schematic configuration diagram showing one embodiment of a defect inspection apparatus for inspecting a defect such as a scratch or a foreign substance on a polished surface in a liquid according to the present invention. FIG. 30 is a diagram showing a state of detection of a foreign object or a scratch when total reflection occurs in the apparatus shown in FIG. 30. FIG. 30 shows an irradiation angle between the P-polarized illumination light and the S-polarized illumination light shown in FIG. FIG. 31 is a diagram showing reflectivity on the surface according to FIG. 31. FIG. 31 is a schematic configuration diagram showing an embodiment different from FIG. 28, and FIG. 32 is a manufacturing line of a semiconductor device according to the present invention. FIG. 33 is a configuration diagram illustrating an example of a management system that manages a device. FIG. 33 illustrates a predetermined manufacturing apparatus (a predetermined manufacturing process). FIG. 34 is a diagram for explaining the principle of detecting foreign matter generated by the method. It is a figure which shows the 1st case of distribution over several wafers with the yield of a chip, FIG. 35 shows the difference with respect to the number of the chip with the foreign substance in a wafer unit in a predetermined manufacturing process. It is a figure which shows the 2nd case of distribution over the several wafer of the yield of a chip without a thing, and the yield of a chip with a foreign substance, and FIG. 36 shows in a predetermined manufacturing process, FIG. 37 is a diagram showing a third case of the distribution over a plurality of wafers of the yield of a chip without foreign matter and the yield of a chip with foreign matter with respect to the number of chips having foreign matter in wafer units, and FIG. In the given manufacturing process, the results of calculating the relationship between the number of chips with foreign particles in each wafer, the yield of chips with no foreign particles, and the yield of chips with foreign particles in each unit are shown. FIG. 38 is a diagram showing the relationship between the number of foreign substances in a chip and the number of chips in which this chip is a good product and a defective product in a predetermined manufacturing process. FIG. 39 is a diagram showing the manufacturing process. In order, the yield of chips without foreign matter and the yield of chips with foreign matter FIG. BEST MODE FOR CARRYING OUT THE INVENTION
本発明をよリ詳細に説述するために、 添付の図面に従ってこれを説明 する。  The present invention will be described in more detail with reference to the accompanying drawings.
本発明に係る L S I等からなる半導体装置 （半導体素子） は、 基板上 に成膜、 露光、 エッチングを繰り返して製造される。 この際、 例えば、 第 1図に示す半導体装置 （半導体素子） 3 0 0は、 高密度化を実現する ためにより微細なパターンを用いて製造される。 更に、 より複雑な回路 を実現するために、 多層の配線パターン （第 1層配線パターン 3 0 5、 第 2層配線パターン 3 0 1、 第 3層配線パターン 3 0 2等） が用いる必 要が生じ、 そのため段差が生じ、 例えば第 2層の配線パターン 3 0 1上 に層間絶縁膜 3 0 3を介して第 3層配線パターン 3 0 2を形成しても、 層間絶縁層 3 0 3の表面がその下の配線パターン 3 0 1の段差の影響を 受けることになる。 そこで、 層間絶縁層 3 0 3の表面を鎖線で示すよう に平坦にするために、 研磨する必要がある。 なお、 3 0 4は第 3層配線 パターンを被覆する層間絶縁膜または保護膜である。 即ち、 第 3層配線 パターン 3 0 2の上に第 4層の配線パターンが形成される場合もある。 A semiconductor device (semiconductor element) comprising an LSI or the like according to the present invention is manufactured by repeatedly forming, exposing, and etching a substrate. At this time, for example, the semiconductor device (semiconductor element) 300 shown in FIG. 1 is manufactured using a finer pattern in order to realize a higher density. Furthermore, in order to realize a more complicated circuit, it is necessary to use a multilayer wiring pattern (first-layer wiring pattern 305, second-layer wiring pattern 301, third-layer wiring pattern 302, etc.). For example, even if the third-layer wiring pattern 302 is formed on the second-layer wiring pattern 301 via the interlayer insulating film 303, the surface of the interlayer insulating layer 303 is formed. Will be affected by the step of the wiring pattern 301 below it. Therefore, it is necessary to polish the surface of the interlayer insulating layer 303 in order to make it flat as indicated by a chain line. 304 is the third layer wiring This is an interlayer insulating film or a protective film that covers the pattern. That is, a fourth-layer wiring pattern may be formed on the third-layer wiring pattern 302 in some cases.
3 0 5は第 1層の配線パターンである。 3 0 6はゲート配線である。 3 2 7は絶縁材からなる素子分離構造を示す。 3 2 8は M O S構造等の能 動素子部を示す。 Reference numeral 2005 denotes a first-layer wiring pattern. Reference numeral 36 denotes a gate wiring. Reference numeral 327 denotes an element isolation structure made of an insulating material. Reference numeral 328 denotes an active element portion such as a MOS structure.
この他、 微細 L S I等の半導体装置 （半導体素子） を製造する際、 ダ マシンにおいて成膜された金属を平坦に研磨する必要もある。 即ち、 微 細 L S Iでは、 電気的配線層が、 微細になるため、 線の電気抵抗が大き くなリ、 L S I として機能しなくなってきている。 そこで、 配線の電気 抵抗を小さくする方法が検討されている。 その一つが、 配線抵抗の小さ い材料である銅、 銀、 金、 白金等の金属を用いる方法である。 ところが、 これらの金属は、 エッチング耐性が高すぎてレジス卜が無い等の理由に よリ、 エッチングにより配線パターンを形成するのが極めて難しい材料 である。 そこで、 エッチングにより配線パターンを形成するのが極めて 難しい材料である配線抵抗の小さい材料である銅、 銀、 金、 白金等の金 属材料からなる配線パターンを、 例えばダマシンという方法を用いて製 造することになる。 第 3図を用いてダマシンについて説明する。 この方 法は、 まず第 3図 （ a ) 〜 （ c ) に示すように、 配線パターンの絶縁膜 パターン （配線のネガパターン） 3 1 5を基板 3 1 1上に形成し、 次に 第 3図 （ d ) に示すようにその絶縁膜パターン 3 1 5の隙間に配線バタ —ン用の金属材料をスパッタやめつき等によって埋め込み成膜し、 その 後、 第 3図 （ e ) に示すように絶縁膜パターン 3 1 5の高さまで研磨す ることにより、 金属配線パターン 3 1 7を形成するものである。 このダ マシンの目的は、 エッチングの難しい材料 （配線抵抗の小さい材料であ る銅、 銀、 金、 白金等の金属材料） で配線パターンを作成することにあ る。 具体的には、 第 3図 （ a ) に示すように、 S i 0 2 系膜形成工程、 およびレジスト塗布工程によって、 基板 3 1 1上に絶縁膜 （ S i 0 2 系 膜） 3 1 2を形成し、 その上にレジスト 3 1 3を塗布する。 次に第 3図 ( b ) に示すように、 露光 ·現像工程によって、 絶縁膜 （ S i 0 2 系膜） 3 1 2上にレジス トパターン 3 1 4を形成する。 次に第 3図 （ c ) に示 すように、 エッチング工程、 およびレジスト除去工程によって、 絶縁膜 ( S i 0 2 系膜） 3 1 2に対してレジス トパターン 3 1 4の通りにエツ チングを施して絶縁膜パターン （ S i 0 2 系膜パターン） 3 1 5を形成 し、 その上のレジス トパターン 3 1 を除去する。 次に第 3図 （ d ) に 示すように金属材料成膜工程により、 絶縁膜パターン 3 1 5の隙間に配 線パターン用の金属材料 （配線抵抗の小さい材料である銅、 銀、 金、 白 金等の金属材料） 3 1 6を埋め込み成膜する。 次に第 3図 （ e ) に示す ように研磨工程により、 絶縁膜パターン 3 1 5の高さまで研磨すること により、 金属配線パターン 3 1 7を形成する。 このように、 基板 3 1 1 上に金属配線パターン 3 1 7を形成するために、 絶縁膜パターン 3 1 5 の隙間に埋め込み成膜された配線パターン用の金属材料 （配線抵抗の小 さい材料である銅、 銀、 金、 白金等の金属材料） 3 1 6を絶縁膜パター ン 3 1 5の高さまで研磨する必要が生じることになる。 In addition, when manufacturing semiconductor devices (semiconductor elements) such as micro LSIs, it is necessary to polish the metal deposited in a damascene flat. In other words, in a micro LSI, since the electric wiring layer becomes fine, the electric resistance of the line becomes large, and the LSI does not function as an LSI. Therefore, methods for reducing the electrical resistance of the wiring are being studied. One method is to use metals with low wiring resistance, such as copper, silver, gold, and platinum. However, these metals are extremely difficult to form a wiring pattern by etching, because the etching resistance is too high and there is no registry. Therefore, a wiring pattern made of a metal material such as copper, silver, gold, or platinum, which is a material having a low wiring resistance, which is a material that is extremely difficult to form a wiring pattern by etching, is manufactured using, for example, a damascene method. Will do. The damascene will be described with reference to FIG. In this method, first, as shown in FIGS. 3 (a) to 3 (c), an insulating film pattern (negative wiring pattern) 315 of the wiring pattern is formed on the substrate 311. Then, FIG. As shown in (d), a metal material for wiring pattern is buried in the gap between the insulating film patterns 315 by spattering, plating, etc., and then formed as shown in FIG. 3 (e). The metal wiring pattern 317 is formed by polishing to the height of the film pattern 315. The purpose of this damascene is to create wiring patterns from materials that are difficult to etch (metal materials such as copper, silver, gold, and platinum, which have low wiring resistance). Specifically, as shown in FIG. 3 (a), the SiO 2 -based film forming step, An insulating film (SiO 2 -based film) 312 is formed on the substrate 311 by a resist coating process, and a resist 313 is coated thereon. Next, as shown in FIG. 3 (b), by exposure and development step, a registry pattern 3 1 4 on the insulating film (S i 0 2 based film) 3 1 2. Next in FIG. 3 (c) to shows, the etching process, and the resist removal process, the insulating film (S i 0 2 based film) 3 1 2 Etsu quenching as described registry pattern 3 1 4 against alms insulating film pattern (S i 0 2 based film pattern) 3 1 5 is formed, to remove the registry pattern 3 1 thereon. Next, as shown in FIG. 3 (d), a metal material for the wiring pattern (copper, silver, gold, white, which is a material having a low wiring resistance) is formed in the gap between the insulating film patterns 315 by a metal material film forming step. A metal material such as gold) is embedded and formed into a film. Next, as shown in FIG. 3 (e), the metal wiring pattern 317 is formed by polishing to the height of the insulating film pattern 315 by a polishing step. In this way, in order to form the metal wiring pattern 3 17 on the substrate 3 1 1 1, a metal material for the wiring pattern (a material having a low wiring resistance) is formed by filling the gap between the insulating film patterns 3 1 5. There is a need to polish a certain metal material such as copper, silver, gold, and platinum) to the height of the insulating film pattern 315.
また微細 L S I等の半導体装置 （半導体素子） において、 M O S構造 のトランジスタ等の能動素子部 3 2 8を分離するための素子分離構造 3 2 7を製造するために、 S i 0 2 系の酸化絶縁膜を研磨して平坦化する 必要がある。 次に M O S構造のトランジスタ等の能動素子部 3 2 8を分 離するための素子分離構造 3 2 7を製造する方法について、 第 5図を用 いて説明する。 第 5図 （ a ) に示すように、 S i 3 N 4層形成工程、 およ びレジス卜塗布工程によリ、 窒素雰囲気中にして S i基板 3 2 1上に、 0 . 1 〜 0 . 2 m程度の薄膜層からなる耐熱衝撃性に優れた S i 3 N 4 層 3 2 2を形成し、 その上にレジス卜 3 2 3を塗布する。 次に、 第 5図 ( b ) に示すように、 露光 ·現像工程により、 レジストパターン 3 24 を形成する。 次に第 5図 （ c ) に示すように、 エッチング工程、 および レジスト除去工程によって、 S i 3 N 4膜 3 2 2および S i基板 3 2 1に 対してレジストパターン 3 24の通りにエッチングを施して素子分離用 の溝 3 2 5を形成し、 その上のレジストパターン 3 2 を除去する。 次 に第 5図 （ d ) に示すように S i 02 系のデポ膜成膜工程によリ、 素子 分離用の溝 3 2 5を埋め込むように CVD等により S i 02 系のデポ膜 3 26を成膜する。 次に第 5図 （ e ) に示すように、 研磨工程により、 成膜された S i 02 系のデポ膜 3 2 6を耐熱衝撃性に優れた S i 3N4層 3 2 2の高さまで研磨する。 このように耐熱衝撃性に優れた S i 3N4層 3 22があるため、 研磨して平坦化する際、 直接 S i基板 3 2 1に接触 することを防止することができる。 次に第 5図 （ f ) に示すように S i 3N4層除去工程により、 S i 3N4層 3 2 2を除去する。 このように S i 3N4層 3 2 2は、 研磨に耐え、 その後 S i基板 3 2 1から除去できるも のであれば良い。 次に第 5図 （ g ) に示す表面酸化工程により、 第 5図 ( f ) において露出した S i基板の表面を酸化させることによって、 素 子 3 2 8の間を S i 02 系の絶縁膜 3 2 7で分離することが可能となる c 即ち、 能動素子部 3 28の間を S i 02 系の絶縁膜で分離した素子分離 構造 3 27を得ることが出来る。 Also, in a semiconductor device (semiconductor element) such as a micro LSI, in order to manufacture an element isolation structure 327 for isolating an active element portion 328 such as a transistor having a MOS structure, a SiO 2 -based oxide insulation is required. The film needs to be polished and planarized. Next, a method of manufacturing an element isolation structure 327 for isolating an active element portion 328 such as a transistor having a MOS structure will be described with reference to FIG. As shown in FIG. 5 (a), the Si 3 N 4 layer forming step and the resist coating step are performed in a nitrogen atmosphere on the Si substrate 321, so that 0.1 to 0. . A Si 3 N 4 layer 3 22 with excellent thermal shock resistance consisting of a thin film layer of about 2 m is formed, and a resist 3 23 is applied thereon. Next, Fig. 5 As shown in (b), a resist pattern 324 is formed by an exposure and development process. Next, as shown in FIG. 5 (c), the Si 3 N 4 film 32 2 and the Si substrate 32 1 are etched according to the resist pattern 324 by an etching step and a resist removing step. Then, a groove 325 for element isolation is formed, and the resist pattern 32 thereon is removed. By the S i 0 2 type deposit film forming process as shown in FIG. 5 (d) to the next re, deposition film of S i 0 2 system by CVD or the like so as to fill the groove 3 2 5 for element isolation 3 26 is deposited. Next, as shown in FIG. 5 (e), the formed SiO 2 -based deposition film 326 was formed by a polishing process to increase the height of the Si 3 N 4 layer 32 2 having excellent thermal shock resistance. Polish to the end. Since the Si 3 N 4 layer 322 having excellent thermal shock resistance is provided, it is possible to prevent the Si 3 N 4 layer 322 from directly contacting the Si substrate 3 21 during polishing and flattening. The S i 3 N 4 layer removal step Subsequently, as shown in FIG. 5 (f), removing the S i 3 N 4 layer 3 2 2. As described above, the Si 3 N 4 layer 3 22 may be any material that can withstand polishing and can be removed from the Si substrate 3 21 thereafter. The next surface oxidation step shown in FIG. 5 (g), by oxidizing the surface of the S i substrate exposed in FIG. 5 (f), between the element 3 2 8 S i 0 2 based insulating The element c can be separated by the film 327, that is, an element isolation structure 327 in which the active element part 328 is separated by a SiO 2 -based insulating film can be obtained.
以上説明したように、 微細 L S I等の半導体装置 （半導体素子） を製 造するために、 化学的、 且つ機械的な研磨による平坦化プロセスが必要 となる。 そしてこの研磨による平坦化プロセスにおいて、 残膜厚を正確 に許容値内にすると共に、 研磨後洗浄した際、 その表面に異物や傷等が 存在しないようにすることが必要となる。  As described above, in order to manufacture a semiconductor device (semiconductor element) such as a fine LSI, a planarization process by chemical and mechanical polishing is required. In the planarization process by this polishing, it is necessary that the remaining film thickness be exactly within an allowable value, and that the surface after cleaning after polishing be free of foreign matter and scratches.
しかしながら、 被平坦化膜が層間絶縁膜 3 0 3の場合には、 光に対し て透明であり、 しかも下部に配線パターン 3 0 1が存在することになる < また研磨後洗浄するまでは、 研磨された半導体基板を液中に保管するこ とによって、 大気にさらすことなく研磨砥粒が研磨面に強固に付着する のを防止するためである。 この場合でも、 残膜厚の計測および異物や傷 等の検査を高精度に実現する必要がある。 However, when the film to be planarized is the interlayer insulating film 303, the film is transparent to light, and the wiring pattern 301 exists below. Further, after polishing, the polished semiconductor substrate is stored in a liquid until cleaning, thereby preventing the abrasive grains from firmly adhering to the polished surface without being exposed to the air. Even in this case, it is necessary to realize the measurement of the remaining film thickness and the inspection of foreign matter and scratches with high accuracy.
そこで、 本発明では、 この下地のパターンの影響を低減し、 高精度な 残膜厚計測を実現することにある。 具体的には、 予め良品とされるバタ ーンが存在するウェハで残膜厚の判っているパターンでの膜厚測定波形 を検出し、 その結果と測定対象からの検出結果を比較することにより、 上記下地パターンの影響は除去され精度の高い残膜厚さが計測される。  Therefore, the present invention is to reduce the influence of the underlying pattern and realize highly accurate remaining film thickness measurement. Specifically, by detecting the waveform of the film thickness measurement in a pattern in which the remaining film thickness is known in advance on a wafer on which a good pattern exists, and comparing the result with the detection result from the object to be measured. The influence of the underlayer pattern is removed, and the remaining film thickness with high accuracy is measured.
また、 精度の高い残膜厚計測は、 パターン及び平坦化膜が形成された 半導体基板 （ウェハ） 上に白色光を照射し、 該半導体基板 （ウェハ） 上 のパターンで、 回折分光された光強度分布を検出することで達成される c また、 このような化学的、 且つ機械的な研磨による平坦化法を、 第 1 図に示すように、 配線工程等に適用した場合において、 第 2図 （ a ) ， ( b ) に示すように、 層間絶縁膜 3 0 3からなる平坦化膜 （研磨面） 上 に大きな傷 3 0 7が存在すると、 第 3層配線パターン用の金属膜を成膜 するときに金属が傷部 3 0 7に入り込み、 エッチングによって第 3層配 線パターンを形成する際に多少オーバーエッチングされるが除去できな い可能性があり、 その結果傷部 3 0 7に入り込んだ金属によって第 3層 配線パターンの間を短絡させる原因となる。 なお、 第 2図 （ b ) は第 2 図 （ a ) の側面断面図である。 また層間絶縁膜 3 0 3からなる平坦化膜 上に異物が存在すると、 第 3層配線パターン用の金属膜を成膜するとき に異物の個所に成膜されないことになリ、 その結果第 3層配線パターン について断線の原因となる。 また層間絶縁膜 3 0 3からなる平坦化膜上 に電気的に導通の異物が存在すると、 第 3層配線パターンの間を短絡さ せる原因となる。 また、 化学的、 且つ機械的な研磨による平坦化法を、 第 3図 （ e ) に 示すように配線工程等に適用した場合においても、 第 4図に示すように S i 0 2 系膜 3 1 5と金属配線パターン 3 1 7とからなる平坦化膜 （研 磨面） 上に大きな傷 3 1 8が存在すると、 金属配線パターン 3 1 7の電 気抵抗が大となり、 長期的に局部的な発熱から断線の原因となり、 信頼 性を低下させることになる。 特にバイポーラ等のように金属配線パター ン 3 1 7に対して高電流を流す半導体素子の場合には、 この現象は顕著 となる。 また平坦化膜上に大きな傷 3 1 8が存在すると、 この傷部に汚 染が付着した場合、 この汚染をその後の洗浄工程では洗浄されにく く、 その後残つた汚染物が内部に拡散していつて半導体素子にダメージを与 える可能性を有することになる。 また S i 0 2 系膜 3 1 5と金属配線パ ターン 3 1 7とからなる平坦化膜上において、 上部配線パターンとのコ ンタク ト部に異物或いは傷が存在すると、 コンタク ト不良の原因となる また平坦化膜上に電気的に導通の異物が存在すると、 金属配線パターン 3 1 7の間を短絡させる原因となる。 In addition, highly accurate measurement of the remaining film thickness is performed by irradiating a semiconductor substrate (wafer) on which a pattern and a flattening film are formed with white light, and diffracting the light intensity of the pattern on the semiconductor substrate (wafer). c is accomplished by detecting the distribution in addition, such chemical, and the flattening method by mechanical polishing, as shown in FIG. 1, in the case of applying the wiring step or the like, Figure 2 ( As shown in a) and (b), if there is a large scratch 307 on the flattening film (polished surface) composed of the interlayer insulating film 303, a metal film for the third layer wiring pattern is formed. Occasionally, the metal enters the scratched part 307, and is slightly over-etched when forming the third-layer wiring pattern by etching, but may not be removed. Short circuit between the third layer wiring pattern with metal Cause that. FIG. 2 (b) is a side sectional view of FIG. 2 (a). Also, if foreign matter is present on the planarization film made of the interlayer insulating film 303, the metal film for the third-layer wiring pattern will not be formed at the place of the foreign matter when the metal film is formed. This causes disconnection of the layer wiring pattern. In addition, if there is an electrically conductive foreign substance on the flattening film made of the interlayer insulating film 303, it may cause a short circuit between the third-layer wiring patterns. Also, when the planarization method by chemical and mechanical polishing is applied to the wiring process as shown in FIG. 3 (e), the SiO 2 film 3 as shown in FIG. If a large scratch 318 is present on the flattening film (polished surface) consisting of 15 and the metal wiring pattern 317, the electrical resistance of the metal wiring pattern 317 will be large, and will be localized for a long time. Unnecessary heat may cause a disconnection, resulting in reduced reliability. In particular, this phenomenon becomes remarkable in the case of a semiconductor device such as a bipolar device which allows a high current to flow through the metal wiring pattern 317. Also, if there is a large scratch 3 18 on the flattening film, if the scratch is contaminated, the contamination is difficult to clean in the subsequent cleaning process, and the remaining contaminants diffuse inside. In some cases, the semiconductor device may be damaged. Further on the planarization film made of S i 0 2 based film 3 1 5 and the metal wiring patterns 3 1 7 for, when foreign matter or scratches present on the co Ntaku isolation portion of the upper wiring pattern, and causes of contactor bets poor In addition, the presence of electrically conductive foreign substances on the flattening film causes a short circuit between the metal wiring patterns 317.
また、 化学的、 且つ機械的な研磨による平坦化法を、 第 5図 （ e ) に 示すように、 トランジスタ等の能動素子部の成膜に用いた場合、 配線ェ 程等で問題になる傷や異物等の欠陥よリ小さな欠陥が問題になる。 具体 的には、 第 5図 （ e ) に示す研磨工程において、 能動素子 3 2 8を形成 する例えば S i 3 N 4層 3 2 2の厚さは、 0 . 0 5〜 0 . 3 ^ m程度と非 常に薄く形成されておリ、 この研磨された表面に、 第 6図 （ a ) ( b ) に示すようにこれ以上の異物や傷 3 2 9が存在すると、 容易に S i側に 入り込み上記能動素子 3 2 8は正常に動作しないことになる。 第 6図 ( a ) は、 第 5図 （ e ) に示す平坦化膜面 （研磨面） を示す平面図であ リ、 第 6図 （ b ) は第 6図 （ a ) の側面断面図である。 従って、 第 5図 ( e ) に示す平坦化膜面 （研磨面） 上に傷や異物等の欠陥が存在しない か否かについて検査してモニタすることによって、 初めて能動素子が正 常に動作する研磨面を得ることができる。 In addition, as shown in FIG. 5 (e), when a planarization method by chemical and mechanical polishing is used for forming a film of an active element portion such as a transistor, a problem that occurs in a wiring process or the like may occur. Small defects are more problematic than defects such as dust and foreign matter. Specifically, in the polishing step shown in FIG. 5 (e), for example, the thickness of the Si 3 N 4 layer 322 forming the active element 328 is 0.05 to 0.3 ^ m. It is formed to a very small extent, and if any more foreign matter or flaws 329 exist on the polished surface as shown in Fig. 6 (a) and (b), it can easily be placed on the Si side. The active element 3 288 does not operate normally. FIG. 6 (a) is a plan view showing the planarized film surface (polished surface) shown in FIG. 5 (e), and FIG. 6 (b) is a side sectional view of FIG. 6 (a). is there. Therefore, there is no defect such as a scratch or foreign matter on the planarized film surface (polished surface) shown in FIG. By inspecting and monitoring whether or not this is the case, it is possible to obtain a polished surface on which the active element operates normally for the first time.
以上説明したように、 化学的、 且つ機械的な研磨による平坦化面に傷 や異物等の欠陥が存在した場合には、 配線パターンの短絡や断線の原因 となり、 しかも半導体素子としての機能や信頼性を低下させることにな る。  As described above, if there is a defect such as a scratch or a foreign substance on the flattened surface due to chemical and mechanical polishing, it may cause a short circuit or disconnection of the wiring pattern, and furthermore, the function and reliability of the semiconductor element may be reduced. Performance will be reduced.
従って、 このような様々な形態での半導体基板 （ウェハ） に傷や異物 等の欠陥が存在するか否かについて、 十分な感度で検査することによつ て、 半導体素子としての機能を得て、 高信頼性を有する半導体素子を実 現することができる。 即ち、 傷や異物等の欠陥が存在するか否かについ て検査する被検査対象が研磨面であるため、 表面の研磨による面あれか らの検出信号成分を十分小さくすることによって研磨による面あれの影 響を低減して、 傷や異物等の欠陥が存在するか否かについて高感度 （高 分解能） で検査することが可能となる。 より具体的には、 検出時の分解 能 （解像度） を向上した光学系を用いることで、 研磨による面あれの影 響を低減して、 傷や異物等の欠陥が存在するか否かについて高感度 （高 分解能） で検査することが可能となる。  Therefore, by inspecting the semiconductor substrate (wafer) in such various forms for defects such as scratches and foreign substances with sufficient sensitivity, the function as a semiconductor element can be obtained. Thus, a semiconductor device having high reliability can be realized. That is, since the object to be inspected for the presence of a defect such as a scratch or a foreign matter is a polished surface, the detection signal component from the surface polished by the surface polishing is made sufficiently small so that the surface polished by the polishing is reduced. It is possible to inspect with high sensitivity (high resolution) whether or not there is a defect such as a scratch or a foreign substance by reducing the influence of the defect. More specifically, by using an optical system with improved resolution (resolution) at the time of detection, the effects of surface roughness due to polishing can be reduced, and the presence or absence of defects such as scratches and foreign matter can be improved. Inspection with high sensitivity (high resolution) becomes possible.
次に、 本発明に係る C M P ( Chemi cal Mechani cal Po l i shing :化学 的、 且つ機械的な研磨） 装置 2 0 0、 残膜厚検出へッ ド 2 1 0、 傷 ·異 物検査装置 2 2 0、 洗浄装置 2 3 0、 および傷 ·異物検査装置 2 4 0を 備えた全体システムについて説明する。 第 7図はこの全体システムの概 略構成を示した図である。 C M P装置 2 0 0は、 研磨布が張り付けられ たプラテンと呼ばれる研磨定盤 2 0 1 と、 研磨定盤 2 0 1の研磨布上に スラリーと呼ばれる研磨砥粒の水けん濁液を供給する供給手段 2 0 3と- 被研磨材である半導体ウェハ 1 を支持し、 スラリーと呼ばれる研磨砥粒 の水けん濁液を流しながら研磨定盤 2 0 1 との間で公転と自転との回転 によって半導体ウェハ 1の表面を研磨する研磨へッ ド 2 0 2と、 上記供 給手段 2 0 3によって供給される研磨砥粒の水けん濁液の種類 （例えば 異なった研磨砥粒からなる。 ） を変えたり、 研磨ヘッ ド 2 0 0の公転お よび自転を行なわせる回転駆動装置の駆動回転速度、 研磨圧力付与手段 によって付与される研磨圧力、 および研磨時間等を制御する制御装置 2 0 とから構成される。 Next, a CMP (Chemical Mechanical Polishing) apparatus 200 according to the present invention, a head 210 for detecting remaining film thickness, a scratch / foreign matter inspection apparatus 22 0, a cleaning device 230, and a scratch / foreign matter inspection device 240 will be described. FIG. 7 is a diagram showing a schematic configuration of the entire system. The CMP device 200 supplies a polishing platen 210 called a platen on which a polishing cloth is adhered, and a supply of a suspension of polishing abrasive grains called a slurry onto the polishing cloth of the polishing platen 201. Means 203-The semiconductor wafer 1 which is the material to be polished is supported, and revolving and rotating between the polishing platen 201 and the polishing platen 201 while flowing a suspension of abrasive grains called slurry. A polishing head 202 for polishing the surface of the semiconductor wafer 1 by means of the above, and a type of a water suspension of the polishing abrasive supplied by the supply means 203 (for example, composed of different abrasives). And a control device 20 for controlling the driving rotation speed of a rotary drive device for rotating the polishing head 200 and revolving and rotating, the polishing pressure applied by the polishing pressure applying means, and the polishing time. Be composed.
制御装置 2 0 4は、 C M P装置 2 0 0に投入される被研磨材である半 導体ウェハ 1の種類に応じて研磨条件 （研磨砥粒の水けん濁液の種類、 研磨へッ ド 2 0 0の公転および自転の回転速度、 研磨圧力および研磨時 間等） が設定される。 そして、 制御装置 2 0 4によって C M P装置 2 0 0に投入される被研磨材である半導体ウェハ 1の種類に応じて予め求め られた大まかな研磨速度から算出される研磨時間だけ （やや少な目の時 間だけ） C M P装置によつて研磨された後、 研磨へッ ド 2 0 2は 2 0 2 ' の位置まで上昇し、 半導体ウェハ 1 に対して純水がかけられて半導体ゥ ェハ 1の研磨面が洗浄される。 この状態において残膜厚検出ヘッ ド 2 1 1は、 半導体ウェハ 1の研磨面に対向するように設置される。 そして、 半導体ウェハ 1の表面の被研磨膜の残膜厚を測定する残膜厚検出装置 2 1 0は、 上記残膜厚検出へッ ド 2 1 1 と残膜厚検出へッ ド 2 1 1で検出 される信号を処理するマイコン等で構成される処理手段 2 1 2とで構成 される。 残膜厚検出装置 2 1 0の処理手段 2 1 2で算出された半導体ゥ ェハ 1の表面の被研磨膜の残膜厚データが、 C M P装置の制御装置 2 0 4にフィードバックされ、 制御装置 2 0 4はこのフィードバックされた 残膜厚データに基いて、 例えば高速研磨から低速高精細研磨に移行制御 すると共に研磨時間を制御して所望の膜厚で平坦化を実行する。 即ち、 残膜厚検出装置 2 1 0によって半導体ウェハ 1の表面の被研磨膜の残膜 厚をモニタすることができるので、 スループッ トの早い高速研磨手法と, 研磨終了間際で、 スループッ トは遅いが、 傷や異物等の欠陥の発生の殆 ど少ない低速高精細研磨手法とによる多段階研磨を実行することが可能 となり、 研磨のスループッ トを向上させると共に、 傷や異物等の欠陥の 発生をなくすことが可能となる。 The control device 204 controls the polishing conditions (type of water suspension of polishing abrasive grains, polishing head 200) according to the type of semiconductor wafer 1 that is the material to be polished to be input into the CMP device 200. 0 rotation and rotation speed, polishing pressure, polishing time, etc.) are set. Then, only the polishing time calculated from the rough polishing speed previously determined according to the type of the semiconductor wafer 1 to be polished into the CMP device 200 by the control device 204 (when the time is slightly shorter). After polishing by the CMP device, the polishing head 202 rises to the position of 202 'and pure water is applied to the semiconductor wafer 1 to polish the semiconductor wafer 1 The surface is cleaned. In this state, the remaining film thickness detection head 211 is installed so as to face the polished surface of the semiconductor wafer 1. The remaining film thickness detecting device 210 for measuring the remaining film thickness of the film to be polished on the surface of the semiconductor wafer 1 includes the remaining film thickness detecting head 211 and the remaining film thickness detecting head 2 1 1 And a processing means 2 12 composed of a microcomputer or the like that processes the signal detected by the microcomputer. The remaining film thickness data of the film to be polished on the surface of the semiconductor wafer 1 calculated by the processing means 2 12 of the remaining film thickness detecting device 210 is fed back to the control device 204 of the CMP device, and the control device Based on the remaining film thickness data fed back, 204 controls the transition from, for example, high-speed polishing to low-speed, high-definition polishing, controls the polishing time, and executes planarization with a desired film thickness. That is, since the remaining film thickness of the film to be polished on the surface of the semiconductor wafer 1 can be monitored by the remaining film thickness detecting device 210, a high-throughput polishing method with a high throughput, Immediately before the end of polishing, it is possible to perform multi-stage polishing using a low-speed and high-definition polishing method that has a low throughput but has almost no defects such as scratches and foreign matter, and improves the polishing throughput. Defects such as scratches and foreign substances can be eliminated.
以上によリ半導体ウェハ 1の表面に対して研磨が終了されると、 半導 体ウェハ 1は、 研磨へッ ド 2 0 2から取り外され、 洗浄装置 2 3 0にお いて洗浄されるまで、 液中に保管されることになる。 その理由は、 大気 中に保管した場合、 水と大気中の酸素との化学反応等によリ半導体ゥェ ハ 1に付着した研磨砥粒がウェハ表面に強固に付着してしまい、 その後 の洗浄ではとれなくなつてしまうからである。 また半導体ウェハの研磨 が終了した研磨面における傷や異物等の欠陥が存在するか否かについて の検査においては、 研磨による表面の微細な荒れから区別して検査をす る必要がある。 また研磨面が層間絶縁膜のように下地に配線パターンが 存在する場合には、 下地の配線パターンからの光の反射が得られないよ うにする必要がある。 そこで、 傷 ·異物検査装置 2 2 0により、 研磨が 終了した半導体ウェハ 1 を液中に保管した状態で、 研磨面における傷や 異物等の欠陥が存在するか否かについて光学的に検査すれば、 研磨砥粒 がウェハ表面に強固に付着してしまうことを防止することができると共 に、 下地の配線パターンからの光の反射が得られないような研磨面での 全反射条件を容易に得ることができる。 ところで、 傷 ·異物検査装置 2 2 0は、 研磨された研磨面を有する半導体ウェハ 1 を浸す液を溜め、 こ の半導体ウェハ 1の研磨面に全反射条件で光を照射するための照明用窓 1 8および研磨面からの散乱反射光を検出する検出用窓 3 5を備えた槽 3と、 検出用窓 3 5を通して得られる研磨面からの散乱反射光を集光す る対物レンズ 3 1 と、 対物レンズ 3 1で集光された光を受光して信号に 変換するリニアイメージセンサからなる検出器 3 4と、 該検出器 3 4で 検出される画素信号を処理して研磨面における傷や異物等の欠陥を検出 するマイコン等で構成される処理手段 2 2 1 とで構成される。 しかしな がら、 研磨面は洗浄する前の状態であり、 研磨砥粒が付着している可能 性が高いので、 傷，異物検査装置 2 2 0は、 研磨面に存在する傷や異物 等の欠陥を研磨砥粒と弁別して検査することが必要となる。 従って、 必 ずしも、 槽 3において液に浸した状態で半導体ウェハ 1の研磨面に存在 する傷や異物等の欠陥を検査する必要はない。 When the polishing of the surface of the semiconductor wafer 1 is completed as described above, the semiconductor wafer 1 is removed from the polishing head 202, and is cleaned until it is cleaned by the cleaning device 230. It will be stored in the liquid. The reason is that when stored in air, the abrasive grains that have adhered to the semiconductor wafer 1 due to the chemical reaction between water and oxygen in the air, etc., will adhere strongly to the wafer surface, and subsequent cleaning This is because it will no longer be possible. In addition, when inspecting whether or not there is a defect such as a scratch or a foreign substance on the polished surface after the polishing of the semiconductor wafer, it is necessary to perform the inspection while distinguishing from the fine roughness of the surface due to polishing. Further, when a wiring pattern exists on the base such as an interlayer insulating film having a polished surface, it is necessary to prevent reflection of light from the wiring pattern on the base. Therefore, if the polished semiconductor wafer 1 is stored in a liquid and optically inspected for defects such as scratches and foreign matter on the polished surface by using a scratch / foreign matter inspection device 220, In addition, it is possible to prevent the abrasive grains from firmly adhering to the wafer surface, and to easily set the conditions for total reflection on the polished surface so that light from the underlying wiring pattern cannot be obtained. Obtainable. Meanwhile, the scratch / foreign matter inspection device 220 stores an immersion liquid for the semiconductor wafer 1 having a polished polished surface, and an illumination window for irradiating the polished surface of the semiconductor wafer 1 with light under the condition of total reflection. 1 and a tank 3 having a detection window 35 for detecting scattered reflected light from the polished surface, and an objective lens 31 for condensing scattered reflected light from the polished surface obtained through the detection window 35. A detector 34 composed of a linear image sensor that receives the light condensed by the objective lens 31 and converts it into a signal; It comprises processing means 221 composed of a microcomputer or the like for processing a detected pixel signal to detect a defect such as a scratch or a foreign matter on the polished surface. However, the polished surface is in a state before being cleaned, and there is a high possibility that the abrasive grains are attached. Therefore, the scratch / foreign matter inspection device 220 is capable of detecting defects such as scratches and foreign matter present on the polished surface. It is necessary to discriminate and inspect abrasive grains. Therefore, it is not necessary to inspect the polished surface of the semiconductor wafer 1 for defects such as scratches and foreign substances while being immersed in the liquid in the tank 3.
洗浄装置 2 3 0は、 C M P装置 2 0 0で研磨された半導体ウェハ 1 を 洗浄して、 研磨面に付着した研磨砥粒等も含めて取り除くものである。 傷 ·異物検査装置 2 4 0は、 洗浄装置 2 3 0によって洗浄された半導 体ウェハ 1の研磨面に存在する傷や異物等の欠陥を検査するものである < この傷 ·異物検査装置 2 4 0は、 洗浄装置 2 3 0によって洗浄された半 導体ウェハ 1の研磨面についての最終検査であるため、 例えば、 残膜厚 検出へッ ド 2 1 0と同様な光学系を設置して研磨面の膜厚を測定するよ うに構成してもよい。 そして傷 ·異物検査装置 2 4 0は、 洗浄装置 2 3 0によって洗浄された半導体ウェハ 1 を載置するステージ系 7 0と、 半 導体ウェハの研磨面に光を照射する照明系 1 0と、 研磨面の傷や異物か らの散乱光を検出する検出器 3 を有する検出光学系 3 0と、 該検出器 3 4から得られる画素信号を処理して研磨面における傷や異物等の欠陥 を検出するマイコン等で構成される処理手段 2 1とで構成される。 コンピュータ 2 5 0は、 半導体ウェハ 1の研磨面について生産管理を 行なうもので、 C M P装置 2 0 0の制御装置 2 0 4、 残膜厚検出装置 2 1 〇の処理手段 2 1 2、 傷 ·異物検査装置 2 2 0の処理手段 2 2 1、 お よび傷 ·異物検査装置 2 4 0の処理手段 2 4 1 とネッ トワークを介して 接続される。  The cleaning device 230 cleans the semiconductor wafer 1 polished by the CMP device 200 and removes the abrasive wafer and the like attached to the polished surface. The scratch / foreign matter inspection device 240 inspects defects such as scratches and foreign matter present on the polished surface of the semiconductor wafer 1 cleaned by the cleaning device 230 < Reference numeral 40 denotes the final inspection of the polished surface of the semiconductor wafer 1 cleaned by the cleaning device 230, so that, for example, the same optical system as the remaining film thickness detection head 210 is installed and polished. You may comprise so that the film thickness of a surface may be measured. The scratch / foreign matter inspection device 240 includes a stage system 70 on which the semiconductor wafer 1 cleaned by the cleaning device 230 is placed, and an illumination system 10 for irradiating the polished surface of the semiconductor wafer with light. A detection optical system 30 having a detector 3 for detecting scattered light from scratches and foreign matter on the polished surface; and processing of pixel signals obtained from the detector 34 to detect defects such as scratches and foreign matter on the polished surface. It comprises processing means 21 comprising a microcomputer or the like for detecting. The computer 250 controls production of the polished surface of the semiconductor wafer 1. The control device 204 of the CMP device 200, the processing means 2 1 2 of the remaining film thickness detecting device 21, scratches and foreign matter The processing means 222 of the inspection device 220 and the processing means 241 of the scratch / foreign matter inspection device 240 are connected via a network.
そして、 コンピュータ 2 5 0は、 C M P装置 2 0 0の制御装置 2 0 4 から C M P装置 2 0 0に投入される被研磨材である半導体ウェハ 1の種 類に応じて設定された研磨条件 （研磨砥粒の水けん濁液の種類、 研磨へ ッ ド 2 0 0の公転および自転の回転速度、 研磨圧力および研磨時間等） に関するデータを得ることができ、 残膜厚検出装置 2 1 0の処理手段 2 1 2から半導体ウェハ 1の種類に応じた残膜厚測定結果を得ることがで き、 傷 ·異物検査装置 2 2 0の処理手段 2 2 1から洗浄前の研磨面に存 在する傷や異物等の欠陥の情報 （該欠陥が発生した位置情報も含む） を 得ることができ、 傷 ·異物検査装置 2 4 0の処理手段 2 1から洗浄後 の最終の研磨面に存在する傷や異物等の欠陥の情報 （該欠陥が発生した 位置情報も含む） や研磨面の膜厚データを得ることができ、 これら得ら れた情報やデータについて半導体ウェハ 1の単位もしくはロッ トの単位 で記憶装置 2 5 1 に格納される。 特に半導体ウェハ 1の研磨面に発生す る傷や異物については、 半導体ウェハ 1の単位で変動することが十分に ありえるので、 上記得られた情報やデータについて半導体ウェハ 1の単 位で記憶装置 2 5 1 に格納することが望ましい。 And, the computer 250 is a control device 204 of the CMP device 200. Conditions set in accordance with the type of the semiconductor wafer 1 to be polished, which is to be polished into the CMP apparatus 200 (the type of the aqueous suspension of the abrasive grains, the revolution of the polishing head 200). And rotation speed of rotation, polishing pressure, polishing time, etc.), and the residual film thickness measurement result corresponding to the type of the semiconductor wafer 1 can be obtained from the processing means 2 12 of the residual film thickness detecting device 210. From the processing means 222 of the scratch / foreign matter inspection device 220, information on defects such as scratches and foreign materials present on the polished surface before cleaning (including information on the position where the defect has occurred) can be obtained. From the processing means 21 of the scratch / foreign matter inspection device 240, information on defects (including the position where the defect occurred) such as scratches and foreign matter present on the final polished surface after cleaning and polishing can be obtained. Thickness data on the surface can be obtained. It is stored in the storage device 2 5 1 1 units or units of lots. In particular, scratches and foreign matter generated on the polished surface of the semiconductor wafer 1 can sufficiently vary in units of the semiconductor wafer 1, and thus the obtained information and data are stored in the storage device 2 in units of the semiconductor wafer 1. It is desirable to store in 5 1.
なお、 2 5 2はディスプレイ等から構成される表示手段である。 2 5 3はキーポードゃ記録媒体等で構成された入力手段である。 2 5 4は印 刷機や記録媒体等で構成された出力手段である。 上記構成により、 コン ピュータ 2 5 0は、 半導体ウェハ 1の単位で、 傷 ·異物検査装置 2 4 0 で検査された最終の研磨面に存在する傷や異物等の欠陥の情報とその時 の研磨条件 （研磨砥粒の水けん濁液の種類、 研磨へッ ド 2 0 0の公転お よび自転の回転速度、 研磨圧力および研磨時間等） に関するデータを対 応させて記憶装置 2 5 1から読みだして表示手段 2 5 2に表示すること ができる。 その結果、 管理者は、 表示手段 2 5 2に表示された情報を見 ながら、 欠陥の発生原因である研磨条件を推定し、 その推定された発生 原因である研磨条件を入力手段 2 5 3を用いて入力することによって、 コンピュータ 2 5 0は、 過去の欠陥情報と研磨条件との対応関係から推 定された研磨条件が正しいか否かについて分析をし、 正しいと判断され たときにはその研磨条件を制御装置 2 0 4にフィードバックする。 する と制御装置 2 0 4は、 C M P装置 2 0 0に対して修正された研磨条件に 変更すべく指令を出して修正された研磨条件で投入された半導体ウェハ 1 に対して研磨が実行される。 これによつて、 多くの欠陥不良をだすこ と無く、 研磨を実行することができる。 Incidentally, reference numeral 255 denotes a display means composed of a display or the like. Reference numeral 253 denotes an input means composed of a keyboard, a recording medium, and the like. Reference numeral 254 denotes an output unit composed of a printing machine, a recording medium, and the like. With the above configuration, the computer 250 can provide information on the defect such as a scratch or a foreign substance present on the final polished surface inspected by the scratch / foreign substance inspection device 240 and the polishing conditions at that time in units of the semiconductor wafer 1. Data related to the type of suspension of polishing abrasive grains, the rotational speed of the polishing head 200 and its rotation, the polishing pressure and the polishing time are read out from the storage device 25 1 in association with each other. Can be displayed on the display means 25 2. As a result, the administrator estimates the polishing condition, which is the cause of the defect, while viewing the information displayed on the display means 25, and inputs the polishing condition, the estimated cause, to the input means 25, 53. By entering using The computer 250 analyzes whether or not the polishing condition estimated from the correspondence between the past defect information and the polishing condition is correct, and when it is determined to be correct, the polishing condition is transmitted to the controller 204. give feedback. Then, the control device 204 issues a command to change the polishing condition to the CMP device 200 so as to change the polishing condition, and the polishing is performed on the semiconductor wafer 1 which is input under the corrected polishing condition. . As a result, polishing can be performed without causing many defect defects.
なお、 上記の説明では、 管理者が表示手段 2 5 2に表示された情報を 見ながら、 欠陥の発生原因である研磨条件を推定したが、 この推定ァリ ゴリズムをコンピュータ 2 5 0内のメモリに予め入力して記憶しておけ ば、 コンピュータ 2 5 0はこの推定アルゴリズムに基いて欠陥の発生原 因である研磨条件を推定し、 この推定された研磨条件が適切であるか否 かについても過去の経歴情報に基いて判断することができる。  In the above description, the administrator estimates the polishing conditions, which are the causes of the defects, while looking at the information displayed on the display means 250, but the estimated algorithm is stored in the memory in the computer 250. If this is input and stored in advance, the computer 250 estimates the polishing condition that is the cause of the defect based on the estimation algorithm, and determines whether the estimated polishing condition is appropriate. It can be determined based on past career information.
次に、 C M P装置 2 0 0と残膜厚検出装置 2 1 0とについて、 第 8図 〜第 2 2図を用いて具体的に説明する。  Next, the CMP device 200 and the remaining film thickness detecting device 210 will be specifically described with reference to FIGS. 8 to 22.
第 8図は C M P装置 2 0 0と残膜厚検出装置 2 1 0とについて示した 正面図、 第 9図は C M P装置 2 0 0について示した斜視図である。 C M P ( Chemi cal Mechani cal Po l i shing ) 装置 2 0 0は、 研磨布 2 0 4が 張り付けられたプラテンと呼ばれる研磨定盤 2 0 1 と、 表面にスラリ一 と呼ばれる研磨砥粒の水けん濁液を流す研磨砥粒の水けん濁液供給手段 2 0 3と、 被研磨材である半導体ウェハを支持し、 公転と自転とが行な われるように 1 2 0度間隔で設置され、 研磨圧力が付与される 3つの研 磨へッ ド 2 0 2とで構成される。 研磨定盤 2 0 1の表面に張り付けられ た研磨布 2 0 4の表面にスラリーと呼ばれる研磨砥粒の水けん濁液を流 しながら、 各研磨ヘッ ド 2 0 2により各半導体ウェハ 1 を支えながら研 磨圧力を付与し、 研磨定盤 2 0 1の公転と研磨へッ ド 2 0 2の自転とに よる回転をさせることによって半導体ウェハ 1の表面に対して多段階の 研磨が施されることになる。 制御装置 2 0 4からの制御信号に基いて、 最初は高速研磨が施され、 研磨終了に近ずいたとき低速の高精細研磨に 切り換えられて移行することになる。 これにより、 高スループッ トで研 磨を行なうことができると共に研磨終了時において表面に傷や異物等の 欠陥の発生を極力なくすことができる。 FIG. 8 is a front view showing the CMP apparatus 200 and the remaining film thickness detecting apparatus 210, and FIG. 9 is a perspective view showing the CMP apparatus 200. A CMP (chemical mechanical polishing) device 200 is composed of a polishing platen 210, called a platen, to which a polishing pad 204 is attached, and a suspension of abrasive grains called a slurry on the surface. A water suspension liquid supply means 203 for polishing abrasive grains and a semiconductor wafer as a material to be polished are supported, and are disposed at 120 ° intervals so that revolving and rotation are performed. And three polishing heads 202. Each semiconductor head 1 is supported by each polishing head 202 while a suspension of polishing abrasive grains, called a slurry, is flown onto the surface of the polishing cloth 204 attached to the surface of the polishing platen 201. While applying polishing pressure, the polishing platen 201 revolves and the polishing head 202 rotates. By performing such rotation, the surface of the semiconductor wafer 1 is polished in multiple stages. Based on the control signal from the control device 204, high-speed polishing is first performed, and when the polishing is approaching the end, the polishing is switched to low-speed high-definition polishing and the process is shifted. As a result, polishing can be performed at a high throughput, and the occurrence of defects such as scratches and foreign substances on the surface at the end of polishing can be minimized.
ところで、 高速研磨においては、 研磨砥粒として大きいもの （具体的 には、 例えば 5 0 n mより大きいもの） を用い、 研磨の際研磨へッ ド 2 0 2を高速回転 （具体的には、 例えば 6 0 r p瓜より大きな回転速さ） させ、 被研磨材と研磨布 （研磨パッ ド） との間の圧力を大きく （具体的 には、 例えば 1 0 0 g / c m 2 より大きな圧力） する。 低速研磨におい ては、 研磨砥粒として小さいもの （具体的には、 例えば 5 0 n mより小 さいもの） を用い、 研磨の際研磨へッ ド 2 0 2を低速回転 （具体的には、 例えば 6 0 r p mより小さな回転速さ） させ、 被研磨材と研磨布 （研磨 パッ ド） との間の圧力を小さく （具体的には、 例えば 1 0 0 g Z c m 2 より小さな圧力） する。 By the way, in high-speed polishing, large abrasive grains (specifically, for example, those larger than 50 nm) are used, and the polishing head 202 is rotated at high speed during polishing (specifically, for example, The rotation speed is greater than 60 rpm, and the pressure between the material to be polished and the polishing pad (polishing pad) is increased (specifically, for example, a pressure greater than 100 g / cm 2 ). In low-speed polishing, small abrasive grains (specifically, for example, smaller than 50 nm) are used, and the polishing head 202 is rotated at a low speed during polishing (specifically, for example, (Rotation speed less than 60 rpm), and reduce the pressure between the workpiece and the polishing pad (polishing pad) (specifically, for example, a pressure less than 100 g Z cm 2 ).
即ち、 制御装置 2 0 4からの制御指令に基いて、 C M P装置 2 0 0に よリ予め求められた大まかな研磨速さから算出される研磨時間だけ （や や少な目の研磨時間だけ） 研磨した後、 研磨へッ ド 2 0 2を 2 0 2 ' の 位置まで上昇させ、 研磨ヘッ ド 2 0 2に支持された半導体ウェハ 1 に純 水をかけて研磨面を洗浄し、 後述する残膜量検出へッ ド 2 1 1 を挿入し, 残膜厚検出装置 2 1 0によりウェハ表面の被研磨膜の残膜厚量を測定す る。 ここで、 残膜厚検出装置 2 1 0により測定された残膜厚量が所定量 に達していれば研磨は終了し、 達していなければ、 処理手段 2 1 2によ つて残膜厚量を制御装置 2 0 4にフィードバックすることによって制御 装置 2 0 4は残膜厚量からその後の研磨時間を算出し、 この算出された 研磨時間の指令を C M P装置 2 0 0に提供することによって算出された 研磨時間だけさらに研磨することになる。 これにより大きく終点研磨量 をはずれる事がなくなる。 That is, based on the control command from the control device 204, the polishing was performed only for the polishing time calculated from the rough polishing speed previously obtained by the CMP device 200 (only a slightly smaller polishing time). Then, the polishing head 202 is raised to the position 202 ', pure water is applied to the semiconductor wafer 1 supported by the polishing head 202 to wash the polished surface, and the remaining film amount described later The detection head 211 is inserted, and the remaining film thickness of the film to be polished on the wafer surface is measured by the remaining film thickness detecting device 210. Here, if the remaining film thickness measured by the remaining film thickness detecting device 210 has reached a predetermined amount, the polishing is finished, and if not, the processing means 212 detects the remaining film thickness. By feeding back to the control device 204, the control device 204 calculates the subsequent polishing time from the remaining film thickness, and the calculated polishing time is calculated. By providing the polishing time command to the CMP apparatus 200, the polishing is further performed by the calculated polishing time. As a result, the amount of polishing at the end point does not greatly deviate.
第 1 0図は、 残膜厚検出へッ ド 2 1 1の第 1の実施例を示す構成図で ある。 即ち、 残膜厚検出へッ ド 2 1 1は、 ハロゲンランプ等から構成さ れた光源 2 6 1 と点光源を形成するピンホール 2 6 2とピンホール 2 6 2から出射した光をほぼ平行光 2 6 5に変換して半導体ウェハ 1の研磨 面に照射する集光レンズ 2 6 3とよりなる照明光学系と、 ハーフミラー 2 6 4と回折格子 2 7 1 と結像レンズ 2 7 2とよりなる結像光学系と、 検出器 3 3 とから構成される。 ピンホール 2 6 2による点光源の像は、 集光レンズ 2 6 3、 半導体ウェハ 1の研磨面 （被平坦化膜） 、 ハーフミ ラ一2 6 4、 回折格子 2 7 1 を介して結像レンズ 2 7 2により検出器 2 7 3上に結像される。 この際、 光源の波長毎に回折格子 3 3 2による回 折角度が異なるため、 検出器 3 3 4上では分光された像として結像され、 第 1 1図に示すような波形が検出される。 第 1 1図は、 検出器 2 7 3上 で分光して検出される波長に対する検出波形を示す。 第 1 2図は、 検出 器 2 7 3上で分光して検出される 1ノ波長に対する検出波形を示す。 第 1 1図の場合は横軸を波長えにし、 第 1 2図の場合は横軸を 1 /波長 λ にした。 第 1 1図に示す波形では、 波長 λの長い方で波形のピーク位置 のピッチがのびる。 ところが第 1 2図に示す波形では、 全ての位置で波 形のピーク位置 （極大または極小の位置） のピッチが等間隔で並ぶ。 従 つて、 残膜厚量 dの算出は、 次に示す （数式 1 ) によって算出すること ができる。  FIG. 10 is a configuration diagram showing a first embodiment of the remaining film thickness detection head 2 11. In other words, the remaining film thickness detection head 211 is a light source 261 composed of a halogen lamp or the like, a pinhole 262 forming a point light source, and light emitted from the pinhole 262 being substantially parallel. An illumination optical system consisting of a condenser lens 263 that converts the light into light 265 and irradiates the polished surface of the semiconductor wafer 1 with a half mirror 264, a diffraction grating 271, an imaging lens 272 And a detector 33. The image of the point light source by the pinhole 262 is formed through the condenser lens 263, the polished surface of the semiconductor wafer 1 (film to be planarized), the half mirror 264, and the diffraction lens 271. An image is formed on the detector 2 7 3 by 2 7 2. At this time, since the diffraction angle of the diffraction grating 332 differs for each wavelength of the light source, it is imaged as a spectral image on the detector 3334, and the waveform shown in FIG. 11 is detected. . FIG. 11 shows a detection waveform with respect to a wavelength detected by spectroscopy on the detector 273. FIG. 12 shows a detection waveform for one wavelength that is spectrally detected on the detector 273. In the case of FIG. 11, the horizontal axis is the wavelength, and in the case of FIG. 12, the horizontal axis is 1 / wavelength λ. In the waveform shown in FIG. 11, the longer the wavelength λ, the longer the pitch of the peak position of the waveform. However, in the waveforms shown in Fig. 12, the pitches of the waveform peak positions (maximum or minimum positions) are arranged at equal intervals at all positions. Therefore, the remaining film thickness d can be calculated by the following (Equation 1).
d = N / ( 2 η · ( Ι / λ , - \ / λ 2 ) ) (数式 1 ) ただし、 Νはピーク位置 （ 1 /え ） からピーク位置 （ 1 Z λ 2 ) まで の間のピークの個数である。 ピークは極大でも、 極小でのどちらでも良 レ、。 nは被研磨材である絶縁膜の屈折率である。 d = N / (2 η · (Ι / λ,-\ / λ 2 )) (Equation 1) where Ν is the peak from the peak position (1 /) to the peak position (1 Z λ 2 ) It is the number. Peaks can be maximum or minimum Les ,. n is the refractive index of the insulating film to be polished.
ここで、 ピンホール 2 6 2は、 1次元のピンホールすなわちスリ ッ ト であっても良い。 要するに光源として、 点光源またはスリ ッ ト光源で形 成し、 研磨面に対してほぼ平行光で照射できれば良い。  Here, the pinhole 262 may be a one-dimensional pinhole, that is, a slit. In short, it is only necessary that the light source be formed by a point light source or a slit light source and be able to irradiate the polished surface with substantially parallel light.
即ち、 検出器 2 7 3上で分光して検出される検出信号波形より、 処理 手段 2 1 2によって以下に説明する原理により、 残膜厚が計測される。 第 1 3図に残膜厚測定対象物の断面図を示す。 この残膜厚測定対象物 (半導体ウェハ） 1は、 例えば下地パターン 1 3 1の上に配線パターン 1 3 2 ( 3 0 1 ) が形成され、 その隙間を埋めさらにその上部にかけて 酸化珪素系 （ S i 0 2 系） の絶縁膜 （被平坦化膜） 1 3 3が形成された ものである。 ここで、 研磨によって平坦化された絶縁膜 1 3 3 ( 3 0 3 ) の表面に照射された光 2 6 5は、 絶縁膜 （被平坦化膜） 1 3 3が透明で あるため、 被平坦化膜 1 3 3の表面、 配線パターン 1 3 2の上部 （上面） 、 配線パターン 1 3 2の底部の 3力所で反射して検出器 2 7 3に届く。 実際には、 下地パターン自体が複雑な上、 さらに下地まで光が届きさら に複雑な波面を形成する。 この際、 この 3つの光束が干渉し合い、 第 1 1図に示した波形が検出される。 従って、 この検出波形は d l 、 d 2、 d 3の 3つの光路差から生じた干渉光が重ね合わさつていることになる。 そこで、 より高精度な計測を実現するためには、 この 3つの干渉光を分 離 （分解） する必要がある。 この分解のためには、 第 1 2図に示す検出 波形の周波数解析が効果を発揮する。 この周波数解析は、 F F T等のフ ーリェ解析でも、 最大ェント口ピ一法等の予測形の周波数解析であって も良い。 このように処理手段 2 1 2により周波数解析をして分離 （分解） し、 この分離されたものから上記 （数式 1 ) に基いて残膜厚 dを測定す ることができる。 That is, the remaining film thickness is measured by the processing means 212 according to the principle described below from the detection signal waveform detected by spectroscopy on the detector 273. FIG. 13 shows a cross-sectional view of the object for measuring the remaining film thickness. In the remaining film thickness measurement target (semiconductor wafer) 1, for example, a wiring pattern 13 2 (301) is formed on a base pattern 13 1, and the gap is further filled. i insulating film (the planarization film of 0 2 system)) 1 3 3 in which are formed. Here, the light 265 applied to the surface of the insulating film 133 (303) planarized by the polishing is flat because the insulating film (film to be planarized) 133 is transparent. The light is reflected at three points on the surface of the oxide film 13 3, the top (upper surface) of the wiring pattern 13 2, and the bottom of the wiring pattern 13 2, and reaches the detector 2 73. In practice, the underlying pattern itself is complicated, and furthermore, light reaches the ground and forms a more complicated wavefront. At this time, the three light beams interfere with each other, and the waveform shown in FIG. 11 is detected. Therefore, this detection waveform is such that interference light generated from three optical path differences of dl, d2, and d3 is superimposed. Therefore, it is necessary to separate (decompose) these three interference lights in order to realize more accurate measurement. For this decomposition, the frequency analysis of the detected waveform shown in Fig. 12 is effective. This frequency analysis may be a Fourier analysis such as an FFT or a predictive frequency analysis such as a maximum entrance peak method. In this way, the frequency analysis is performed by the processing means 2 12 and separated (decomposed), and the remaining film thickness d can be measured from the separated one based on the above (Equation 1).
以上の方法で残膜厚は高精度に計測できるが、 下地パターンが特に複 雑な場合は、 精度が落ちることがある。 このような場合にも精度を保つ ためには、 第 I 4図に示すようにある特定のピークに着目し、 そのピー クの横方向への変動 δを検出 （モニタ） しても良い。 これにより、 さら に高精度な検出が可能になる。 この場合、 ピークの移動 δは、 残膜厚量 に対して必ずしも線形に変わらない場合がある。 そのため、 さらに高精 度な検出のためには、 予め測定された移動量と残膜厚量の関係を表した テーブルを用いると良い。 この換算は、 もちろんマイコン等の処理手段 2 1 2上で自動的に為される。 With the above method, the remaining film thickness can be measured with high accuracy. In rough cases, accuracy may decrease. In order to maintain the accuracy even in such a case, attention may be paid to a specific peak as shown in FIG. 14 and the lateral fluctuation δ of the peak may be detected (monitored). This allows for more accurate detection. In this case, the peak shift δ may not always change linearly with the remaining film thickness. Therefore, for more accurate detection, it is preferable to use a table showing the relationship between the amount of movement measured in advance and the amount of remaining film thickness. This conversion is automatically performed on the processing means 2 12 such as a microcomputer.
第 1 5図は、 残膜厚検出へッ ド 2 1 1の第 2の実施例を示す構成図で ある。 即ち、 半導体ウェハ 1において層間絶縁膜 1 3 3 ( 3 0 3 ) を研 磨して平坦化する場合、 層間絶縁膜 1 3 3 ( 3 0 3 ) の下に配線パター ン 1 3 2 ( 3 0 1 ) が規則的に形成されている。 従って、 研磨された層 間絶縁膜 1 3 3 ( 3 0 3 ) に対して照明光 2 6 5を照射した際、 規則的 に配列された配線パターン 1 3 2 ( 3 0 1 ) が回折格子の役目をして、 層間絶縁膜 1 3 3 ( 3 0 3 ) から分光された反射光が得られ、 この分光 された光を検出器 2 7 3で受光することによって、 第 1 1図に示すよう な信号を検出することができる。 そこで、 処理手段 2 1 2によって、 第 1 2図に示す信号に変換することによって、 （数式 1 ) に基いて残膜厚 量を算出することができる。 当然、 より高精度に残膜厚量を算出するた めには、 F F Τ等のフーリエ解析や最大エントロピ一法等の予測形の周 波数解析等を用いて干渉光を分離 （分解） する必要がある。  FIG. 15 is a configuration diagram showing a second embodiment of the remaining film thickness detection head 2 11. That is, when the interlayer insulating film 133 (303) is polished and flattened on the semiconductor wafer 1, the wiring pattern 133 (300) is provided below the interlayer insulating film 133 (303). 1) is regularly formed. Therefore, when the polished inter-layer insulating film 13 3 (30 3) is irradiated with the illumination light 265, the regularly arranged wiring patterns 13 2 (30 1) form the diffraction grating. As a function, the reflected light separated from the interlayer insulating film 133 (303) is obtained, and the separated light is received by the detector 273, as shown in FIG. Signal can be detected. Therefore, the remaining film thickness can be calculated based on (Equation 1) by converting the signals into the signals shown in FIG. 12 by the processing means 2 12. Of course, in order to calculate the remaining film thickness with higher accuracy, it is necessary to separate (decompose) the interference light using Fourier analysis such as FF や or frequency analysis of the prediction type such as the maximum entropy method. There is.
第 1 6図は、 残膜厚検出へッ ド 2 1 1の第 3の実施例を示す構成図で ある。 この第 3の実施例は、 基本的には第 1 5図に示す第 2の実施例と 同様である。 即ち、 半導体ウェハ 1 において層間絶縁膜 1 3 3 ( 3 0 3 ) を研磨して平坦化する場合、 層間絶縁膜 1 3 3 ( 3 0 3 ) の下に配線パ ターン 1 3 2 ( 3 0 1 ) が規則的に形成されている。 残膜厚検出へッ ド 2 1 1の第 3の実施例は、 ハロゲンランプ等から構成された光源 2 6 1 と点光源を形成するピンホール 2 6 2とピンホール 2 6 2から出射した 光をほぼ平行光 2 6 5に変換してこの照明光 2 6 5を半導体ウェハ 1の 研磨された層間絶縁膜 1 3 3 ( 3 0 3 ) に対して斜め方向から照射する 集光レンズ 2 6 3とよりなる照明光学系と、 結像レンズ 2 7 2よりなる 結像光学系と、 分光されて結像された像を検出する検出器 2 7 3とから 構成される。 従って、 研磨された層間絶縁膜 1 3 3 ( 3 0 3 ) に対して 照明光 2 6 5を照射した際、 規則的に配列された配線パターン 1 3 2FIG. 16 is a configuration diagram showing a third embodiment of the head 211 for detecting the remaining film thickness. The third embodiment is basically the same as the second embodiment shown in FIG. That is, when the interlayer insulating film 133 (303) is polished and flattened in the semiconductor wafer 1, the wiring pattern 133 (303) is provided below the interlayer insulating film 133 (303). ) Are regularly formed. Head for detecting remaining film thickness In the third embodiment of the present invention, a light source 261, which is constituted by a halogen lamp, etc., a pinhole 262 forming a point light source, and light emitted from the pinhole 262 are converted into substantially parallel light 265. And an illumination optical system comprising a condensing lens 263 for irradiating the illumination light 2665 to the polished interlayer insulating film 133 (303) of the semiconductor wafer 1 from an oblique direction. An imaging optical system including an imaging lens 272 and a detector 273 for detecting an image that has been split and formed. Therefore, when the polished interlayer insulating film 1 3 3 (3 0 3) is irradiated with the illumination light 2 65, the regularly arranged wiring patterns 1 3 2
( 3 0 1 ) が回折格子の役目をして、 層間絶縁膜 1 3 3 ( 3 0 3 ) から 分光された反射光が得られ、 この分光された光を結像レンズ 2 7 2によ つて結像させ、 この結像した分光像を検出器 2 7 3で受光することによ つて、 第 1 1図に示すような信号を検出することができる。 そこで、 処 理手段 2 1 2によって、 第 1 2図に示す信号に変換することによって、(301) functions as a diffraction grating, and the reflected light that is spectrally separated from the interlayer insulating film 133 (303) is obtained. The spectrally separated light is converted by the imaging lens 272. By forming an image and receiving the formed spectral image by the detector 273, a signal as shown in FIG. 11 can be detected. Therefore, by converting the signals into the signals shown in FIG. 12 by the processing means 2 12,
(数式 1 ) に基いて残膜厚量を算出することができる。 当然、 より高精 度に残膜厚量を算出するためには、 F F T等のフーリェ解析や最大ェン トロピー法等の予測形の周波数解析等を用いて干渉光を分離 （分解） す る必要がある。 The remaining film thickness can be calculated based on (Equation 1). Of course, in order to calculate the remaining film thickness with higher accuracy, it is necessary to separate (decompose) the interference light using Fourier analysis such as FFT or frequency analysis of the prediction type such as the maximum entropy method. There is.
第 1 7図は、 残膜厚検出へッ ド 2 1 1の第 4の実施例を示す構成図で ある。 即ち、 残膜厚検出へッ ド 2 1 1は、 白色光源 3 3 1 と、 ハーフミ ラー 3 3 3と、 該白色光源 3 3 1から照射された白色光を集光して半導 体ウェハ 1の研磨面に照射し、 半導体ウェハ 1の研磨面 （被平坦化膜） よリ得られる回折光を検出器 3 3 4上に結像する集光レンズ （結像レン ズ） 3 3 2と、 該結像された回折像を受光して回折像信号に変換する検 出器 3 3 4とによって構成される。 第 1 8図は、 検出器 3 3 4によって 検出される回折像面 1 4 5における回折像 1 4 6の強度分布を示す。 第 1 9図は、 回折像面における u方向 （半径方法） についての残膜厚の変 化に応じた回折像の強度分布の変化 1 4 1 、 1 2を示す。 従って、 処 理手段 2 1 2内のメモリに予め複数の残膜厚量に応じた回折像の強度分 布を測定して記憶しておく ことにより、 処理手段 2 1 2は、 検出器 3 3 で検出される回折像の強度分布から上記メモリに記憶された複数の残 膜厚量に応じた回折像の強度分布について補間することによって残膜厚 量を算出することができる。 FIG. 17 is a configuration diagram showing a fourth embodiment of the remaining film thickness detection head 2 11. That is, the remaining film thickness detection head 211 is formed of a white light source 331, a half mirror 3333, and a semiconductor wafer 1 which condenses the white light emitted from the white light source 3311. A condenser lens (imaging lens) 332 that forms an image on the detector 3334 by irradiating the polished surface of the semiconductor wafer 1 with the diffracted light obtained from the polished surface (film to be planarized) of the semiconductor wafer 1; A detector 334 for receiving the formed diffraction image and converting it into a diffraction image signal. FIG. 18 shows the intensity distribution of the diffraction image 146 on the diffraction image surface 144 detected by the detector 334. Fig. 19 shows the change of the remaining film thickness in the u-direction (radius method) on the diffraction image plane. 14 shows changes in the intensity distribution of the diffraction image according to the transformation. Therefore, by measuring and storing in advance the intensity distribution of the diffraction image corresponding to a plurality of remaining film thicknesses in the memory in the processing means 2 12, the processing means 2 12 The remaining film thickness can be calculated by interpolating the intensity distribution of the diffraction image corresponding to the plurality of remaining film thicknesses stored in the memory from the intensity distribution of the diffraction image detected in step (1).
第 2 0図は、 残膜厚測定のための他の実施例を示す構成図ある。 この 実施例は、 残膜厚測定のためのテーパのついた透明基板からなる試料 2 8 1 を支持する小型の研磨へッ ド 2 0 2 aを備え、 本来の研磨へッ ド 2 0 2による半導体ウェハ 1 に対する研磨と同様に上記試料 2 8 1に対し て研磨布 2 0 4を張り付けた研磨定盤 2 0 1 との間において研磨を施す ように構成する。 即ち、 研磨へッ ド 2 0 2 aも研磨へッ ド 2 0 2と同様 に研磨圧が付与されて自転するように回転駆動される。 この実施例の場 合、 半導体ウェハ 1 に対する被研磨材が絶縁膜 3 0 3、 3 2 6である場 合には、 この絶縁膜 3 0 3、 3 2 6の材質と上記試料 2 8 1の材質と同 じにすることによって、 半導体ウェハ 1 に対する研磨量と試料 2 8 1に 対する研磨量と一致させることができる。 いずれにしても、 予め半導体 ウェハ 1 に対する研磨量と試料 2 8 1 に対する研磨量との相関関係を求 めておく ことが必要である。 このように半導体ウェハ 1 に対する研磨量 と試料 2 8 1 に対する研磨量との相関関係が把握できているので、 試料 2 8 1 に対して残膜厚を測定することによって半導体ウェハ 1 に対する 残膜厚を算出することができる。  FIG. 20 is a block diagram showing another embodiment for measuring the remaining film thickness. This embodiment is provided with a small polishing head 202a for supporting a sample 281, which is made of a tapered transparent substrate for measuring the remaining film thickness, and uses the original polishing head 202. In the same manner as the polishing of the semiconductor wafer 1, the sample 281 is configured to be polished with a polishing platen 201 on which a polishing cloth 204 is adhered. That is, similarly to the polishing head 202, the polishing head 202a is rotationally driven so as to rotate by applying a polishing pressure. In the case of this embodiment, when the material to be polished for the semiconductor wafer 1 is the insulating film 303, 326, the material of the insulating film 303, 326 and the material of the sample 281, By using the same material, the polishing amount for the semiconductor wafer 1 and the polishing amount for the sample 281 can be matched. In any case, it is necessary to determine in advance the correlation between the polishing amount for the semiconductor wafer 1 and the polishing amount for the sample 28 1. Since the correlation between the amount of polishing for the semiconductor wafer 1 and the amount of polishing for the sample 28 1 has been grasped in this manner, the remaining film thickness for the semiconductor wafer 1 is measured by measuring the remaining film thickness for the sample 28 1. Can be calculated.
この実施例は、 研磨へッ ド 2 0 2 aに、 レーザ等のコヒーレント光源 2 8 2と、 ハーフミラー 2 8 3と、 検出器 2 8 4とを備え、 研磨へッ ド 2 0 2 aに支持された試料 （テーパのついた透明基板） 2 8 1 に対して 裏側から窓 2 8 5を通してコヒ一レン卜光を照射し、 テーパのついた透 明基板 2 8 1からの干渉縞像 （第 2 1図 （ a ) に示す） 2 8 6を検出器 2 8 4で検出する干渉光学系を形成している。 ここで、 コヒ一レント光 源 2 8 2は、 必ずしもレーザである必要はなく 、 ハロゲンランプ等の白 色光源を用い、 光学系全体の中で、 コヒーレント状態を形成しても良い。In this embodiment, a polishing head 202 a, a coherent light source 282 such as a laser, a half mirror 283 and a detector 284 are provided, and a polishing head 202 a is provided. The supported sample (tapered transparent substrate) 281 was irradiated with coherent light from the back through window 285 from behind, and the tapered transparent substrate was exposed. An interference optical system is formed in which an interference fringe image (shown in FIG. 21 (a)) from the bright substrate 281 is detected by a detector 284. Here, the coherent light source 282 does not necessarily need to be a laser, but may use a white light source such as a halogen lamp to form a coherent state in the entire optical system.
5 具体的には、 時間的かつ空間的にコヒーレントな状態つま り、 波長の帯 域を限定するフィルターと、 ピンホール、 1次元のピンホール （スリ ツ ト） を挿入しても良い。 従って、 検出器 2 8 4は、 第 2 1図 （ a ) に示 す干渉縞像 2 8 6を受光して試料 2 8 1の残膜厚量に応じて第 2 1図 ( b ) に示す信号 2 8 7、 2 8 8が得られる。 そこで処理手段 2 1 2に i O おいて信号 2 8 7、 2 8 8のシフ ト量 5 1 を算出することによって、 試 料 2 8 1の残膜厚量を求めることができ、 その結果半導体ウェハ 1 に対 する研磨量と試料 2 8 1 に対する研磨量との相関関係から半導体ウェハ 1 に対する残膜厚量を算出することができる。 この実施例の場合、 研磨 中いつでも残膜厚量を算出することができる。 研磨中は、 試料 2 8 1のMore 5 specifically, Ri temporally and spatially coherent state That, a filter to limit the bandwidth of the wavelength, pinhole, may be inserted one-dimensional pinhole (Sri Tsu g). Therefore, the detector 284 receives the interference fringe image 286 shown in FIG. 21 (a) and receives the interference fringe image 286 shown in FIG. 21 (b) according to the remaining film thickness of the sample 281. Signals 287 and 288 are obtained. Therefore, by calculating the shift amount 51 of the signals 287 and 288 in the processing means 211 with i O, the remaining film thickness of the sample 281 can be obtained. The remaining film thickness for the semiconductor wafer 1 can be calculated from the correlation between the polishing amount for the wafer 1 and the polishing amount for the sample 28 1. In the case of this embodiment, the remaining film thickness can be calculated at any time during polishing. During polishing, the sample 2
1 5 研磨面と研磨布 2 0 4との間に研磨砥粒の水けん濁液が介在することに なるが、 この研磨砥粒の水けん濁液の影響を大きく受けることなく、 第 2 1図 （ a ) に示す干渉縞が検出できることが実験により確認できた。 なお、 上記実施例は、 研磨中に残膜厚量を算出するために、 研磨へッ ド 2 0 2 aの裏側に、 レーザ等のコヒーレント光源 2 8 2と、 ハーフミ 1 5 Water-suspension liquid of abrasive grains during the polishing surface and the polishing cloth 2 0 4 is the intervention, without greatly influenced by the abrasive grains of the water-suspension liquid, a second 1 Experiments confirmed that the interference fringes shown in Figure (a) could be detected. In the above embodiment, in order to calculate the amount of remaining film thickness during polishing, a coherent light source 282 such as a laser and a half-mirror were provided on the back side of the polishing head 202a.
20 ラー 2 8 3と、 検出器 2 8 4とからなる照明光学系および検出光学系を 備えた場合について説明したが、 この照明光学系および検出光学系を試 料 2 8 1 と対向するように設置しても良い。 この場合、 研磨へッ ド 2 0 2 aに支持された試料 2 8 1 に対して残膜厚量を測定するためには、 第 8図に示すように、 研磨へッ ド 2 0 2 aを 2 0 2 ' の位置まで上昇させ.Although the case where the illumination optical system and the detection optical system composed of the 20-color 2831 and the detector 2884 are provided has been described, the illumination optical system and the detection optical system are set so as to face the sample 2811. May be installed. In this case, in order to measure the remaining film thickness of the sample 281 supported on the polishing head 202a, as shown in FIG. 8, the polishing head 202a was used. Raise to position 2 0 2 '.
25 研磨へッ ド 2 0 2 aに支持された試料 2 8 1 に対して純水をかけて試料 25 Sample 2 8 1 supported by polishing head 202 a
2 8 1の研磨面を洗浄する必要がある。 即ち、 研磨された試料 （テ一パ のついた透明基板） 2 8 1 を支持した研磨へッ ド 2 0 2 aに対して、 第 8図に示す残膜厚検出へッ ド 2 1 1 と同様に試料 2 8 1の残膜厚量を測 定することができる。 It is necessary to clean the polished surface of 281. That is, the polished sample (taper For the polishing head 202a supporting the 281, the remaining film thickness of the sample 281, as with the remaining film thickness detection head 211 shown in FIG. The quantity can be measured.
第 2 2図は、 残膜厚測定のための第 2 0図とは異なる他の実施例を示 す構成図ある。 この実施例は、 残膜厚測定のための平行な透明基板から なる試料 2 9 1 を支持する小型の研磨へッ ド 2 0 2 aを備え、 本来の研 磨へッ ド 2 0 2による半導体ウェハ 1 に対する研磨と同様に上記試料 2 9 1に対して研磨布 2 0 を張り付けた研磨定盤 2 0 1 との間において 研磨を施すように構成する。 即ち、 研磨へッ ド 2 0 2 aも研磨へッ ド 2 0 2と同様に研磨圧が付与されて自転するように回転駆動される。 この 実施例の場合、 半導体ウェハ 1に対する被研磨材が絶縁膜 3 0 3、 3 2 6である場合には、 この絶縁膜 3 0 3、 3 2 6の材質と上記試料 2 9 1 の材質と同じにすることによって、 半導体ウェハ 1に対する研磨量と試 料 2 9 1 に対する研磨量と一致させることができる。 いずれにしても、 予め半導体ウェハ 1 に対する研磨量と試料 2 9 1 に対する研磨量との相 関関係を求めておく ことが必要である。 このように半導体ウェハ 1 に対 する研磨量と試料 2 9 1 に対する研磨量との相関関係が把握できている ので、 試料 2 9 1に対して残膜厚を測定することによって半導体ウェハ 1 に対する残膜厚を算出することができる。  FIG. 22 is a block diagram showing another embodiment different from FIG. 20 for measuring the remaining film thickness. This example has a small polishing head 202a supporting a sample 291, which is a parallel transparent substrate for measuring the remaining film thickness, and has a semiconductor polishing method using the original polishing head 202. As in the case of polishing the wafer 1, the sample 291 is polished with the polishing platen 201 on which the polishing cloth 20 is adhered. That is, similarly to the polishing head 202, the polishing head 202a is also driven to rotate by applying a polishing pressure and rotating. In the case of this embodiment, when the material to be polished for the semiconductor wafer 1 is the insulating film 303, 326, the material of the insulating film 303, 326 and the material of the sample 291, By making the same, the amount of polishing for the semiconductor wafer 1 and the amount of polishing for the sample 29 1 can be matched. In any case, it is necessary to determine in advance the correlation between the polishing amount for the semiconductor wafer 1 and the polishing amount for the sample 291. Since the correlation between the amount of polishing on the semiconductor wafer 1 and the amount of polishing on the sample 291 has been grasped in this manner, the remaining film on the semiconductor wafer 1 is measured by measuring the remaining film thickness of the sample 291. The film thickness can be calculated.
この実施例は、 研磨へッ ド 2 0 2 aに、 試料 2 9 1の研磨面において ほぼ重なるように検出光軸 2 9 4に対して対称に斜め方向からレーザ等 のコヒーレント光 2 9 3 a、 2 9 3 bを照射する照射光学系と、 結像レ ンズ 2 9 2と、 検出器 2 8 4とを備え、 研磨へッ ド 2 0 2 aに支持され た試料 （平行な透明基板） 2 9 1の研磨面においてほぼ重なるように、 試料 2 9 1の裏側から窓 2 8 5を通して検出光軸 2 9 4に対して対称に 斜め方向からコヒーレント光 2 9 3 a、 2 9 3 bを照射することによつ て、 結像レンズ 2 9 2によって結像される透明基板 2 9 1からの干渉縞 像 （第 2 1図 （ a ) に示す） 2 8 6を検出器 2 84で検出できるように 干渉光学系を形成する。 従って、 検出器 2 8 4は、 第 2 1図 （ a ) に示 す干渉縞像 2 8 6を受光して試料 2 9 1の残膜厚量に応じて第 2 1図 ( b ) に示す信号 2 8 7、 2 8 8が得られる。 そこで処理手段 2 1 2に おいて信号 2 8 7、 2 8 8のシフ ト量 5 1 を算出することによって、 試 料 2 9 1の残膜厚量を求めることができ、 その結果半導体ウェハ 1 に対 する研磨量と試料 2 9 1 に対する研磨量との相関関係から半導体ウェハ 1 に対する残膜厚量を算出することができる。 この実施例の場合、 研磨 中いつでも残膜厚量を算出することができる。 研磨中は、 試料 2 9 1の 研磨面と研磨布 2 04との間に研磨砥粒の水けん濁液が介在することに なるが、 第 2 0図に示す実施例と同様に研磨砥粒の水けん濁液の影響を 大きく受けることなく、 第 2 1図 （ a ) に示す干渉縞を検出することが できる。 In this embodiment, the coherent light such as a laser is applied to the polishing head 202 a from an oblique direction symmetrically with respect to the detection optical axis 294 so as to substantially overlap the polished surface of the sample 29 1. Specimen (parallel transparent substrate) supported by a polishing head 202a, comprising an irradiation optical system for irradiating 293b and 293b, an imaging lens 292, and a detector 284 The coherent light beams 293 a and 293 b are obliquely symmetrical with respect to the detection optical axis 294 through the window 285 from the back side of the sample 291 so that they almost overlap each other on the polished surface of the sample 291. By irradiating The interference optical system so that the interference fringe image (shown in Fig. 21 (a)) 2886 from the transparent substrate 291 formed by the imaging lens 2992 can be detected by the detector 284 To form Therefore, the detector 284 receives the interference fringe image 286 shown in FIG. 21 (a) and receives the interference fringe image 286 shown in FIG. 21 (b) according to the remaining film thickness of the sample 291. Signals 287 and 288 are obtained. Therefore, the remaining film thickness of the sample 291 can be obtained by calculating the shift amount 51 of the signals 287 and 288 in the processing means 2 12, and as a result, the semiconductor wafer 1 The remaining film thickness for the semiconductor wafer 1 can be calculated from the correlation between the polishing amount for the semiconductor wafer 1 and the polishing amount for the sample 29 1. In the case of this embodiment, the remaining film thickness can be calculated at any time during polishing. During polishing, a water suspension of abrasive grains is interposed between the polished surface of the sample 291 and the polishing cloth 204. However, as in the example shown in FIG. The interference fringes shown in Fig. 21 (a) can be detected without being greatly affected by the water suspension.
以上説明したように、 第 2 0図および第 2 2図に示す実施例は、 研磨 の速さ （研磨レート） を研磨中に実時間でモニタできるため、 事前に膜 厚を測定しておく ことによリ残膜厚量をモニタでき、 高速研磨から高精 度の低速研磨への切り換えを最終的に傷や異物等の欠陥が発生しない限 界に近ずけた時間まで遅らせることができ、 その結果、 半導体ウェハ 1 に対して最終的に傷や異物等の欠陥が存在しない平坦化された研磨面を 高スループッ 卜で製造することができる。  As described above, in the embodiment shown in FIGS. 20 and 22, since the polishing speed (polishing rate) can be monitored in real time during polishing, the film thickness must be measured in advance. The amount of residual film thickness can be monitored, and the switching from high-speed polishing to high-precision low-speed polishing can be delayed until the time when defects such as scratches and foreign matter do not finally occur is reached. As a result, a flattened polished surface free of defects such as scratches and foreign substances can be manufactured at a high throughput with respect to the semiconductor wafer 1.
また、 半導体ウェハ （半導体基板） 1 に対して第 3図に示すようにダ マシンと呼ばれるプロセスを適用した場合において、 第 3図 （ e ) に示 す如く金属膜 3 1 6を CMP装置 2 0 0で研磨する際にも、 残膜厚量と して下部の S i 02 系の絶縁膜パターン 3 1 5が露出した時点を予測も しくは検出することが必要となる。 そこで、 第 3図 （ d ) に示す断面構 造を有する半導体ウェハ 1 を研磨へッ ド 2 0 2に支持し、 該半導体ゥェ ノ、 1の表面の金属膜 3 1 6を研磨定盤 2 0 1 に張り付けられた研磨布 2 0 4との間で研磨砥粒の水けん濁液によって研磨し、 下部の S i 0 2 系 の絶縁膜のパターン 3 1 5が露出したと予想される時点において、 第 8 図に示すように、 研磨へッ ド 2 0 2を 2 0 2 ' の位置まで上昇させ、 研 磨ヘッ ド 2 0 2に支持された半導体ウェハ 1に対して純水をかけて半導 体ウェハ 1の研磨面を洗浄し、 残膜厚検出へッ ド 2 1 1 によリ絶縁膜パ ターン 3 1 5が露出した配線パターンの厚さを光学的に光干渉を用いて 測定することができ、 研磨の終点について適切であるか否かについて判 定することができる。 即ち、 表面に金属膜 3 1 6のみが形成された状態 では、 干渉は起こらないために平坦な検出波形として検出され、 金属膜 3 1 6の下部の絶縁膜パターン 3 1 5が露出すると絶縁膜 3 1 5の下面 からの反射光 （基板 3 1 1の表面が絶縁膜から形成されている場合には 絶縁膜 3 1 5の下面からはごく僅かの反射光しか得られない。 ） と金属 配線パターン 3 1 7あるいは絶縁膜 3 1 5の表面からの反射光との干渉 による波形が検出されることによって、 研磨の終点について適切である か否かについて判定することができる。 特に残膜厚検出へッ ド 2 1 1と して第 1 6図に示す第 3の実施例を用いると構成が簡単で適切である。 次に、 傷 ·異物等の欠陥検査装置 2 4 0について、 第 2 3図〜第 2 6 図を用いて具体的に説明する。 Also, when a process called damascene is applied to the semiconductor wafer (semiconductor substrate) 1 as shown in FIG. 3, the metal film 3 16 is applied to the CMP device 20 as shown in FIG. Even when polishing at 0, it is necessary to predict or detect the point in time when the lower SiO 2 -based insulating film pattern 3 15 is exposed as the remaining film thickness. Therefore, the cross-sectional structure shown in Fig. 3 (d) A semiconductor wafer 1 having a structure is supported on a polishing head 202, and a metal film 3 16 on the surface of the semiconductor nano 1 is connected to a polishing cloth 204 adhered to a polishing platen 201. It was polished by abrasive grains of the water-suspension liquid between, at the time a pattern 3 1 5 of the lower S i 0 2 based insulating film is expected to have exposed, as shown in FIG. 8, the polishing The head 202 is raised to the position 202 ', and the semiconductor wafer 1 supported by the polishing head 202 is washed with pure water to wash the polished surface of the semiconductor wafer 1. The thickness of the wiring pattern with the exposed insulating film pattern 3 15 can be optically measured by optical interference using the remaining film thickness detecting head 2 1 1, which is appropriate for the end point of polishing. Or not. In other words, when only the metal film 316 is formed on the surface, no interference occurs, so that a flat detection waveform is detected. When the insulating film pattern 315 below the metal film 316 is exposed, the insulating film is formed. Reflected light from the lower surface of 315 (only a small amount of reflected light is obtained from the lower surface of the insulating film 315 when the surface of the substrate 315 is formed of an insulating film) and metal wiring By detecting a waveform due to interference with the pattern 317 or the light reflected from the surface of the insulating film 315, it can be determined whether or not the polishing end point is appropriate. In particular, when the third embodiment shown in FIG. 16 is used as the remaining film thickness detection head 211, the configuration is simple and appropriate. Next, the defect inspection apparatus 240 for scratches / foreign matter will be specifically described with reference to FIGS. 23 to 26. FIG.
第 2 3図は、 本発明に係る傷 ·異物等の欠陥検査装置 2 4 0の第 1の 実施例を示す構成図である。 この第 1の実施例は、 アルゴンレーザ 1 し ビームエキスパンダ 1 2、 2分の 1波長板 1 3、 偏光素子 1 4、 偏光素 子 1 4の偏光の向きを変える偏光素子回転機構 1 5、 シリンドリカル等 の集光レンズ 1 6、 入射角度可変機構 1 7より構成される照明系 1 ◦と. 対物レンズ 3 1、 偏光素子 3 2、 空間フィルタ 3 3、 検出器 3 4より構 成される検出光学系 3 0と、 2値化回路 5 1、 座標生成回路 5 2、 検出 結果メモリ 5 4、 コンピュータ 5 3、 検出結果表示手段 5 5より構成さ れるデータ処理系 2 4 1と、 ローディング · アン口一ディング手段 7 、 x y zステージ 7 1、 自動焦点検出系 7 3、 zステージコントローラ 7 5、 x yステージコントローラ 7 2よリ構成されるステージ系 7 0とよ リ構成される。 なお、 データ処理系 （処理手段） 2 4 1 を構成するコン ピュータ 5 3は、 管理用のコンピュータ 2 5 0とネッ トワークを介して 接続されている。 FIG. 23 is a configuration diagram showing a first embodiment of the defect inspection apparatus 240 for flaws and foreign matter according to the present invention. In the first embodiment, an argon laser 1, a beam expander 12, a half-wave plate 13, a polarizing element 14, a polarizing element rotating mechanism 15 for changing the polarization direction of the polarizing element 14, An illumination system 1 consisting of a condenser lens 16 such as a cylindrical lens and a variable incident angle mechanism 17 and an objective lens 31, a polarizing element 32, a spatial filter 33, and a detector 34. The detection optical system 30 formed, the binarization circuit 51, the coordinate generation circuit 52, the detection result memory 54, the computer 53, and the detection result display means 55 A loading / unloading means 7, an xyz stage 71, an automatic focus detection system 73, a z stage controller 75, and an xy stage controller 72. The computer 53 constituting the data processing system (processing means) 24 1 is connected to the management computer 250 via a network.
まず、 C M P装置 2 0 0で研磨されて少なく とも洗浄装置 2 3 0で洗 浄された半導体ウェハ 1は、 洗浄装置 2 3 0から搬送手段を用いてロー ディング位置まで搬送され、 ローディング手段 7 4によリ研磨面を上側 に向けて x y zステージ 7 1上に載置される。  First, the semiconductor wafer 1 polished by the CMP device 200 and washed by at least the cleaning device 230 is transported from the cleaning device 230 to a loading position using a transporting device, and is loaded by the loading device 74. It is placed on the xyz stage 71 with the polished surface facing upward.
そして、 予めコンピュータ 5 3に対して入力されて設定された検査範 囲データが x yステージコントローラ 7 2に提供され、 X yステージコ ントローラ 7 2の制御に基づき、 X yステージ 7 1が X yに走査される c この際、 自動焦点検出系 7 3による検出結果に基づく zステージコント ローラ 7 5の制御によリ、 上記 X y走査期間中、 半導体ウェハ 1の研磨 面が自動的に焦点位置に合わされる。 同時に x yステージコントローラ 7 2の出力は、 座標生成回路 5 2に導かれ、 検査位置の座標の作成に用 いられる。 Inspection range data input and set in advance to the computer 53 is provided to the xy stage controller 72, and the xy stage 71 is changed to xy based on the control of the xy stage controller 72. at this time the scanned c, by the control of the z stage controller 7 5 based on the detection results of the automatic focus detecting system 7 3 Li, in the X y scanning period, polished surface of the semiconductor wafer 1 is automatically focus position Are combined. At the same time, the output of the xy stage controller 72 is led to a coordinate generation circuit 52, which is used to create the coordinates of the inspection position.
ここで、 自動焦点検出系 7 3は、 縞パターンを投影してそのピンぼけ 量から焦点位置を検出するものでも、 ナイフエツヂと 2分割センサを用 い 2分割センサの出力差 （あるいは比） から焦点位置を検出するもので も、 あるいは、 静電容量タイプのセンサにより z位置を計測するもので もかまわない。  Here, the automatic focus detection system 73 detects the focus position based on the amount of defocus by projecting a stripe pattern. It may be one that detects the position, or one that measures the z position with a capacitance type sensor.
y zステージ 7 1上に載置された半導体ウェハ 1の研磨面上に傷や 異物等の欠陥が存在しないか否かについての検査が次に説明するように 行なわれる。 即ち、 アルゴンレーザ 1 1から射出した光は、 ビームェキ スパンダ 1 2でビーム径が拡大され、 2分の 1波長板 1 3を通して円ま たは楕円偏光に変換され、 偏光素子 1 4により S偏光または P偏光に変 換され、 シリンドリカルレンズ等の集光レンズ 1 6で細帯状に集光され て半導体ウェハ 1上の平坦化された研磨面に照射される。 半導体ウェハ 1の研磨面から射出した光は、 検出レンズ 3 1で集光されて偏光素子 3 2またはノおよび空間フィルタ 3 3を通して検出器 3 4により検出され る。 即ち、 半導体ウェハ 1の研磨面に対して集光レーザ光が斜め方向か ら照射され、 X yステージ 7 1が走査され、 半導体ウェハ 1の研磨面か らの散乱回折光が対物レンズ 3 1 に入り、 半導体ウェハ 1の研磨面が例 えば層間絶縁膜 3 0 3の場合、 その下に配線パターン 3 0 1が存在する ことにより、 この規則的に配置された配線パターン 3 0 1からの散乱反 射光を偏光素子 3 2または空間フィルタ 3 3で遮光し、 半導体ウェハ 1 の研磨面から発生する散乱回折光による像を例えばリニアセンサ （ C C D ) で構成された検出器 3 4で受光して検出信号 3 7を出力する。 この 検出信号 3 7は、 2値化回路 5 1 によって所望の閾値で 2値化信号に変 換され、 この 2値化信号において所望の閾値を越えた研磨面に存在する 傷や異物等の欠陥を示す検出出力と、 その検出出力が得られたときの座 標生成回路 5 2から得られる研磨面上の発生位置の座標とがコンビユー タ 5 3からの指令に基いて対応付けされて半導体ウェハ毎に検出結果メ モリ 5 4に格納される。 各半導体ウェハに付与された番号を読取り手段 3 8で読み取ってコンピュータ 5 3および座標生成回路 5 2に入力する ことによって、 欠陥を示す検出出力とその発生位置の座標とが半導体ゥ ェハ毎に検出結果メモリ 5 4に格納されることになる。 後述するように. 検出結果メモリ 5 4には、 傷と異物とに弁別してそれらの発生位置の座 標とが対応させて半導体ウェハ毎に格納されるので、 コンピュータ 5 3 はこれら格納されたデータを読出すことによって半導体ウェハ毎、 また は複数の半導体ウェハに亘つての、 またはロッ ト単位での、 半導体ゥェ ハ上に発生した傷や異物についての分布をマツプとして収集することが でき、 それを表示手段 5 5に表示することもできると共に管理用のコン ピュータ 2 5 0に提供して記憶装置 2 5 1 に記憶させたり表示手段 2 5 2に表示をすることもできる。 またコンピュータ 5 3は、 半導体ウェハ 毎の、 またはロッ ト単位毎の半導体ウェハ上に発生した傷や異物の個数 等の変化 （変動） を収集することができ、 それを表示手段 5 5に表示す ることもできると共に管理用のコンピュータ 2 5 0に提供して記憶装置 2 5 1 に記憶させたり表示手段 2 5 2に表示をすることもできる。 scratches on the polished surface of the semiconductor wafer 1 placed on the yz stage 7 1 An inspection as to whether or not there is a defect such as a foreign substance is performed as described below. That is, the light emitted from the argon laser 11 has its beam diameter expanded by the beam expander 12, is converted into circular or elliptically polarized light through the half-wave plate 13, and is S-polarized or polarized by the polarizing element 14. The light is converted into P-polarized light, condensed in a narrow band shape by a condensing lens 16 such as a cylindrical lens, and is irradiated onto the flattened polished surface on the semiconductor wafer 1. Light emitted from the polished surface of the semiconductor wafer 1 is condensed by the detection lens 31 and is detected by the detector 34 through the polarizing element 32 or the filter and the spatial filter 33. That is, the polished surface of the semiconductor wafer 1 is irradiated with condensed laser light from an oblique direction, the xy stage 71 is scanned, and the scattered diffraction light from the polished surface of the semiconductor wafer 1 is applied to the objective lens 31. In the case where the polished surface of the semiconductor wafer 1 is, for example, the interlayer insulating film 303, the wiring pattern 301 underneath causes scattering scattering from the regularly arranged wiring pattern 301. The emitted light is shielded by a polarizing element 32 or a spatial filter 33, and an image due to scattered diffraction light generated from the polished surface of the semiconductor wafer 1 is received by a detector 34 constituted by, for example, a linear sensor (CCD), and a detection signal is received. 3 7 is output. The detection signal 37 is converted into a binarized signal by a binarization circuit 51 at a desired threshold, and a defect such as a scratch or a foreign substance present on the polished surface exceeding the desired threshold in the binarized signal. And the coordinates of the occurrence position on the polished surface obtained from the coordinate generation circuit 52 when the detection output is obtained are associated with each other based on a command from the computer 53 and the semiconductor wafer It is stored in the detection result memory 54 every time. By reading the number assigned to each semiconductor wafer by the reading means 38 and inputting it to the computer 53 and the coordinate generation circuit 52, the detection output indicating the defect and the coordinates of the position where the defect is generated can be obtained for each semiconductor wafer. It is stored in the detection result memory 54. As will be described later, the detection result memory 54 stores the positions of the occurrence positions of the scratches and the foreign matters by discriminating them from each other. Since the target is stored for each semiconductor wafer in correspondence with each other, the computer 53 reads out the stored data to read the stored data for each semiconductor wafer, for a plurality of semiconductor wafers, or for each lot. The distribution of flaws and foreign matter generated on the semiconductor wafer can be collected as a map, which can be displayed on the display means 55 and provided to the management computer 250 for storage. The information can be stored in the device 25 1 or displayed on the display means 25 2. Also, the computer 53 can collect changes (fluctuations) in the number of scratches or foreign substances generated on the semiconductor wafer for each semiconductor wafer or for each lot, and display them on the display means 55. It can also be provided to the management computer 250 and stored in the storage device 251, or displayed on the display means 252.
上記検出器 3 4から得られる検出波形の一例を第 2 4図に示す。 第 2 4図 （ a ) ( b ) には、 半導体ウェハ 1の表面 （研磨面） に照射した光 ビーム 1 0 Ίを示す。 第 2 4図 （ a ) は成膜後及び CMP処理後におい て表面 （研磨面） に面荒れがある場合、 第 2 4図 （ b ) は面荒れがなく 異物 4 1が存在する場合をそれぞれ示す。 第 2 4図 （ c ) 、 （ d ) にそ れぞれの場合における散乱光を検出器 3 4で受光して得られる検出信号 波形 1 0 9、 1 1 0を示す。 ところで、 第 24図 （ c ) に示す表面の面 荒れに基づく信号波形 1 0 9と、 第 2 4図 （ d ) に示す表面に存在する 傷や異物 4 1 に基づく信号波形 1 1 0とを区別する必要がある。 第 2 4 図 （ c ) 、 （ d ) に示すような信号波形 1 0 9、 1 1 0が検出されれば、 適当な閾値 1 1 1 を設定することで、 傷や異物と面荒れとを区別して検 出することができる。 しかしながら、 特に検出器 3 4によって検出する 際の画素サイズが大きい場合 （たとえば照明領域全域を 1つの信号とし て検出する場合） には、 第 24図 （ e ) 、 ( f ) に示すように面荒れと 傷や異物との区別がつきにく くなる。 第 24図 （ e ) 、 ( f ) では、 検 出器 3 4によって斜線の部分全体が積分された形 1 1 3、 1 1 4で検出 されるため相対的に傷や異物 4 1の信号 1 1 4が小くなリ、 その結果傷 や異物を面荒れと区別して検出することができない。 つま り、 表面 （研 磨面） 上に換算したときの検出器 3 4によって検出する画素の大きさは、 許される限り小さくするのが望ま しい。 具体的には、 たとえば、 8イン チウェハの検査時間を 3 0秒としたい場合、 検出器 3 4としてリニアセ ンサ （ C C D ) を 4段並列で構成し、 信号のサンプリング測度を 1 4 M H zとした場合、 検出画素のサイズを、 表面 （研磨面） 上に換算して 7 μ m平方とする必要がある。 C C D自体の画素サイズが例えば 1 3 平方とした場合、 対物レンズ 3 1 による結像倍率を約 1 . 9倍にすれば 良い。 この検出画素サイズの値は、 これら他のパラメータとの関係で目 的に応じて選択されるべきものである。 検出感度を十分にしたい場合、 表面 （研磨面） 上に換算して Ι μ π！〜 2 ； m平方程度にするのが望まし レヽ An example of the detection waveform obtained from the detector 34 is shown in FIG. FIGS. 24 (a) and (b) show a light beam 10 ° applied to the surface (polished surface) of the semiconductor wafer 1. FIG. Fig. 24 (a) shows the case where the surface (polished surface) is rough after film formation and after the CMP treatment, and Fig. 24 (b) shows the case where the surface is not rough and foreign matter 41 is present. Show. FIGS. 24 (c) and (d) show the detection signal waveforms 109 and 110 obtained by receiving the scattered light with the detector 34 in each case. By the way, the signal waveform 109 based on the surface roughness shown in FIG. 24 (c) and the signal waveform 110 based on the scratch or foreign matter 41 present on the surface shown in FIG. Need to be distinguished. If signal waveforms 109 and 110 as shown in Fig. 24 (c) and (d) are detected, by setting an appropriate threshold value 111, scratches, foreign matter and surface roughness can be eliminated. It can be detected separately. However, especially when the pixel size at the time of detection by the detector 34 is large (for example, when the entire illumination area is detected as one signal), as shown in FIGS. 24 (e) and (f), the surface Difficult to distinguish between rough and scratches or foreign objects. Fig. 24 (e) and (f) show the detection Since the entire shaded area is detected by the output unit 3 4 in the form of 1 1 3 and 1 1 4, the signal 1 1 4 of the flaw or foreign material 4 1 is relatively small, resulting in the flaw or foreign material. Cannot be detected separately from surface roughness. In other words, it is desirable that the size of the pixel detected by the detector 34 when converted on the surface (polished surface) be as small as possible. Specifically, for example, if it is desired to set the inspection time of an 8-inch wafer to 30 seconds, a linear sensor (CCD) is configured as a 4-stage parallel detector 34 and the signal sampling rate is set to 14 MHz. In this case, the size of the detection pixel needs to be 7 μm square on the surface (polished surface). If the pixel size of the CCD itself is, for example, 13 square, the imaging magnification by the objective lens 31 may be about 1.9 times. The value of the detection pixel size should be selected according to the purpose in relation to these other parameters. If you want to have sufficient detection sensitivity, convert to μπ! ~ 2; It is desirable to make it about m square.
また、 面荒れを検出する場合は、 第 2 4図 （ c ) に示す閾値 1 1 2に すればよい。 即ち、 C M P装置 2 0 0において、 研磨条件を設定する際、 面荒れの情報が必要とする場合には、 この傷 * 異物等の欠陥検査装置 2 To detect surface roughness, the threshold value may be set to the threshold value 112 shown in FIG. 24 (c). That is, when information on surface roughness is required when setting polishing conditions in the CMP apparatus 200, the defect inspection apparatus 2
4 0で検出してやれば良い。 It should be detected at 40.
ここで、 2値化回路 5 1は面荒れの信号を消去するためであり、 必ず しも 2値化回路である必要はない。 即ち、 検出器 3 4で検出される信号 に対して多値の閾値で量子化した画像データに変換してその画像データ 及び表面 （研磨面） 上における位置座標とを対応させて検出結果メモリ Here, the binarization circuit 51 is for erasing a rough surface signal, and need not necessarily be a binarization circuit. That is, the signal detected by the detector 34 is converted into image data quantized by a multi-valued threshold, and the image data is correlated with the position coordinates on the surface (polished surface), and the detection result memory is stored.
5 に格納させても良い。 この場合、 コンピュータ 5 3は、 検出結果メ モリ 5 4に格納されたデータを読出すことによって半導体ウェハ 1の表 面 （研磨面） 上に発生した傷の大きさによって分類処理し、 その良否の 判定をすることができるという効果を発揮する。 また、 複数の閾値の内 のいずれか （複数であっても良い） を、 面荒れを検出する閾値として用 いることで、 面荒れのレベル、 あるいば面荒れの分布を計測することカ でき、 その結果を管理用のコンピュータ 2 5 0を介して C M P装置 2 0 0にフィードパックすることによって、 C M P装置 2 0 0において、 研 磨条件を最適化することができる。 5 may be stored. In this case, the computer 53 reads out the data stored in the detection result memory 54 and performs a classification process according to the size of the flaw generated on the surface (polished surface) of the semiconductor wafer 1 to determine whether the quality is good or bad. This has the effect of making a determination. Also, out of multiple thresholds By using either (or more than one) as the threshold for detecting surface roughness, the level of surface roughness, or distribution of surface roughness, can be measured, and the results can be used for management. By performing feed-packing to the CMP apparatus 200 via the computer 250, the polishing conditions in the CMP apparatus 200 can be optimized.
また、 コンピュータ 5 3は、 検出結果メモリ 5 に格納された半導体 ウェハ 1毎の検出結果 （面荒れについて除去された量子化された画像デ ータ） から、 第 2 5図 （ a ) に示すように傷 4 0は通常複数の連続した (あるいは断続的に連続した） 形で出現し、 第 2 5図 （ b ) に示すよう に異物 4 1は通常孤立した形で出現するという統計的 ·経験的な知見に 基づく形状認識処理によって傷と異物とに分類する。 そして、 コンビュ ータ 5 3は、 半導体ウェハ 1毎に、 傷と分類された画像データに対して 隣接する傷を一つの連続した傷としてグループ化し、 このグループ化さ れた個数を計数することによって半導体ウェハ 1毎の傷の数を算出して 検出結果メモリ 5 に格納することができ、 半導体ウェハ 1毎の傷の数 の管理が可能となる。 但し、 このグループ化の処理は必ずしも常に有用 で るとは限らず、 半導体ウェハ 1毎 （全面で） の傷部の面積を管理す る場合には、 グループ化の処理は必要にならないことは明らかである。 このグループ化の処理は、 通常の画像処理のアルゴリズムとして知られ ているラベリ ングアルゴリズムを使って実施される。 さらにこの処理は コンピュータ 5 3によりソフ ト的に行なうと説明したが、 専用のハード ウェア （回路） により実現しても良い。  The computer 53 obtains the detection results (quantized image data from which surface roughness has been removed) for each semiconductor wafer 1 stored in the detection result memory 5 as shown in FIG. 25 (a). Scratches 40 usually appear in multiple continuous (or intermittently continuous) forms, and as shown in Fig. 25 (b), the foreign matter 41 usually appears in an isolated form. Are classified into flaws and foreign substances by shape recognition processing based on basic knowledge. Then, for each semiconductor wafer 1, the computer 53 groups adjacent flaws into one continuous flaw with respect to the image data classified as flaws, and counts the number of the grouped flaws. The number of flaws for each semiconductor wafer 1 can be calculated and stored in the detection result memory 5, and the number of flaws for each semiconductor wafer 1 can be managed. However, this grouping process is not always useful, and it is clear that the grouping process is not necessary when managing the area of the scratches on each semiconductor wafer 1 (over the entire surface). It is. This grouping process is performed using a labeling algorithm known as a normal image processing algorithm. Further, it has been described that this processing is performed softly by the computer 53, but it may be realized by dedicated hardware (circuit).
また、 連続したり、 非常に近接している画像パターンに対して同じラ ベルを付与してグループ化する処理は、 傷と異物の分類に用いることが できる。 すなわち傷は通常複数の連続した （あるいは断続的に連続した） 形で出現し、 異物は通常孤立した形で出現するからである。 さらに、 面 荒れを消去した信号に対してハードウェアでグルーピングすることで検 出結果メモリ 5 4の容量を節約することができる。 In addition, the process of assigning the same label to continuous or very close image patterns and grouping them can be used for classification of scratches and foreign matter. This is because wounds usually appear in multiple continuous (or intermittent) forms, and foreign bodies usually appear in an isolated form. Furthermore, the face By grouping the signals from which the roughness has been eliminated by hardware, the capacity of the detection result memory 54 can be saved.
即ち、 コンピュータ 5 3は、 半導体ウェハ毎に、 検出結果メモリ 5 4 に格納された 2値化画像データを読出して、 第 2 5図に示すように、 画 像処理により形状を認識して線状に伸びた傷 4 0であるか、 粒子状の異 物 4 1であるかの判定を行ない、 傷 4 0と判定されたときには傷を示す 2値化画像データからその傷 4 0の面積 S sおよび最大長さ Lを求めて 傷の判定基準と比較して良否の判定を行なってその結果を検出結果メモ リ 5 4に発生位置の座標に対応させて格納し、 異物 4 1 と判定されたと きには異物を示す 2値化画像データからその異物 4 1の面積 S f を求め て異物の判定基準と比較して良否の判定を行なってその結果を検出結果 メモリに発生位置の座標に対応させて格納する。 このように、 研磨面に 発生した欠陥が傷なのか、 異物なのかを認識するのは、 良否の判定基準 が異なると共に、 傷を発生させる研磨条件と異物を発生させる研磨条件 が異なるからである。 従って、 コンピュータ 5 3力 半導体ウェハ 1毎 に、 研磨面の傷や異物等の欠陥についての検査結果 （傷の発生状況と異 物の発生状況とを区別して把握された情報である。 ） 4 5を、 検出結果 メモリ 5 4から読出して、 ネッ トワークを介して管理用のコンピュータ 2 5 0に提供することによって、 管理用のコンピュータ 2 5 0は、 傷の 発生状況と異物の発生状況とを区別して把握でき、 しかも C M P装置 2 0 0の制御装置 2 0 4から現在の C M P条件が把握できるので、 研磨面 に発生した傷や異物の原因である C M P条件を究明することが容易に可 能となり、 この究明された C M P条件を修正すべく、 制御装置 2 0 4に フィードバックすることが可能となる。 これによつて、 C M P装置 2 0 0は、 制御装置 2 0 4からの指令または制御に基いて、 C M P条件を修 正することによって、 半導体ウェハ 1の研磨面に傷や異物の発生を無く して歩留ま り向上を果たすことができる。 また C M P装置 2 0 0が研磨 条件の設定に研磨面の面荒れ情報も必要とするならば、 制御装置 2 0 4 が傷 ·異物等の検査装置 2 4 0の処理手段 2 1からその情報の提供を 管理用のコンピュータ 2 5 0を介して受けるようにすれば良い。 That is, the computer 53 reads out the binarized image data stored in the detection result memory 54 for each semiconductor wafer, and recognizes the shape by image processing as shown in FIG. It is determined whether the scratch is a stretch 40 or a particle-like foreign matter 41, and when the scratch 40 is determined, the area S s of the scratch 40 is determined from the binarized image data indicating the scratch. And the maximum length L is determined, the pass / fail judgment is made by comparing it with the scratch judgment criteria, and the result is stored in the detection result memory 54 in correspondence with the coordinates of the occurrence position. In this case, the area S f of the foreign substance 4 1 is obtained from the binarized image data indicating the foreign substance, is compared with the foreign substance determination standard, and the quality is determined, and the result is detected. And store. Recognizing whether a defect generated on the polished surface is a scratch or a foreign substance is because the criteria for quality are different and the polishing conditions for generating the scratch and the polishing conditions for generating the foreign substance are different. . Therefore, for each computer 5 3 semiconductor wafer 1, inspection results for defects such as scratches and foreign matter on the polished surface (information obtained by distinguishing the occurrence of scratches from the occurrence of foreign substances) 4 5 Is read out from the detection result memory 54 and provided to the management computer 250 via the network, so that the management computer 250 distinguishes between the occurrence of scratches and the occurrence of foreign matter. Since the current CMP conditions can be grasped separately from the control device 204 of the CMP device 200, it is easy to find out the CMP conditions that are the cause of scratches or foreign matter on the polished surface. In order to correct the determined CMP conditions, it is possible to feed back to the controller 204. As a result, the CMP apparatus 200 corrects the CMP conditions based on a command or control from the control unit 204 so that the polishing surface of the semiconductor wafer 1 is free from scratches and foreign matter. Yield can be improved. Also, if the CMP apparatus 200 also needs surface roughness information of the polished surface to set the polishing conditions, the control unit 204 will send the information from the processing means 21 of the inspection apparatus 240 for scratches and foreign matter. Provision may be made via the management computer 250.
ところで、 半導体ウェハ 1上の平坦化された研磨面としては、 第 1図 および第 2図に示すように、 配線パターン 3 0 1上に絶縁膜 3 0 3が形 成されている場合と、 第 3図 （ e ) および第 4図に示すように基板 （表 面が絶縁膜で形成されている場合もある。 ） 3 1 1上に絶縁膜パターン 3 1 5と配線パターン 3 1 7とが形成されている場合と、 第 5図 （ e ) および第 6図に示すように S i 0 2 系の絶縁膜パターン 3 2 5と S i 3 N 4のパターン 3 2 2とが形成されている場合とがある。 そして半導体 ウェハ 1上の平坦化された研磨面には、 研磨による僅かな面荒れが生じ ている。 By the way, as shown in FIG. 1 and FIG. 2, the planarized polished surface on the semiconductor wafer 1 includes a case where an insulating film 303 is formed on a wiring pattern 301 and a case where As shown in Fig. 3 (e) and Fig. 4, the substrate (the surface may be formed of an insulating film) 3 11 The insulating film pattern 3 15 and the wiring pattern 3 17 are formed on 1 1 and if it is, FIG. 5 (e) and sixth when the pattern 3 2 2 S i 0 2 based insulating film pattern 3 2 5 and S i 3 N 4 is formed as shown in FIG. There is. Then, the flattened polished surface on the semiconductor wafer 1 is slightly roughened by polishing.
第 3図 （ e ) および第 4図に示す場合には、 研磨面に絶縁膜パターン 3 1 5と配線パターン 3 1 7とが存在することになる。 しかしながら、 絶縁膜パターン 3 1 5と配線パターン 3 1 7とは表面の反射率が相違す ることになる。 従って、 面荒れによる絶縁膜パターン 3 1 5の表面から 発生する散乱回折光を検出器 3 4が受光して得られる信号波形と、 面芒 ノ ill れによる配線パターン 3 1 7の表面から発生する散乱回折光を検出器 3 4が受光して得られる信号波形との間において強度が相違することにな る。 そこで、 コンピュータ 5 3は、 検出器 3 4から得られる信号 3 7か ら絶縁膜パターン 3 1 5の領域と配線パターン 3 1 7の領域とを判定し 配線パターン 3 1 7の領域から検出器 3 4によって得られる信号に対し ては 2値化回路 5 1 に対して高い閾値を設定し、 絶縁膜パターン 3 1 5 の領域から検出器 3 4によって得られる信号に対しては 2値化回路 5 1 に対して低い閾値を設定することによって面荒れによって生じる信号を 消去することができる。 なお、 この場合、 コンピュータ 5 3が絶縁膜パ ターン 3 1 5の領域と配線パターン 3 1 7の領域とを判定するまで、 検 出器 3 4から得られる画像信号を記憶して所定の時間遅延させる必要が ある。 また、 傷についても、 絶縁膜パターン 3 1 5の表面に発生した傷 から発生する散乱光の強度は、 配線パターン 3 1 7の表面に発生しだ傷 から発生する散乱光の強度よリも弱くなるが、 半導体素子として支障の あるのは、 前述した通り、 配線パターン 3 1 7の表面に発生した傷であ るため、 絶縁膜パターン 3 1 5の表面に発生した傷については感度が落 ちて正確に認識できなかったとしても問題にはならない。 また、 異物に ついては、 絶縁膜パターン 3 1 5と配線パターン 3 1 7とについて同様 な散乱光強度が得られることから問題にならない。 In the case shown in FIG. 3 (e) and FIG. 4, the insulating film pattern 315 and the wiring pattern 317 exist on the polished surface. However, the insulating film pattern 315 and the wiring pattern 317 have different surface reflectivities. Therefore, a signal waveform obtained by the detector 34 receiving the scattered diffracted light generated from the surface of the insulating film pattern 3 15 due to the surface roughness, and a signal waveform generated from the surface of the wiring pattern 3 17 due to the surface mark The intensity is different from the signal waveform obtained by the detector 34 receiving the scattered diffraction light. Therefore, the computer 53 determines the area of the insulating film pattern 315 and the area of the wiring pattern 317 from the signal 37 obtained from the detector 34, and determines the area of the wiring pattern 317 from the area of the wiring pattern 317. For the signal obtained by (4), a high threshold is set for the binarization circuit 51, and for the signal obtained by the detector 34 from the region of the insulating film pattern 3 15, the binarization circuit 5 is set. By setting a low threshold for 1 Can be erased. In this case, the image signal obtained from the detector 34 is stored for a predetermined time until the computer 53 determines the area of the insulating film pattern 315 and the area of the wiring pattern 317. Need to be done. Also, the intensity of scattered light generated from scratches generated on the surface of the insulating film pattern 315 is weaker than the intensity of scattered light generated from scratches generated on the surface of the wiring pattern 317. However, as described above, the problem with the semiconductor element is the damage on the surface of the wiring pattern 317, and the sensitivity of the damage on the surface of the insulating film pattern 315 decreases. It doesn't matter if you don't recognize it correctly. Regarding foreign matter, no problem occurs because the same scattered light intensity can be obtained for the insulating film pattern 315 and the wiring pattern 317.
ところで、 上記説明では、 面荒れによって生じる信号を消去するため に、 絶縁膜パターン 3 1 5の領域と配線パターン 3 1 7の領域とで閾値 を変えるようにしたが、 絶縁膜パターン 3 1 5の表面に発生した傷につ いて認識できなくても良ければ、 領域に関係無く配線パターン 3 1 7の 表面に発生した面荒れを消去できる高い閾値に設定すればよい。 これに より、 コンピュータ 5 3による絶縁膜パターン 3 1 5の領域と配線バタ ーン 3 1 7の領域との判定および閾値の変更が不要となる。 以上説明し たように、 第 3図 （ e ) および第 4図に示す場合において、 研磨面に発 生した異物や傷について、 検査することが可能となる。  By the way, in the above description, the threshold value is changed between the region of the insulating film pattern 3 15 and the region of the wiring pattern 3 17 in order to erase a signal caused by surface roughness. If it is not necessary to be able to recognize the scratches generated on the surface, it is sufficient to set a high threshold that can eliminate the surface roughness generated on the surface of the wiring pattern 317 regardless of the area. This eliminates the need for the computer 53 to determine the region of the insulating film pattern 315 and the region of the wiring pattern 317 and change the threshold. As described above, in the cases shown in FIGS. 3 (e) and 4, it is possible to inspect for foreign substances and scratches generated on the polished surface.
第 5図 （ e ) および第 6図に示す場合には、 研磨面に絶縁膜パターン 3 2 5と S i 3N4層 3 2 2とが存在することになる。 しかし、 絶縁膜パ ターン 3 2 5も S i 3N4層 3 2 2も照明光に対して同じような特性を示 すことによって、 第 2 4図 （ c ) 、 ( d ) に示すような閾値 1 1 1 によ つて面荒れによって生じる信号を消去することができ、 その結果研磨面 における異物や傷について、 検査することが可能となる。 特に素子分離 構造を作るために要求されるのは、 第 6図に示すように S i 3 N 4層 3 2 2に傷 3 2 9が発生しないことであるので、 この傷 3 2 9が確実に検出 できるように、 閾値等の感度を設定すれば良い。 In the case shown in FIGS. 5 (e) and 6, the insulating film pattern 325 and the Si 3 N 4 layer 3222 exist on the polished surface. However, both the insulating film pattern 325 and the Si 3 N 4 layer 322 show similar characteristics to the illumination light, and as shown in FIGS. 24 (c) and (d), The threshold value 1 1 1 eliminates the signal generated by the surface roughness, and as a result, it becomes possible to inspect the polished surface for foreign substances and scratches. Especially element isolation What is required to make the structure is that no scratches 329 occur in the Si 3 N 4 layer 3 22 as shown in FIG. 6, so this scratch 329 can be reliably detected. Thus, the sensitivity such as the threshold may be set.
なお、 第 2 3図に示す傷 ·異物等の欠陥検査装置 2 4 0における照明 光の光源としては、 アルゴンレーザ 1 1である必要はなく、 他の波長の レーザ光源、 例えば、 ヘリウムネオンレーザ、 赤色の半導体レーザ （ガ リウムアルミニウム砒素化合物半導体レーザ） 、 S H G ( 2次高調波） を用いた光源、 キセノンランプ、 水銀ランプ等の放電管光源、 ハロゲン ランプ等のフイラメントランプであってよい。  The light source of the illumination light in the defect inspection apparatus 240 for scratches and foreign matter shown in FIG. 23 does not need to be an argon laser 11 but a laser light source of another wavelength, for example, a helium neon laser, It may be a red semiconductor laser (gallium aluminum arsenide compound semiconductor laser), a light source using SHG (second harmonic), a discharge tube light source such as a xenon lamp or a mercury lamp, or a filament lamp such as a halogen lamp.
また、 空間フィルタ 3 3、 2分の 1波長板 1 3、 偏光素子 1 4、 3 2 は必ずしも必要ではない。 これらのフィルタは、 傷の形状の分類、 異物 あるいは欠陥といった凹凸形状の分類等に用いるものである。 具体的に は、 照射光として S偏光 （電界ベク トルが入射面に垂直な光束） を用い ることで、 半導体ウェハ 1の表面 （研磨面） の面荒れが軽減され、 異物, スクラッチ ·傷の検出感度を向上させることができる。 逆に、 P偏光 (電界ベク トルが入射面に平行な光束） にすることにより、 表面の面荒 れを高感度で検出することができる。 これらのモードは、 評価されるべ き対象物に応じて選択されるものである。  Further, the spatial filter 33, the half-wave plate 13 and the polarizing elements 14 and 32 are not necessarily required. These filters are used to classify the shape of a flaw, and to classify uneven shapes such as foreign matter or defects. Specifically, by using S-polarized light (light flux whose electric field vector is perpendicular to the incident surface) as irradiation light, surface roughness of the surface (polished surface) of the semiconductor wafer 1 is reduced, and foreign matter, scratches and scratches are reduced. Detection sensitivity can be improved. Conversely, by using P-polarized light (a light beam whose electric field vector is parallel to the plane of incidence), surface roughness can be detected with high sensitivity. These modes are selected according to the object to be evaluated.
第 2 6図には、 第 2 3図に示す傷 ·異物等の欠陥検査装置 2 4 0にお いて、 照明を 2方向照明にした場合を模式的に示す。 第 2 3図に示す実 施例では、 照明の入射面に垂直な方向に近い方向を持つ傷が強調され検 出される。 そこで第 2 6図に示したように互いに直角な方向 1 0 1、 1 0 2、 1 0 3、 1 0 4から斜め照明することによりこの指向性は軽減さ れる。 もちろん 4方向でなく、 直角な 2方向 1 0 1、 1 0 2でもよい。 また直角でない方向も含めて 4方向 1 0 3、 1 0 5、 1 0 6、 1 0 4で も良い。 しかしながら照明光束 2 ( 1 0 7 ) を実現するという立場から は、 先に示した直角な 2方向あるいは 4方向が望ま しい。 FIG. 26 schematically shows a case where the illumination is two-way illumination in the defect inspection apparatus 240 for scratches and foreign matter shown in FIG. In the embodiment shown in FIG. 23, a flaw having a direction close to the direction perpendicular to the plane of incidence of the illumination is emphasized and detected. Therefore, as shown in FIG. 26, this directivity can be reduced by obliquely illuminating from directions 101, 102, 103, 104 perpendicular to each other. Of course, instead of four directions, two perpendicular directions 101 and 102 may be used. Also, four directions 103, 105, 106, and 104, including directions that are not right angles, may be used. However, from the standpoint of realizing illumination flux 2 (1 0 7) It is desirable that two or four perpendicular directions shown above are used.
また、 第 2 7図には、 第 2 3図に示す傷 ·異物等の欠陥検査装置 2 4 0において、 全方向から照明する手法を示す。 この実施例は、 光源 1 I 、 ビームエキスパンダ 1 8、 1 9、 中央をく リ貫いたミラー 3 8より構成 される照明光学系と、 対物レンズ 3 1、 結像レンズ 3 7、 検出器 3 4よ り構成される検出光学系と、 第 2 3図に示すステージ系 7 0、 およびデ ータ処理系 2 4 1 より構成される。  FIG. 27 shows a method of illuminating from all directions in the defect inspection apparatus 240 for flaws and foreign matter shown in FIG. In this embodiment, an illumination optical system composed of a light source 1 I, beam expanders 18 and 19, a mirror 38 penetrating the center, an objective lens 31, an imaging lens 37, and a detector 3 4 and a stage optical system 70 shown in FIG. 23 and a data processing system 24 1.
この実施例では、 照明光学系により半導体ウェハ 1の表面 （研磨面） 上の 1点が全方位から照明される。 半導体ウェハ 1の表面から反射した 光は、 中央をく り貫いたミラー 3 8により 0次反射光が遮光され、 傷や 異物等の欠陥からの散乱光のみがミラ一 3 8を通って結像レンズ 3 7に よって検出器 3 4に結像されて検出される。 この方法では、 半導体ゥェ ハ 1の表面上の 1点のみの照明であるから、 Θステージを回転させなが ら Xステージを走査することにより、 照明光束を半導体ウェハ 1の表面 に対して螺旋状に走査するのが効率的である。 従って、 ステージ系には X z Sステージ系を用いている。 もちろん、 ステージ系は第 2 3図に示 す X y zステージであっても本質的な問題ではないのは言うまでもない c また、 データ処理系 2 1等の構成は第 2 3図のものと等価である。 この方法では、 全方向から照明するため、 第 2 3図に示した方法よリ さらに、 傷等の検出で、 指向性が軽減される。 In this embodiment, one point on the surface (polished surface) of the semiconductor wafer 1 is illuminated from all directions by the illumination optical system. The light reflected from the surface of the semiconductor wafer 1 is shielded from the 0th-order reflected light by the mirror 38 penetrating the center, and only the scattered light from defects such as scratches or foreign matter passes through the mirror 38 to form an image. The image is formed on the detector 34 by the lens 37 and detected. In this method, since only one point on the surface of the semiconductor wafer 1 is illuminated, the illuminating light beam spirals with respect to the surface of the semiconductor wafer 1 by scanning the X stage while rotating the stage. Scanning is efficient. Therefore, the X z S stage system is used for the stage system. Of course, the stage system is also of course c not an essential problem even shown to X yz stage to the second 3 figures, configurations such as the data processing system 2 1 is equivalent to that of the second 3 Figure is there. In this method, since illumination is performed from all directions, the directivity is further reduced by detecting a flaw or the like as compared with the method shown in FIG.
次に、 傷 ·異物等の欠陥検査装置 2 2 0の実施例について、 第 2 8図 〜第 3 1図を用いて具体的に説明する。  Next, an embodiment of the defect inspection apparatus 220 for scratches / foreign matter will be specifically described with reference to FIGS. 28 to 31. FIG.
この実施例は、 C M P装置 2 0 0で研磨された半導体ウェハ 1は洗浄 装置 2 3 0によって洗浄するまでは、 液中に保管されることを利用して、 液中において研磨面上の傷や異物等の欠陥を検査するものである。  This embodiment utilizes the fact that a semiconductor wafer 1 polished by a CMP apparatus 200 is stored in a liquid until it is cleaned by a cleaning apparatus 230, so that scratches on the polished surface in the liquid can be prevented. This is to inspect for defects such as foreign matter.
第 2 8図は、 液中での研磨面上の傷や異物等の欠陥を検査する傷 ·異 物等の欠陥検査装置 2 2 0の実施例を示した概略構成図である。 Fig. 28 shows scratches and defects for inspecting defects such as scratches and foreign matter on the polished surface in liquid. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic configuration diagram showing an embodiment of a defect inspection apparatus 220 for an object or the like.
この実施例は、 第 2 3図とほぼ同様な構成である。 槽 3の液中の中に 半導体ウェハ 1 を載置するステージ 7 1 を備え、 照明系 1 0は槽 3の外 側に設け、 検出系 3 0はケーシング 3 6に納めるように構成する。 処理 手段 2 4 1 については、 第 2 3図と同様である。 従って、 照明系 1 0か らの照明光は照明用窓 1 8を通して液中の半導体ウェハ 1の表面 （研磨 面） に照射し、 液中の半導体ウェハ 1の表面からの散乱光を検出用窓 3 5を通して検出光学系 3 0で検出する。 半導体ウェハ 1が液中に存在す るためウェハを載置するステージは固定で、 静止した半導体ウェハ 1 に 対し、 照明光学系 1 0と検出光学系 3 0を走査する構成が望ま しいが.、 勿論ステージを走査する構成であっても良い。 また、 照明用窓 1 8、 検 出用窓 3 5は、 液体への光の入射の際、 液表面の揺らぎにより照明、 検 出光がゆがむのを避けるためのものである。  This embodiment has substantially the same configuration as that of FIG. A stage 71 for placing the semiconductor wafer 1 in the liquid in the tank 3 is provided. The illumination system 10 is provided outside the tank 3, and the detection system 30 is housed in the casing 36. The processing means 24 1 is the same as in FIG. Therefore, the illumination light from the illumination system 10 irradiates the surface (polished surface) of the semiconductor wafer 1 in the liquid through the illumination window 18 and the scattered light from the surface of the semiconductor wafer 1 in the liquid is detected. Through 35, detection is performed by the detection optical system 30. Since the semiconductor wafer 1 exists in the liquid, the stage on which the wafer is placed is fixed, and it is desirable that the illumination optical system 10 and the detection optical system 30 scan the stationary semiconductor wafer 1. Of course, a configuration for scanning the stage may be used. The illumination window 18 and the detection window 35 are provided to prevent the illumination and detection light from being distorted due to fluctuations in the liquid surface when light enters the liquid.
この方法は、 研磨された半導体ウェハ 1が液中に保管されるためこの 保管中に検査できるという効果がある。  This method has an effect that the polished semiconductor wafer 1 is stored in a liquid, so that the inspection can be performed during the storage.
また、 液を半導体ウェハの表面の平坦化膜の屈折率よリ大きくするこ とで、 以下に説明する全反射の現象を積極的に用いることができる。 平 坦化膜が屈折率 1. 4 6 0 2の石英系を用いた場合、 液体としてたとえ ば、 屈折率 1. 5 8 6のァニリン、 屈折率 1. 4 7 3のグリセリン、 屈 折率 1 . 4 6 0 7の 4塩化炭素、 屈折率 1. 7 3 7のジョードメタン、 屈折率 1. 5 1 6のセダ油、 屈折率 1 . 4 8のパラフィン油、 屈折率 1 . 6 6の α—ブロモナフタレン、 屈折率 1 . 5 0 1 2のべンゼン等が考え られる。  By making the liquid larger than the refractive index of the flattening film on the surface of the semiconductor wafer, the phenomenon of total reflection described below can be used positively. When the flattening film is made of quartz with a refractive index of 1.462, for example, liquids such as aniline with a refractive index of 1.586, glycerin with a refractive index of 1.473, and a refractive index of 1 460 carbon tetrachloride, refraction index 1.73 7 jade methane, refraction index 1.516 seda oil, refraction index 1.48 paraffin oil, refraction index 1.66 α —Bromonaphthalene, benzene with a refractive index of 1.5012, etc. are considered.
第 2 9図に全反射が生じている際の異物あるいは傷の検出の様子を示 す。 屈折率 η 1の媒質から屈折率 η 2 ( η 1 >η 2 ) の媒質に光が入射 する際、 s i n 0 2 = ( n l Zn 2 ) ' s i n e i〉 lとなる、 Θ 1が 存在する。 Θ 1がこの値より大きい場合、 全反射が起こる。 この場合、 平坦化のための酸化膜の内部にパターンが形成されている場合でも、 内 部に光が届かないため、 内部パターンの影響をなくすことができ、 検出 感度を飛躍的に向上させることができる。 表面に異物あるいは、 欠陥が 存在した場合、 上記の条件が崩れ光が散乱するため、 全くの暗い背景に 対して、 異物あるいは欠陥が光ることになる。 Fig. 29 shows how foreign matter or scratches are detected when total reflection occurs. When light enters from a medium with a refractive index η 1 to a medium with a refractive index η 2 (η 1> η 2), sin 0 2 = (nl Zn 2) 'sinei> l, Θ 1 Exists. If Θ1 is greater than this value, total internal reflection will occur. In this case, even if a pattern is formed inside the oxide film for planarization, since light does not reach the inside, the effect of the internal pattern can be eliminated and the detection sensitivity can be dramatically improved. Can be. If there is a foreign substance or defect on the surface, the above conditions are broken and the light is scattered, so that the foreign substance or defect shines on a completely dark background.
第 3 0図に第 2 9図に示す表面での反射率を示す。 P偏光 4 7及び S 偏光 4 8の時の値をそれぞれ示す。  FIG. 30 shows the reflectance at the surface shown in FIG. 29. The values for P-polarized light 47 and S-polarized light 48 are shown, respectively.
第 3 1図に、 別の実施例を示す。 この実施例は、 照明窓 1 8を介し光 を半導体ウェハ 1の表面の全面あるいは一部に照射し、 検出窓 3 5を介 し照明した領域を 2次元の検出器 3 4上に結像レンズ 3 1 によリ結像さ せた構成である。 本実施例も上記の全反射の条件を用いている。 この全 反射の条件を用いることにより下地パターンの影響を除けるため、 検出 の画素サイズを大きくでき、 このような 2次元センサ 3 4を用いても広 い領域を一度に検査できる。 たとえば、 1 0 0 0 X 1 0 0 0画素の C C Dカメラを用いると 7 ミクロン画素で 7 m m X 7 m mの領域を検査でき る。 これは、 傷あるいは、 面あれのモニタとして十分な面積である。 さ らに、 検査面積を広げたい場合には、 画素サイズを大きくするか、 ステ ップアンドリ ピートで、 検査エリアを大きく しても良い。 また、 検査ェ リアを犠牲にして画素サイズを小さく し、 検出感度を上げても良い。 次に、 傷 · 異物等の欠陥検査装置 2 4 0の処理手段 2 4 1から得られ る傷 ·異物等の欠陥検査データおよび完成されたテスタ 2 5 0の処理手 段 2 5 1から得られる半導体素子の電気的特性データに基いて半導体ゥ ェハ 1の製造ライン 4 0 0についての管理用コンピュータ 2 5 0による 生産管理について第 3 2図〜第 3 9図を用いて説明する。  FIG. 31 shows another embodiment. In this embodiment, light is irradiated onto the entire surface or a part of the surface of the semiconductor wafer 1 through an illumination window 18, and an area illuminated through a detection window 35 is formed on an imaging lens 34 on a two-dimensional detector 34. In this configuration, the image is re-imaged by 3 1. This embodiment also uses the above conditions for total reflection. By using the condition of the total reflection, the influence of the underlying pattern can be eliminated, so that the pixel size of the detection can be increased. Even with such a two-dimensional sensor 34, a wide area can be inspected at a time. For example, using a 1000 × 100 pixel CCD camera, a 7 micron pixel can inspect a 7 mm × 7 mm area. This is enough area for a scratch or rough surface monitor. If the inspection area needs to be increased, the pixel size may be increased, or the inspection area may be enlarged by step-and-repeat. Further, the detection sensitivity may be increased by reducing the pixel size at the expense of the inspection area. Next, the defect inspection data of the scratches / foreign matter obtained from the processing means 2 41 of the defect inspection apparatus 240 for flaws / foreign matter and the processing means 25 1 of the completed tester 250 obtained from the processing means 25 1 The production management of the production line 400 of the semiconductor wafer 1 by the management computer 250 based on the electrical characteristic data of the semiconductor element will be described with reference to FIGS. 32 to 39.
第 3 2図は、 本発明に係る半導体ウェハ 1の製造ライン 4 0 0につい ての管理用コンピュータ 2 5 0による生産管理についての全体的な構成 を示す図である。 第 7図にも同様な構成を示している。 半導体ウェハ 1 の製造ライン 40 0は、 代表的に、 スパッタ等の金属成膜工程、 レジス トパターン形成工程 （レジスト塗布工程、 露光工程、 および現像工程等 からなる。 ） 、 およびエッチング工程 （レジストパターン除去工程も含 む） からなる配線パターン 3 0 1を形成する配線パターン形成工程 40 1と、 配線パターン 3 0 1上に CVD装置等によって絶縁膜 3 0 3を形 成する絶縁膜形成工程 40 2と、 該絶縁膜形成工程 40 2で形成された 絶縁膜 3 0 3の表面を平坦化するために CM P装置 2 0 0によって研磨 して洗浄装置 2 3 0によって洗浄する研磨工程 40 3と、 スパッタ等の 金属成膜工程、 レジストパターン形成工程 （レジスト塗布工程、 露光ェ 程、 および現像工程等からなる。 ） 、 およびエッチング工程 （レジスト パターン除去工程も含む） からなリ、 前記研磨工程で平坦化された絶縁 膜 3 0 3上に配線パターン 3 0 1を形成する配線パターン形成工程 40 4と、 該配線パターン形成工程 404で形成された配線パターン 3 0 2 上に絶縁膜や保護膜 3 04を CVD装置等によって形成する絶縁膜形成 工程 40 5とから構成される。 即ち、 配線パターン形成工程 40 1およ び配線パターン形成工程 404においては、 スパッタ装置、 レジスト塗 布装置、 露光装置、 エッチング装置等が用いられる。 また絶縁膜形成ェ 程 40 2および絶縁膜形成工程 40 5は、 CVD装置等が用いられる。 4 1 1、 4 1 2、 4 1 3 ( 204 ) 、 4 1 4、 4 1 5は、 各工程に備え られた装置を制御する制御装置を示す。 従って、 制御装置 4 1 1 , 1 2、 1 3 ( 2 04 ) 、 4 1 4、 4 1 5からは、 投入される半導体ゥェ ハ 1毎に対して成膜、 エッチング、 露光、 研磨等の製造条件が得られる, 傷 ·異物等の欠陥検査装置 240は、 半導体ウェハ 1の製造ライン 40 0における所望の工程 （工程内でも良い。 ） 40 1、 40 3、 404か ら 42 1、 4 2 2、 4 2 3で示すようにサンプリングされた傷 '異物等 の欠陥を検査する必要のある半導体ウェハ 1に対して傷 ·異物等の欠陥 の検査が行なわれる。 第 7図においては、 傷 · 異物等の欠陥検査装置 2 4◦は、 CMP装置 20 0によって研磨され、 洗浄装置 2 3 0によって 洗浄された半導体ウェハ 1の表面に対して傷 ·異物等の欠陥を検査する ことについて説明したが、 第 3 2図においては、 傷 ·異物等の欠陥検査 装置 240は、 製造ライン 40 0を構成する所望の装置 （設備） から得 られる半導体ウェハ 1 を全数または口ッ ト単位または所定の枚数単位で サンプリングして、 その半導体ウェハ 1の表面に発生した傷 ·異物等の 欠陥を検査する。 またこの傷 ·異物等の欠陥検査装置 240は、 製造ラ イン 40 0において、 必要とする工程の間に設置しても良い。 この場合 傷 ·異物等の欠陥検査装置 240の台数は増加するが、 定常的に半導体 ウェハ 1の表面に発生した傷 ·異物等の欠陥を検査することができる。 FIG. 32 shows a production line 400 of the semiconductor wafer 1 according to the present invention. 1 is a diagram showing an overall configuration of production management by all management computers 250. FIG. FIG. 7 shows a similar configuration. The production line 400 of the semiconductor wafer 1 typically includes a metal film forming process such as sputtering, a resist pattern forming process (a resist coating process, an exposure process, a developing process, etc.), and an etching process (resist pattern). A wiring pattern forming step 401 for forming a wiring pattern 301 including a removing step), and an insulating film forming step 402 for forming an insulating film 303 on the wiring pattern 301 by a CVD apparatus or the like. A polishing step 403 in which the surface of the insulating film 303 formed in the insulating film forming step 402 is polished by a CMP apparatus 200 and planarized by a cleaning apparatus 230 in order to flatten the surface thereof; Metal film forming process such as sputtering, resist pattern forming process (consisting of resist coating process, exposure process, developing process, etc.), and etching process (including resist pattern removing process) A wiring pattern forming step 404 for forming a wiring pattern 301 on the insulating film 303 flattened in the polishing step, and a wiring pattern 302 formed in the wiring pattern forming step 404 An insulating film forming step 405 in which an insulating film and a protective film 304 are formed thereon by a CVD apparatus or the like. That is, in the wiring pattern forming step 401 and the wiring pattern forming step 404, a sputtering device, a resist coating device, an exposure device, an etching device and the like are used. In the insulating film forming step 402 and the insulating film forming step 405, a CVD apparatus or the like is used. Reference numerals 411, 412, 413 (204), 414, and 415 denote control devices for controlling devices provided in each process. Therefore, the control devices 411, 12, 13 (204), 414, and 415 form the film formation, etching, exposure, polishing, etc. for each semiconductor wafer 1 to be input. The defect inspection device 240 for obtaining scratches, foreign matter, etc., which can obtain the manufacturing conditions, can be used in the desired process (may be within the process) in the manufacturing line 400 of the semiconductor wafer 1. As shown by 421, 422, 432, the semiconductor wafer 1 that needs to be inspected for defects such as scratches and foreign matter is inspected for defects such as damage and foreign matter. In FIG. 7, the defect inspection device 24◦ for scratches / contaminants, etc., is polished by the CMP device 200 and the surface of the semiconductor wafer 1 cleaned by the cleaning device 230 is subjected to defects such as scratches / contaminations. In FIG. 32, the defect inspection device 240 for scratches, foreign matter, etc. is used to inspect all or all of the semiconductor wafers 1 obtained from desired devices (equipment) constituting the production line 400. Sampling is performed in units of a unit or a predetermined number of units, and defects such as scratches and foreign substances generated on the surface of the semiconductor wafer 1 are inspected. Further, the defect inspection device 240 for scratches, foreign matter, etc. may be installed between required steps in the production line 400. In this case, although the number of the defect inspection devices 240 such as scratches / foreign matter increases, the defect such as scratches / foreign matter generated on the surface of the semiconductor wafer 1 can be regularly inspected.
43 0は、 動作試験が可能なほぼ完成した半導体素子に対して電気的 な特性の検査を行なうテスタである。 43 1はテスタ 43 0における電 気的な特性の検査処理を行なうコンピュータ等によって構成された処理 手段である。 従って、 テスタ 43 0の処理手段 43 1は、 半導体ウェハ 1毎における半導体素子 （半導体チップ） の電気的な特性結果を得るこ とができる。  Reference numeral 430 denotes a tester for inspecting electrical characteristics of a substantially completed semiconductor device capable of performing an operation test. Reference numeral 431 denotes processing means constituted by a computer or the like for performing an inspection process of the electrical characteristics in the tester 430. Therefore, the processing means 431 of the tester 430 can obtain the results of the electrical characteristics of the semiconductor elements (semiconductor chips) for each semiconductor wafer 1.
管理用コンピュータ 2 5 0は、 傷 '異物等の欠陥検査装置 240の処 理手段 24 1、 テスタ 43 0の処理手段 43 1、 製造装置の制御装置 4 1 1、 4 1 2、 4 1 3 ( 2 04 ) 、 4 1 4、 4 1 5とネッ トワーク 40 9で接続されている。 従って、 管理用コンピュータ 2 5 0は、 テスタ 4 3 0の処理手段 43 1から半導体ウェハ 1毎における半導体素子 （半導 体チップ） の電気的な特性結果が得られ、 半導体ウェハ単位での歩留ま リを算出することができる。 更に管理用コンピュータ 2 5 0は、 傷 .異 物等の欠陥検査装置 2 4 0の処理手段 2 1から製造工程毎の半導体ゥ ェハ 1毎の表面に発生した傷や異物について弁別して発生位置の座標も 含めて得ることができる。 即ち、 製造工程毎に表面に発生した傷や異物 を検出するためには、 第 3 3図 （ a ) に示すある製造工程に投入される 前の半導体ウェハ 1の表面に存在する傷や異物 4 4 1 と、 第 3 3図 （ b ) に示す投入された後 （上記ある製造工程で製造された後） の半導体ゥェ ハ 1の表面に存在する傷や異物 4 4 1 、 4 4 2とを比較して、 同じ位置 座標に検出されたのは投入される前の 1つ前の工程或いは全ての前工程 において発生した傷や異物 4 4 1 と判定して消去し、 異なる位置座標に 新たに検出されたのはこのある製造工程によって発生した傷や異物 4 4 2と判定する。 これらの判定処理は、 傷 ·異物等の欠陥検査装置 2 4 0 の処理手段 2 4 1で行なっても良い。 The management computer 250 includes processing means 24 1 for the defect inspection device 240 for scratches and foreign matter, processing means 43 1 for the tester 430, and control devices 4 1 1, 4 1 2 and 4 1 3 for the manufacturing equipment ( 204), 414, 415 and network 409. Therefore, the management computer 250 obtains the electrical characteristic results of the semiconductor elements (semiconductor chips) for each semiconductor wafer 1 from the processing means 431 of the tester 43, and the yield per semiconductor wafer. Can be calculated. Further, the management computer 250 is damaged. From the processing means 21 of the defect inspection apparatus 240 for objects and the like, it is possible to discriminate scratches and foreign substances generated on the surface of each semiconductor wafer 1 in each manufacturing process and obtain the coordinates including the coordinates of the generated positions. That is, in order to detect the scratches and foreign substances generated on the surface in each manufacturing process, the scratches and foreign substances existing on the surface of the semiconductor wafer 1 before being put into a certain manufacturing process shown in FIG. 4 1, as shown in FIG. 33 (b), the scratches and foreign substances 4 4 1, 4 4 2 existing on the surface of the semiconductor wafer 1 after being charged (after being manufactured in the above-mentioned manufacturing process). Is compared, the one detected at the same position coordinate is judged to be the scratch or foreign matter generated in the previous process or all the previous processes before input, and erased. Are determined to be scratches or foreign substances 442 caused by this certain manufacturing process. These determination processes may be performed by the processing means 241 of the defect inspection device 240 for flaws and foreign matter.
即ち、 管理用コンピュータ 2 5 0は、 傷 ·異物等の欠陥検査装置 2 4 0の処理手段 2 4 1から得られる製造工程毎の半導体ウェハ 1毎の表面. に発生した発生位置の座標も含めた異物の情報と、 テスタ 4 3 0の処理 手段 4 3 1から得られる半導体ウェハ 1毎における半導体素子 （半導体 チップ） の電気的な特性結果の情報とから、 製造工程毎に、 第 3 4図〜 第 3 6図に示すようなウェハ単位での異物の存在するチップ数に対する 異物無チップと異物有チップとの各々にける歩留ま りを算出することが できる。 第 3 4図〜第 3 6図の各々は、 ある製造工程において、 所定の 枚数の半導体ウェハに亘つての、 ウェハ単位での異物の存在するチップ 数における異物無チップの歩留ま リと異物有チップの歩留ま リとの関係 を示したものである。  That is, the management computer 250 includes the coordinates of the position of occurrence on the surface of each semiconductor wafer 1 for each manufacturing process obtained from the processing means 241 of the defect inspection device 240 for scratches and foreign matter. For each manufacturing process, the information on the foreign matter that has been generated and the information on the electrical characteristics of the semiconductor elements (semiconductor chips) for each semiconductor wafer 1 obtained from the processing means 431 of the tester 4340 are used. ~ Yield for each of the chip having no foreign matter and the chip having foreign matter can be calculated with respect to the number of chips having foreign matter on a wafer basis as shown in Fig. 36. Each of FIGS. 34 to 36 shows, in a certain manufacturing process, the yield and the foreign matter of a chip without foreign matter in the number of chips having foreign matter per wafer over a predetermined number of semiconductor wafers. This shows the relationship with the yield of the existing chips.
第 3 4図に示す場合は、 ウェハ単位において、 異物の存在するチップ 数 （異物有チップ数） が増加するに従って異物有チップの歩留ま り （ 1 枚のウェハから得られる全チップ数に対する異物有チップの良品率 ： 異 物無チップは全て良品として取り扱う。 ） は低下し、 異物の存在するチ ップ数 （異物有チップ数） が増加しても異物無チップの歩留ま リ （ 1枚 のウェハから得られる異物無チップの全数に対する異物無チップの良品 率） は高い一定の値であることを示す。 即ち、 ある製造工程から、 第 3 4図に示すデータが得られた場合、 異物が正常に検出されていることが わかると共に、 異物が主な不良原因と判定することができ、 その結果を 表示手段 2 5 2に表示することもできる。 In the case shown in Fig. 34, as the number of chips with foreign matter (the number of foreign matter-containing chips) increases in a wafer unit, the yield of foreign matter-containing chips (the number of foreign matter with respect to the total number of chips obtained from one wafer) Non-defective chip rate: different All non-product chips are handled as good products. ) Decreases, and even if the number of chips with foreign particles (the number of chips with foreign particles) increases, the yield of chips without foreign particles (the number of chips with no foreign particles relative to the total number of chips without foreign particles obtained from one wafer) The non-defective rate is a high and constant value. That is, when the data shown in Fig. 34 is obtained from a certain manufacturing process, it can be understood that the foreign matter is normally detected, and the foreign matter can be determined as the main cause of the defect, and the result is displayed. It can also be displayed in means 25 2.
第 3 5図に示す場合は、 ウェハ単位において、 異物の存在するチップ 数 （異物有チップ数） が増加するに従って異物有チップの歩留まリ （ 1 枚のウェハから得られる全チップ数に対する異物有チップの良品率 ： 異 物無チップは全て良品として取り扱う。 ） は低下し、 異物の存在するチ ップ数 （異物有チップ数） が増加するに従って異物無チップの歩留まり ( 1枚のウェハから得られる異物無チップの全数に対する異物無チップ の良品率） も低下していることを示す。 即ち、 異物無チップの歩留ま り も異物の存在するチップ数 （異物有チップ数） に関係していることから、 異物無チップ上に異物が存在しているのに係らず、 検出できていないこ とを示す。 従って、 ある製造工程から、 第 3 5図に示すデータが得られ た場合、 異物が正常に検出できていないことがわかると共に、 異物が主 な不良原因と判定することができ、 その結果を表示手段 2 5 2に表示す ることもできる。 管理用コンピュータ 2 5 0が第 3 5図に示す結果が得 られたら、 傷 ·異物等の欠陥検査装置 2 4 0の処理手段 2 4 1 にフィー ドパック して、 見落とし無く検査できるように感度調整などをする必要 がある。 或いは、 さらに高感度の異物検査装置を用いる必要がある。 具 体的には、 検査時間を長くする、 または光あるいは S E M式の外観検査 装置を用いる等の対策が考えられる。  In the case shown in Fig. 35, as the number of chips with foreign particles (the number of chips with foreign particles) increases on a wafer basis, the yield of chips with foreign particles (the number of foreign particles relative to the total number of chips obtained from one wafer) Non-defective chip rate: All chips without foreign substances are treated as non-defective products.) As the number of chips with foreign substances (number of chips with foreign substances) increases, the yield of chips without foreign substances (from one wafer) This indicates that the percentage of non-contaminated chips with respect to the total number of obtained non-contaminated chips is also lower. That is, since the yield of chips without foreign matter is also related to the number of chips with foreign matter (the number of chips with foreign matter), detection is possible regardless of the presence of foreign matter on the chip without foreign matter. Indicates that there is not. Therefore, if the data shown in Fig. 35 is obtained from a certain manufacturing process, it can be understood that foreign matter has not been detected normally, and foreign matter can be determined as the main cause of failure, and the result is displayed. It can also be displayed in means 25 2. When the management computer 250 obtains the results shown in Fig. 35, feed it into the processing means 241 of the defect inspection device 240 for scratches and foreign matter, and adjust the sensitivity so that inspection can be performed without oversight. You need to do something like that. Alternatively, it is necessary to use a more sensitive foreign substance inspection device. Specifically, measures such as prolonging the inspection time or using a light or SEM type visual inspection device can be considered.
第 3 6図に示す場合は、 ウェハ単位において、 異物の存在するチップ 数 （異物有チップ数） が増加するに従って異物有チップの歩留ま りは低 下し、 異物の存在するチップ数 （異物有チップ数） が増加しても異物無 チップの歩留ま リは異物有チップの歩留ま リと同様に低くほぼ一定の値 であることを示す。 即ち、 異物無チップの歩留まりも異物の存在するチ ップ数 （異物有チップ数） に関係せずに、 歩留まりを下げていることか らして、 歩留ま りを下げている不良原因が異物以外 （例えばプロセス要 因） にもあることを示している。 もし、 異物有チップの歩留ま りも異物 の存在するチップ数 （異物有チップ数） に関係せずに一定であれば、 歩 留まりを下げている不良原因が異物以外であることがわかる。 従って、 ある製造工程から、 第 3 6図に示すデータが得られた場合、 歩留ま りを 下げている不良原因が異物以外 （例えばプロセス要因） にもあると判定 することができ、 その結果を表示手段 2 5 2に表示することもできる。 In the case shown in Fig. 36, the chips with foreign matter exist in wafer units. As the number (the number of foreign chips) increases, the yield of foreign chips decreases, and even if the number of foreign chips (the number of foreign chips) increases, the yield of foreign chips does not increase. It shows a low and almost constant value, similar to the yield of chips with foreign matter. In other words, the yield of chips without foreign matter is not related to the number of chips with foreign matter (the number of chips with foreign matter), but the yield is lowered. It indicates that there are other factors (for example, process factors). If the yield of foreign particles is constant irrespective of the number of chips with foreign particles (the number of foreign particles), it can be understood that the cause of the decrease in yield is other than foreign particles. Therefore, if the data shown in Fig. 36 is obtained from a certain manufacturing process, it can be determined that the cause of the defect that reduces the yield is other than foreign matter (for example, process factors), and as a result, Can be displayed on the display means 25 2.
また管理用コンピュータ 2 5 0は、 傷 ·異物等の欠陥検査装置 2 4 0 の処理手段 2 4 1から得られる製造工程毎の半導体ウェハ毎の表面に発 生した発生位置の座標も含めた異物の情報と、 テスタ 4 3 0の処理手段 4 3 1から得られる半導体ウェハ 1毎における半導体素子 （半導体チッ プ） の電気的な特性結果の情報とから、 製造工程毎に、 第 3 7図に示す ようなロッ ト単位での異物の存在するチップ数 （異物有チップ数） の変 化と異物無チップについて歩留ま りの変化と異物有チップについての歩 留ま りの変化を算出することができる。 異物有チップについての歩留ま リは、 本来異物有チップ数と相関関係があるはずである。 即ち、 異物有 チップ数が減少すれば、 異物有チップについての歩留ま りは向上し、 有 チップ数が増加すれば、 異物有チップについての歩留ま りは悪くなるは ずである。 他方、 異物について確実に検査できている場合には、 異物無 チップについての歩留ま りは、 異物有チップ数と相関関係がないはずで ある。 従って、 異物について確実に検査できていると仮定した場合、 異 物無チップについての歩留ま りが異物有チップ数と相関がとれない場合 には、 異物無チップについて歩留ま りを下げている原因として異物以外 (例えばプロセス要因） であることを判定することができる。 In addition, the management computer 250 is provided with a foreign substance including coordinates of a generation position generated on the surface of each semiconductor wafer in each manufacturing process obtained from the processing means 241 of the defect inspection apparatus 240 such as a scratch and a foreign substance. The information of the electrical characteristics of the semiconductor elements (semiconductor chips) for each semiconductor wafer 1 obtained from the processing means 431 of the tester 4330 is shown in FIG. Calculate the change in the number of chips with foreign particles (the number of chips with foreign particles), the change in yield for chips with no foreign particles, and the change in yield for chips with foreign particles in lot units as shown in the figure. Can be. The yield of chips with foreign particles should have a correlation with the number of chips with foreign particles. That is, if the number of foreign chips decreases, the yield of foreign chips increases, and if the number of foreign chips increases, the yield of foreign chips must decrease. On the other hand, if foreign matter can be reliably inspected, the yield for chips without foreign matter should not be correlated with the number of chips with foreign matter. Therefore, if it is assumed that foreign matter can be reliably inspected, If the yield of a chip without a substance cannot be correlated with the number of chips with a foreign substance, it is determined that the cause of the decrease in the yield of a chip without a foreign substance is other than a foreign substance (for example, a process factor). be able to.
また管理用コンピュータ 2 5 0は、 傷 ·異物等の欠陥検査装置 2 4 0 の処理手段 2 4 1から得られる製造工程毎の半導体ウェハ毎の表面に発 生した発生位置の座標も含めた異物の情報と、 テスタ 4 3 0の処理手段 4 3 1から得られる半導体ウェハ 1毎における半導体素子 （半導体チッ プ） の電気的な特性結果の情報とから、 製造工程毎に、 第 3 8図に示す ような半導体ウェハ単位または複数枚に亘る半導体ウェハでの 1チップ 内に存在する異物数とそのチップについての良品 （良品としては完全良 品とビッ ト救済などで良品になるものとがある。 ） 、 不良品の数との関 係を算出することができる。 当然、 1チップ内に存在する異物数が増加 すると、 そのチップが不良品になる確率は高くなるはずである。 即ち、 1チップ内に存在する異物数が増加すると、 本来は不良品になる確率 = (不良品のチップ数 良品のチップ数） が高くなるはずである。 もし、 この関係が成立する場合には、 不良発生原因の主たるものが異物による ものと判定でき、 もしこの関係が成立しない場合には、 不良発生原因の 主たるものが異物以外のプロセス要因であるものとして判定することが できる。  In addition, the management computer 250 is provided with a foreign substance including coordinates of a generation position generated on the surface of each semiconductor wafer in each manufacturing process obtained from the processing means 241 of the defect inspection apparatus 240 such as a scratch and a foreign substance. The information of the electrical characteristics of the semiconductor elements (semiconductor chips) for each semiconductor wafer 1 obtained from the processing means 431 of the tester 4330 are shown in FIG. As shown below, the number of foreign substances present in one chip in a semiconductor wafer unit or a plurality of semiconductor wafers, and the non-defective product of the chip (a non-defective product includes a completely non-defective product and a non-defective product obtained by bit rescue). ), The relationship with the number of defective products can be calculated. Naturally, as the number of foreign substances in one chip increases, the probability that the chip becomes defective should increase. In other words, if the number of foreign substances present in one chip increases, the probability of a defective product = (the number of defective products and the number of non-defective products) should increase. If this relationship is established, it can be determined that the main cause of the failure is due to foreign matter, and if this relationship is not established, the main cause of the failure is a process factor other than the foreign matter. Can be determined.
また管理用コンピュータ 2 5 0は、 傷 ·異物等の欠陥検査装置 2 4 0 の処理手段 2 1から得られる製造工程毎の半導体ウェハ毎の表面に発 生した発生位置の座標も含めた異物の情報と、 テスタ 4 3 0の処理手段 4 3 1から得られる半導体ウェハ 1毎における半導体素子 （半導体チッ プ） の電気的な特性結果の情報とから、 第 3 9図に示すように同一半導 体ウェハについての製造工程順に、 異物無チップの歩留ま りと異物有チ ップの歩留ま リとの推移を算出することができる。 異物について確実に 検査できていると仮定した場合、 工程 Dおよび Gにおいては、 歩留まり を下げている原因の主が異物であると判定できるので、 異物の発生を防 止する対策を施せば良い。 異物について確実に検査できていると仮定し た場合、 工程 Eおよび Fにおいては、 歩留ま りを下げている原因が異物 以外であると判定することができると共に、 異物検査をやめることもで きる。 これにより、 経済的、 かつ効率的に検査装置を使用することがで さる。 Further, the management computer 250 is capable of detecting the foreign matter including the coordinates of the occurrence position generated on the surface of each semiconductor wafer in each manufacturing process obtained from the processing means 21 of the defect inspection device 240 for scratches and foreign matter. From the information and the information on the electrical characteristics of the semiconductor elements (semiconductor chips) for each semiconductor wafer 1 obtained from the processing means 431 of the tester 43, the same semiconductor as shown in FIG. It is possible to calculate the transition between the yield of a chip without foreign matter and the yield of a chip with foreign matter in the order of the manufacturing process of the body wafer. Make sure foreign matter Assuming that the inspection can be performed, in steps D and G, it is possible to determine that the cause of the decrease in yield is mainly foreign matter, and therefore measures should be taken to prevent the generation of foreign matter. Assuming that foreign matter can be reliably inspected, in processes E and F, it is possible to determine that the cause of the decrease in yield is other than foreign matter, and it is also possible to stop foreign matter inspection. Wear. This makes it possible to use the inspection equipment economically and efficiently.
以上異物について第 3 3図〜第 3 9図を用いて説明したが、 傷につい て適用することも可能であることは明らかである。  Although foreign substances have been described above with reference to FIGS. 33 to 39, it is clear that they can be applied to wounds.
また、 管理用コンピュータ 2 5 0には、 製造装置の制御装置 4 1 1、 4 1 2、 4 1 3 ( 2 04 ) 、 4 1 4、 4 1 5から、 少なくとも、 ロッ ト 単位毎の製造条件 （保守、 清掃等に関する情報も含む） が入力されて、 製造された半導体ウェハに対応させて検査データと一緒に記憶装置 2 5 1に格納されている。 従って、 管理用コンピュータ 2 5 0は、 各製造ェ 程における異物や傷等の発生原因を究明し、 その結果を製造装置の制御 装置 4 1 1、 4 1 2、 4 1 3 ( 2 04 ) 、 4 1 4、 4 1 5にフィードバ ックすることができると共に表示手段 2 5 2に表示などして出力するこ ともできる。 また、 管理用コンピュータ 2 50は、 半導体素子としての 歩留ま りを低下させている原因が所定の製造工程におけるプロセス要因 と判定した場合には、 記憶装置 2 5 1に格納された所定の製造工程にお ける過去の製造条件の推移から調整すべき製造条件を選定してその結果 を所定の製造工程を構成する製造装置の制御装置にフィードバックする ことができると共に表示手段 2 5 2に表示などして出力することもでき る。 各製造装置の制御装置 4 1 1、 4 1 2、 4 1 3 ( 2 04 ) 、 4 1 . 4 1 5は、 管理用コンピュータ 2 50からフィードバックされる情報に 基いて、 各製造装置の製造条件を制御することによって、 半導体素子を 高歩留ま リで製造することが可能となる。 産業上の利用可能性 In addition, the management computer 250 includes at least the manufacturing conditions for each lot from the control devices 411, 412, 413 (204), 4114 and 415 of the manufacturing equipment. (Including information on maintenance, cleaning, etc.) is input and stored in the storage device 251, together with the inspection data, corresponding to the manufactured semiconductor wafer. Therefore, the management computer 250 investigates the cause of the occurrence of foreign matter, scratches, etc. in each manufacturing process, and the result is used as the control device 411, 412, 413 (204), Feedback can be made to 414 and 415, and it can also be displayed on the display means 252 and output. In addition, when the management computer 250 determines that the cause of the decrease in the yield as a semiconductor element is a process factor in a predetermined manufacturing process, the management computer 250 stores the predetermined manufacturing data stored in the storage device 251. It is possible to select the manufacturing conditions to be adjusted from the transition of the past manufacturing conditions in the process and feed back the result to the control device of the manufacturing equipment that constitutes the specified manufacturing process, and display it on the display means 252. Can also be output. The control devices 4 1 1, 4 1 2, 4 1 3 (2 04) and 4 1. 4 1 5 of each manufacturing device are based on the information fed back from the management computer 250, and By controlling the It can be manufactured at high yields. Industrial applicability
以上のように、 本発明によれば、 半導体ウェハに対して研磨して平坦 化する際、 研磨の終了点を検出できるので、 研磨の過剰 · 不足等の不良 を防ぐことができ、 その結果半導体素子を高歩留ま りで、 且つ高スルー プッ トで製造することができる効果を奏する。  As described above, according to the present invention, the end point of polishing can be detected when the semiconductor wafer is polished and planarized, so that defects such as excessive and insufficient polishing can be prevented, and as a result, This has the effect that the device can be manufactured with a high yield and a high throughput.
また本発明によれば、 半導体ウェハに対して研磨して平坦化した際、 平坦化時の傷、 異物、 面あれ等の欠陥を検査してその結果を研磨工程に フィードバックすることにより、 不良を作り込むことを低減して、 半導 体素子を高歩留ま リで製造することができる効果を奏する。  Further, according to the present invention, when a semiconductor wafer is polished and flattened, defects such as scratches, foreign matter, surface roughness and the like at the time of flattening are inspected, and the result is fed back to the polishing process, whereby defects are reduced. The effect of reducing fabrication is that semiconductor elements can be manufactured at a high yield.
また本発明によれば、 半導体ウェハに対して研磨して平坦化する際、 残膜量を実時間でモニタして、 研磨レートの早い高速研磨と高精度な低 速研磨とを切り換え制御が可能となり、 その結果研磨による傷、 異物、 面あれ等の欠陥の発生を防止して半導体素子を高歩留ま りで、 且つ高ス ループッ トで製造することができる効果を奏する。  Also, according to the present invention, when polishing and flattening a semiconductor wafer, the amount of remaining film is monitored in real time, and switching between high-speed polishing with a high polishing rate and low-speed polishing with high accuracy can be controlled. As a result, it is possible to prevent the occurrence of defects such as scratches, foreign matter, surface roughness, etc. due to polishing, and to produce an effect that a semiconductor device can be manufactured with a high yield and with a high throughput.
また本発明によれば、 洗浄工程の前後で異物の検査を可能とできるの で、 洗浄による異物除去のモニタを実現でき、 歩留りの低下を未然に防 ぐことができる。  Further, according to the present invention, it is possible to inspect foreign substances before and after the cleaning step, so that it is possible to monitor the removal of foreign substances by cleaning, and to prevent a decrease in yield.
また本発明によれば、 傷や異物等の欠陥検査結果に基いて、 不良発生 原因を推定することが可能となり、 その結果早期に不良発生原因を取り 除く ことが可能となり、 半導体素子を高歩留ま りで製造することができ る効果を奏する。  Further, according to the present invention, it is possible to estimate the cause of the failure based on the result of the defect inspection such as a scratch or a foreign substance, and as a result, the cause of the failure can be removed at an early stage. It has the effect that it can be manufactured by stopping.
また本発明によれば、 平坦化すべき被研磨材に対して化学的、 且つ機 械的な研磨を施した際発生する傷や異物等の欠陥および面荒れを低減し て半導体装置 （半導体素子） を高歩留まりで製造することができる効果 を奏する。 Further, according to the present invention, a semiconductor device (semiconductor element) is provided which reduces defects and surface roughness such as scratches and foreign substances generated when a material to be planarized is subjected to chemical and mechanical polishing. That can be manufactured with high yield To play.
また本発明によれば、 化学的、 且つ機械的な研磨を用いて半導体基板 上に素子分離構造を欠陥を生じることなく形成することができる効果を 奏する。  Further, according to the present invention, there is an effect that an element isolation structure can be formed on a semiconductor substrate without causing defects by using chemical and mechanical polishing.
また本発明によれば、 化学的、 且つ機械的な研磨を用いて基板上にェ ツチングが難しい金属材料で配線パターンを欠陥を生じることなく形成 することができる効果を奏する。  Further, according to the present invention, there is an effect that a wiring pattern can be formed on a substrate by using chemical and mechanical polishing with a metal material which is difficult to etch without causing defects.
また本発明によれば、 不良の発生原因が傷や異物等の欠陥によるもの であるか否かについて究明できるようにしてその対策を施すことができ る効果を奏する。  Further, according to the present invention, it is possible to determine whether or not the cause of the defect is due to a defect such as a scratch or a foreign substance, and to take measures against the defect.
また本発明によれば、 欠陥検査工程またはその手段における欠陥検査 の信頼度を向上して高歩留ま リで半導体装置を製造することができる効 果を奏する。  Further, according to the present invention, it is possible to improve the reliability of the defect inspection in the defect inspection step or its means, and to produce a semiconductor device with a high yield.
このように、 本発明は、 半導体装置を製造する方法に適しているもの である。  As described above, the present invention is suitable for a method for manufacturing a semiconductor device.

Claims

請 求 の 範 囲 The scope of the claims
1 . 基板上に形成された被研磨材に対して化学的、 且つ機械的な研磨を 施して平坦化して半導体装置を製造する半導体装置の製造方法におい て、 前記被研磨材に対して化学的、 且つ機械的な研磨を施す際に該被 研磨材の残膜厚を測定し、 この測定された被研磨材の残膜厚に応じて 前記化学的、 且つ機械的な研磨を制御することを特徴とする半導体装 置の製造方法。 1. A method for manufacturing a semiconductor device in which a semiconductor device is manufactured by subjecting a material to be polished formed on a substrate to chemical and mechanical polishing and flattening to manufacture a semiconductor device. And measuring the remaining film thickness of the material to be polished when performing mechanical polishing, and controlling the chemical and mechanical polishing according to the measured remaining film thickness of the material to be polished. Characteristic manufacturing method of semiconductor device.
2 . 半導体基板上に形成された被研磨材に対して化学的、 且つ機械的な 研磨を施して平坦化して半導体装置を製造する半導体装置の製造方法 において、 前記被研磨材に対して化学的、 且つ機械的な研磨を施す際 に該被研磨材の残膜厚を測定し、 この測定された被研磨材の残膜厚に 応じて前記化学的、 且つ機械的な高速研磨から低速研磨に切り換え制 御することを特徴とする半導体装置の製造方法。  2. A method for manufacturing a semiconductor device in which a semiconductor device is manufactured by subjecting a material to be polished formed on a semiconductor substrate to chemical and mechanical polishing and flattening to manufacture a semiconductor device. And when the mechanical polishing is performed, the remaining film thickness of the material to be polished is measured. According to the measured remaining film thickness of the material to be polished, the chemical and mechanical polishing is changed from high-speed polishing to low-speed polishing. A method for manufacturing a semiconductor device, comprising controlling switching.
3 . 半導体基板上に薄い研磨ストツバ層を形成する研磨ストツバ層形成 工程と、 該研磨ス トツパ層も含めて前記半導体基板に対して素子分離 用の凹部を堀込むエッチング工程と、 該エッチング工程によって堀込 まれた凹部を絶縁膜で埋めるように成膜する絶縁膜成膜工程と、 該絶 縁膜成膜工程で成膜された絶縁膜に対して化学的、 且つ機械的な研磨 を施して平坦化して前記研磨ストツバ層の表面を露出する研磨工程と、 該研磨工程で露出した研磨ストツバ層を取り除く研磨ストツバ除去ェ 程と、 該研磨ストツバ除去工程で研磨ストツバ層が取り除かれた半導 体基板の表面を酸化して酸化層を形成する酸化工程とを有し、 前記半 導体基板に対して素子分離構造を形成することを特徴とする半導体装 置の製造方法。  3. a polishing stopper layer forming step of forming a thin polishing stopper layer on the semiconductor substrate, an etching step of digging a recess for element isolation in the semiconductor substrate including the polishing stopper layer, An insulating film forming step of forming a film so as to fill the dug recess with an insulating film; and chemically and mechanically polishing and flattening the insulating film formed in the insulating film forming step. Polishing step for exposing the surface of the polishing stove layer by polishing, removing the polishing stove layer exposed in the polishing step, and a semiconductor substrate from which the polishing stove layer has been removed in the polishing stove removing step. An oxidation step of oxidizing a surface of the semiconductor device to form an oxide layer, wherein an element isolation structure is formed on the semiconductor substrate.
4 . 基板上に絶縁膜パターンを形成する絶縁膜パターン形成工程と、 該 絶縁膜パターン形成工程で形成された絶縁膜パタ一ンの隙間に配線用 の金属材料を埋め込むように成膜する成膜工程と、 該成膜工程で成膜 された金属材料に対して化学的、 且つ機械的な研磨を施して平坦化す る研磨工程とを有し、 前記絶縁膜パターンの隙間に配線パターンを形 成することを特徴とする半導体装置の製造方法。 4. an insulating film pattern forming step of forming an insulating film pattern on the substrate; A film forming step of embedding a metal material for wiring in a gap of the insulating film pattern formed in the insulating film pattern forming step; and a chemical forming method for the metal material formed in the film forming step. And a polishing step of performing mechanical polishing to make the surface flat by mechanical polishing, and forming a wiring pattern in a gap between the insulating film patterns.
. 基板上に形成された被研磨材に対して化学的、 且つ機械的な研磨を 施して平坦化する研磨工程と、 該研磨工程によって平坦化された研磨 面に発生する面荒れまたは欠陥についての発生状態を検査する検査ェ 程とを有し、 該検査工程で検査された研磨面における面荒れまたは欠 陥についての発生状態を前記研磨工程にフィ一ドバック して研磨条件 を制御することを特徴とする半導体装置の製造方法。A polishing step of performing a chemical and mechanical polishing on a material to be polished formed on a substrate to flatten the material, and a method for removing surface roughness or defects generated on the polished surface flattened by the polishing step. An inspection step of inspecting the occurrence state, wherein the occurrence state of surface roughness or defect on the polished surface inspected in the inspection step is fed back to the polishing step to control the polishing conditions. Manufacturing method of a semiconductor device.
. 基板上に形成された被研磨材に対して化学的、 且つ機械的な研磨を 施して平坦化する研磨工程と、 該研磨工程によって平坦化された研磨 面を洗浄する洗浄工程と、 該洗浄工程によって洗浄された研磨面に発 生する面荒れまたは欠陥についての発生状態を検査する検査工程とを 有し、 該検査工程で検査された研磨面における面荒れまたは欠陥につ いての発生状態を前記研磨工程にフイードバックして研磨条件を制御 することを特徴とする半導体装置の製造方法。A polishing step of performing chemical and mechanical polishing on a material to be polished formed on a substrate to planarize the polishing object; a cleaning step of cleaning the polished surface planarized by the polishing step; An inspection process for inspecting the state of occurrence of surface roughness or defects occurring on the polished surface cleaned in the process, and detecting the occurrence state of surface roughness or defects on the polished surface inspected in the inspection process. A method for manufacturing a semiconductor device, comprising: feeding back to the polishing step to control polishing conditions.
. 基板上に形成された被研磨材に対して化学的、 且つ機械的な研磨を 施して平坦化する研磨工程と、 該研磨工程によって平坦化された研磨 面を洗浄する洗浄工程と、 該洗浄工程の前と後とにおいて研磨面に発 生する面荒れまたは欠陥についての発生状態を検査する検査工程とを 有し、 該検査工程で検査された研磨面における面荒れまたは欠陥につ いての発生状態を前記研磨工程にフィ一ドバック して研磨条件を制御 することを特徴とする半導体装置の製造方法。A polishing step of performing chemical and mechanical polishing on a material to be polished formed on a substrate to planarize the polishing object; a cleaning step of cleaning the polished surface planarized by the polishing step; An inspection process for inspecting the state of occurrence of surface roughness or defects occurring on the polished surface before and after the process, wherein the occurrence of surface roughness or defects on the polished surface inspected in the inspection process is included. A method of manufacturing a semiconductor device, comprising: controlling a polishing condition by feeding back a state to the polishing step.
. 基板上に形成された被研磨材に対して化学的、 且つ機械的な研磨を 施して平坦化する研磨工程と、 該研磨工程によって平坦化された研磨 面に発生する面荒れと区別して傷や異物についての発生状態を検査す る検査工程とを有し、 該検査工程で検査された研磨面における傷ゃ異 物についての発生状態を前記研磨工程にフィ一ドパックすることを特 徴とする半導体装置の製造方法。 . Chemical and mechanical polishing of the material to be polished formed on the substrate A polishing step of performing polishing and flattening, and an inspection step of inspecting the state of occurrence of scratches and foreign matter in distinction from surface roughness occurring on the polished surface flattened by the polishing step. A method for manufacturing a semiconductor device, characterized in that a state of occurrence of a flaw on the polished surface is fed-packed in the polishing step.
. 製造ラインの所定の製造工程において製造された複数の半導体基板 に亘つての半導体基板上の各半導体装置毎の欠陥の発生状態を検査す る欠陥検査工程と、 前記製造ラインによって製造された複数の半導体 基板に亘つての半導体基板から得られる各半導体装置についての電気 的特性検査を行なって良品または不良品の判定を行なう電気的特性検 査工程と、 前記欠陥検査工程で検査された複数の半導体基板上の各半 導体装置毎の異物の発生状態と前記電気的特性検査工程で判定された 複数の半導体基板に亘つての各半導体装置の良品または不良品の結果 との相関関係に基いて、 不良の発生原因が欠陥によるものであるか否 かについて究明する不良発生原因究明工程とを有することを特徴とす る半導体装置の製造方法。 A defect inspection step of inspecting a state of occurrence of a defect for each semiconductor device on the semiconductor substrate over a plurality of semiconductor substrates manufactured in a predetermined manufacturing process of the manufacturing line; and a plurality of semiconductor devices manufactured by the manufacturing line. An electrical characteristic inspection step of performing an electrical characteristic inspection on each semiconductor device obtained from the semiconductor substrate over the semiconductor substrate to determine a non-defective product or a defective product; and a plurality of semiconductor devices inspected in the defect inspection process. Based on the correlation between the state of generation of foreign matter for each semiconductor device on the semiconductor substrate and the results of non-defective products or defective products of each semiconductor device over the plurality of semiconductor substrates determined in the electrical characteristic inspection step. A method for determining the cause of a failure to determine whether the cause of the failure is due to a defect.
0 . 製造ラインの所定の製造工程において製造された複数の半導体基 板に亘つての半導体基板上の各半導体装置毎の欠陥の発生状態を検査 する欠陥検査工程と、 前記製造ラインによって製造された複数の半導 体基板に亘つての半導体基板から得られる各半導体装置についての電 気的特性検査を行なって良品または不良品の判定を行なって良品率ま たは不良品率を算出する電気的特性検査工程と、 前記欠陥検査工程で 検査された複数の半導体基板上の各半導体装置毎の異物の発生状態と 前記電気的特性検査工程で算出された複数の半導体基板に亘つての各 半導体装置の良品率または不良品率との相関関係に基いて、 不良の発 生原因が欠陥によるものであるか否かについて究明する不良発生原因 究明工程とを有することを特徴とする半導体装置の製造方法。 0. a defect inspection step of inspecting a state of occurrence of a defect for each semiconductor device on the semiconductor substrate over a plurality of semiconductor substrates manufactured in a predetermined manufacturing process of the manufacturing line; The electrical characteristics of each semiconductor device obtained from a semiconductor substrate over a plurality of semiconductor substrates are determined by determining the non-defective or defective products by performing an electrical characteristic test and calculating the non-defective or defective product ratio. A characteristic inspection step, a state of foreign matter occurrence for each semiconductor device on the plurality of semiconductor substrates inspected in the defect inspection step, and a semiconductor device over the plurality of semiconductor substrates calculated in the electrical characteristic inspection step The cause of failure to determine whether the cause of failure is due to defects based on the correlation with the percentage of good or defective products A method for manufacturing a semiconductor device, comprising: an investigation step.
1 . 製造ラインの所定の製造工程において製造された複数の半導体基 板に亘つての半導体基板上の各半導体装置毎の欠陥の発生状態を検査 する欠陥検査工程と、 製造ラインによって製造された複数の半導体基 板に亘つての半導体基板から得られる各半導体装置についての電気的 特性検査を行なって良品または不良品の判定を行なう電気的特性検査 工程と、 前記前記電気的特性検査工程で判定された複数の半導体基板 に亘つての各半導体装置の良品または不良品の結果と前記欠陥検査ェ 程で検査された複数の半導体基板上の各半導体装置毎の欠陥の発生状 態との相関関係に基いて、 前記欠陥検査工程における不良品となる欠 陥の発生状態を検査できているか否かを評価し、 この評価結果を前記 欠陥検査工程にフィ一ドバックする欠陥検査評価工程とを有すること を特徴とする半導体装置の製造方法。  1. A defect inspection step of inspecting the state of occurrence of a defect for each semiconductor device on a semiconductor substrate over a plurality of semiconductor substrates manufactured in a predetermined manufacturing process of a manufacturing line, and a plurality of semiconductor devices manufactured by the manufacturing line. An electrical characteristic inspection step of performing an electrical characteristic inspection on each semiconductor device obtained from the semiconductor substrate over the semiconductor substrate to determine a non-defective or defective product; and an electrical characteristic inspection step. The correlation between the result of non-defective product or defective product of each semiconductor device over the plurality of semiconductor substrates and the state of occurrence of defects for each semiconductor device on the plurality of semiconductor substrates inspected in the defect inspection step. Then, it is evaluated whether or not the state of occurrence of a defect as a defective product in the defect inspection step has been inspected, and the result of the evaluation is fed back to the defect inspection step. The method of manufacturing a semiconductor device characterized by having an evaluation process.
2 . 製造ラインの所定の製造装置において製造された複数の半導体基 板に亘つての半導体基板上の各半導体装置毎の欠陥の発生状態を検査 する欠陥検査手段と、 前記製造ラインによって製造された複数の半導 体基板に亘つての半導体基板から得られる各半導体装置についての電 気的特性検査を行なって良品または不良品の判定を行なう電気的特性 検査手段と、 前記欠陥検査手段で検査された複数の半導体基板上の各 半導体装置毎の異物の発生状態と前記電気的特性検査手段で判定され た複数の半導体基板に亘つての各半導体装置の良品または不良品の結 果との相関関係に基いて、 不良の発生原因が欠陥によるものであるか 否かについて究明する不良発生原因究明手段とを有し、 該不良発生原 因究明手段で究明された不良発生原因を所定の製造装置にフィ一ドバ ックすることを特徴とする半導体装置の製造システム。  2. Defect inspection means for inspecting a state of occurrence of a defect of each semiconductor device on a semiconductor substrate over a plurality of semiconductor substrates manufactured by a predetermined manufacturing apparatus of a manufacturing line; An electrical characteristic inspection unit that performs an electrical characteristic inspection on each semiconductor device obtained from the semiconductor substrate over a plurality of semiconductor substrates to determine a non-defective product or a defective product; Between the generation state of foreign substances for each semiconductor device on the plurality of semiconductor substrates and the results of non-defective or defective products of each semiconductor device over the plurality of semiconductor substrates determined by the electrical characteristic inspection means. And a means for investigating whether or not the defect is caused by a defect based on the defect originating means. Manufacturing system for a semiconductor device, which comprises Fi one Dubai click the manufacturing apparatus.
3 . 製造ラインの所定の製造装置において製造された複数の半導体基 板に亘つての半導体基板上の各半導体装置毎の欠陥の発生状態を検査 する欠陥検査手段と、 前記製造ラインによって製造された複数の半導 体基板に亘つての半導体基板から得られる各半導体装置についての電 気的特性検査を行なって良品または不良品の判定を行なって良品率ま たは不良品率を算出する電気的特性検査手段と、 前記欠陥検査手段で 検査された複数の半導体基板上の各半導体装置毎の異物の発生状態と 前記電気的特性検査手段で算出された複数の半導体基板に亘つての各 半導体装置の良品率または不良品率との相関関係に基いて、 不良の発 生原因が欠陥によるものであるか否かについて究明する不良発生原因 究明手段とを有し、 該不良発生原因究明手段で究明された不良発生原 因を所定の製造装置にフィードバックすることを特徴とする半導体装 置の製造システム。 3. A plurality of semiconductor substrates manufactured by a predetermined manufacturing equipment on the manufacturing line Defect inspection means for inspecting the state of occurrence of defects for each semiconductor device on the semiconductor substrate over the board; and each semiconductor obtained from the semiconductor substrate over a plurality of semiconductor substrates manufactured by the manufacturing line. Electrical characteristic inspection means for performing an electrical characteristic inspection on the device to determine a non-defective or defective product and calculating a non-defective or defective rate, and a plurality of semiconductor substrates inspected by the defect inspection means Based on the correlation between the state of generation of foreign matter for each semiconductor device and the percentage of non-defective products or defective products of each semiconductor device over a plurality of semiconductor substrates calculated by the electrical characteristic inspection means, Means for determining the cause of failure to determine whether the cause of the failure is due to a defect, and feed back the cause of failure determined by the means for determining the cause of failure to a predetermined manufacturing apparatus. Manufacturing system of the semiconductor equipment, characterized in that.
4 . 製造ラインの所定の製造装置において製造された複数の半導体基 板に亘つての半導体基板上の各半導体装置毎の欠陥の発生状態を検査 する欠陥検査手段と、 製造ラインによって製造された複数の半導体基 板に亘つての半導体基板から得られる各半導体装置についての電気的 特性検査を行なって良品または不良品の判定を行なう電気的特性検査 手段と、 前記前記電気的特性検査手段で判定された複数の半導体基板 に直っての各半導体装置の良品または不良品の結果と前記欠陥検査ェ 程で検査された複数の半導体基板上の各半導体装置毎の欠陥の発生状 態との相関関係に基いて、 前記欠陥検査手段における不良品となる欠 陥の発生状態を検査できているか否かを評価し、 この評価結果を前記 欠陥検査手段にフィ一ドバックする欠陥検査評価手段とを有すること を特徴とする半導体装置の製造 4. Defect inspection means for inspecting the state of occurrence of defects for each semiconductor device on a semiconductor substrate over a plurality of semiconductor substrates manufactured by predetermined manufacturing equipment on a manufacturing line, and a plurality of semiconductor devices manufactured by the manufacturing line. Electrical characteristic inspection means for performing an electrical characteristic inspection on each semiconductor device obtained from the semiconductor substrate over the semiconductor substrate to determine a non-defective product or a defective product; and The correlation between the result of non-defective product or defective product of each semiconductor device directly on the plurality of semiconductor substrates and the state of occurrence of defects of each semiconductor device on the plurality of semiconductor substrates inspected in the defect inspection step. The defect inspection means evaluates whether the defect inspection means has inspected the state of occurrence of a defect as a defective product, and feeds the evaluation result back to the defect inspection means. Manufacturing a semiconductor device and having an evaluation unit
PCT/JP1998/000669 1997-02-19 1998-02-18 Method for manufacturing semiconductor device and system therefor WO1998037576A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004038327A1 (en) * 2002-10-24 2004-05-06 Hitachi, Ltd. Film-thickness inspection method for thin-film device and production method for thin-film device

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000306963A (en) 1999-04-22 2000-11-02 Mitsubishi Electric Corp Semiconductor device and its manufacture, and semiconductor manufacture device and manufacture system
US6671051B1 (en) * 1999-09-15 2003-12-30 Kla-Tencor Apparatus and methods for detecting killer particles during chemical mechanical polishing
US7041599B1 (en) * 1999-12-21 2006-05-09 Applied Materials Inc. High through-put Cu CMP with significantly reduced erosion and dishing
KR20020012387A (en) * 2000-08-07 2002-02-16 윤종용 Method for polishing in semiconductor device processing and apparatus for performing the same
JP2002124496A (en) 2000-10-18 2002-04-26 Hitachi Ltd Method and apparatus for detecting and measuring end point of polishing process, method for manufacturing semiconductor device using the same, and apparatus for manufacturing the same
JP3757143B2 (en) 2001-10-11 2006-03-22 富士通株式会社 Semiconductor device manufacturing method and semiconductor device
JP4529366B2 (en) * 2003-03-26 2010-08-25 株式会社ニコン Defect inspection apparatus, defect inspection method, and hole pattern inspection method
JP4694150B2 (en) * 2003-06-20 2011-06-08 東京エレクトロン株式会社 Processing method and processing system
JP2008155292A (en) * 2006-12-21 2008-07-10 Disco Abrasive Syst Ltd Substrate processing method and processing apparatus
JP2008159651A (en) * 2006-12-21 2008-07-10 Elpida Memory Inc Multilayer wiring, laminated aluminum wiring, semiconductor device, and method for manufacturing the same
JP2010030007A (en) * 2008-07-30 2010-02-12 Disco Abrasive Syst Ltd Grinder and scratch detection apparatus
JP2015076555A (en) * 2013-10-10 2015-04-20 株式会社ディスコ Processing device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05326690A (en) * 1992-05-14 1993-12-10 Sony Corp Isolation region formation method, manufacture of semiconductor device, and semiconductor device
JPH06295892A (en) * 1992-10-15 1994-10-21 Nec Corp Polishing method and formation of metal wiring
JPH07221055A (en) * 1994-02-02 1995-08-18 Sumitomo Metal Ind Ltd Wiring formation method
JPH0825194A (en) * 1994-07-12 1996-01-30 Mitsubishi Materials Shilicon Corp Method and device for polishing semiconductor wafer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05326690A (en) * 1992-05-14 1993-12-10 Sony Corp Isolation region formation method, manufacture of semiconductor device, and semiconductor device
JPH06295892A (en) * 1992-10-15 1994-10-21 Nec Corp Polishing method and formation of metal wiring
JPH07221055A (en) * 1994-02-02 1995-08-18 Sumitomo Metal Ind Ltd Wiring formation method
JPH0825194A (en) * 1994-07-12 1996-01-30 Mitsubishi Materials Shilicon Corp Method and device for polishing semiconductor wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004038327A1 (en) * 2002-10-24 2004-05-06 Hitachi, Ltd. Film-thickness inspection method for thin-film device and production method for thin-film device

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