+

WO1998014989A1 - Element de memoire a condensateur polymere - Google Patents

Element de memoire a condensateur polymere Download PDF

Info

Publication number
WO1998014989A1
WO1998014989A1 PCT/DE1997/001666 DE9701666W WO9814989A1 WO 1998014989 A1 WO1998014989 A1 WO 1998014989A1 DE 9701666 W DE9701666 W DE 9701666W WO 9814989 A1 WO9814989 A1 WO 9814989A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory cell
storage
capacitor
selection transistor
polymer
Prior art date
Application number
PCT/DE1997/001666
Other languages
German (de)
English (en)
Inventor
Walter Hartner
Günther SCHINDLER
Carlos Mazure-Espejo
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1998014989A1 publication Critical patent/WO1998014989A1/fr

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures

Definitions

  • the invention relates to a memory cell which has the following features:
  • a selection transistor a selection transistor; a storage capacitor connected to the selection transistor and containing a storage dielectric,
  • Such memory cells have long been known in a wide variety of designs for use in read / write memories.
  • a problem with increasing integration density and the associated reduction in size of the memory cells is always the integration of the storage capacitors, the dimensions of which, owing to the capacities to be retained and the dielectric constant of the storage dielectric remaining approximately the same, were not allowed to decrease as much as the dimensions of the selection transistors.
  • This problem appears to be solved by the use of paraelectric or ferroelectric substances such as perovskite-like materials as the storage dielectric, which have a very large dielectric constant (up to 400) and therefore allow the dimensions of the storage capacitors to be reduced while maintaining the capacitance.
  • a deposition temperature is required for the deposition of the above-mentioned paraelectric or ferroelectric substances, which is above the melting temperature of aluminum, which is used as the preferred metal for metallizing a structure from selection transistors, so that the metallization of the structure from selection transistors takes place only after the storage capacitors have been completed can. Therefore, completely prefabricated structures made of selection transistors cannot be used to apply the storage capacitors.
  • the aim of the invention is to develop the memory cell mentioned at the outset in such a way that, despite the use of a paraelectric or ferroelectric substance as the storage dielectric, it is simple to manufacture without the above-mentioned. To have disadvantages and to specify a method for their production.
  • the storage dielectric is a polymer
  • the deposition temperatures of the polymers which are suitable as storage dielectrics for the storage cell described are considerably lower than the melting temperature of, for example, aluminum. It is therefore in the manufacture of memory arrays that are made up of a number of those described above. benen memory cells exist, possible to apply the storage capacitors on completely prefabricated structures from selection transistors and thus to simplify the manufacturing process or to make it less critical with regard to contamination effects.
  • a subset of the polymers which have paraelectric or ferroelectric properties are copolymers which are therefore suitable as a storage dielectric, as proposed in one embodiment of the invention.
  • the area of use of the memory cells according to the invention coincides with the area of use of previous memory cells, so that one
  • DRAM Dynamic Random Access Memory
  • ROM Read Only Memory
  • the polymers nylon 11, nylon 9, nylon 7 or nylon 5 can, for example, as provided in one embodiment of the invention, be used as storage dielectrics with ferroelectric properties.
  • a further embodiment of the invention provides that the copolymers vinylidene fluoride or trifluoroethylene are used as storage dielectrics with ferroelectric properties.
  • the structures of the storage capacitors used are not limited when using polymers or copolymers as storage dielectrics compared to previously known capacitor structures.
  • One embodiment of the invention thus provides for the storage capacitors to be designed as stacked capacitors. ren, in this embodiment a plurality of layers of conductive material and storage dielectric are alternately arranged above the selection transistor.
  • a further embodiment provides for the capacitors to be designed as trench capacitors, the storage capacitor being arranged in a pot-like manner on one level above the selection transistor.
  • a further embodiment provides for the storage capacitor to be designed as a fin capacitor or fin-stacked capacitor.
  • the capacitor here has a structure as described, for example, in US Pat. No. 5,290,726.
  • Embodiments are the subject of claims 10 or 11.
  • the two electrodes and the storage dielectric of the storage capacitor are deposited in several steps over the selection transistor, wherein the structure of the selection transistors is preferably metallized before deposition of the respective storage capacitors.
  • FIG. 1 shows an embodiment of a memory cell according to the invention in cross section.
  • storage capacitor 4 is arranged as a trench capacitor above a selection transistor 2, a first electrode 8 of the storage capacitor 4 being conductively connected to a first connection 3 of the selection transistor.
  • the first electrode 8 covers the entire surface of a pot-like depression 7 in a first main area 5 above the selection transistor 2 and sections of the first main surface 5 adjacent to the pot-like depression 7.
  • a storage dielectric 6 is arranged above the first electrode 8 of the storage capacitor 4 and covered by a second electrode 10.
  • a polymer e.g. B. used a copolymer. This polymer can have ferroelectric or paraelectric properties.
  • a polymer z. B. nylon 11, nylon 9, nylon 7 or nylon 5 or vinylidene fluoride or trifluoroethylene can be used.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un élément de mémoire (1) comportant un transistor de sélection (2) ainsi qu'un condensateur (4) relié à ce dernier, le condensateur (4) renfermant un diélectrique (8) constitué d'un polymère présentant notamment des caractéristiques ferro-électriques.
PCT/DE1997/001666 1996-09-30 1997-08-07 Element de memoire a condensateur polymere WO1998014989A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19640239A DE19640239A1 (de) 1996-09-30 1996-09-30 Speicherzelle mit Polymerkondensator
DE19640239.5 1996-09-30

Publications (1)

Publication Number Publication Date
WO1998014989A1 true WO1998014989A1 (fr) 1998-04-09

Family

ID=7807399

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1997/001666 WO1998014989A1 (fr) 1996-09-30 1997-08-07 Element de memoire a condensateur polymere

Country Status (3)

Country Link
DE (1) DE19640239A1 (fr)
TW (1) TW365066B (fr)
WO (1) WO1998014989A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002043071A1 (fr) * 2000-11-27 2002-05-30 Thin Film Electronics Asa Circuit de memoire ferroelectrique et son procede de fabrication
WO2003046922A3 (fr) * 2001-11-16 2003-08-14 Infineon Technologies Ag Montage a semi-conducteurs avec transistors a base de semi-conducteurs organiques et de cellules de memoire d'ecriture-lecture non volatiles
US6872969B2 (en) 2002-01-09 2005-03-29 Samsung Sdi Co., Ltd. Non-volatile memory device and matrix display panel using the same

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2002340795A1 (en) 2001-05-07 2002-11-18 Advanced Micro Devices, Inc. Reversible field-programmable electric interconnects
CN1276518C (zh) 2001-05-07 2006-09-20 先进微装置公司 使用复合分子材料的浮置栅极存储装置
WO2002091495A2 (fr) 2001-05-07 2002-11-14 Coatue Corporation Memoire moleculaire
WO2002091494A1 (fr) 2001-05-07 2002-11-14 Advanced Micro Devices, Inc. Element de commutation ayant un effet memoire
KR100900080B1 (ko) * 2001-05-07 2009-06-01 어드밴스드 마이크로 디바이시즈, 인코포레이티드 자기 조립형 폴리머 막을 구비한 메모리 디바이스 및 그제조 방법
WO2002091385A1 (fr) 2001-05-07 2002-11-14 Advanced Micro Devices, Inc. Cellule de memoire moleculaire
US6858481B2 (en) 2001-08-13 2005-02-22 Advanced Micro Devices, Inc. Memory device with active and passive layers
US6768157B2 (en) 2001-08-13 2004-07-27 Advanced Micro Devices, Inc. Memory device
KR100860134B1 (ko) 2001-08-13 2008-09-25 어드밴스드 마이크로 디바이시즈, 인코포레이티드 메모리 셀
US6806526B2 (en) 2001-08-13 2004-10-19 Advanced Micro Devices, Inc. Memory device
US6838720B2 (en) 2001-08-13 2005-01-04 Advanced Micro Devices, Inc. Memory device with active passive layers
US7012276B2 (en) 2002-09-17 2006-03-14 Advanced Micro Devices, Inc. Organic thin film Zener diodes

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60113474A (ja) * 1983-11-25 1985-06-19 Nippon Telegr & Teleph Corp <Ntt> 半導体装置及びその製造方法
US4860254A (en) * 1986-01-31 1989-08-22 Bayer Aktiengesellschaft Non-volatile electronic memory
US5356500A (en) * 1992-03-20 1994-10-18 Rutgers, The State University Of New Jersey Piezoelectric laminate films and processes for their manufacture

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5423285A (en) * 1991-02-25 1995-06-13 Olympus Optical Co., Ltd. Process for fabricating materials for ferroelectric, high dielectric constant, and integrated circuit applications

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60113474A (ja) * 1983-11-25 1985-06-19 Nippon Telegr & Teleph Corp <Ntt> 半導体装置及びその製造方法
US4860254A (en) * 1986-01-31 1989-08-22 Bayer Aktiengesellschaft Non-volatile electronic memory
US5356500A (en) * 1992-03-20 1994-10-18 Rutgers, The State University Of New Jersey Piezoelectric laminate films and processes for their manufacture

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 009, no. 266 (E - 352) 23 October 1985 (1985-10-23) *
YAMAUCHI N: "A METAL-INSULATOR-SEMICONDUCTOR (MIS) DEVICE USING A FERROELECTRIC POLYMER THIN FILM IN THE GATE INSULATOR", JAPANESE JOURNAL OF APPLIED PHYSICS, vol. 25, no. 4, PART 1, April 1986 (1986-04-01), pages 590 - 594, XP000021841 *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002043071A1 (fr) * 2000-11-27 2002-05-30 Thin Film Electronics Asa Circuit de memoire ferroelectrique et son procede de fabrication
US6734478B2 (en) 2000-11-27 2004-05-11 Thin Film Electronics Asa Ferroelectric memory circuit and method for its fabrication
AU2002223165B2 (en) * 2000-11-27 2005-02-17 Thin Film Electronics Asa A ferroelectric memory circuit and method for its fabrication
RU2259605C2 (ru) * 2000-11-27 2005-08-27 Тин Филм Электроникс Аса Ферроэлектрический запоминающий контур и способ его изготовления
CN100342453C (zh) * 2000-11-27 2007-10-10 薄膜电子有限公司 铁电存储电路及其制造方法
WO2003046922A3 (fr) * 2001-11-16 2003-08-14 Infineon Technologies Ag Montage a semi-conducteurs avec transistors a base de semi-conducteurs organiques et de cellules de memoire d'ecriture-lecture non volatiles
US7208823B2 (en) 2001-11-16 2007-04-24 Infineon Technologies Ag Semiconductor arrangement comprising transistors based on organic semiconductors and non-volatile read-write memory cells
US6872969B2 (en) 2002-01-09 2005-03-29 Samsung Sdi Co., Ltd. Non-volatile memory device and matrix display panel using the same
DE10300746B4 (de) * 2002-01-09 2008-02-07 Samsung SDI Co., Ltd., Suwon Nichtflüchtiges Speicherelement und Anzeigematrizen sowie deren Anwendung

Also Published As

Publication number Publication date
TW365066B (en) 1999-07-21
DE19640239A1 (de) 1998-04-02

Similar Documents

Publication Publication Date Title
DE19935947B4 (de) Verfahren zum Ausbilden von Zwischenverbindungen in einem ferroelektrischen Speicherbauelement
DE19543539C1 (de) Verfahren zur Herstellung einer Speicherzellenanordnung
EP0740347B1 (fr) Structure de mémoire à semi-conducteurs utilisant un diélectrique ferroélectrique et méthode de fabrication
DE69529942T2 (de) Verfahren zur Herstellung eines Halbleiterbauelements mit einem kapazitiven Element
DE19521489B4 (de) Kondensatorplatte und Kondensator, je in einer Halbleitervorrichtung gebildet, die Verwendung eines solchen Kondensators als Speicherkondensator einer Halbleitervorrichtung, Verfahren zur Herstellung eines Kondensators und Verwendung eines solchen Verfahrens zur Herstellung von DRAM-Vorrichtungen
DE4402216C2 (de) Halbleiterbauelement mit Kondensatoren und zu seiner Herstellung geeignetes Verfahren
WO1998014989A1 (fr) Element de memoire a condensateur polymere
DE19860829B4 (de) Verfahren zur Herstellung eines Halbleiterbausteins
DE3910033A1 (de) Halbleiterspeicher und verfahren zu dessen herstellung
EP0744772A1 (fr) Cellule de stockage DRAM à transistor vertical et son procédé de fabrication
EP0740348B1 (fr) Structure de mémoire à semi-conducteurs utilisant un diélectrique ferroélectrique et méthode de fabrication
DE19640246A1 (de) Halbleiteranordnung mit geschützter Barriere für eine Stapelzelle
DE4126046A1 (de) Herstellungsverfahren und struktur eines dram-speicherzellenkondensators
DE4029256C2 (de) Halbleiterspeichervorrichtung mit wenigstens einer DRAM-Speicherzelle und Verfahren zu deren Herstellung
EP0989612A1 (fr) Réseau de cellules de mémoire et procédé de fabrication
DE19608182C2 (de) Dielektrischer Dünnfilm und Kondensator mit diesem für Halbleitervorrichtung und deren Herstellungsverfahren
DE69022621T2 (de) Integrierter ferro-elektrischer Kondensator.
DE4442432A1 (de) Verfahren zum Herstellen von Kondensatoren in Halbleiterspeichervorrichtungen
DE3543937C2 (fr)
DE4034995C2 (de) Hochintegriertes Halbleiterspeicherbauelement und Verfahren zu seiner Herstellung
EP0931341B1 (fr) Procede de production d&#39;ensembles memoires a semiconducteur sans couches d&#39;arret
EP0862207A1 (fr) Procédé de fabrication d&#39;une capacité ensillonée de type DRAM
EP0931342B1 (fr) Ensemble memoire a semiconducteur sans couches d&#39;arret et son procede de fabrication
DE4016347C2 (de) Verfahren zum Herstellen einer dynamischen RAM-Speicherzelle
DE69220725T2 (de) Herstellungsverfahren eines Kondensatorelementes für ein DRAM

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CN JP KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

Ref document number: 1998516092

Format of ref document f/p: F

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载