+

WO1998013880A1 - GRILLE POLY-Si/POLY-SiGe POUR DISPOSITIFS CMOS - Google Patents

GRILLE POLY-Si/POLY-SiGe POUR DISPOSITIFS CMOS Download PDF

Info

Publication number
WO1998013880A1
WO1998013880A1 PCT/US1997/004987 US9704987W WO9813880A1 WO 1998013880 A1 WO1998013880 A1 WO 1998013880A1 US 9704987 W US9704987 W US 9704987W WO 9813880 A1 WO9813880 A1 WO 9813880A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
poly
polysilicon
gate oxide
sige
Prior art date
Application number
PCT/US1997/004987
Other languages
English (en)
Inventor
Deepak Kumar Nayak
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Publication of WO1998013880A1 publication Critical patent/WO1998013880A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/2807—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being Si or Ge or C and their alloys except Si
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • This invention relates generally to the manufacture of high performance semiconductor devices and, more particularly, to the manufacture of high performance sub-micron semiconductor devices and, even more particularly, to a gate structure to suppress boron penetration into thin gate oxides.
  • the semiconductor industry is increasingly characterized by a growing trend toward fabricating larger and more complex circuits on a given semiconductor chip. This is being achieved by reducing the size of individual devices within the circuits and spacing the devices closer together. The reduction of the size of individual devices and the closer spacing brings about improved electrical performance.
  • MOS integrated circuits in which the component devices have gate dimensions as small as 0.35 microns or less. Devices having such small dimensions suffer from certain problems that are not of serious concern when the gate dimensions are greater than about 1 micron.
  • the scaling rules that apply to these small devices call for very thin gate oxide layers, typically equivalent to 30 - 80 Angstroms of silicon dioxide.
  • Conventional gate oxide layers which consist of thermally grown silicon dioxide, may be inadequate in several respects when they are made this thin. For example, such thin oxide layers tend to exhibit a high density of pinholes.
  • These layers are also very permeable to boron which is used as a dopant for the polysilicon used as a gate material. As a result, for example, boron from a p + doped polysilicon gate electrode can readily penetrate the thin oxide layer and contaminate the underlying channel during subsequent, high-temperature processing.
  • enhancement-mode MOSFETs with suitable V, (threshold voltage) values could only be fabricated as p-channel devices using aluminum or n * -doped polysilicon gates and uniform lightly doped n-substrates. This is because, at that time it was not possible to produce enhancement-mode n- channel MOSFETs using n ⁇ -poly or Al gates on a uniform, lightly doped p-substrate because such structures exhibit a negative threshold voltage.
  • V ion implantation it became possible to build NMOSFETs with positive V t s by adjusting channel doping profiles.
  • enhancement-mode and depletion-mode NMOSFETs could then be fabricated with little extra difficulty. Since n-channel transistors have greater drive current and hence speed, NMOS replaced PMOS as the dominant digital IC technology. However, when CMOS became the main technology for VLSI in the late 1980s, the need for enhancement-mode p- channel MOSFETs returned.
  • n-well CMOS technology as well as in twin-well CMOS technology, the situation changes because in n-well CMOS technology the doping in the n-well is about lOx the doping in the substrate, making it at least 10 '/cm 3 .
  • Twin-well CMOS technology has become the well-architecture technology of choice as the gate lengths decrease below about 1 micron.
  • the substrate doping density must be 2-3xl0 lc /cm 3 . Therefore, the V, values of PMOS devices made with n + - poly gates in either n-well or twin-well CMOS technology will be at least -1.5V which is too large in magnitude.
  • the threshold voltages of the n-channel and p-channel devices in CMOS circuits should also have comparable magnitudes. In addition, to allow for maximum current-driving capability, they should be as small as possible. For example, for 5V CMOS technology, desirable threshold voltages are 0.6 to 0.8V for V l ⁇ and -0.6 to -0.8V for V Tp .
  • n-type polysilicon The most common choice for the gate material has been heavily doped n-type polysilicon. For long- channel devices it has been possible to adjust both V Tn and V T ⁇ with implants of boron into the channel.
  • n * poly is the gate electrode in a PMOS device
  • V 1( to -0.7V is not simple, especially when the channel is shrunk below about 1 microns.
  • further shrinkage of the device requires the gate oxide to be thinner which makes the use of boron to adjust V Tp in this type of device even less feasible since larger doses of boron are needed.
  • An alternative is to use p + polysilicon as the gate material for PMOS devices. This appears to be mandatory when the channel length becomes smaller than 0.5 ⁇ m.
  • enhancement-mode surface-channel devices are desirable due to improved short-channel effect of these devices.
  • the dual-poly (n"-poly gate for NMOS and p + -poly gate for PMOS) technology has been the trend in recent years, which produces surface-channel CMOS devices.
  • a major problem with p ⁇ polysilicon gates when a thin gate oxide is used is poor V ⁇ process control in the PMOS devices, due to penetration of the boron into the gate oxide and, ever worse, into the silicon substrate. It has been shown that boron will penetrate gate oxides that are less than or equal to 12.5 nm thick during a 900 degree Centigrade, 30 minute post- implant anneal in N : , .
  • the problem that is presented to process engineers in specifying process parameters is that for the p + polysilicon gate to act as a good conductor, so that drive currents are high, for example, it is necessary to have a uniformly heavily doped polysilicon gate.
  • the gate is doped by first ion implanting the dopant ions into the gate at a selected implant energy and then annealing at a selected temperature for a selected period of time to drive the dopant ions into the polysilicon gate.
  • the dopant ions would be driven only until there is a uniform concentration profile across the polysilicon gate to the p + - polysilicon/gate-oxide interface and nothing beyond.
  • the extent of the penetration of the dopant ions depends upon the process parameters, namely, the implant energy and dosage level at which the ions are implanted, the anneal temperature at which the ions are driven into the gate, and the period of time at which the anneal step is conducted. If one of these parameters is incorrect, the dopant ions will be driven either too far or not far enough. If the dopant ions are driven too far the problems, as discussed above occur. If the dopant ions are not driven far enough there is an area above the p'-polysilicon/gate-oxide interface that has a deficiency of dopant ions. This deficiency of dopant ions exhibits an effect known as the poly-depletion effect. Poly depletion decreases the effective gate capacitance of the device and degrades device current drive.
  • a gate structure and a method of manufacturing the structure in which boron diffusion into a gate oxide layer is suppressed includes a semiconductor substrate on which a gate oxide is formed.
  • a boron diffusion suppression layer is formed on the gate oxide and can be either doped or undoped poly-SiGe.
  • a doped or undoped polysilicon layer is formed on the poly-SiGe layer. The undoped polysilicon layer is implanted with dopant ions and heat treated to diffuse the dopant ions into the polysilicon layer and the poly-SiGe layer.
  • Figure 1 is a diagram showing the structure as taught by the present invention in nmos.
  • Figure 2 is a diagram showing the structure as taught by the present invention in pmos.
  • Figure 3 shows boron concentration profiles in a polysilicon gate structure.
  • FIG. l there is shown an nmos semiconductor device 10 incorporating the present invention.
  • the device 10 is formed on a p-silicon conductivity type substrate 12 which has two n+ regions 14 and 16 which are the drain and source regions, respectively, in the device 10.
  • a gate oxide region 18 is formed on the substrate 12 between the drain region 14 and the source region 16.
  • the thickness of the gate oxide region 18 is in the range of 20 - 70 Angstroms and the thickness selected depends on the dimensions of the overall device. For example, for 0.25 micron or smaller devices, a gate oxide thickness less than 60 Angstroms is necessary. For 0.1 micron devices, the gate oxide thickness is required to be in the range of 20 - 40 Angstroms.
  • the gate oxide is typically silicon dioxide, Si0 2 .
  • the poly-SiGe material is an alloy of silicon and germanium with the percentage of germanium in the range of 30-70%.
  • the thickness of the poly-SiGe layer 20 is in the range of 10 - 200 Angstroms.
  • the poly-SiGe layer 20 can be undoped or in-situ doped while being deposited. In one embodiment of the invention, undoped poly-SiGe is deposited on the gate oxide layer 18 and the polysilicon layer 22 is deposited on poly-SiGe layer 20.
  • the thickness of the polysilicon layer 22 is in the range of 500 - 3000 Angstroms.
  • the polysilicon layer 22 can be deposited undoped and boron implanted into the surface of the polysilicon layer 22 followed by a heat treatment to diffuse the boron ions into the polysilicon layer 22 and into the poly-SiGe layer 20.
  • the polysilicon layer 22 can be deposited either in-situ doped or undoped as discussed above, that is, doped by implantation. Referring now to Figure 2 there is shown a pmos semiconductor device 24 incorporating the present invention.
  • the device 24 is formed on an n- silicon conductivity type substrate 26 which has two p+ regions 28 and 30 which are the drain and source regions, respectively, in the device 24.
  • a gate oxide region 32 is formed on the substrate 26 between the drain region 28 and 30.
  • the thickness of the gate oxide region 32 is in the range of 20 - 70 Angstroms and the thickness selected depends on dimensions of the overall device. For example, for 0.25 micron or smaller devices, a gate oxide thickness of less than 60 Angstroms is necessary. For 0.1 micron devices, the gate oxide thickness is required to be in the range of 30 - 40 Angstroms.
  • the gate oxide is typically silicon dioxide, Si0 2 .
  • the gate oxide region 32 there is a layer of poly-SiGe 34.
  • the poly-SiGe 34 material is an alloy of silicon and germanium with the percentage of germanium in the range of 30-70%.
  • the thickness of poly-SiGe layer 34 is in the range of 10 - 200 Angstroms.
  • the poly-SiGe layer 34 can be undoped or in-situ doped while being deposited. In one embodiment of the invention, undoped poly-SiGe is deposited on the gate oxide layer 32 and the polysilicon layer 36 is deposited on the poly-SiGe layer 34.
  • the thickness of the polysilicon layer 36 is in the range of 500 - 3000 Angstroms.
  • the polysilicon layer 36 can be deposited undoped and boron implanted into the surface of the polysilicon layer 36 followed by a heat treatment to diffuse the boron ions into the polysilicon layer 36 and into the poly-SiGe layer 20.
  • the polysilicon layer 36 can be deposited either in-situ doped or undoped as discussed above, that is, doped by implantation.
  • FIG. 3 there is shown boron concentration profiles at various stages of the manufacturing process.
  • the boron concentration profiles are superimposed over a typical semiconductor device at 38.
  • the relative concentration is given along the axis 40 and the depth into the structure coincides with the structure as shown along the axis
  • the typical structure 38 is formed on a silicon substrate 44 of a selected conductivity type, a gate oxide layer 46, typically made of Si0_, a poly-SiGe layer 48, and a polysilicon layer 50.
  • the curve 52 represents the boron ion concentration profile as implanted. As can be appreciated, the highest boron ion concentration immediately after implant is in the polysilicon layer 50 with decreasing concentration in the poly-SiGe layer 48. Ideally, there is no boron ion penetration into the SiO, layer 46 through the interface 54.
  • the curve 56 represents the boron ion concentration profile after heat treatment which is done to drive a higher concentration of boron ions into the poly-SiGe layer 48.
  • the ideal concentration profile is for the curve 56 to be uniform across the polysilicon layer 50 and the poly-SiGe layer 48 with no boron ion concentration indicated across the interface 54 into the gate oxide layer 46.
  • the boron ion concentration profile curve 56 follows the curve 60 which shows a decreased concentration in the poly-SiGe layer 48 and a much less concentration beyond the interface 54 indicated by 61.
  • the decreased concentration of boron ions in the oxide layer 46 improves oxide reliability, and the suppressed diffusion into the gate oxide layer 46 prevents the boron ions from reaching the substrate 44 which improves pmos threshold stability.
  • Boron doped poly-SiGe provides a symmetric V t for nmos and pmos. This provides for single polysilicon devices which have similar surface channel characteristics .

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Cette invention se rapporte à une structure et à un procédé de fabrication d'une telle structure, qui permet de supprimer la diffusion de bore à l'intérieur d'une couche d'oxyde de grille. Cette structure, que l'on forme sur un substrat semi-conducteur, comprend une couche d'oxyde de grille formée sur ledit substrat semi-conducteur, une couche de poly-SiGe dopé ou non dopé formée sur la couche d'oxyde de grille. On forme une couche de silicium polycristallin sur la couche de poly-SiGe. Cette couche de silicium polycristallin peut être dopée ou non dopée. Lorsqu'elle n'est pas dopée, les ions dopants de bore sont incorporés au silicium polycristallin et diffusés par processus thermique au sein de la couche même de silicium polycristallin ainsi qu'à l'intérieur de la couche non dopée de poly-SiGe.
PCT/US1997/004987 1996-09-25 1997-03-25 GRILLE POLY-Si/POLY-SiGe POUR DISPOSITIFS CMOS WO1998013880A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US71952496A 1996-09-25 1996-09-25
US08/719,524 1996-09-25

Publications (1)

Publication Number Publication Date
WO1998013880A1 true WO1998013880A1 (fr) 1998-04-02

Family

ID=24890405

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1997/004987 WO1998013880A1 (fr) 1996-09-25 1997-03-25 GRILLE POLY-Si/POLY-SiGe POUR DISPOSITIFS CMOS

Country Status (1)

Country Link
WO (1) WO1998013880A1 (fr)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0859402A3 (fr) * 1997-01-21 1999-08-25 Texas Instruments Incorporated Méthode de fabrication d'une électrode MOS
FR2791177A1 (fr) * 1999-03-19 2000-09-22 France Telecom Procede de realisation d'une grille en forme de champignon ou grille en "t"
WO2001061749A1 (fr) * 2000-02-17 2001-08-23 Koninklijke Philips Electronics N.V. DISPOSITIF A SEMI-CONDUCTEUR COMPRENANT UN CIRCUIT CMOS INTEGRE QUI PRESENTE DES TRANSISTORS MOS POURVUS D'ELECTRODES DE GRILLE EN SILICIUM-GERMANIUM (Si1-x Gex) ET SON PROCEDE DE PRODUCTION
GB2373922A (en) * 2001-02-09 2002-10-02 Samsung Electronics Co Ltd SiGe CMOS gate electrodes
FR2823009A1 (fr) * 2001-04-02 2002-10-04 St Microelectronics Sa Procede de fabrication d'un transistor vertical a grille isolee a faible recouvrement de la grille sur la source et sur le drain, et circuit integre comportant un tel transistor
WO2002009178A3 (fr) * 2000-07-21 2002-10-10 Motorola Inc Appareil semi-conducteur et procede de formation du meme
WO2005091338A3 (fr) * 2004-03-17 2005-12-08 Lam Res Corp Polysilicium doublement dope et gravure de silicium germanium
WO2006062869A1 (fr) * 2004-12-07 2006-06-15 Thunderbird Technologies, Inc. Transistors a effet de champ (fet) de fermi, a silicium contraint, a ingenierie de grille
DE10260860B4 (de) * 2002-12-23 2008-07-10 Robert Bosch Gmbh Schicht aus Si1-xGex, Verfahren zu deren Herstellung und mikromechanisches Bauelement damit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4914046A (en) * 1989-02-03 1990-04-03 Motorola, Inc. Polycrystalline silicon device electrode and method
JPH0425176A (ja) * 1990-05-18 1992-01-28 Seiko Instr Inc 半導体装置の製造方法
JPH0575136A (ja) * 1991-09-17 1993-03-26 Oki Electric Ind Co Ltd ゲート電極構造の形成方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4914046A (en) * 1989-02-03 1990-04-03 Motorola, Inc. Polycrystalline silicon device electrode and method
JPH0425176A (ja) * 1990-05-18 1992-01-28 Seiko Instr Inc 半導体装置の製造方法
JPH0575136A (ja) * 1991-09-17 1993-03-26 Oki Electric Ind Co Ltd ゲート電極構造の形成方法

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
J-M HWANG ET AL: "New gate electrodes for fullx depleted SOI/CMOS; TiN and Poly SiGe", PROCEEDINGS OF THE INTERNATIONAL SOI CONFERENCE, PONTE VEDRA BEACH, FL., OCT. 6 - 8, 1992, no. -, 6 October 1992 (1992-10-06), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 148 - 149, XP000529355 *
KISTLER N ET AL: "SYMMETRIC CMOS IN FULLY-DEPLETED SILICON-ON-INSULATOR USING P+- POLYCRYSTALLINE SI-GE GATE ELECTRODES", PROCEEDINGS OF THE INTERNATIONAL ELECTRON DEVICES MEETING, WASHINGTON, DEC. 5 - 8, 1993, 5 December 1993 (1993-12-05), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 727 - 730, XP000481716 *
PATENT ABSTRACTS OF JAPAN vol. 016, no. 188 (E - 1198) 7 May 1992 (1992-05-07) *
PATENT ABSTRACTS OF JAPAN vol. 017, no. 401 (E - 1404) 27 July 1993 (1993-07-27) *
SUN S C ET AL: "RAPID THERMAL CHEMICAL VAPOR DEPOSITION OF IN-SITU NITROGEN-DOPED POLYSILICON FOR DUAL GATE CMOS", 1995 SYMPOSIUM ON VLSI TECHNOLOGY. DIGEST OF TECHNICAL PAPERS, KYOTO, JUNE 6 - 8, 1995, no. SYMP. 15, 6 June 1995 (1995-06-06), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 121/122, XP000580849 *
TSU-JAE KING: "A POLYCRYSTALLINE-SI1-XGEX-GATE CMOS TECHNOLOGY", INTERNATIONAL ELECTRON DEVICES MEETING, SAN FRANCISCO, DEC. 9 - 12, 1990, no. -, 9 December 1990 (1990-12-09), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 253 - 256, XP000279564 *

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0859402A3 (fr) * 1997-01-21 1999-08-25 Texas Instruments Incorporated Méthode de fabrication d'une électrode MOS
FR2791177A1 (fr) * 1999-03-19 2000-09-22 France Telecom Procede de realisation d'une grille en forme de champignon ou grille en "t"
WO2000057461A1 (fr) * 1999-03-19 2000-09-28 France Telecom Procede de realisation d'une grille en forme de champignon ou grille en 't'
WO2001061749A1 (fr) * 2000-02-17 2001-08-23 Koninklijke Philips Electronics N.V. DISPOSITIF A SEMI-CONDUCTEUR COMPRENANT UN CIRCUIT CMOS INTEGRE QUI PRESENTE DES TRANSISTORS MOS POURVUS D'ELECTRODES DE GRILLE EN SILICIUM-GERMANIUM (Si1-x Gex) ET SON PROCEDE DE PRODUCTION
WO2002009178A3 (fr) * 2000-07-21 2002-10-10 Motorola Inc Appareil semi-conducteur et procede de formation du meme
GB2373922A (en) * 2001-02-09 2002-10-02 Samsung Electronics Co Ltd SiGe CMOS gate electrodes
US6524902B2 (en) 2001-02-09 2003-02-25 Samsung Electronics Co., Ltd. Method of manufacturing CMOS semiconductor device
GB2373922B (en) * 2001-02-09 2003-04-16 Samsung Electronics Co Ltd CMOS semiconductor device, and method of manufacturing the same
FR2823009A1 (fr) * 2001-04-02 2002-10-04 St Microelectronics Sa Procede de fabrication d'un transistor vertical a grille isolee a faible recouvrement de la grille sur la source et sur le drain, et circuit integre comportant un tel transistor
US6861684B2 (en) 2001-04-02 2005-03-01 Stmicroelectronics S.A. Method of fabricating a vertical insulated gate transistor with low overlap of the gate on the source and the drain, and an integrated circuit including this kind of transistor
DE10260860B4 (de) * 2002-12-23 2008-07-10 Robert Bosch Gmbh Schicht aus Si1-xGex, Verfahren zu deren Herstellung und mikromechanisches Bauelement damit
WO2005091338A3 (fr) * 2004-03-17 2005-12-08 Lam Res Corp Polysilicium doublement dope et gravure de silicium germanium
US7682985B2 (en) 2004-03-17 2010-03-23 Lam Research Corporation Dual doped polysilicon and silicon germanium etch
WO2006062869A1 (fr) * 2004-12-07 2006-06-15 Thunderbird Technologies, Inc. Transistors a effet de champ (fet) de fermi, a silicium contraint, a ingenierie de grille

Similar Documents

Publication Publication Date Title
US5783469A (en) Method for making nitrogenated gate structure for improved transistor performance
EP0944921B1 (fr) Procede de fabrication d'un circuit integre comportant des epaisseurs d'oxyde de grille differentes
US8859360B2 (en) Method of manufacturing semiconductor device with offset sidewall structure
US6828185B2 (en) CMOS of semiconductor device and method for manufacturing the same
US7867851B2 (en) Methods of forming field effect transistors on substrates
CN101675513A (zh) 高k栅极介电质互补金属氧化物半导体结构的阈值调整
US5719081A (en) Fabrication method for a semiconductor device on a semiconductor on insulator substrate using a two stage threshold adjust implant
US5851922A (en) Process for fabricating a device using nitrogen implantation into silicide layer
JPH04255266A (ja) Ｍｏｓトランジスタを半導体ウエハ上にｖｌｓｉ構造に形成するための改良された方法
US5872049A (en) Nitrogenated gate structure for improved transistor performance and method for making same
US20070200160A1 (en) Semiconductor device and method of fabricating the same
US4839301A (en) Blanket CMOS channel stop implant employing a combination of n-channel and p-channel punch-through implants
US5932919A (en) MOSFETs with improved short channel effects
US5457060A (en) Process for manufactuirng MOSFET having relatively shallow junction of doped region
US20020155665A1 (en) Formation of notched gate using a multi-layer stack
US6030862A (en) Dual gate oxide formation with minimal channel dopant diffusion
WO1998013880A1 (fr) GRILLE POLY-Si/POLY-SiGe POUR DISPOSITIFS CMOS
US6051460A (en) Preventing boron penetration through thin gate oxide of P-channel devices by doping polygate with silicon
EP1291905B1 (fr) Procédé pour la fabrication d'un dispositif sémiconducteur
US5817536A (en) Method to optimize p-channel CMOS ICs using Qbd as a monitor of boron penetration
US6054374A (en) Method of scaling dielectric thickness in a semiconductor process with ion implantation
US20020068407A1 (en) MOS transistor fabrication method
US4987088A (en) Fabrication of CMOS devices with reduced gate length
JP3145929B2 (ja) 半導体装置の製造方法
JPH11204783A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP KR

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: JP

Ref document number: 1998515595

Format of ref document f/p: F

122 Ep: pct application non-entry in european phase
点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载