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WO1998056002A1 - Nouvelle architecture de decodage et de matrice de memoire flash - Google Patents

Nouvelle architecture de decodage et de matrice de memoire flash Download PDF

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Publication number
WO1998056002A1
WO1998056002A1 PCT/US1998/011082 US9811082W WO9856002A1 WO 1998056002 A1 WO1998056002 A1 WO 1998056002A1 US 9811082 W US9811082 W US 9811082W WO 9856002 A1 WO9856002 A1 WO 9856002A1
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WO
WIPO (PCT)
Prior art keywords
line
word
source
memory cells
flash memory
Prior art date
Application number
PCT/US1998/011082
Other languages
English (en)
Inventor
Peter Wung Lee
Fu-Chang Hsu
Hsing-Ya Tsao
Original Assignee
Peter Wung Lee
Hsu Fu Chang
Tsao Hsing Ya
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/872,475 external-priority patent/US5777924A/en
Application filed by Peter Wung Lee, Hsu Fu Chang, Tsao Hsing Ya filed Critical Peter Wung Lee
Priority to JP11502640A priority Critical patent/JP2000516380A/ja
Publication of WO1998056002A1 publication Critical patent/WO1998056002A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G11C11/5635—Erasing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3431—Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step

Definitions

  • the present invention relates to the design and circuit structure of a flash memory, and more specifically to the architecture of word line and source line decoders of a flash memory.
  • flash memory devices have been widely used in computer related equipment and other electronic appliances as storage devices.
  • the nonvolatile and on-chip programmable capabilities of a flash memory are very important for storing data in many applications.
  • flash memories are frequently used for the BIOS storage of a personal computer.
  • the small physical size of flash memories also makes them very suitable for portable applications. Therefore, they have been used for storing programs and data for many portable electronic devices such as cellular phones, digital cameras and video game platforms.
  • RAM normal random access memory
  • EPROM-type flash memory features a byte-program and a block-erase capability with each block containing a number of bytes.
  • a flash memory has to erase the data of a whole block of memory cells, i. e., an erase block, and then program the new data byte by byte.
  • the block erase scheme not only is inflexible but also has an undesirable problem called over-erasure.
  • the over-erasure results from the inherent difference between the speed of erasing of each memory cell. Because a large number of cells are erased together, the cells having fast speed of erasing may be over-erased below 0V, while the cells having slow speed are not successfully erased yet. The over-erased cells will conduct leakage current and cause the malfunction of bit line (BL) sense amplifiers.
  • BL bit line
  • U.S. Pat. No. 5,548,551 provides a negative voltage decoder for erasing either one memory cell or a block of memory cells for a non-volatile memory.
  • a small (multiple bytes) and flexible (random and multiple word lines) erase size for the erase operation of a flash memory can be accomplished without any memory disturbance and over-erasure problems.
  • the primary object of this invention is to provide a circuit structure that offers the capability of erasing memory cells on a small and flexible number of word lines of a flash memory.
  • Another object of this invention is to provide a method of erasing a multiple number of word line pairs simultaneously as well as verifying each individual word line one at time.
  • Yet another object of this invention is to provide a memory circuit structure and methods of operating the memory circuit to eliminate the memory disturbance and over-erasure problems that often occur in a conventional flash memory circuit.
  • a further object of this invention is to provide a source line circuit having segmented source lines so that the flash memory cells of a small segment in a word line can be erased without source disturbance.
  • a further object of this invention is to provide a source line circuit having segmented source lines so that the flash memory cells of a small segment in a word line can be erased without source disturbance. It is also an object of the invention to provide a new bias condition for erasing one of more segments in a word line and reduce the gate disturbance to non-selected segments. It is also another object of the invention to provide a novel erase operation flow to reduce the over-erasure and disturbance for achieving accurate memory cell's threshold voltage control.
  • the memory cells of the flash memory circuit of this invention are divided into a number of banks.
  • the memory cells in each memory bank are organized as a plurality of rows and a plurality of columns.
  • the sources of the memory cells of two adjacent rows are wired together and connected to a common source line.
  • Each memory bank of this invention has its own word line decoder and source line decoder.
  • the source line decoder has a source line latch associated with it for providing desired voltage levels under various memory operations. Address lines to the word line decoder and the source line decoder choose the selected word line and source line for memory operations.
  • each word line decoder has both odd and even word line latches associated with it.
  • the preferred mode of operation of this invention is to select two adjacent word lines which share the common source line from each memory bank for erasing.
  • negative voltages can be applied through the word line latches to both word lines and a positive voltage such as 5V can be applied through the source line latch to provide an appropriate bias condition for the erase operation.
  • the word line under verification can be applied a verifying voltage through one word line latch while the other word line latch can provide a low voltage sufficient enough to cut off the over-erased memory cells on the other word line that is not under verification. Therefore, the false reading that usually exists in verifying a single word line is eliminated.
  • each word line can be stopped erasing after being verified by applying appropriate voltage through its associated word line latch to reduce the over-erase problem.
  • a multiple number of memory banks each having two word lines that share the same source line for erasing can be erased simultaneously with one erase operation.
  • the erase size can be from a word line pair to a large number of multiple word line pairs.
  • a second embodiment of this invention there are also two latches associated with the decoder.
  • One of the latches controls if the word line voltage of a selected memory row is provided by either the other latch or by the address lines.
  • the address lines and the latches By supplying appropriate voltages to the address lines and the latches, a multiple pairs of word lines in a memory bank can be erased simultaneously and verified one by one properly. Nevertheless, if all the word lines in a memory bank are selected for erasing, any other memory bank can only have all its word lines erased or not at the same time because the address lines that may also provide word line voltages for this embodiment are shared by all memory banks. Therefore, for the erase operation, the preferred mode is to erase a multiple pairs of word lines less than the size of a memory bank in one erase operation or to erase a multiple memory banks simultaneously.
  • the third embodiment uses an additional latch for controlling how the word line voltage is supplied. With the additional latch, the device of a control circuit of the word line decoder can be better protected under certain conditions.
  • the fourth embodiment which also uses an additional latch reduces the address lines required for both the word line decoder and the source line decoder to a half. The flexibility and preferred mode of operation for the two embodiments are the same as that of the second embodiment.
  • This invention also presents a source line circuit that allows the selection of the memory cells of a small segment in a row for erasing.
  • a source line circuit that allows the selection of the memory cells of a small segment in a row for erasing.
  • the preferred mode of an erase operation in this invention is to erase the memory cells of two adjacent word lines that share a same source line simultaneously
  • a post-programming approach is provided for restoring the data of disturbed memory cells if only the memory cells of a single word line are erased at one time.
  • Two modes of erasing memory cells are disclosed for erasing multiple word lines and multiple segments in a word line respectively. A different bias condition is used in each mode.
  • a combined method that takes advantage of the benefits of both modes is presented to eliminate the over-erasure problem, save erasing time and reduce consumed power.
  • FIG. 1 shows a first embodiment of the circuit of a memory bank of the present invention including a bank decoder, a word line decoder with even and odd word line latch, and a source line decoder with a source line latch.
  • FIG. 2 shows the word line decoder circuit of the first embodiment shown in FIG. 1.
  • FIG. 3 a shows the memory array circuit of a memory bank and the operational conditions of the decoder circuit for various memory operations.
  • FIG. 3b summarizes the control signals for the first embodiment of this invention under different memory operations.
  • FIG. 4 shows a second embodiment of the circuit of a memory bank of the present invention including a bank decoder, a word line decoder with a word line latch and a source line decoder with a source line latch.
  • shows the word line decoder circuit of the second embodiment shown in FIG 4 summarizes the control signals for the second embodiment of this invention under different memory operations shows a third embodiment for the circuit of a memory bank of this invention shows a fourth embodiment for the circuit of a memory bank of this invention shows a latch circuit for providing three voltage levels shows a latch circuit for providing two voltage levels shows a memory array circuit having segmented source lines of this invention shows an alternative memory array circuit having segmented source lines of this invention shows an exemplary layout for the memory array circuit of FIG 10a shows an exemplary gating device which can be used to replace the gating device of FIG 2 shows an exemplary gating device which can be used to replace the gating device of FIG 5 shows another exemplary gating device which can be used to replace the gating device of FIG 5 shows
  • the flash memory circuit comprises a word line (WL) decoder 50, a source line (SL) decoder 60 and a memory bank 80 having an array of memory cells.
  • Each memory bank has an odd WL latch 10, an even WL latch 20 and an SL latch 30 associated with it.
  • a bank decoder 40 for selecting different memory banks of the flash memory is also shown.
  • the WL latches and the SL latch are controlled by the bank decoder.
  • XT1-XT4 and XTB 1-XTB4 are address lines that work with the WL decoder 50 to pass or block the voltages from the WL latches to the word lines.
  • ST1-ST4 and STB1-STB4 are address lines that control the SL decoder 60 to pass or block the voltage from the SL latch to the source lines.
  • An XS word control line is connected to a ground voltage in this embodiment.
  • the decoder circuit as shown in FIG. 1 allows the erasure of the memory cells on a single word line by applying a negative voltage to the word line and a positive 5V voltage to the source line.
  • a single word line may comprise 128 or 256 bytes.
  • two adjacent word lines share a same source line as shown in FIG. 1.
  • WL1 and WL2 share one source line SL1. If only WL1 is selected for erasing, erase disturbance may occur on the adjacent non-selected word line WL2.
  • a method of overcoming the drawback of erasing a single selected WL is to read and store the programmed data of the memory cells on its adjacent WL before the erasing. During the erase-verification, the adjacent WL is turned off. After the selected WL has been successfully verified, the data of the memory cells of its source-disturbed adjacent WL after erasing are read and the previously stored data before erasing are retrieved. The read data and stored data are compared. If the data do not match, a program operation is performed to re-program the stored data to the disturbed memory cells.
  • the circuit shown in the first embodiment of this invention has the flexibility of erasing any number of selected WLs as long as their adjacent WLs that may be disturbed are remembered first and restored later.
  • a preferred operation of the flash memory circuit of the first embodiment is to simultaneously erase two adjacent WLs having a shared source line so that verification can be accomplished without disturbance.
  • the odd and even WL latches 10, 20 of this invention provide the capability of erasing the memory cells on the two adjacent WLs altogether.
  • both odd and even WL latches in a selected memory bank apply negative voltages to a selected pair of WLs, and the SL latch in the selected memory bank applies a positive voltage to a selected SL, a pair of word lines can be erased simultaneously and then verified one by one as long as appropriate address signals are sent to the address lines.
  • All other WLs in the selected memory bank can be grounded through the word control line XS if they are not selected for erasing by the address lines.
  • non- selected SLs can also be grounded. Therefore, no memory cells other than the selected memory cells are affected by the biased voltages being applied for the erase operation. The memory disturbance problem is eliminated.
  • each memory bank has its own odd and even WL latches as well as an SL latch, the erase operation can be applied independently without affecting other memory banks. Consequently, the erase size of the flash memory is very flexible and can be as small as a pair of WLs or a plurality of pairs of WLs.
  • the memory banks selected for erasing can be almost randomly located anywhere within the flash memory.
  • the decoder circuit is shown in FIG. 2 again. It can be seen that a p-n transistor pair and another n transistor control if each word line will be connected to a WL latch or grounded to the word control line XS. It is important to note that the preferred erase operation of this embodiment selects a plurality of memory banks with only a pair of WLs from each memory bank to erase if a multiple pairs of WLs are to be erased all at once. By doing so, the disturbance problem can be avoided. From the user's point of view, the logical addresses of the erased memory WLs may still be continuous.
  • the bank decoder of this embodiment ensures that only one pair of WLs are selected from each physical memory bank.
  • the circuit as shown in FIG. 1 can erase more than one pair of WLs in one memory bank at once, the advantage of this invention can not be fully realized unless only a pair of WLs from each memory bank are erased simultaneously.
  • the source line decoder 60 comp ⁇ ses a plurality of source gating devices each having two transistors for controlling the connection of a source line to either the SL latch 30 or a source control line SLS
  • the address lines ST1-ST4 and STB1 ⁇ STB4 controls the source gating devices for connecting one of the source lines to the SL latch 30
  • ST1-ST4 have the same logic as XT1-XT4 but may have different voltages
  • STB1-STB4 have the same logic as XTB1-XTB4 but may have different voltages
  • both odd and even WL latches apply ground voltages to XD1 and XD2 respectively Because the conditions of the address lines XT1-XT4 and XTB1-XTB4 have been determined by the WLs selected for erasing, WLl and WL2 are connected to the ground voltage of XD1 and XD2 respectively, and WL3-WL8 are also passed with the ground voltage of XS Therefore, none of the WLs is affected by the erase operation
  • the threshold voltage of each cell on each erased WL is verified sequentially to check if the erase operation is finished
  • the WL to be verified is applied a positive low voltage such as 1 5V
  • the other erased WLs are applied a negative low voltage such as -3V to cut off all the memory cells on them even if any of the cells has been over-erased and having a threshold voltage between 0V and -3V
  • the cut-off negative voltage is dependent on the threshold voltages of the over-erased cells It is detected before the erase-ve ⁇ fication by lowering down the erased WL voltage until no memory cell current is sensed
  • the detail of determining the threshold voltage is disclosed in U S patent application Ser. Nr. 08/823,571 filed March 25, 1997 assigned to the same assignee of this invention.
  • the non-selected WLs are applied a small or ground voltage, such as OV.
  • the address lines are applied appropriate voltages to select WLl, i.e., a power supplying voltage Vdd for XT1, -3V for XT2-XT4, - 3V for XTB 1 and Vdd for XTB2-XTB4.
  • the odd WL latch applies the verifying voltage, i.e. 1.5V, to XDl and the even WL latch applies the cut-off negative voltage such as -3V to XD2.
  • Mia and M2a as well as Mlb and M2b are turned on, and Mlc and M2c are turned off to pass XDl and XD2 to WLl and WL2 respectively.
  • M3a ⁇ M8a as well as M3b ⁇ M8b are turned off and M3c ⁇ M8c are turned on to pass the XS signal to WL3-WL8. Therefore, WLl is applied the verifying voltage 1.5V, WL2 is applied the cut-off voltage - 3V, and WL3-WL8 are grounded in the memory bank.
  • both odd and even WL latches apply a negative cut-off voltage -3V to XDl and XD2 respectively. Because the address lines are shared, the bias conditions make WLl and WL2 connected to the cut-off voltage -3V of XDl and XD2 respectively, and WL3-WL8 passed with the ground voltage of XS. For other memory banks that have no WL selected for erasing at all, both WL latches apply 0V to XDl and XD2 respectively. Therefore, WLl and WL2 are grounded to 0V of XDl and XD2 correspondingly and WL3-WL8 are grounded to 0V of XS.
  • WLl of the first memory bank After the verification, if WLl of the first memory bank fails the erase- verification, it will be erased again with the same operation conditions that have been described earlier. If it passes the verification, WLl will be applied a negative cut-off voltage to stop erasing and cut-off the over-erased memory cells at the same time if there are any over-erased cells. Under this situation, the operation conditions of the next erase cycle are similar to those conditions which have been described earlier except that the odd WL latch in the first memory bank will apply a negative cut-off voltage to XDl .
  • the present invention provides a decoder circuit for erasing multiple and random WL pairs at the same time. It should be noted that the erase operation of each individual WL is stopped independently. Because each erased WL is controlled by either an even WL latch or an odd WL latch, the erase operation of the WL that already passes the erase-verification can be stopped by resetting its corresponding WL latch to an erase-inhibit state. It is not necessary to wait for the WL that has the slowest speed of being erased to complete erasing before other WLs can be stopped erasing. The advantage of being able to stop erasing independently is that the problem associated with over-erasure of conventional flash memories is greatly reduced.
  • the flash memory of this invention requires three control gate voltages for the WLs when erase-verification is performed.
  • a negative cut-off voltage as mentioned in the previous paragraph is necessary.
  • U.S. patent No. 5,687,121 and U.S. patent application Ser. Nr. 08/676,066 that both are assigned to the same assignee of this invention disclose a method for applying at least three voltages from the WL latches. The technique is incorporated in this invention for providing three different control gate voltages to the WLs.
  • FIG. 3 a shows an example of the bias conditions for various memory operations of the word lines in one memory bank.
  • both WLl and WL2 have been selected for erasing, i.e., XDl, XD2 and SLX have been connected to WLl, WL2 and SL1 respectively by the address lines.
  • the conditions for an erase operation and an erase-verify operation have been described in the earlier discussion in connection with FIG. 2.
  • both XDl and XD2 are -8V and SLX is 5V.
  • XDl For erase-verification of WLl, XDl is +1.5V, XD2 is a negative cut-off voltage -Vx that has been assumed -3V in the earlier discussion, and SLX is OV
  • XDl is a voltage +0 5 V
  • XD2 is a negative cut-off voltage -Vx
  • SLX is OV
  • XDl is +5V
  • XD2 is a negative cut-off voltage -Vx
  • SLX is OV
  • XDl For programming WLl, XDl is +8V, and both XD2 and SLX are OV
  • Three voltages are required for erase, erase-venfy, over-erase-venfy, and repair operations For WLs selected for erasing, an operating voltage is applied For a WL that is erase-venfied or over-erase-ve ⁇ fied, an erase-
  • FIG 4 shows a second embodiment of the present invention
  • the flash memory circuit comprises a WL decoder 51, an SL decoder 60 and a memory bank 80 having an array of memory cells
  • Each memory bank has a WL latch 11, an SL latch 30, and a word control line (XS) latch 70 associated with the bank
  • a bank decoder 40 selects different memory banks of the flash memory
  • the SL decoder 60, the SL latch 30, the memory bank 80 and the bank decoder 40 are identical to those described in the first embodiment The same numerals are also used to identify these circuit blocks
  • the word line decoder 51 there are a plurality of word gating devices each having three transistors for controlling the connection of word lines
  • WLl is controlled by a gating device having transistors Mia, Mlb and Mlc
  • the WL decoder circuit 51 as shown in FIG 4 can connect each WL within a memory bank to either its address line XT (one
  • the preferred mode of operation of the decoder circuit of this embodiment has an erase size being an even number less than the size of a memory bank, or a multiple of the size of a memory bank
  • the WL decoder circuit 51 of a memory bank is shown again in FIG 5a
  • Each memory bank has only one WL latch for generating XD signal
  • the XD signal is sent to the common gates of a p-n transistor pair as shown in FIG 5a
  • Each address line XT is sent to the drain of a p-MOS transistor
  • the drains of two n-MOS transistors are tied together and connected to the XS latch 70 Therefore, either XT or XS is passed to a WL according to the XD signal
  • Eight WLs are shown in one memory bank in this example
  • XT1-XT4 The voltages of XT1-XT4 are -8V, XT5-XT8 are 0V, XTB1-XTB4 are +1V, and XTB5-XTB8 are -8V to select WL1-WL4 of the memory bank for erasing
  • the WL latch and the XS latch of the selected memory bank apply -8V to XD and XS respectively Under these conditions, Mla ⁇ M4a as well as Mlb ⁇ M4b are turned off and Mlc ⁇ M4c are turned on to pass a negative voltage -8V from XS to the selected word lines WL1-WL4 In the mean time, M5b ⁇ M8b as well as M5c ⁇ M8c are turned off and M5a ⁇ M8a are turned on to pass a OV from XT5-XT8 to the non-selected word
  • XT1-XT8 and XTB1-XTB8 are shared by respective WLs in each memory bank, the bias conditions of XT1-XT8 and XTB1-XTB8 have been determined by the WLs of the memory bank selected for erasing as described in the previous paragraph
  • the control of the non-selected memory banks has to be accomplished by appropriate XD and XS voltages within the memory bank. For memory banks that are not selected for erasing, XD is applied -8V and XS is applied OV.
  • the corresponding XT can be applied a negative cut-off voltage for passing to the WL
  • a negative cut-off voltage low enough to turn off the memory cells on WLl is applied to XT1
  • the negative cut-off voltage is lower than the determined threshold voltage as discussed earlier in connection with the referenced U S patent application Ser Nr 08/823,571
  • a good example of the negative cut-off voltage may be - 3 V XT IB is also applied -8V Mlc is turned off and the negative bias voltage turns on Mia and passes itself to WLl
  • the remaining word lines WL2-WL4 are not affected and their erase operation continue
  • each word line can be verified individually
  • a verifying voltage such as +1 5V is applied to XT1
  • XT2-XT4 are applied a negative cut-off voltage -3V
  • XT5-XT8 are applied 0V
  • XTB1 is applied a negative cut-off voltage -3V
  • XTB2-XTB4 are applied 0V
  • XTB5-XTB8 are applied a negative cut-off voltage -3V
  • Both XD and XS are applied a negative cut-off voltage -3V from the WL latch and the XS latch respectively
  • M2a ⁇ M4a as well as M2b ⁇ M4b are turned off and M2c ⁇ M4c are turned on to pass the negative cut-off voltage -3N from XS to word lines WL2-WL4 that are erased but not under verification
  • M5b ⁇ M8b as well as M5c ⁇ M8c are turned off and M5
  • the second embodiment also allows the erasing of multiple memory banks all at once All the WLs of each selected memory bank must be erased or stopped together
  • XT1-XT8 are applied OV and XTB1-XTB8 are applied either -8V or OV
  • the corresponding WL latch applies OV to XD and the corresponding XS latch applies -8V to XS
  • Mla ⁇ M8a are turned off and Mlb ⁇ M8b as well as Mlc ⁇ M8c are turned on Therefore, WL1-WL8 are applied a voltage -8V passed from XS for erasing
  • the corresponding WL latch applies -8N to XD and the corresponding XS latch applies OV to XS Consequently, Mla ⁇ M8a are turned on and Mlb ⁇ M8b as well as Mlc ⁇ M8c are turned off
  • the XS latch applies a negative cut-off voltage as discussed before, such as -3V, to XS
  • the negative cut-off voltage at XS is passed to all the WLs in the memory bank to shut off the memory cells because Mla ⁇ M8a are turned off and Mlb ⁇ M8b as well as Mlc ⁇ M8c are turned on
  • Each erased WL has to be verified individually If WLl of a memory bank is to be ve ⁇ fied, XT1 is applied a verifying voltage +1 5V and XT2-XT8 are applied a negative cut-off voltage -3V XTB1 is applied a negative cut-off voltage -3V and XTB2-XTB8 are applied OV
  • both XD and XS are applied a negative cut-off voltage -3V from the WL latch and the XS latch respectively Under these conditions, M2a ⁇ M8a as well as M2b ⁇ M8b are turned off and M2c ⁇ M8c are turned on to pass the negative cut-off voltage -3V from XS to word lines WL2-WL8 that are erased but not under verification
  • Mlb as well as Mlc are turned off and Mia is turned on to pass the verifying voltage +1 5V from XT1 to WLl for verification
  • Mia is turned on to pass the verifying voltage +1 5V from XT1
  • FIG 6 shows a third embodiment of this invention
  • the flash memory circuit comprises a WL decoder 52, an SL decoder 60 and a memory bank 80 having an array of memory cells
  • Each memory bank has a first WL latch 11, a second WL latch 12, an SL latch 30, and an XS latch 70 associated with the bank
  • a bank decoder 40 selects different memory banks of the flash memory
  • This embodiment is almost identical to the second embodiment desc ⁇ bed earlier except that two WL latches are used to send XDl and XD2 signals to the gates of the p-MOS transistor and n-MOS transistor in the WL decoder 52 respectively
  • This embodiment offers some protection on the p-n transistors in certain cases because the two gates of each p-n transistor pair are not connected together and the two WL latches can provide different voltages
  • XD2 can be applied +1V for turning on the n-MOS transistor in order to pass XS signal to a WL and the p- MOS transistor can
  • FIG 7 shows a fourth embodiment of this invention
  • the flash memory circuit comprises a WL decoder 53, an SL decoder 60 and a memory bank 80 having an array of memory cells
  • Each memory bank has an odd WL latch 10, an even WL latch 20, an SL latch 30, and an XS latch 70 associated with the bank
  • a bank decoder 40 selects different memory banks of the flash memory
  • This embodiment is also very similar to the second embodiment except that even and odd WL latches are used to control even and odd WLs separately in the memory bank As shown in FIG 7, only half of the address lines are required in the WL decoder 53 of this embodiment In other words, each pair of
  • the additional WL latch 20 saves half of the address lines for this embodiment but provides equivalent decoding function
  • a source line is shared by every two adjacent WLs as shown in the embodiments of FIGs 1, 4, 6, and 7
  • each WL also has an n-transistor of which the gate is coupled to the WL, the source is connected to the shared source line and the dram is connected to a common SLY line as shown in FIGs 1, 4, 6 and 7
  • the n- transistor is denoted as Ml 00 in FIG 1
  • the common SLY line and the transistor Ml 00 for the source lines serve to drain large cell current of multiple bits in parallel when it is required during program operation of the flash memory array Therefore, for the layout of the circuit, a narrow metal line of one word line width can be used for each source line
  • the four embodiments described so far provide the erasure of a flexible number of WLs from two to a large number of WLs
  • the invention further provides an innovative way of dividing a WL pair into a plurality of segments so that the memory cells in each segment of the WL pair can be selectively erased
  • FIG 10a it is assumed that the memory cells in the memory array have a number of bit lines BL1, BL2, , BLN, BL(N+1), , BL(2N), , and so on
  • the word line pair WLl and WL2 are divided into a plurality of segments each having N bit lines Take the first segment having bit lines BL1, BL2, , BLN as an example
  • the sources of these memory cells are wired together to form a segmented source line SL11 and then connected to the source line SL1 through an n-MOS transistor M50 Similarly, the sources of the memory cells on the first segment of WL3 and WL4 pair are wired together to form a segmented
  • a prior art U S patent No 4,949,309 discloses a similar but different source line circuit that also has two transistors controlling the circuit
  • a first metal layer is used for both bit lines and source lines that run vertically, and the controlling transistors are constructed with a second polysilicon (Poly2) layer
  • An exemplary layout of the circuit structure of FIG 10a is shown in FIG 1 The layout shows two segments of four WLs. SLC1 and SLC2 are the source segment control lines of the first and second segments respectively.
  • a first polysilicon (Polyl) layer is used to form the floating gates of the memory cells and the second polysilicon (Poly2) layer is used for the word lines.
  • This invention presents the layout as shown in FIG. 11 in which the source segment control lines SLC1 and SLC2 as well as the transistors M50 and M60 are constructed with the Polyl layer. Because in the flash memory technology the Polyl layer is used to form the isolated floating gate of all memory cells, the Polyl layer without the mask of Poly2 layer is etched away. This is done by using a self-aligned etching (SAE) technique with a special SAE mask. In this invention, however, the transistors M50 and M60 as well as control lines SLC1 and SLC2 have to be protected from being etched away. Therefore, the traditional SAE layer can be modified to exclude these Polyl devices and its Polyl gate lines from the regular Polyl lines which are overlapping with the first metal lines of bit lines. No extra mask is required.
  • SAE self-aligned etching
  • Transistors Mia, Mlb and Mlc of FIG. 2 form a gating device that is used for the first embodiment and transistors Mia, Mlb and Mlc of FIG. 5 form another gating device that can be used for the second embodiment.
  • the gating device can be modified in many ways by designing the circuit properly.
  • the circuit of FIG. 12a can be used to replace Mia, Mlb and Mlc of FIG. 2.
  • the circuit of FIG. 12a can be used to replace Mia, Mlb and Mlc of FIG. 2.
  • FIGJ2c has identical function as the circuit formed by Mia, Mlb and Mlc of FIG. 5.
  • the exemplary circuits shown and illustrated above are presented only for the convenience of explaining the principle of this invention. A person skilled in the field should be able to make modification that comes within the spirit of this invention based on the above described principle.
  • a decoder circuit of a flash memory provides appropriate bias conditions for different memory operations to ensure that the flash memory functions properly
  • there are two types of conventional bias conditions widely used for an erase operation They can generally be catego ⁇ zed into a source erasing method and a negative-gate erasing method Both methods rely on the Fowler-Nordheim tunneling mechanism to extract electrons from a floating gate to a source through a very thin oxide between the overlap region of the floating gate and the source To trigger the tunneling current, a sufficient electncal field has to be applied between the source and the gate
  • the source erasing method applies a +12V to the source line and a OV to the word line with the bit line being left floating It is the very high source voltage that provides a sufficient electric field to accomplish the erase operation
  • the negative-gate erasing method applies a -8V to the word line and a +5V to the source line with the bit line floating Because the gate has a negative voltage, the method requires a lower source voltage to provide enough electric field for the erase operation
  • the drawback of the source erasing method is that the high source voltage increases the requirement of a higher breakdown voltage for the memory cell as well as its peripheral circuit devices Therefore, a deeper junction as well as a thicker gate oxide of a peripheral transistor are needed These requirements make the memory device less shrinkable In addition, a higher source voltage also increases the difficulty of current supply which becomes a serious problem if the voltage is generated from an on-chip circuitry Typically, a voltage generator has to provide approximately 5mA to activate 64KB memory cells erasure (lOnA / cell) However, the supplying current of a high voltage generator decreases drastically if the output voltage increases Therefore, the source erasing method is less suitable for portable applications, which generally has only a single power supply Vcc and requires on-chip high voltage generation As a result, the negative-gate erasing method is more favorable due to its lower source voltage The lower source voltage can be easily generated on-chip, or even directly supplied by the power supply Vcc, if 5V Vcc is used It should be noted that there is no
  • the conventional source erasing method can be used for erasing one or more segments of a WL or WL pairs of this invention
  • the source of the selected segment is applied a positive voltage such as + 12V and the gate of the selected segment is grounded
  • the circuit of this invention as shown in FIGs 10a and 10b, only the segmented source lines of the selected segments are applied the high voltage
  • the segmented source lines of the non-selected segments are floating
  • both source disturbance and gate disturbance are eliminated
  • the required source current is much less than the high supplying current required for erasing 64k Bytes of memory cells as pointed out earlier
  • this bias condition still has the drawbacks of requiring thicker oxides and deeper junctions that have been discussed
  • the preferred bias condition for erasing one or multiple segments of a selected WL pair is applying a moderately negative voltage such as -4V to the gate line and a moderately positive voltage such as +7V to the source line with the bit line floating. Because the coupling ratio of a control gate (a word line) to a floating gate is approximately 50%, by adding 2V to the source voltage of a conventional negative-gate erasing method, the gate voltage can be reduced by approximately 4V, which significantly reduces the gate disturbance but still maintains the same electrical field for erasing memory_cell's data.
  • a WL is usually applied 5V. Therefore, the gate disturbance caused by a moderately negative voltage -4V on the non-selected segments in an erase operation is no more than the gate disturbance caused by a read operation. It is definitely negligible.
  • the source voltage is increased, the source disturbance of non-selected segments is not increased. Because each segment has its own decoded segmented source line such as SL1 1 or SL12 as shown in FIG. 10a, the segmented source lines of non- selected segments in the same WL pair are left floating.
  • the moderately positive source voltage frees the requirement of a thicker oxide and a large supply current of conventional source erasing method.
  • the breakdown voltage (BVDSS) of the current device technology widely used is approximately higher than 8V.
  • the moderately positive source line voltage is still lower than the breakdown voltage. Therefore, it is not necessary to increase the oxide thickness or the junction depth for the peripheral devices.
  • the +7V source line voltage can be easily achieved by an on-chip pump circuit which requires only one stage if 5V Vcc is used or two stages if 3V Vcc is used. Consequently, the new bias condition offers the advantages of negligible gate disturbance and easily pumped source voltage over the conventional bias conditions. It is also compatible with current device manufacturing technology. It is also worth mentioning that the source line voltage and the gate line voltage just described are only an example. Other moderate values can also be used.
  • the bias conditions used for the flash memory of this invention are as follows.
  • the bias condition of the conventional negative- gate erasing method is appropriate and favored for erasing the memory cells of one or multiple WL pairs because it has the advantage of a lower source voltage.
  • the bias condition for the conventional source erasing method or the moderate method can be used for erasing the memory cells of one or more segments of a WL or WL pair.
  • the most appropriate bias condition is adaptively used according to the size of the erase operation to be executed
  • the preferred mode of operation of the flash memory circuits of this invention is to erase a word line pair or word line segment pair that share a same source line at the same time
  • the circuits also allow the erasure of the memory cells on a single word line It is even possible to erase the memory cells of a single bytes or a small segment of a single word line Nevertheless, the memory cells of adjacent non-selected word lines or word line segments may be stressed and disturbed
  • a method of overcoming the drawback of erasing a single selected word line is to remember and store the programmed data of the stressed memory cells on the non-selected adjacent WL before the erase operation After the selected WL has been successfully erased and verified, the stored data of its adjacent WL before erasing are retrieved and compared with the read data of the memory cells on the disturbed WL after erasing A post-programming operation is performed to restore the data if these data do not match within a safe read margin
  • this approach can also be applied to a conventional flash memory circuit, the present invention provides
  • FIG 13 shows a flow chart of the procedure for post-programming the stressed memory cells after an erase operation assuming that these memory cells are not selected for erasing and their data have been stored for retrieval It can be summarized as follows l
  • the memory data of the stressed memory cells are read and compared with the stored memory data li Venfy data "0" which has a threshold voltage around 4V in a 3V operation If it fails, the memory cell is post-programmed to restore its threshold voltage back to more than 4V If the allowable erase time is exceeded before being successfully re-programmed, the flash memory device is considered defective in Ve ⁇ fy data "1" which has a threshold voltage around IV in a 3V operation If it fails, the memory cell is post-programmed to restore its threshold voltage back to IV If the allowable erase time is exceeded before being successfully programmed, the flash memory device is considered defective.
  • This mode of the erase operation is called multiple word line mode It can be summarized as follows a Select the word lines that are to be erased b Read the memory data from the memory cells of the adjacent non-selected word lines that will suffer from data disturbance during the erase operation, i e , each word line that shares a same source line with a word line which has been selected for erasing, and store the data in either on-chip or off-chip temporary storage devices such as static random access memories (SRAM) c Apply an appropriate bias condition to the selected word lines for erasing one or more word lines and shut off the other non-selected word lines d Apply an erase pulse to the selected word lines e Verify the memory cells on the selected word lines If all the selected word lines have successfully passed the verification, go to step g f.
  • SRAM static random access memories
  • step e Re-select the word lines that fail the verification in step e for the next cycle of the erase operation and go to step c if the allowable erase time limit has not been reached If the allowable erase time limit has been exceeded, the erase operation is terminated and flash memory device is considered defective g Execute a post-programming procedure as shown in FIG. 13.
  • step f the selected word lines that have passed the verification will be reset as non-selected and the erase pulse will not be applied to these word lines in the next cycle of the erase operation This significantly reduces the number of over-erased cells
  • the conventional flash memory keeps on erasing these word lines until all the selected word lines are successfully erased and verified
  • step f the operation goes back to step c and the bias condition is updated according to the memory cells' threshold voltage which is detected in the verification step as discussed earlier.
  • the flash memory circuit of this invention may also divide the memory cells on word lines into a number of segments For erasing memory cells of one or multiple segments of a single word line, the operation is similar except that the non-selected memory cells that suffer from the word line disturbance on the selected word line also have to be read and stored in a temporary storage device such as a SRAM in addition to the memory cells of the adjacent non-selected word line that suffer from the source disturbance Those memory cells have to be verified and restored if they have been disturbed during the erase operation
  • FIG 15 shows a flow chart of the method of erasing one or multiple segments of a single word line or a word line pair in this invention This mode of the erase operation is named as a multiple segment mode It can be summarized as follows
  • step G Apply an appropriate bias condition to the selected word line segments for erasing one or more word line segments and shut off non-selected word line segments as well as other non-selected word lines D Apply an erase pulse to the selected word line segments E Ve ⁇ fy the memory cells on the selected word line segments If all the selected word line segments have successfully passed the ve ⁇ fication, go to step G
  • step F Re-select the word line segments that fail the verification in step E for the next cycle of the erase operation and go to step C if the allowable erase time limit has not been reached If the allowable erase time limit has been exceeded, the erase operation is terminated and flash memory device is considered defective
  • each selected segment can be stopped from being erased after it has passed the verification in step F
  • the bias condition presented earlier by providing a moderately positive voltage to the segmented source lines and a moderately negative voltage to the gate should be used for the selected word line segments in step C of the erase operation
  • the segmented source lines of non-selected word line segments should be left floating
  • the bias condition reduces gate disturbance to the non-selected word line segments
  • This invention further provides a two-step operation for further enhancing the erase operation of the disclosed flash memory circuits by combining the benefits of both methods of FIGs 14 and 15
  • a conventional flash memory circuit if there are some memory cells that take significantly long time to erase when the memory cells of a multiple of word lines are selected for erasing, all the other selected cells have to be continuously erased until these slow cells are successfully erased This not only increases the number of over
  • the flow chart of FIG 16 shows a new method of erasing multiple word lines
  • the erase operation as shown in FIG 16 comp ⁇ ses both multiple word line and multiple segment modes
  • the selected word lines are erased by the multiple word line mode of operation, in which all the selected multiple word lines are erased together and each word line that passes verification is independently stopped from being erased
  • the erase operation is switched to the multiple segment mode In the multiple segment mode, the word lines which still have memory cells not successfully erased are detected and erased WL by WL
  • the erase pulse is applied to the multiple segments which contain the memory cells not successfully erased Each segment can be independently stopped from being erased when it passes the ve ⁇ fication After all the segments of a word line are successfully erased and verified, the next word line which contains memory cells not successfully erased is detected and the multiple segment mode erasing proceeds The multiple segment mode of the erase operation will be repeated until all the memory cells on the selected word lines are successfully erased and verified Nearly all the steps executed in the method of FIG 14 are repeated in FIG 16 except step f In step f , the method of FIG 16 determines whether the erase operation should be switched to the multiple segment mode if the allowable erase time limit has not been reached The decision can be made based on a number of factors such as the number of erase pulses applied, the number of memory cells fail the verification, or the minimum threshold voltage of erased memory cells
  • a few examples of deciding if a multiple word line mode of erasing should be switched to a multiple segment mode are given as follows Assumes that the memory cells of multiple word lines are selected for erasing Five word lines represent a portion of the total selected word lines A pre-determined condition for changing the mode can be set as when the total number of word lines that fail the erase-verification becomes less than 5 The total number of erase pulses that have been applied to the selected word lines may also be used as an additional constraint As an example, if the number of erase pulses has exceeded a pre-determined number such as 100 and the total number of word lines that fail the erase- ve ⁇ fication is less than 5, the multiple segment mode of erasing can be triggered It is also reasonable to use the maximum threshold voltage of the memory cells as an additional c ⁇ te ⁇ on The point of switching from a multiple word line mode to a multiple segment mode can be when the maximum threshold voltage of the memory cells that fail the erase- ve ⁇ fication is higher than a pre-determined value such as 3 V and the
  • the erase operation goes back to the method of FIG. 14. If the erase operation is switched to the multiple segment mode, the word line segments of each word line are identified based on the verification result. The identified word line segments of each word line are then selected for erasing by means of the method as shown in FIG. 15. By being able to switch to the multiple segment mode, the word line segments that do not contain the slow memory cells will be less disturbed by the long erasing time. Therefore, the over-erasure problem is eliminated and the power consumption is significantly reduced.

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Abstract

Cette invention se rapporte à un circuit de mémoire flash ayant un décodeur (50) de ligne de mot doté de bascules pour les lignes de mots paires (10) et impaires (20) et un décodeur (60) de ligne de source doté d'une bascule (30) de ligne de source. Le décodeur (50) de ligne de mot et le décodeur de ligne de source rendent possible l'effacement simultané de cellules de mémoire de deux lignes de mots adjacentes et la vérification de cellules de mémoire, ligne de mot par ligne de mot. L'effacement simultané de deux rangées adjacentes permet aux réalisations de cette invention de résoudre les problèmes de sur-effacement et de perturbation de la source associés aux circuits de mémoires flash classiques. Cette architecture de décodage permet un effacement à dimension variable, qui peut aller de l'effacement d'une paire de lignes de mots à celui d'un grand nombre de multiples paires de lignes de mots. En divisant les cellules de mémoire d'une ligne de mot en un certain nombre de segments, le circuit de décodage rend possible la sélection de cellules de mémoire d'un segment de ligne de mot en vue de leur effacement.
PCT/US1998/011082 1997-06-05 1998-06-01 Nouvelle architecture de decodage et de matrice de memoire flash WO1998056002A1 (fr)

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KR101937816B1 (ko) * 2012-04-23 2019-01-11 에스케이하이닉스 주식회사 래치 회로 및 비휘발성 메모리 장치

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