WO1998056002A1

WO1998056002A1 - Novel flash memory array and decoding architecture

Info

Publication number: WO1998056002A1
Application number: PCT/US1998/011082
Authority: WO
Inventors: Peter Wung Lee; Fu-Chang Hsu; Hsing-Ya Tsao
Original assignee: Peter Wung Lee; Hsu Fu Chang; Tsao Hsing Ya
Priority date: 1997-06-05
Filing date: 1998-06-01
Publication date: 1998-12-10
Also published as: JP2000516380A

Abstract

A flash memory circuit having a word line decoder (50) with even (10) and odd (20) word line latches and a source line decoder (60) with a source line latch (30) is disclosed. The word line decoder (5) and source line decoder (60) provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminate over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that can be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing.

Description

NOVEL FLASH MEMORY ARRAY AND DECODING ARCHITECTURE

FIELD OF INVENTION

The present invention relates to the design and circuit structure of a flash memory, and more specifically to the architecture of word line and source line decoders of a flash memory.

BACKGROUND OF THE INVENTION

In recent years, flash memory devices have been widely used in computer related equipment and other electronic appliances as storage devices. The nonvolatile and on-chip programmable capabilities of a flash memory are very important for storing data in many applications. As an example, flash memories are frequently used for the BIOS storage of a personal computer. In addition, the small physical size of flash memories also makes them very suitable for portable applications. Therefore, they have been used for storing programs and data for many portable electronic devices such as cellular phones, digital cameras and video game platforms. Different from a normal random access memory (RAM) that can be randomly read, erased and programmed on a byte basis, a conventional EPROM-type flash memory features a byte-program and a block-erase capability with each block containing a number of bytes. Because the data within a memory block can not be selected for erasure individually, a flash memory has to erase the data of a whole block of memory cells, i. e., an erase block, and then program the new data byte by byte. The block erase scheme, however, not only is inflexible but also has an undesirable problem called over-erasure. The over-erasure results from the inherent difference between the speed of erasing of each memory cell. Because a large number of cells are erased together, the cells having fast speed of erasing may be over-erased below 0V, while the cells having slow speed are not successfully erased yet. The over-erased cells will conduct leakage current and cause the malfunction of bit line (BL) sense amplifiers.

To add more flexibility for erasing memory cells, isolate non-selected memory cells and avoid disturbance of data, U.S. Pat. No. 5,548,551 provides a negative voltage decoder for erasing either one memory cell or a block of memory cells for a non-volatile memory. In practical applications, however, it is desired that a small (multiple bytes) and flexible (random and multiple word lines) erase size for the erase operation of a flash memory can be accomplished without any memory disturbance and over-erasure problems.

SUMMARY OF THE INVENTION This invention has been made to overcome the above mentioned drawbacks of a conventional flash memory. The primary object of this invention is to provide a circuit structure that offers the capability of erasing memory cells on a small and flexible number of word lines of a flash memory. Another object of this invention is to provide a method of erasing a multiple number of word line pairs simultaneously as well as verifying each individual word line one at time. Yet another object of this invention is to provide a memory circuit structure and methods of operating the memory circuit to eliminate the memory disturbance and over-erasure problems that often occur in a conventional flash memory circuit. A further object of this invention is to provide a source line circuit having segmented source lines so that the flash memory cells of a small segment in a word line can be erased without source disturbance. A further object of this invention is to provide a source line circuit having segmented source lines so that the flash memory cells of a small segment in a word line can be erased without source disturbance. It is also an object of the invention to provide a new bias condition for erasing one of more segments in a word line and reduce the gate disturbance to non-selected segments. It is also another object of the invention to provide a novel erase operation flow to reduce the over-erasure and disturbance for achieving accurate memory cell's threshold voltage control.

The memory cells of the flash memory circuit of this invention are divided into a number of banks. The memory cells in each memory bank are organized as a plurality of rows and a plurality of columns. The sources of the memory cells of two adjacent rows are wired together and connected to a common source line. Each memory bank of this invention has its own word line decoder and source line decoder. The source line decoder has a source line latch associated with it for providing desired voltage levels under various memory operations. Address lines to the word line decoder and the source line decoder choose the selected word line and source line for memory operations. In a first preferred embodiment, each word line decoder has both odd and even word line latches associated with it. For the erase operation, the preferred mode of operation of this invention is to select two adjacent word lines which share the common source line from each memory bank for erasing. When the memory cells of the two adjacent word lines are erased, negative voltages can be applied through the word line latches to both word lines and a positive voltage such as 5V can be applied through the source line latch to provide an appropriate bias condition for the erase operation. When the memory cells are erase-verified, the word line under verification can be applied a verifying voltage through one word line latch while the other word line latch can provide a low voltage sufficient enough to cut off the over-erased memory cells on the other word line that is not under verification. Therefore, the false reading that usually exists in verifying a single word line is eliminated. In addition, each word line can be stopped erasing after being verified by applying appropriate voltage through its associated word line latch to reduce the over-erase problem. According to the embodiment, a multiple number of memory banks each having two word lines that share the same source line for erasing can be erased simultaneously with one erase operation. The erase size can be from a word line pair to a large number of multiple word line pairs.

In a second embodiment of this invention, there are also two latches associated with the decoder. One of the latches controls if the word line voltage of a selected memory row is provided by either the other latch or by the address lines. By supplying appropriate voltages to the address lines and the latches, a multiple pairs of word lines in a memory bank can be erased simultaneously and verified one by one properly. Nevertheless, if all the word lines in a memory bank are selected for erasing, any other memory bank can only have all its word lines erased or not at the same time because the address lines that may also provide word line voltages for this embodiment are shared by all memory banks. Therefore, for the erase operation, the preferred mode is to erase a multiple pairs of word lines less than the size of a memory bank in one erase operation or to erase a multiple memory banks simultaneously.

Two additional embodiments provide similar functions to the second embodiment are also disclosed. The third embodiment uses an additional latch for controlling how the word line voltage is supplied. With the additional latch, the device of a control circuit of the word line decoder can be better protected under certain conditions. The fourth embodiment which also uses an additional latch reduces the address lines required for both the word line decoder and the source line decoder to a half. The flexibility and preferred mode of operation for the two embodiments are the same as that of the second embodiment.

This invention also presents a source line circuit that allows the selection of the memory cells of a small segment in a row for erasing. By dividing the memory array of a memory bank into a number of segments each comprising a number of columns, the sources of the memory cells of two adjacent rows in a segment can be wired together to form a segmented source line. Each segmented source line on the same word line is connected to a shared source line through a source segment control transistor having a gate coupled to a source segment control line. Therefore, the memory cells on a word line can be erased segment by segment.

Although the preferred mode of an erase operation in this invention is to erase the memory cells of two adjacent word lines that share a same source line simultaneously, a post-programming approach is provided for restoring the data of disturbed memory cells if only the memory cells of a single word line are erased at one time. Two modes of erasing memory cells are disclosed for erasing multiple word lines and multiple segments in a word line respectively. A different bias condition is used in each mode. A combined method that takes advantage of the benefits of both modes is presented to eliminate the over-erasure problem, save erasing time and reduce consumed power.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a first embodiment of the circuit of a memory bank of the present invention including a bank decoder, a word line decoder with even and odd word line latch, and a source line decoder with a source line latch.

FIG. 2 shows the word line decoder circuit of the first embodiment shown in FIG. 1.

FIG. 3 a shows the memory array circuit of a memory bank and the operational conditions of the decoder circuit for various memory operations.

FIG. 3b summarizes the control signals for the first embodiment of this invention under different memory operations.

FIG. 4 shows a second embodiment of the circuit of a memory bank of the present invention including a bank decoder, a word line decoder with a word line latch and a source line decoder with a source line latch. shows the word line decoder circuit of the second embodiment shown in FIG 4 summarizes the control signals for the second embodiment of this invention under different memory operations shows a third embodiment for the circuit of a memory bank of this invention shows a fourth embodiment for the circuit of a memory bank of this invention shows a latch circuit for providing three voltage levels shows a latch circuit for providing two voltage levels shows a memory array circuit having segmented source lines of this invention shows an alternative memory array circuit having segmented source lines of this invention shows an exemplary layout for the memory array circuit of FIG 10a shows an exemplary gating device which can be used to replace the gating device of FIG 2 shows an exemplary gating device which can be used to replace the gating device of FIG 5 shows another exemplary gating device which can be used to replace the gating device of FIG 5 shows a flow chart of a post-programming method of this invention for reprogramming the memory cells that suffer from data disturbance when the memory cells of a word line pair are not simultaneously selected for erasing shows a first mode of the erase operation of this invention in which the memory cells of a multiple of word lines are selected for erasing shows a second mode of the erase operation of this invention in which the memory cells of a multiple of word line segments are selected for erasing shows a third mode of the erase operation of this invention which combines the benefits of the first and second modes of FIGs 14 and 15 for erasing the memory cells of a multiple of word lines DETAILED DESCRIPTION OF THE INVENTION

The present invention divides a flash memory into a plurality of memory banks. With reference to the first embodiment of this invention as shown in FIG. 1, the flash memory circuit comprises a word line (WL) decoder 50, a source line (SL) decoder 60 and a memory bank 80 having an array of memory cells. Each memory bank has an odd WL latch 10, an even WL latch 20 and an SL latch 30 associated with it. A bank decoder 40 for selecting different memory banks of the flash memory is also shown. The WL latches and the SL latch are controlled by the bank decoder. XT1-XT4 and XTB 1-XTB4 are address lines that work with the WL decoder 50 to pass or block the voltages from the WL latches to the word lines. ST1-ST4 and STB1-STB4 are address lines that control the SL decoder 60 to pass or block the voltage from the SL latch to the source lines. An XS word control line is connected to a ground voltage in this embodiment.

By means of either the WL latch 10 or 20 and the SL latch 30, the decoder circuit as shown in FIG. 1 allows the erasure of the memory cells on a single word line by applying a negative voltage to the word line and a positive 5V voltage to the source line. (In general, a single word line may comprise 128 or 256 bytes.) However, in the flash memory design of this invention, two adjacent word lines share a same source line as shown in FIG. 1. For example, WL1 and WL2 share one source line SL1. If only WL1 is selected for erasing, erase disturbance may occur on the adjacent non-selected word line WL2. A method of overcoming the drawback of erasing a single selected WL is to read and store the programmed data of the memory cells on its adjacent WL before the erasing. During the erase-verification, the adjacent WL is turned off. After the selected WL has been successfully verified, the data of the memory cells of its source-disturbed adjacent WL after erasing are read and the previously stored data before erasing are retrieved. The read data and stored data are compared. If the data do not match, a program operation is performed to re-program the stored data to the disturbed memory cells. With this method, the circuit shown in the first embodiment of this invention has the flexibility of erasing any number of selected WLs as long as their adjacent WLs that may be disturbed are remembered first and restored later. A preferred operation of the flash memory circuit of the first embodiment, however, is to simultaneously erase two adjacent WLs having a shared source line so that verification can be accomplished without disturbance. The odd and even WL latches 10, 20 of this invention provide the capability of erasing the memory cells on the two adjacent WLs altogether. If both odd and even WL latches in a selected memory bank apply negative voltages to a selected pair of WLs, and the SL latch in the selected memory bank applies a positive voltage to a selected SL, a pair of word lines can be erased simultaneously and then verified one by one as long as appropriate address signals are sent to the address lines.

All other WLs in the selected memory bank can be grounded through the word control line XS if they are not selected for erasing by the address lines. Similarly, non- selected SLs can also be grounded. Therefore, no memory cells other than the selected memory cells are affected by the biased voltages being applied for the erase operation. The memory disturbance problem is eliminated. In addition, each memory bank has its own odd and even WL latches as well as an SL latch, the erase operation can be applied independently without affecting other memory banks. Consequently, the erase size of the flash memory is very flexible and can be as small as a pair of WLs or a plurality of pairs of WLs. In addition, the memory banks selected for erasing can be almost randomly located anywhere within the flash memory.

To explain the operation of the WL decoder 50 in more detail, the decoder circuit is shown in FIG. 2 again. It can be seen that a p-n transistor pair and another n transistor control if each word line will be connected to a WL latch or grounded to the word control line XS. It is important to note that the preferred erase operation of this embodiment selects a plurality of memory banks with only a pair of WLs from each memory bank to erase if a multiple pairs of WLs are to be erased all at once. By doing so, the disturbance problem can be avoided. From the user's point of view, the logical addresses of the erased memory WLs may still be continuous. However, the bank decoder of this embodiment ensures that only one pair of WLs are selected from each physical memory bank. Although the circuit as shown in FIG. 1 can erase more than one pair of WLs in one memory bank at once, the advantage of this invention can not be fully realized unless only a pair of WLs from each memory bank are erased simultaneously.

An example of erasing two pairs of WLs is used to explain the operational conditions of the decoder circuit shown in FIG. 2. It is assumed that both WLl and WL2 of first and second memory banks are selected for erasing. The address lines are applied appropriate voltages to select WLl and WL2, 1 e , 0V for XT1, -8V for XT2-XT4, -8V for XTB1 and 0V for XTB2-XTB4 The XS line in this embodiment is always grounded In the two selected memory banks, both odd and even WL latches apply -8V to XD1 and XD2 respectively In the word line decoder 50, there are a plurality of word gating devices each having three transistors for controlling the connection of word lines For example, WLl is controlled by transistors Mia, Mlb and Mlc Each word line can be connected to either a WL latch or the word control line XS Under these bias conditions, Mia and M2a as well as Mlb and M2b are turned on, and Mlc and M2c are turned off to pass XD1 and XD2 to WLl and WL2 M3a~M8a as well as M3b~M8b are turned off and M3c~M8c are turned on to pass the XS signal to WL3-WL8 Therefore, WLl as well as WL2 are applied -8V for erasing and WL3-WL8 are grounded and not selected in both memory banks

The source line decoder 60 compπses a plurality of source gating devices each having two transistors for controlling the connection of a source line to either the SL latch 30 or a source control line SLS The address lines ST1-ST4 and STB1~STB4 controls the source gating devices for connecting one of the source lines to the SL latch 30 In general, ST1-ST4 have the same logic as XT1-XT4 but may have different voltages and STB1-STB4 have the same logic as XTB1-XTB4 but may have different voltages

For other memory banks not selected for erasing, both odd and even WL latches apply ground voltages to XD1 and XD2 respectively Because the conditions of the address lines XT1-XT4 and XTB1-XTB4 have been determined by the WLs selected for erasing, WLl and WL2 are connected to the ground voltage of XD1 and XD2 respectively, and WL3-WL8 are also passed with the ground voltage of XS Therefore, none of the WLs is affected by the erase operation

After a predetermined erasing time the threshold voltage of each cell on each erased WL is verified sequentially to check if the erase operation is finished The WL to be verified is applied a positive low voltage such as 1 5V The other erased WLs are applied a negative low voltage such as -3V to cut off all the memory cells on them even if any of the cells has been over-erased and having a threshold voltage between 0V and -3V The cut-off negative voltage is dependent on the threshold voltages of the over-erased cells It is detected before the erase-veπfication by lowering down the erased WL voltage until no memory cell current is sensed The detail of determining the threshold voltage is disclosed in U S patent application Ser. Nr. 08/823,571 filed March 25, 1997 assigned to the same assignee of this invention.

The non-selected WLs are applied a small or ground voltage, such as OV. Assuming that WLl of the first memory bank is verified, the address lines are applied appropriate voltages to select WLl, i.e., a power supplying voltage Vdd for XT1, -3V for XT2-XT4, - 3V for XTB 1 and Vdd for XTB2-XTB4. In the first memory bank where the verified WLl is located, the odd WL latch applies the verifying voltage, i.e. 1.5V, to XDl and the even WL latch applies the cut-off negative voltage such as -3V to XD2. Under these bias conditions, Mia and M2a as well as Mlb and M2b are turned on, and Mlc and M2c are turned off to pass XDl and XD2 to WLl and WL2 respectively. M3a~M8a as well as M3b~M8b are turned off and M3c~M8c are turned on to pass the XS signal to WL3-WL8. Therefore, WLl is applied the verifying voltage 1.5V, WL2 is applied the cut-off voltage - 3V, and WL3-WL8 are grounded in the memory bank.

In the second memory bank that has an erased WLl which is not under verification, both odd and even WL latches apply a negative cut-off voltage -3V to XDl and XD2 respectively. Because the address lines are shared, the bias conditions make WLl and WL2 connected to the cut-off voltage -3V of XDl and XD2 respectively, and WL3-WL8 passed with the ground voltage of XS. For other memory banks that have no WL selected for erasing at all, both WL latches apply 0V to XDl and XD2 respectively. Therefore, WLl and WL2 are grounded to 0V of XDl and XD2 correspondingly and WL3-WL8 are grounded to 0V of XS.

After the verification, if WLl of the first memory bank fails the erase- verification, it will be erased again with the same operation conditions that have been described earlier. If it passes the verification, WLl will be applied a negative cut-off voltage to stop erasing and cut-off the over-erased memory cells at the same time if there are any over-erased cells. Under this situation, the operation conditions of the next erase cycle are similar to those conditions which have been described earlier except that the odd WL latch in the first memory bank will apply a negative cut-off voltage to XDl .

Based on the forgoing discussion, the present invention provides a decoder circuit for erasing multiple and random WL pairs at the same time. It should be noted that the erase operation of each individual WL is stopped independently. Because each erased WL is controlled by either an even WL latch or an odd WL latch, the erase operation of the WL that already passes the erase-verification can be stopped by resetting its corresponding WL latch to an erase-inhibit state. It is not necessary to wait for the WL that has the slowest speed of being erased to complete erasing before other WLs can be stopped erasing. The advantage of being able to stop erasing independently is that the problem associated with over-erasure of conventional flash memories is greatly reduced.

A keen reader may notice that if a pair of WLs sharing a same SL are erased simultaneously, the verified WL may suffer false reading when it is under erase-verification unless the adjacent WL is cut off. Conventionally, the control gate of the WL not for verification is grounded. However, if a memory cell on the adjacent WL has been over- erased, it can not be shut-off by grounding its control gate. Because the over-erased memory cell conducts current and shares the same source line with the WL being verified, the erase-verification may give an incorrect result. As described in the above example, a negative cut-off voltage determined by the technique disclosed in the referenced U.S. patent application Ser. Nr. 08/823,571 is applied to the adjacent WL to eliminate the false reading problem.

It is also worth while to mention that the flash memory of this invention requires three control gate voltages for the WLs when erase-verification is performed. In addition to the verifying voltage and the ground voltage as used in a conventional flash memory, a negative cut-off voltage as mentioned in the previous paragraph is necessary. U.S. patent No. 5,687,121 and U.S. patent application Ser. Nr. 08/676,066 that both are assigned to the same assignee of this invention disclose a method for applying at least three voltages from the WL latches. The technique is incorporated in this invention for providing three different control gate voltages to the WLs. FIG. 3 a shows an example of the bias conditions for various memory operations of the word lines in one memory bank. It is assumed that both WLl and WL2 have been selected for erasing, i.e., XDl, XD2 and SLX have been connected to WLl, WL2 and SL1 respectively by the address lines. The conditions for an erase operation and an erase-verify operation have been described in the earlier discussion in connection with FIG. 2. For erase operation, both XDl and XD2 are -8V and SLX is 5V. For erase-verification of WLl, XDl is +1.5V, XD2 is a negative cut-off voltage -Vx that has been assumed -3V in the earlier discussion, and SLX is OV For over-erase- verification of WLl, XDl is a voltage +0 5 V, XD2 is a negative cut-off voltage -Vx, and SLX is OV For repairing WLl, XDl is +5V, XD2 is a negative cut-off voltage -Vx, SLX is OV For programming WLl, XDl is +8V, and both XD2 and SLX are OV A summary of required WL voltages of this embodiment under different operations is as follows Three voltages are required for erase, erase-venfy, over-erase-venfy, and repair operations For WLs selected for erasing, an operating voltage is applied For a WL that is erase-venfied or over-erase-veπfied, an erase-venfy voltage or a repair voltage is applied For a WL that has been erased but not under verification, a negative cut-off voltage is applied to shut off the WL For WLs that have not been selected for erasing, they are grounded It should be noted that after the repair operation, all over-erased WLs are recovered It is not necessary to shut off the over-erased memory cells any more Therefore, only two voltages are required for program and read operations An operating voltage is applied to the programmed or read WL and the other WLs are grounded A summary of the control signals for the first embodiment of this invention under different memory operations is listed in FIG 3 b

FIG 4 shows a second embodiment of the present invention In this embodiment, the flash memory circuit comprises a WL decoder 51, an SL decoder 60 and a memory bank 80 having an array of memory cells Each memory bank has a WL latch 11, an SL latch 30, and a word control line (XS) latch 70 associated with the bank A bank decoder 40 selects different memory banks of the flash memory The SL decoder 60, the SL latch 30, the memory bank 80 and the bank decoder 40 are identical to those described in the first embodiment The same numerals are also used to identify these circuit blocks In the word line decoder 51, there are a plurality of word gating devices each having three transistors for controlling the connection of word lines For example, WLl is controlled by a gating device having transistors Mia, Mlb and Mlc By means of the WL latch 11, the SL latch 30, and the XS latch 70, the WL decoder circuit 51 as shown in FIG 4 can connect each WL within a memory bank to either its address line XT (one of XT1-XT4) or the XS latch 70 If the number of WLs selected for erasing is less than the size of a memory bank, the WL latch 11 of the memory bank sends a negative voltage to XD that makes the connection of each WL in the memory bank dependent on its respective address line XT If the address line is a negative voltage, the corresponding WL is connected to the XS latch 70 which provides a negative voltage for erasing If the address line is grounded, the corresponding WL is also grounded Due to less flexibility of the WL decoder 51, if the number of WLs selected for erasing is greater than the size of a memory bank, this embodiment can only erase all the WLs of one or more memory banks altogether and the erase size has to be a multiple of the size of a memory bank In other words, if all the WLs within one memory bank have been selected for erasing, all the WLs of any other memory bank have to be either selected for erasing or not selected for erasing Although the erase size is not as flexible as the first embodiment, it is still possible to have very flexible erase size by using two erase operations

As can be seen from FIG 4, two adjacent word lines share a same source line It is difficult to avoid the memory disturbance problem As discussed in the first embodiment, it is preferred that two adjacent WLs be erased altogether at the same time although any number of WLs less than the size of a memory bank can be selected for erasing Therefore, the preferred mode of operation of the decoder circuit of this embodiment has an erase size being an even number less than the size of a memory bank, or a multiple of the size of a memory bank

For describing the operation of the second embodiment, the WL decoder circuit 51 of a memory bank is shown again in FIG 5a Each memory bank has only one WL latch for generating XD signal The XD signal is sent to the common gates of a p-n transistor pair as shown in FIG 5a Each address line XT is sent to the drain of a p-MOS transistor The drains of two n-MOS transistors are tied together and connected to the XS latch 70 Therefore, either XT or XS is passed to a WL according to the XD signal Eight WLs are shown in one memory bank in this example

To illustrate how the decoder works, the case of selecting only a number of WLs less than the size of a memory bank for erasing is discussed first The voltages of XT1-XT4 are -8V, XT5-XT8 are 0V, XTB1-XTB4 are +1V, and XTB5-XTB8 are -8V to select WL1-WL4 of the memory bank for erasing The WL latch and the XS latch of the selected memory bank apply -8V to XD and XS respectively Under these conditions, Mla~M4a as well as Mlb~M4b are turned off and Mlc~M4c are turned on to pass a negative voltage -8V from XS to the selected word lines WL1-WL4 In the mean time, M5b~M8b as well as M5c~M8c are turned off and M5a~M8a are turned on to pass a OV from XT5-XT8 to the non-selected word lines WL5-WL8

Because XT1-XT8 and XTB1-XTB8 are shared by respective WLs in each memory bank, the bias conditions of XT1-XT8 and XTB1-XTB8 have been determined by the WLs of the memory bank selected for erasing as described in the previous paragraph The control of the non-selected memory banks has to be accomplished by appropriate XD and XS voltages within the memory bank. For memory banks that are not selected for erasing, XD is applied -8V and XS is applied OV. Because the voltages of its WL1-WL4 are passed from XS as described in the previous paragraph, they are OV The voltages passed from XT5-XT8 to WL5-WL8 are also OV Therefore, all the WLs are not selected for erasing

To stop erasing any word line of the selected WLs, the corresponding XT can be applied a negative cut-off voltage for passing to the WL For example, if only WLl has passed the erase-verification, a negative cut-off voltage low enough to turn off the memory cells on WLl is applied to XT1 The negative cut-off voltage is lower than the determined threshold voltage as discussed earlier in connection with the referenced U S patent application Ser Nr 08/823,571 A good example of the negative cut-off voltage may be - 3 V XT IB is also applied -8V Mlc is turned off and the negative bias voltage turns on Mia and passes itself to WLl The remaining word lines WL2-WL4 are not affected and their erase operation continue

After an erase operation for WL1-WL4, each word line can be verified individually For verifying the word line WLl, a verifying voltage such as +1 5V is applied to XT1, XT2-XT4 are applied a negative cut-off voltage -3V and XT5-XT8 are applied 0V XTB1 is applied a negative cut-off voltage -3V, XTB2-XTB4 are applied 0V and XTB5-XTB8 are applied a negative cut-off voltage -3V Both XD and XS are applied a negative cut-off voltage -3V from the WL latch and the XS latch respectively Under these conditions, M2a~M4a as well as M2b~M4b are turned off and M2c~M4c are turned on to pass the negative cut-off voltage -3N from XS to word lines WL2-WL4 that are erased but not under verification In the mean time, M5b~M8b as well as M5c~M8c are turned off and M5a~M8a are turned on to pass a 0V from XT5~XT8 to the non-selected word lines WL5-WL8 Mlb as well as Mlc are turned off and Mia is turned on to pass the verifying voltage +1 5V from XT1 to WLl for verification

As mentioned before, the second embodiment also allows the erasing of multiple memory banks all at once All the WLs of each selected memory bank must be erased or stopped together For the case of erasing multiple memory banks, XT1-XT8 are applied OV and XTB1-XTB8 are applied either -8V or OV For each memory bank selected for erasing, the corresponding WL latch applies OV to XD and the corresponding XS latch applies -8V to XS Under this circumstance, Mla~M8a are turned off and Mlb~M8b as well as Mlc~M8c are turned on Therefore, WL1-WL8 are applied a voltage -8V passed from XS for erasing For each memory bank not selected for erasing, the corresponding WL latch applies -8N to XD and the corresponding XS latch applies OV to XS Consequently, Mla~M8a are turned on and Mlb~M8b as well as Mlc~M8c are turned off WL1-WL8 are applied OV passed from XT1-XT8 respectively

Although the WLs of each selected memory bank must be erased or stopped together it is possible that one memory bank is stopped erasing while the other memory bank continues its erase operation When it is necessary to stop a selected memory bank, the XS latch applies a negative cut-off voltage as discussed before, such as -3V, to XS The negative cut-off voltage at XS is passed to all the WLs in the memory bank to shut off the memory cells because Mla~M8a are turned off and Mlb~M8b as well as Mlc~M8c are turned on

Each erased WL has to be verified individually If WLl of a memory bank is to be veπfied, XT1 is applied a verifying voltage +1 5V and XT2-XT8 are applied a negative cut-off voltage -3V XTB1 is applied a negative cut-off voltage -3V and XTB2-XTB8 are applied OV For the memory bank having the verified WLl, both XD and XS are applied a negative cut-off voltage -3V from the WL latch and the XS latch respectively Under these conditions, M2a~M8a as well as M2b~M8b are turned off and M2c~M8c are turned on to pass the negative cut-off voltage -3V from XS to word lines WL2-WL8 that are erased but not under verification In the mean time, Mlb as well as Mlc are turned off and Mia is turned on to pass the verifying voltage +1 5V from XT1 to WLl for verification For other memory banks that have been erased but not under verification, the corresponding WL latch applies +1V to XD and the corresponding XS latch also applies a negative cut-off voltage -3V to XS Under this circumstance, Mla~M8a are turned off and Mlb~M8b are turned on Mlc is turned off and M2c~M8c are turned on It can be understood that all the word lines WLJ-WL8 are applied the negative cut-off voltage -3V passed from XS so that the verification of WLl in the selected memory bank is not disturbed For each memory bank not selected for erasing, the corresponding WL latch applies +1V to XD and the corresponding XS latch applies OV to XS Consequently, Mla~M8a are turned off and Mlb~M8b are turned on Mlc is turned on and M2c~M8c are turned off The circuit condition also allows WL1-WL8 to be applied OV passed from XS FIG 5b summarizes the control signals for the second embodiment of this invention under different memory operations

FIG 6 shows a third embodiment of this invention In this embodiment, the flash memory circuit comprises a WL decoder 52, an SL decoder 60 and a memory bank 80 having an array of memory cells Each memory bank has a first WL latch 11, a second WL latch 12, an SL latch 30, and an XS latch 70 associated with the bank A bank decoder 40 selects different memory banks of the flash memory This embodiment is almost identical to the second embodiment descπbed earlier except that two WL latches are used to send XDl and XD2 signals to the gates of the p-MOS transistor and n-MOS transistor in the WL decoder 52 respectively This embodiment offers some protection on the p-n transistors in certain cases because the two gates of each p-n transistor pair are not connected together and the two WL latches can provide different voltages As an example, XD2 can be applied +1V for turning on the n-MOS transistor in order to pass XS signal to a WL and the p- MOS transistor can be shut off by applying 0V to XDl to avoid being broken down due to a large voltage difference between its source and gate

FIG 7 shows a fourth embodiment of this invention In this embodiment, the flash memory circuit comprises a WL decoder 53, an SL decoder 60 and a memory bank 80 having an array of memory cells Each memory bank has an odd WL latch 10, an even WL latch 20, an SL latch 30, and an XS latch 70 associated with the bank A bank decoder 40 selects different memory banks of the flash memory This embodiment is also very similar to the second embodiment except that even and odd WL latches are used to control even and odd WLs separately in the memory bank As shown in FIG 7, only half of the address lines are required in the WL decoder 53 of this embodiment In other words, each pair of

WLs controlled by odd and even WL latches share an address line of XT1-XT4 Compared to the second embodiment, the additional WL latch 20 saves half of the address lines for this embodiment but provides equivalent decoding function

It should be noted that all the embodiments of this invention require that three different voltages be available to control signals such as XD in the first embodiment or XT in second, third and fourth embodiments for operation An earlier U S patent application 08/676,066 assigned to the same assignee of this invention discloses a latch circuit that can provide three different voltages Another U S patent application 08/823,571 assigned to the same assignee of this invention discloses methods of memory operations by applying different voltages for avoiding over-erasure problems The WL latches of this invention uses the latch circuit and the methods described in the referenced applications An example of such a latch circuit is shown in FIG 8 The circuit comprises first 100 and second 200 latches, and an output driver 400 If the first latch 200 stores a high voltage level for point B, the output driver 400 provides V3 to VOUT Otherwise, the output driver provides VI or V2 according to the high or low voltage level stored in the latch 100 for point A RES1, RES2, SI, S2 and S3 are control signals for setting and resetting the latch circuit as well as controlling it for proper operations under different modes Some of signal lines of this invention such as XS, SLX and XD in the second embodiment and XT in the first embodiment require latches that can provide two voltages An example of a two voltage latch as shown in FIG 9 can be used The operation of the latch is similar to that of FIG 8 except that only two voltage levels are available

According to this invention, a source line is shared by every two adjacent WLs as shown in the embodiments of FIGs 1, 4, 6, and 7 In the memory array, each WL also has an n-transistor of which the gate is coupled to the WL, the source is connected to the shared source line and the dram is connected to a common SLY line as shown in FIGs 1, 4, 6 and 7 The n- transistor is denoted as Ml 00 in FIG 1 The common SLY line and the transistor Ml 00 for the source lines serve to drain large cell current of multiple bits in parallel when it is required during program operation of the flash memory array Therefore, for the layout of the circuit, a narrow metal line of one word line width can be used for each source line A prior art paper titled "A new Decoding Scheme and Erase Sequence for 5V Only Sector Erasable Flash Memory", published in 1992 Symposium on VLSI Circuits

Digest of Technical Papers by Mitsubishi shows a flash memory using a wide metal line of four word line width for two source lines due to a large cell current required during program The common SLY line and the transistor Ml 00 in this invention make it possible to use a narrow metal line for a shared source line

The four embodiments described so far provide the erasure of a flexible number of WLs from two to a large number of WLs The invention further provides an innovative way of dividing a WL pair into a plurality of segments so that the memory cells in each segment of the WL pair can be selectively erased As shown in FIG 10a, it is assumed that the memory cells in the memory array have a number of bit lines BL1, BL2, , BLN, BL(N+1), , BL(2N), , and so on The word line pair WLl and WL2 are divided into a plurality of segments each having N bit lines Take the first segment having bit lines BL1, BL2, , BLN as an example The sources of these memory cells are wired together to form a segmented source line SL11 and then connected to the source line SL1 through an n-MOS transistor M50 Similarly, the sources of the memory cells on the first segment of WL3 and WL4 pair are wired together to form a segmented source line SL12 and then connected to the source line SL2 through another n-MOS transistor M60 The gates of the n-MOS transistors M50 and M60 are connected to a source segment control line SLC1 The control line SLC1 determines if M50 or M60 should be turned on to connect the corresponding segmented source line SL11 or SL12 to SL1 or SL2 respectively By controlling the voltage on SLC1, this invention further provides the capability of erasing only a segment of memory cells on each WL In other words, sub-WL erasing capability is accomplished by the circuit structure as shown in FIG 10a FIG 10b shows an alternative circuit structure for providing segmented source lines In FIG 10b, each segmented source line such as SL1 1 has two source segment control lines running on both sides of the segment (but connected to the same control line voltage SLC1) and two transistors M50a and M50b to control the connection of SL11 to SL1 To achieve multiple and flexible segment erasing, a method of using an SLCN latch for each SLCN signal can be applied The detail of this method of operation has been disclosed in U S patent No 5,646,890 assigned to the same assignee of this invention

A prior art U S patent No 4,949,309 discloses a similar but different source line circuit that also has two transistors controlling the circuit In the layout shown in U S patent No 4,949,309, a first metal layer is used for both bit lines and source lines that run vertically, and the controlling transistors are constructed with a second polysilicon (Poly2) layer An exemplary layout of the circuit structure of FIG 10a is shown in FIG 1 The layout shows two segments of four WLs. SLC1 and SLC2 are the source segment control lines of the first and second segments respectively. In the layout of a flash memory circuit, a first polysilicon (Polyl) layer is used to form the floating gates of the memory cells and the second polysilicon (Poly2) layer is used for the word lines. Due to the high density, there is no space available for building other transistors with the Poly2 layer. This invention presents the layout as shown in FIG. 11 in which the source segment control lines SLC1 and SLC2 as well as the transistors M50 and M60 are constructed with the Polyl layer. Because in the flash memory technology the Polyl layer is used to form the isolated floating gate of all memory cells, the Polyl layer without the mask of Poly2 layer is etched away. This is done by using a self-aligned etching (SAE) technique with a special SAE mask. In this invention, however, the transistors M50 and M60 as well as control lines SLC1 and SLC2 have to be protected from being etched away. Therefore, the traditional SAE layer can be modified to exclude these Polyl devices and its Polyl gate lines from the regular Polyl lines which are overlapping with the first metal lines of bit lines. No extra mask is required.

In the above description, two types of gating devices for controlling the connection of word lines to word line latches, XS latches or XT address lines in a word line decoder have been shown. Transistors Mia, Mlb and Mlc of FIG. 2 form a gating device that is used for the first embodiment and transistors Mia, Mlb and Mlc of FIG. 5 form another gating device that can be used for the second embodiment. It should be noted the gating device can be modified in many ways by designing the circuit properly. For example, the circuit of FIG. 12a can be used to replace Mia, Mlb and Mlc of FIG. 2. Similarly, the circuit of FIG. 12b or FIGJ2c has identical function as the circuit formed by Mia, Mlb and Mlc of FIG. 5. The exemplary circuits shown and illustrated above are presented only for the convenience of explaining the principle of this invention. A person skilled in the field should be able to make modification that comes within the spirit of this invention based on the above described principle.

Although in the above disclosure fixed voltages such as XD = -8V, SLX = +5V for erasing selected word lines and other bias conditions have been described to illustrate and explain the operations of different embodiments, these bias conditions should not be deemed to limit the scope of the invention. As an example, it may be preferred to have XD

= ON SLX = +12V and ST1-ST4 = 13V for the embodiment of FIG. 1 in some circuit systems for erasing memory cells In addition, the negative cut-off voltage mentioned many times above is a variable voltage determined while the verify operation is performed This voltage is then used to determine the optimal programming and erasing voltages With the disclosed embodiments, a person skilled in the field should be able to choose vanous bias conditions to achieve optimal memory operations based on the teaching of this invention and the different system requirements for a practical application

As described above, it can be seen that a decoder circuit of a flash memory provides appropriate bias conditions for different memory operations to ensure that the flash memory functions properly In the flash memory industry, there are two types of conventional bias conditions widely used for an erase operation They can generally be categoπzed into a source erasing method and a negative-gate erasing method Both methods rely on the Fowler-Nordheim tunneling mechanism to extract electrons from a floating gate to a source through a very thin oxide between the overlap region of the floating gate and the source To trigger the tunneling current, a sufficient electncal field has to be applied between the source and the gate

The source erasing method applies a +12V to the source line and a OV to the word line with the bit line being left floating It is the very high source voltage that provides a sufficient electric field to accomplish the erase operation The negative-gate erasing method applies a -8V to the word line and a +5V to the source line with the bit line floating Because the gate has a negative voltage, the method requires a lower source voltage to provide enough electric field for the erase operation

The drawback of the source erasing method is that the high source voltage increases the requirement of a higher breakdown voltage for the memory cell as well as its peripheral circuit devices Therefore, a deeper junction as well as a thicker gate oxide of a peripheral transistor are needed These requirements make the memory device less shrinkable In addition, a higher source voltage also increases the difficulty of current supply which becomes a serious problem if the voltage is generated from an on-chip circuitry Typically, a voltage generator has to provide approximately 5mA to activate 64KB memory cells erasure (lOnA / cell) However, the supplying current of a high voltage generator decreases drastically if the output voltage increases Therefore, the source erasing method is less suitable for portable applications, which generally has only a single power supply Vcc and requires on-chip high voltage generation As a result, the negative-gate erasing method is more favorable due to its lower source voltage The lower source voltage can be easily generated on-chip, or even directly supplied by the power supply Vcc, if 5V Vcc is used It should be noted that there is no supplying current concern for a negative gate voltage because there is no DC current flowing on the gate The negative-gate erasing method can be very well used in the flash memory circuits of this invention disclosed above for erasing one WL, one WL pair, multiple WLs or multiple WL pairs However, the conventional negative-gate erasing method is not suitable for taking advantage of the very flexible size of an erase operation, which may erase only a portion of a WL pairs, provided by the circuit of this invention As discussed earlier, a WL or WL pair in the memory array of this invention may be divided into a plurality of segments as shown in FIGs 10a and 10b so that the memory cells in each segment of the WL or WL pair can be selectively erased Each segment can be as small as a single byte When the bias condition of negative-gate erasing method is applied for erasing one or multiple segments of a WL pair, the segments that are not selected for erasing suffer from gate disturbance because a same negative gate voltage is applied to both selected segments and non-selected segments The high negative gate voltage will remove electrons of the floating gate during a long erasing time

To minimize the gate disturbance, the conventional source erasing method can be used for erasing one or more segments of a WL or WL pairs of this invention In the conventional source erasing method, the source of the selected segment is applied a positive voltage such as + 12V and the gate of the selected segment is grounded According to the circuit of this invention as shown in FIGs 10a and 10b, only the segmented source lines of the selected segments are applied the high voltage The segmented source lines of the non-selected segments are floating Thus, both source disturbance and gate disturbance are eliminated Because only a few memory cells are erased in this case, the required source current is much less than the high supplying current required for erasing 64k Bytes of memory cells as pointed out earlier However, this bias condition still has the drawbacks of requiring thicker oxides and deeper junctions that have been discussed

To overcome the problem, a moderate method having a preferred moderate bias condition for the erase operation has been developed to fully benefit the very flexible erasing size of the decoder circuits disclosed above The preferred bias condition for erasing one or multiple segments of a selected WL pair is applying a moderately negative voltage such as -4V to the gate line and a moderately positive voltage such as +7V to the source line with the bit line floating. Because the coupling ratio of a control gate (a word line) to a floating gate is approximately 50%, by adding 2V to the source voltage of a conventional negative-gate erasing method, the gate voltage can be reduced by approximately 4V, which significantly reduces the gate disturbance but still maintains the same electrical field for erasing memory_cell's data. Considering a memory read operation, a WL is usually applied 5V. Therefore, the gate disturbance caused by a moderately negative voltage -4V on the non-selected segments in an erase operation is no more than the gate disturbance caused by a read operation. It is definitely negligible. Although the source voltage is increased, the source disturbance of non-selected segments is not increased. Because each segment has its own decoded segmented source line such as SL1 1 or SL12 as shown in FIG. 10a, the segmented source lines of non- selected segments in the same WL pair are left floating. In addition, the moderately positive source voltage frees the requirement of a thicker oxide and a large supply current of conventional source erasing method. The breakdown voltage (BVDSS) of the current device technology widely used is approximately higher than 8V. According to the preferred bias condition of this invention, the moderately positive source line voltage is still lower than the breakdown voltage. Therefore, it is not necessary to increase the oxide thickness or the junction depth for the peripheral devices. Furthermore, the +7V source line voltage can be easily achieved by an on-chip pump circuit which requires only one stage if 5V Vcc is used or two stages if 3V Vcc is used. Consequently, the new bias condition offers the advantages of negligible gate disturbance and easily pumped source voltage over the conventional bias conditions. It is also compatible with current device manufacturing technology. It is also worth mentioning that the source line voltage and the gate line voltage just described are only an example. Other moderate values can also be used.

In connection with the forgoing discussion, the bias conditions used for the flash memory of this invention are as follows. The bias condition of the conventional negative- gate erasing method is appropriate and favored for erasing the memory cells of one or multiple WL pairs because it has the advantage of a lower source voltage. The bias condition for the conventional source erasing method or the moderate method can be used for erasing the memory cells of one or more segments of a WL or WL pair. In other words, in this invention, the most appropriate bias condition is adaptively used according to the size of the erase operation to be executed

As pointed out in this disclosure, although the preferred mode of operation of the flash memory circuits of this invention is to erase a word line pair or word line segment pair that share a same source line at the same time, the circuits also allow the erasure of the memory cells on a single word line It is even possible to erase the memory cells of a single bytes or a small segment of a single word line Nevertheless, the memory cells of adjacent non-selected word lines or word line segments may be stressed and disturbed A method of overcoming the drawback of erasing a single selected word line is to remember and store the programmed data of the stressed memory cells on the non-selected adjacent WL before the erase operation After the selected WL has been successfully erased and verified, the stored data of its adjacent WL before erasing are retrieved and compared with the read data of the memory cells on the disturbed WL after erasing A post-programming operation is performed to restore the data if these data do not match within a safe read margin Although this approach can also be applied to a conventional flash memory circuit, the present invention provides the advantage that only memory cells on a disturbed word line has to restored This is because in this invention the memory cells on the adjacent word line can be turned off to minimize data disturbance when a single word line is erased Therefore, only disturbed memory cells have to be reprogrammed Conventional flash memory circuits, however, a whole block of memory cells have to be erased and reprogrammed

FIG 13 shows a flow chart of the procedure for post-programming the stressed memory cells after an erase operation assuming that these memory cells are not selected for erasing and their data have been stored for retrieval It can be summarized as follows l The memory data of the stressed memory cells are read and compared with the stored memory data li Venfy data "0" which has a threshold voltage around 4V in a 3V operation If it fails, the memory cell is post-programmed to restore its threshold voltage back to more than 4V If the allowable erase time is exceeded before being successfully re-programmed, the flash memory device is considered defective in Veπfy data "1" which has a threshold voltage around IV in a 3V operation If it fails, the memory cell is post-programmed to restore its threshold voltage back to IV If the allowable erase time is exceeded before being successfully programmed, the flash memory device is considered defective. iv If both data "0" and "1" are successfully restored to the memory cells, the post- programming is completed The above post-programming procedure can be used to overcome the data disturbance when the flash memory circuits of this invention are used to erase a multiple of word lines that may not be fully paired with each pair sharing a same source line FIG. 14 shows a flow chart of the method of erasing a multiple of word lines in this invention This mode of the erase operation is called multiple word line mode It can be summarized as follows a Select the word lines that are to be erased b Read the memory data from the memory cells of the adjacent non-selected word lines that will suffer from data disturbance during the erase operation, i e , each word line that shares a same source line with a word line which has been selected for erasing, and store the data in either on-chip or off-chip temporary storage devices such as static random access memories (SRAM) c Apply an appropriate bias condition to the selected word lines for erasing one or more word lines and shut off the other non-selected word lines d Apply an erase pulse to the selected word lines e Verify the memory cells on the selected word lines If all the selected word lines have successfully passed the verification, go to step g f. Re-select the word lines that fail the verification in step e for the next cycle of the erase operation and go to step c if the allowable erase time limit has not been reached If the allowable erase time limit has been exceeded, the erase operation is terminated and flash memory device is considered defective g Execute a post-programming procedure as shown in FIG. 13.

Note that there are three novel points in the erase operation of this invention over the prior art Firstly, in step f, the selected word lines that have passed the verification will be reset as non-selected and the erase pulse will not be applied to these word lines in the next cycle of the erase operation This significantly reduces the number of over-erased cells In contrast, the conventional flash memory keeps on erasing these word lines until all the selected word lines are successfully erased and verified Secondly, if the memory cells have to be continuously erased in step f , the operation goes back to step c and the bias condition is updated according to the memory cells' threshold voltage which is detected in the verification step as discussed earlier. In contrast, the conventional flash memory goes back to step d and the bias condition is never updated Thirdly, step b and step g are taken to post-program the data of the memory cells which suffer from erase disturbance In contrast, none of the prior art introduces this operation As discussed before, the flash memory circuit of this invention may also divide the memory cells on word lines into a number of segments For erasing memory cells of one or multiple segments of a single word line, the operation is similar except that the non-selected memory cells that suffer from the word line disturbance on the selected word line also have to be read and stored in a temporary storage device such as a SRAM in addition to the memory cells of the adjacent non-selected word line that suffer from the source disturbance Those memory cells have to be verified and restored if they have been disturbed during the erase operation FIG 15 shows a flow chart of the method of erasing one or multiple segments of a single word line or a word line pair in this invention This mode of the erase operation is named as a multiple segment mode It can be summarized as follows

A Select the word line segments that are to be erased

B Read the memory data from the memory cells that will suffer from data disturbance during the erase operation including the memory cells of the non-selected word line segments on the same word line and the memory cells of the adjacent non-selected word lines, and store the data in either on-chip or off-chip temporary storage devices such as static random access memories (SRAM)

C Apply an appropriate bias condition to the selected word line segments for erasing one or more word line segments and shut off non-selected word line segments as well as other non-selected word lines D Apply an erase pulse to the selected word line segments E Veπfy the memory cells on the selected word line segments If all the selected word line segments have successfully passed the veπfication, go to step G

F Re-select the word line segments that fail the verification in step E for the next cycle of the erase operation and go to step C if the allowable erase time limit has not been reached If the allowable erase time limit has been exceeded, the erase operation is terminated and flash memory device is considered defective

G Execute a post-programming procedure as shown in FIG 13

Similar to FIG 14, each selected segment can be stopped from being erased after it has passed the verification in step F It should be noted that the bias condition presented earlier by providing a moderately positive voltage to the segmented source lines and a moderately negative voltage to the gate should be used for the selected word line segments in step C of the erase operation The segmented source lines of non-selected word line segments should be left floating As discussed before, the bias condition reduces gate disturbance to the non-selected word line segments The methods as shown in the flow charts of FIGs 14 and 15 have been designed for erasing the memory cells of a multiple of word lines and word line segments respectively This invention further provides a two-step operation for further enhancing the erase operation of the disclosed flash memory circuits by combining the benefits of both methods of FIGs 14 and 15 In a conventional flash memory circuit, if there are some memory cells that take significantly long time to erase when the memory cells of a multiple of word lines are selected for erasing, all the other selected cells have to be continuously erased until these slow cells are successfully erased This not only increases the number of over-erased cells but also wastes time and power The drawback and problems of over-erasure have been described earlier in this application Alternatively, the method according to this invention illustrated in FIG 14 can independently stop the erase operation on a word line basis to avoid the problems However, if the slow cells happen to distribute among many different word lines, the drawbacks can not be overcome by the method of stop erasing an individual word line

To overcome the problem, the flow chart of FIG 16 shows a new method of erasing multiple word lines The erase operation as shown in FIG 16 compπses both multiple word line and multiple segment modes At the beginning, the selected word lines are erased by the multiple word line mode of operation, in which all the selected multiple word lines are erased together and each word line that passes verification is independently stopped from being erased After most of the selected word lines are successfully erased and veπfied, the erase operation is switched to the multiple segment mode In the multiple segment mode, the word lines which still have memory cells not successfully erased are detected and erased WL by WL

For each word line that requires further erasing, the erase pulse is applied to the multiple segments which contain the memory cells not successfully erased Each segment can be independently stopped from being erased when it passes the veπfication After all the segments of a word line are successfully erased and verified, the next word line which contains memory cells not successfully erased is detected and the multiple segment mode erasing proceeds The multiple segment mode of the erase operation will be repeated until all the memory cells on the selected word lines are successfully erased and verified Nearly all the steps executed in the method of FIG 14 are repeated in FIG 16 except step f In step f , the method of FIG 16 determines whether the erase operation should be switched to the multiple segment mode if the allowable erase time limit has not been reached The decision can be made based on a number of factors such as the number of erase pulses applied, the number of memory cells fail the verification, or the minimum threshold voltage of erased memory cells

A few examples of deciding if a multiple word line mode of erasing should be switched to a multiple segment mode are given as follows Assumes that the memory cells of multiple word lines are selected for erasing Five word lines represent a portion of the total selected word lines A pre-determined condition for changing the mode can be set as when the total number of word lines that fail the erase-verification becomes less than 5 The total number of erase pulses that have been applied to the selected word lines may also be used as an additional constraint As an example, if the number of erase pulses has exceeded a pre-determined number such as 100 and the total number of word lines that fail the erase- veπfication is less than 5, the multiple segment mode of erasing can be triggered It is also reasonable to use the maximum threshold voltage of the memory cells as an additional cπteπon The point of switching from a multiple word line mode to a multiple segment mode can be when the maximum threshold voltage of the memory cells that fail the erase- veπfication is higher than a pre-determined value such as 3 V and the total number of word lines that fail the erase-verification is less than 5 It should be noted that the above word line number and voltage values are just examples and should not deem to limit the scope of the invention.

If it is determined that the multiple word line mode should continue, the erase operation goes back to the method of FIG. 14. If the erase operation is switched to the multiple segment mode, the word line segments of each word line are identified based on the verification result. The identified word line segments of each word line are then selected for erasing by means of the method as shown in FIG. 15. By being able to switch to the multiple segment mode, the word line segments that do not contain the slow memory cells will be less disturbed by the long erasing time. Therefore, the over-erasure problem is eliminated and the power consumption is significantly reduced.

Claims

What is claimed is 1 A flash memory array comprising a plurality of flash memory cells being arranged in a plurality of rows and a plurality of columns, each of said flash memory cells having a control gate, a drain and a source, a plurality of odd word lines each connecting the control gates of all the flash memory cells in a same odd row, a plurality of even word lines each connecting the control gates of all the flash memory cells in a same even row, a plurality of bit lines each connecting the drains of all the flash memory cells in a same column, and a plurality of source lines each connecting the sources of all the flash memory cells in an odd row and an associated even row next to the odd row 2 The flash memory array according to claim 1, further comprising at least a column of transistors each having a gate coupled to a word line of a row of memory cells for connecting the source line associated with the row to a source current draining line for shunting high cell current in a program operation, said associated source line being connected to a first ground and said source current draining line being connected to a second ground in a program operation 3 The flash memory array according to claim 1 , wherein each of said plurality of source lines is disconnected from the sources of the memory cells of an odd row and an associated even rows, said memory array is divided into a plurality of segments each compπsing a number of columns, and each segment has a plurality of segmented source lines each being formed by wiring the sources of all the memory cells in an odd row and an associated even row next to the odd row within the segment together and then connected to the source line associated with the odd and even rows through at least one source segment control transistor having a gate coupled to a source segment control line of the segment 4 The flash memory array according to claim 3, wherein said source segment control line and said source segment control transistor are constructed with a first polysilicon layer, and said plurality of odd and even word lines and the control gates of said plurality of flash memory cells are formed by a second polysilicon layer A flash memory circuit having a plurality of flash memory banks each comprising a flash memory array including a plurality of flash memory cells being arranged in a plurality of rows and a plurality of columns, each of said flash memory cells having a control gate, a drain and a source, a plurality of odd word lines each connecting the control gates of all the flash memory cells in a same odd row, a plurality of even word lines each connecting the control gates of all the flash memory cells in a same even row, a plurality of bit lines each connecting the drains of all the flash memory cells in a same column, and a plurality of source lines each connecting the sources of all the flash memory cells in an odd row and an associated even row next to the odd row, a bank decoder, a source line voltage controlled by said bank decoder, a source line decoder having a source control line, a plurality of source primary address lines and source secondary address lines, each source primary address line having a corresponding source secondary address line, and a plurality of source gating devices each being coupled to a source primary address line and a corresponding source secondary address line for connecting a source line to either said source line voltage or said source control line, an odd word line voltage controlled by said bank decoder, an even word line voltage controlled by said bank decoder, and a word line decoder having a word control line, a plurality of word pπmary address lines and word secondary address lines, each word primary address line having a corresponding word secondary address line, and a plurality of word gating devices each being coupled to a word primary address line and a corresponding word secondary address line for connecting an odd word line to either said odd word line voltage or said word control line, or for connecting an even word line to either said even word line voltage or said word control line, wherein an odd word gating device and an adjacent even word gating device being coupled to a same word primary address line and a same secondary address line for connecting an odd word line and an even word line respectively at the same time The flash memory circuit according to claim 5, further comprising a source line latch controlled by said bank decoder for providing said source line voltage, an odd word line latch controlled by said bank decoder for providing said odd word line voltage, and an even word line latch controlled by said bank decoder for providing said even word line voltage The flash memory circuit according to claim 6, each of said source gating devices further comprising first and second transistors having gates coupled to a source primary address line and a corresponding source secondary address line respectively for connecting a source line to either said source line latch or said source control line The flash memory circuit according to claim 6, each of said word gating devices further comprising a pair of n-channel and p-channel transistors having gates coupled to a word primary address line and a corresponding word secondary address line respectively for connecting an odd word line to said odd word line latch, or for connecting an even word line to said even word line latch, and an n-channel transistor having a gate coupled to a word secondary address line for connecting an odd or even word line to said word control line; wherein the word secondary address line coupled to said n-channel transistor is the same word secondary address line coupled to said pair of transistors and the word line connected by said n-channel transistor is the same word line connected by said pair of transistors. 9. The flash memory circuit according to claim 6, further comprising at least a column of transistors each having a gate coupled to a word line of a row of memory cells for connecting the source line associated with the row to a source current draining line for shunting high cell current in a program operation, said associated source line being connected to a first ground and said source current draining line being connected to a second ground in a program operation. 10. The flash memory circuit according to claim 6, each of said source gating devices further comprising: first and second transistors having gates coupled to a source primary address line and a corresponding source secondary address line respectively for connecting a source line to either said source line latch or said source control line; each of said word gating devices further comprising: a pair of n-channel and p-channel transistors having gates coupled to a word primary address line and a corresponding word secondary address line respectively for connecting an odd word line to said odd word line latch, or for connecting an even word line to said even word line latch; and an n-channel transistor having a gate coupled to a word secondary address line for connecting an odd or even word line to said word control line; wherein the word secondary address line coupled to said n-channel transistor is the same word secondary address line coupled to said pair of transistors and the word line connected by said n-channel transistor is the same word line connected by said pair of transistors; and said memory array further comprising: at least a column of transistors each having a gate coupled to a word line of a row of memory cells for connecting the source line associated with the row to a source current draining line for shunting high cell current in a program operation, said associated source line being connected to a first ground and said source current draining line being connected to a second ground in a program operation. 1 1. The flash memory circuit according to claim 6, wherein each of said plurality of source lines is disconnected from the sources of the memory cells of an odd row and an associated even rows, said memory array is divided into a plurality of segments each comprising a number of columns, and each segment has a plurality of segmented source lines each being formed by wiring the sources of all the memory cells in an odd row and an associated even row next to the odd row within the segment together and then connected to the source line associated with the odd and even rows through at least one source segment control transistor having a gate coupled to a source segment control line of the segment. 12. The flash memory circuit according to claim 1 1, wherein said source segment control line and said source segment control transistor are constructed with a first polysilicon layer, and said plurality of odd and even word lines and the control gates of said plurality of flash memory cells are formed by a second polysilicon layer. 13. A flash memory circuit having a plurality of flash memory banks each comprising: a flash memory array including: a plurality of flash memory cells being arranged in a plurality of rows and a plurality of columns, each of said flash memory cells having a control gate, a drain and a source; a plurality of word lines each connecting the control gates of all the flash memory cells in a same row; a plurality of bit lines each connecting the drains of all the flash memory cells in a same column; and a plurality of source lines each connecting the sources of all the flash memory cells in an odd row and an associated even row next to the odd row; a bank decoder; a source line voltage controlled by said bank decoder, a source line decoder having a source control line, a plurality of source primary address lines and source secondary address lines, each source primary address line having a corresponding source secondary address line, and a plurality of source gating devices each being coupled to a source primary address line and a corresponding source secondary address line for connecting a source line to either said source line voltage or said source control line, a word control line controlled by said bank decoder, a word line voltage controlled by said bank decoder, and a word line decoder having a plurality of word primary address lines and word secondary address lines, each word primary address line having a corresponding word secondary address line, and a plurality of word gating devices each being coupled to a word secondary address line and controlled by said word line voltage for connecting a word line to either a corresponding word primary address line or said word control line The flash memory circuit according to claim 13 further comprising a source line latch controlled by said bank decoder for providing said source line voltage, a word control latch controlled by said bank decoder for providing said word control line; and a word line latch controlled by said bank decoder for providing said word line voltage The flash memory circuit according to claim 14, each of said source gating devices further comprising first and second transistors having gates coupled to a source primary address line and a corresponding source secondary address line respectively for connecting a source line to either said source line latch or said source control line The flash memory circuit according to claim 14, each of said word gating devices further compπsing a pair of p-channel and n-channel transistors having gates connected together and coupled to said word line latch for connecting a word line to a word pπmary address line or said word control latch, and an n-channel transistor having a gate coupled to a word secondary address line for connecting the word line being connected to said pair of transistors to said word control latch, wherein the word secondary address line coupled to said n-channel transistor is the corresponding word secondary address line of the word pπmary address line coupled to said pair of transistors The flash memory circuit according to claim 14, said memory array further comprising at least a column of transistors each having a gate coupled to a word line of a row of memory cells for connecting the source line associated with the row to a source current draining line for shunting high cell current in a program operation, said associated source line being connected to a first ground and said source current draining line being connected to a second ground in a program operation The flash memory circuit according to claim 14, each of said source gating devices further comprising first and second transistors having gates coupled to a source primary address line and a corresponding source secondary address line respectively for connecting a source line to either said source line latch or said source control line, each of said word gating devices further comprising a pair of p-channel and n-channel transistors having gates connected together and coupled to said word line latch for connecting a word line to a word primary address line or said word control latch, and an n-channel transistor having a gate coupled to a word secondary address line for connecting the word line being connected to said pair of transistors to said word control latch, wherein the word secondary address line coupled to said n-channel transistor is the same word secondary address line coupled to said pair of transistors; and said memory array further comprising: at least a column of transistors each having a gate coupled to a word line of a row of memory cells for connecting the source line associated with the row to a source current draining line for shunting high cell current in a program operation, said associated source line being connected to a first ground and said source current draining line being connected to a second ground in a program operation. 19. The flash memory circuit according to claim 14, wherein each of said plurality of source lines is disconnected from the sources of the memory cells of an odd row and an associated even rows, said memory array is divided into a plurality of segments each comprising a number of columns, and each segment has a plurality of segmented source lines each being formed by wiring the sources of all the memory cells in an odd row and an associated even row next to the odd row within the segment together and then connected to the source line associated with the odd and even rows through at least one source segment control transistor having a gate coupled to a source segment control line of the segment. 20. The flash memory circuit according to claim 19, wherein said source segment control line and said source segment control transistor are constructed with a first polysilicon layer, and said plurality of word lines and the control gates of said plurality of flash memory cells are formed by a second polysilicon layer. 21. A flash memory circuit having a plurality of flash memory banks each comprising: a flash memory array including: a plurality of flash memory cells being arranged in a plurality of rows and a plurality of columns, each of said flash memory cells having a control gate, a drain and a source; a plurality of word lines each connecting the control gates of all the flash memory cells in a same row; a plurality of bit lines each connecting the drains of all the flash memory cells in a same column; and a plurality of source lines each connecting the sources of all the flash memory cells in an odd row and an associated even row next to the odd row, a bank decoder, a source line voltage controlled by said bank decoder, a source line decoder having a source control line, a plurality of source primary address lines and source secondary address lines, each source primary address line having a corresponding source secondary address line, and a plurality of source gating devices each being coupled to a source primary address line and a corresponding source secondary address line for connecting a source line to either said source line voltage or said source control line, a word control line controlled by said bank decoder, a first word line voltage controlled by said bank decoder, a second word line voltage controlled by said bank decoder, and a word line decoder having a plurality of word primary address lines and word secondary address lines, each word primary address line having a corresponding word secondary address line, and a plurality of word gating devices each being coupled to a word secondary address line and controlled by said first and second word line voltages for connecting a word line to either a corresponding word primary address line or said word control line The flash memory circuit according to claim 21 further comprising a source line latch controlled by said bank decoder for providing said source line voltage, a word control latch controlled by said bank decoder for providing said word control line, a first word line latch controlled by said bank decoder for providing said first word line voltage; and a second word line latch controlled by said bank decoder for providing said second word line voltage. 23. The flash memory circuit according to claim 22, each of said source gating devices further comprising first and second transistors having gates coupled to a source primary address line and a corresponding source secondary address line respectively for connecting a source line to either said source line latch or said source control line. 24. The flash memory circuit according to claim 22, each of said word gating devices further comprising: a pair of p-channel and n-channel transistors having gates coupled to said first and second word line latches respectively for connecting a word line to a word primary address line or to said word control latch; and an n-channel transistor having a gate coupled to a word secondary address line for connecting the word line being connected to said pair of transistors to said word control latch; wherein the word secondary address line coupled to said n-channel transistor is the corresponding word secondary address line of the word primary address line coupled to said pair of transistors. 25. The flash memory circuit according to claim 22, said memory array further comprising at least a column of transistors each having a gate coupled to a word line of a row of memory cells for connecting the source line associated with the row to a source current draining line for shunting high cell current in a program operation, said associated source line being connected to a first ground and said source current draining line being connected to a second ground in a program operation. 26. The flash memory circuit according to claim 22, each of said source gating devices further comprising: first and second transistors having gates coupled to a source primary address line and a corresponding source secondary address line respectively for connecting a source line to either said source line latch or said source control line; each of said word gating devices further comprising a plurality of word pπmary address lines and word secondary address lines, each word pπmary address line having a corresponding word secondary address line, and a plurality of word gating devices each being coupled to a word secondary address line and controlled by said first and second word line voltages for connecting a word line to either a corresponding word pπmary address line or said word control line, and said memory array further compπsing at least a column of transistors each having a gate coupled to a word line of a row of memory cells for connecting the source line associated with the row to a source current draining line for shunting high cell current in a program operation, said associated source line being connected to a first ground and said source current draining line being connected to a second ground in a program operation The flash memory circuit according to claim 22, wherein each of said plurality of source lines is disconnected from the sources of the memory cells of an odd row and an associated even rows, said memory array is divided into a plurality of segments each comprising a number of columns, and each segment has a plurality of segmented source lines each being formed by wiring the sources of all the memory cells in an odd row and an associated even row next to the odd row within the segment together and then connected to the source line associated with the odd and even rows through at least one source segment control transistor having a gate coupled to a source segment control line of the segment The flash memory circuit according to claim 27, wherein said source segment control line and said source segment control transistor are constructed with a first polysilicon layer, and said plurality of word lines and the control gates of said plurality of flash memory cells are formed by a second polysilicon layer A flash memory circuit having a plurality of flash memory banks each comprising a flash memory array including a plurality of flash memory cells being arranged in a plurality of rows and a plurality of columns, each of said flash memory cells having a control gate, a drain and a source; a plurality of odd word lines each connecting the control gates of all the flash memory cells in a same odd row; a plurality of even word lines each connecting the control gates of all the flash memory cells in a same even row; a plurality of bit lines each connecting the drains of all the flash memory cells in a same column; and a plurality of source lines each connecting the sources of all the flash memory cells in an odd row and an associated even row next to the odd row; a bank decoder; a source line voltage controlled by said bank decoder; a source line decoder having: a source control line; a plurality of source primary address lines and source secondary address lines, each source primary address line having a corresponding source secondary address line; and a plurality of source gating devices each being coupled to a source primary address line and a corresponding source secondary address line for connecting a source line to either said source line voltage or said source control line; a word control line controlled by said bank decoder; an odd word line voltage controlled by said bank decoder; an even word line voltage controlled by said bank decoder; and a word line decoder having: a plurality of word primary address lines and word secondary address lines, each word primary address line having a corresponding word secondary address line; and a plurality of word gating devices each being coupled to a word secondary address line and controlled by said odd word line voltage for connecting an odd word line to either a corresponding word primary address line or said word control line, or being coupled to a word secondary address line and controlled by said even word line voltage for connecting an even word line to either a corresponding word primary address line or said word control line; wherein an odd word gating device and an adjacent even word gating device being coupled to a same word primary address line and a same secondary address line for connecting an odd word line and an even word line respectively at the same time The flash memory circuit according to claim 29, further comprising a source line latch controlled by said bank decoder for providing said source line voltage, a word control latch controlled by said bank decoder for providing said word control line, an odd word line latch controlled by said bank decoder for providing said odd word line voltage, and an even word line latch controlled by said bank decoder for providing said even word line voltage The flash memory circuit according to claim 30, each of said source gating devices further compπsing first and second transistors having gates coupled to a source primary address line and a corresponding source secondary address line respectively for connecting a source line to either said source line latch or said source control line The flash memory circuit according to claim 30, each of said word gating devices further comprising a pair of p-channel and n-channel transistors having gates connected together and coupled to said odd word line latch for connecting an odd word line to a word primary address line or to said word control latch, or having gates connected together and coupled to said even word line latch for connecting an even word line to a word primary address line or to said word control latch, and an n-channel transistor having a gate coupled to a word secondary address line for connecting the word line being connected to said pair of transistors to said word control latch, wherein the word secondary address line coupled to said n-channel transistor is the corresponding word secondary address line of the word primary address line coupled to said pair of transistors The flash memory circuit according to claim 30, said memory array further comprising at least a column of transistors each having a gate coupled to a word line of a row of memory cells for connecting the source line associated with the row to a source current draining line for shunting high cell current in a program operation, said associated source line being connected to a first ground and said source current draining line being connected to a second ground in a program operation The flash memory circuit according to claim 30, each of said source gating devices further comprising first and second transistors having gates coupled to a source primary address line and a corresponding source secondary address line respectively for connecting a source line to either said source line latch or said source control line, each of said word gating devices further compπsing a pair of p-channel and n-channel transistors having gates connected together and coupled to said odd word line latch for connecting an odd word line to a word primary address line or to said word control latch, or having gates connected together and coupled to said even word line latch for connecting an even word line to a word primary address line or to said word control latch, and an n-channel transistor having a gate coupled to a word secondary address line for connecting the word line being connected to said pair of transistors to said word control latch, wherein the word secondary address line coupled to said n-channel transistor is the corresponding word secondary address line of the word primary address line coupled to said pair of transistors, and said memory array further comprising at least a column of transistors each having a gate coupled to a word line of a row of memory cells for connecting the source line associated with the row to a source current draining line for shunting high cell current in a program operation, said associated source line being connected to a first ground and said source current draining line being connected to a second ground in a program operation 35. The flash memory circuit according to claim 30, wherein each of said plurality of source lines is disconnected from the sources of the memory cells of an odd row and an associated even rows, said memory array is divided into a plurality of segments each comprising a number of columns, and each segment has a plurality of segmented source lines each being formed by wiring the sources of all the memory cells in an odd row and an associated even row next to the odd row within the segment together and then connected to the source line associated with the odd and even rows through at least one source segment control transistor having a gate coupled to a source segment control line of the segment 36 The flash memory circuit according to claim 35, wherein said source segment control line and said source segment control transistor are constructed with a first polysilicon layer, and said plurality of odd and even word lines and the control gates of said plurality of flash memory cells are formed by a second polysilicon layer 37 A method of simultaneously erasing the memory cells of two adjacent rows each having a word line and both sharing a source line in a selected memory bank of a flash memory circuit having a plurality of memory banks each including a bank decoder, a word line decoder and a source line decoder, comprising the steps of sending appropriate address signals to the word line decoder of the selected memory bank for selecting two adjacent word lines, sending appropriate address signals to the source line decoder of the selected memory bank for selecting the source line shared by the selected adjacent word lines, applying a first voltage to the selected adjacent word lines from said bank decoder of the selected memory bank, applying a second voltage to the selected source line from said bank decoder of the selected memory bank, and applying a third voltage to the word lines of other non-selected memory banks; wherein said first and second voltages providing sufficient voltage difference for erasing the memory cells connected to the selected word lines. 38. The method of simultaneously erasing the memory cells of two adjacent rows according to claim 37, further including a method of erase-verifying the memory cells of the two erased rows one row at a time, said erase-verifying method comprising the steps of: sending appropriate address signals to the word line decoder of the selected memory bank for selecting two erased adjacent word lines; sending appropriate address signals to the source line decoder of the selected memory bank for selecting the source line shared by the selected adjacent word lines; applying a third voltage to one of the selected adjacent word lines under verification from said bank decoder; and applying a fourth voltage to the other word line of the selected adjacent word lines while a fifth voltage is applied to the word lines of other non-selected memory banks; wherein said third voltage verifies if the memory cells connected to the word line under verification are erased properly, said fourth voltage provides a sufficiently low voltage for shutting off all the memory cells connected to the other word line of the selected adjacent word lines; and said fifth voltage grounds all the word lines of other non- selected memory banks 39. The method of simultaneously erasing the memory cells of two adjacent rows according to claim 38, wherein said bank decoder includes odd and even word line latches for providing voltages to odd and even word lines respectively, and a source line latch for providing a voltage to a source line. 40. A method of erase-verifying the memory cells of two erased adjacent rows each having a word line and both sharing a source line one row at a time in a selected memory bank of a flash memory circuit having a plurality of memory banks each including a bank decoder, a word line decoder and a source line decoder, comprising the steps of: sending appropriate address signals to the word line decoder of the selected memory bank for selecting two erased adjacent word lines; sending appropriate address signals to the source line decoder of the selected memory bank for selecting the source line shared by the selected adjacent word lines, applying a first voltage to one of the selected adjacent word lines under verification from said bank decoder, and applying a second voltage to the other word line of the selected adjacent word lines while a third voltage is applied to the word lines of other non-selected memory banks, wherein said first voltage verifies if the memory cells connected to the word line under veπfication are erased properly, said second voltage provides a sufficiently low voltage for shutting off all the memory cells connected to the other word line of the selected adjacent word lines, and said third voltage grounds all the word lines of other non- selected memory banks A method of memory operation for erasing and verifying the memory cells of one or more word lines in a flash memory circuit, comprising the steps of A selecting the word lines that are to be erased, B identifying memory cells that will be disturbed if the word lines selected in step A are applied an appropriate erase bias condition, C reading the data of the memory cells identified in step B and storing the data in a temporary storage device, D setting up said appropriate erase bias condition for the memory cells of the word lines selected for erasing and non-erase bias conditions for the memory cells of other non-selected word lines, E applying an erase pulse to the word lines selected for erasing, F performing data verification for the memory cells of the word lines selected for erasing, G going to step I if the memory cells of all the word lines selected for erasing have passed the data verification of step F , H updating the selection of the word lines for erasing by excluding the word lines in which all memory cells have passed the data verification of step F and returning to step D if a pre-determined time limit is not exceeded, otherwise going to step P , I. reading new data of a first group of memory cells identified in step B. and executing data "1" verification for said first group of memory cells, said first group of memory cells having data value "1" stored in said temporary storage device; J. continuing step L. if said data "1" verification of step I. succeeds, otherwise executing step K.; K. post-programming data "1" to the memory cells of said first group and returning to step I. if said data "1" verification of step I. fails and a pre-determined time limit is not exceeded, otherwise going to step P.; L. reading new data of a second group of memory cells identified in step B. and executing data "0" verification for said second group of memory cells, said second group of memory cells having data value "0" stored in said temporary storage device; M. going to step O. if said data "0" verification of step L. succeeds, otherwise executing step N.; N. post-programming data "0" to the memory cells of said first group and returning to step L. if said data "0" verification of step L. fails and a pre-determined time limit is not exceeded, otherwise going to step P.; O. exiting said memory operation successfully; P. exiting said memory operation and declaring said flash memory circuit defective. 42. The method of memory operation for erasing and verifying the memory cells of one or word lines in a flash memory circuit according to claim 41, wherein step H. is replaced by a procedure comprising the steps of: HI . going to step P. if a pre-determined time limit is exceeded; H2. updating the selection of the word lines for erasing by excluding the word lines in which all memory cells have passed the data verification of step F. and returning to step D. if a pre-determined condition is not satisfied; H3. identifying the word lines that have memory cells failing the data verification of step F. and executing a memory segment erase operation for each identified word line, said memory segment erase operation comprising the steps of: a dividing the memory cells on the word line into a plurality of segments, b selecting the segments that are to be erased, c identifying the memory cells that will be disturbed if the segments selected in step a are applied an appropπate erase bias condition, d reading the data of the memory cells identified in step c and storing the data in a temporary storage device, e setting up said appropriate erase bias condition for the memory cells of the segments selected for erasing and non-erase bias conditions for the memory cells of other non-selected segments and non-selected word lines, f applying an erase pulse to the segments selected for erasing, g performing data verification for the memory cells of the segments selected for erasing, h going to step j if the memory cells of all the segments selected for erasing have passed the data verification of step g , l updating the selection of the segments for erasing by excluding the segments in which all memory cells have passed the data verification of step g and returning to step e if a pre-determined time limit is not exceeded, otherwise going to step q , j reading new data of a first group of memory cells identified in step c and executing data "1" verification for said first group of memory cells, said first group of memory cells having data value "1" stored in said temporary storage device, k continuing step m if said data "1" verification of step j succeeds, otherwise executing step 1 , 1 post-programming data "1" to the memory cells of said first group and returning to step j if said data "1" verification of step j fails and a pre-determined time limit is not exceeded, otherwise going to step q , m reading new data of a second group of memory cells identified in step c and executing data "0" verification for said second group of memory cells, said second group of memory cells having data value "0" stored in said temporary storage device, n going to step p if said data "0" verification of step m succeeds, otherwise executing step o , o post-programming data "0" to the memory cells of said first group and returning to step m if said data "0" veπfication of step m fails and a pre-determined time limit is not exceeded, otherwise going to step q , p exiting said memory operation successfully, q exiting said memory operation and declaπng said flash memory circuit defective The method of memory operation for erasing and verifying the memory cells of one or word lines in a flash memory circuit according to claim 42, wherein said appropriate erase bias condition for the memory cells of the segments selected for erasing in step e is the bias condition of a source erasing method and the sources of the memory cells of non-selected segments are floating The method of memory operation for erasing and verifying the memory cells of one or word lines in a flash memory circuit according to claim 42, wherein said appropπate erase bias condition for the memory cells of the segments selected for erasing in step e is the bias condition of a moderate method and the sources of the memory cells of non- selected segments are floating A method of memory operation for erasing and verifying the memory cells of a plurality of segments of a word line in a flash memory circuit, comprising the steps of a selecting the segments that are to be erased, b identifying the memory cells that will be disturbed if the segments selected in step a are applied an appropriate erase bias condition, c reading the data of the memory cells identified in step b and stoπng the data in a temporary storage device, d setting up said appropriate erase bias condition for the memory cells of the segments selected for erasing and non-erase bias conditions for the memory cells of other non-selected segments and non-selected word lines, e applying an erase pulse to the segments selected for erasing, f performing data verification for the memory cells of the segments selected for erasing, g going to step i if the memory cells of all the segments selected for erasing have passed verification, h updating the selection of the segments for erasing by excluding the segments in which all memory cells have passed verification and returning to step d if a pre- determined time limit is not exceeded, otherwise going to step p, i reading new data of a first group of memory cells identified in step b and executing data "1" verification for said first group of memory cells, said first group of memory cells having data value "1" stored in said temporary storage device, j continuing step 1 if said data "1" verification of step i succeeds, otherwise executing step k , k post-programming data "1" to the memory cells of said first group and returning to step i if said data "1" verification of step i fails and a pre-determined time limit is not exceeded, otherwise going to step p , 1 reading new data of a second group of memory cells identified in step b and executing data "0" verification for said second group of memory cells, said second group of memory cells having data value "0" stored in said temporary storage device, m going to step o if said data "0" verification of step 1 succeeds, otherwise executing step n., n post-programming data "0" to the memory cells of said first group and returning to step 1 if said data "0" verification of step 1 fails and a pre-determined time limit is not exceeded, otherwise going to step p , o exiting said memory operation successfully, p. exiting said memory operation and declaring said flash memory circuit defective The method of memory operation for erasing and verifying the memory cells of one or word lines in a flash memory circuit according to claim 45, wherein said appropriate erase bias condition for the memory cells of the segments selected for erasing in step d. is the bias condition of a source erasing method and the sources of the memory cells of non-selected segments are floating. 47. The method of memory operation for erasing and verifying the memory cells of one or word lines in a flash memory circuit according to claim 45, wherein said appropriate erase bias condition for the memory cells of the segments selected for erasing in step d. is the bias condition of a moderate method and the sources of the memory cells of non- selected segments are floating.