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WO1996013060A1 - Procede de liaison directe de corps plans et objets fabriques selon ledit procede a partir de ces corps plans - Google Patents

Procede de liaison directe de corps plans et objets fabriques selon ledit procede a partir de ces corps plans Download PDF

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Publication number
WO1996013060A1
WO1996013060A1 PCT/EP1995/004136 EP9504136W WO9613060A1 WO 1996013060 A1 WO1996013060 A1 WO 1996013060A1 EP 9504136 W EP9504136 W EP 9504136W WO 9613060 A1 WO9613060 A1 WO 9613060A1
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WO
WIPO (PCT)
Prior art keywords
bodies
components
disc
polishing
article
Prior art date
Application number
PCT/EP1995/004136
Other languages
German (de)
English (en)
Inventor
Herbert GÜTTLER
Dirk Walliser
Original Assignee
Daimler-Benz Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19944445348 external-priority patent/DE4445348A1/de
Application filed by Daimler-Benz Aktiengesellschaft filed Critical Daimler-Benz Aktiengesellschaft
Publication of WO1996013060A1 publication Critical patent/WO1996013060A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/24—Preliminary treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the invention relates to a method for the direct connection of planar surfaces of bodies according to the preamble of claim 1 and to objects produced by the method with planar bodies.
  • a standard method for permanently connecting surfaces is used, for example, in semiconductor technology for so-called wafer direct bonding of silicon wafers.
  • the silicon surfaces are subjected to a polishing and cleaning procedure, whereby typical maximum roughnesses of several, ten nm to a few ⁇ m are achieved.
  • the surfaces are then chemically prepared, e.g. a hydrophilization or a plasma etching process, followed by joining the two surfaces and baking the composite body at process temperatures from about 800 ° C to 1400 ° C.
  • a liquid medium is often placed between the two surfaces as a bonding agent.
  • an insulating layer of S1O2 is introduced between the surfaces to be connected by oxidizing one of the two panes.
  • an electrical voltage in the kV range between the two surfaces and heating to several hundred degrees By applying an electrical voltage in the kV range between the two surfaces and heating to several hundred degrees, a permanent shift of the ions is induced by the impressed electric field leads to a permanent connection without applied voltage.
  • conductive adhesives or in particular soldering agents are used.
  • the high-temperature step when baking the connection makes it difficult to use such a contacting method, since it cannot be used for any material combination.
  • This step is very problematic or prohibits, in particular, for completely structured and metallized semiconductor wafers, for example when attaching heat sinks or heat spreaders.
  • the effects of the high temperatures lead to undesired diffusion processes within the possible component up to the destruction of its electrical function.
  • soldering processes in particular are critical with regard to their environmental compatibility. Therefore, semiconductor technology is used for reasons of environmental compatibility as well as cleanliness due to increasingly solder-free processes.
  • processes are used there in which, for example, the second surface is melted directly onto the surface to be contacted.
  • semiconductor technology for example, the so-called.
  • Flip chip Technology in which a large number of individual contact areas in the form of contact balls are melted onto a large-area component at the same time. 25 process steps are necessary before the actual soldering process, which makes this process considerably more expensive.
  • the heat load of the connecting body is very high in such a melting process.
  • thermal expansion coefficients of any adhesive and / or solder and the surfaces to be connected generally. are different and thus lead to aging and fatigue of the contact.
  • solder and adhesive layers represent additional interfaces, e.g. in the case of a desired heat dissipation from the contact area, increase the thermal resistance drastically.
  • One way to improve this problem is to reduce the thickness of the layers and the number of interfaces in the contact area.
  • a method which uses moderate process temperatures ( ⁇ 500 ° C) and thin membranes.
  • Yablonovic (Appl. Phys. Lett., Vol. 56, p. 2410 (1990)) describes a method especially for III-V components in which a thin semiconductor layer in the form of a membrane of a few nm thickness is deposited on a surface elastically deformed and adapts to the surface contour of the underlying surface under the influence of the van der Waals forces.
  • the process is not suitable for industrial use and is restricted to components which are produced by means of molecular beam epitaxy processes.
  • the invention is based on the object of an environmentally compatible method which can be carried out at room temperature to provide solid connections on at least two planar surfaces of bodies and to provide articles produced by the method from at least two interconnected bodies.
  • the invention provides a connection method that can permanently connect surfaces made of any materials to one another without the use of solder and / or adhesives and at ambient temperatures below 100 ° C.
  • the prerequisite for this is that the two surfaces to be joined are brought sufficiently close together, e.g. at a distance smaller than e.g. 10 nm. This is possible with surfaces that have a low surface roughness below 10 nm, in particular less than or equal to 2 nm.
  • the method enables permanent adhesive bonds between two flat surfaces with roughnesses ⁇ 10 nm of bodies to be permanently established.
  • the Casimir effect is known from the literature (H. B. G. Casimir, Proc. Con. Net. Akad. Wet., Vol. 51, p. 793 (1948)). It describes the effect of adhesive forces between bodies that are brought together at extremely small distances. These binding forces are comparable to or greater than those of the chemical bonds if the distances fall below certain limits, typically a few nm.
  • Fig. 1a shows the course of the attraction as a function of
  • Fig. 2 one of two bodies with two opposite
  • Fig. 3 is a multi-layer component in
  • connection methods of surfaces described above are still used for soldering and / or adhesive agents and the use of high temperatures to bake the connection points.
  • solder and / or adhesive which minimizes the number of interfaces between the surfaces, and problems with the different coefficients of thermal expansion of these agents are eliminated. At the same time, the problem of high-temperature treatment after assembly is also eliminated.
  • connection forces are largely independent of the material properties of the surfaces and in particular different materials can be joined together over a large area, this represents a particularly suitable application for the invention.
  • connection technology according to the invention essentially flat surfaces with low surface roughness are important, which are also not contaminated by deposited dust particles.
  • micromechanical sensors such as Pressure sensors in which the anodic bonding process is replaced by the process according to the invention
  • connections of the component heat sink type e.g. in power transistors, high-frequency transistors, semiconductor lasers, semiconductor laser arrays, at
  • a composite body according to the invention, or the manufacturing process therefor, is sketched as exemplary embodiment 1 in FIG. 2. It connects a heat sink W, e.g. Diamond, with a semiconductor substrate B, which carries integrated circuits.
  • a heat sink W e.g. Diamond
  • a semiconductor substrate B which carries integrated circuits.
  • the through e.g. Mechanical polishing of flat ground bodies adheres so strongly that subsequent separation often leads to the destruction of the semiconductor substrate.
  • layers W of this type can also be polished on both sides and thus enable a layer structure that allows three-dimensional integration (exemplary embodiment 2 in FIG. 3).
  • a major advantage of the invention The process over the prior art is its universal applicability.
  • a preferred form of polishing is a type of mechanical polishing on a turntable in connection with a chemical removal process, as is usually used in the polishing of semiconductor wafers.
  • a disc with integrated components B in Alternately bonded with a heat-absorbing body or a heat-spreading layer W.
  • Embodiment 3 describes an ohmic connection according to the invention (FIG. 4).
  • the surface of the high-resistance substrate is polished.
  • the doping of the later contacts to increase the ohmic conductivity and the structuring of the substrate, the contact areas remaining raised, are carried out.
  • the fourth step is to apply an auxiliary layer, for example made of lacquer.
  • the auxiliary layer and raised contacts are leveled together and uniformly, for example by lapping and polishing, in order to achieve a low surface roughness.
  • the disk to be polished is opposed to a rotating, high-flat disk, with chemical removal in addition to mechanical removal.
  • a local super polish on roughness stiffness of 1-3 nm is carried out in the sixth step with the usual means. For example, ion beam processing is used and the surface is bombarded with argon ions.
  • the same process steps are then also carried out on the chip to be contacted. As the last step twelve, the chip and substrate are joined together with a contact pressure of 1-20 bar, preferably 1-5 bar, and the contact is established in this way.
  • the contact pressure can be increased to, for example, up to 20 bar in the case of surfaces which are not completely flat and which still have a large bending area. It is important that at least a large part of the surface is held together with high attractive surface connecting forces. Even if, for example, approximately 1/20 of the surfaces come closer to one another at distances of less than 10 nm, it is no longer possible to separate the components from one another mechanically.
  • the contact pressure of 20 bar is now taken over by the surface connection force and increased to a multiple.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)

Abstract

L'invention concerne un procédé de liaison directe de corps plans, d'une plaque de substrat et d'une plaque porte-contact à monter sur cette dernière, tous ces éléments présentant des surfaces particulièrement planes. Ce procédé consiste à égaliser la rugosité des surfaces à assembler des deux plaques, jusqu'à ce que les surfaces présentent une profondeur de rugosité inférieure à 10 nm, puis à nettoyer les surfaces avant de les empiler directement les unes sur les autres.
PCT/EP1995/004136 1994-10-24 1995-10-23 Procede de liaison directe de corps plans et objets fabriques selon ledit procede a partir de ces corps plans WO1996013060A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DEP4437964.1 1994-10-24
DE4437964 1994-10-24
DE19944445348 DE4445348A1 (de) 1994-12-20 1994-12-20 Verfahren zum elektrisch leitfähigen Verbinden von Körpern mit planaren Oberflächen
DEP4445348.5 1994-12-20

Publications (1)

Publication Number Publication Date
WO1996013060A1 true WO1996013060A1 (fr) 1996-05-02

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PCT/EP1995/004136 WO1996013060A1 (fr) 1994-10-24 1995-10-23 Procede de liaison directe de corps plans et objets fabriques selon ledit procede a partir de ces corps plans

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Country Link
WO (1) WO1996013060A1 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999010927A1 (fr) * 1997-08-29 1999-03-04 Farrens Sharon N Procede de soudage de tranches in situ par plasma
WO2001069676A3 (fr) * 2000-03-13 2002-03-07 Sun Microsystems Inc Procede et appareil de liaison de substrats
EP1209735A2 (fr) * 2000-10-24 2002-05-29 Shinko Electric Industries Co. Ltd. Dispositif semi-conducteur et son procédé de fabrication
EP1277232A1 (fr) * 2000-03-22 2003-01-22 Ziptronix, Inc. Procede d'integration tridimensionnel d'un appareil et appareil integre
US6780759B2 (en) 2001-05-09 2004-08-24 Silicon Genesis Corporation Method for multi-frequency bonding
US7126212B2 (en) 1999-10-01 2006-10-24 Ziptronix, Inc. Three dimensional device integration method and integrated device
US10312217B2 (en) 2000-02-16 2019-06-04 Invensas Bonding Technologies, Inc. Method for low temperature bonding and bonded structure
US11760059B2 (en) 2003-05-19 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Method of room temperature covalent bonding

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0136050A1 (fr) * 1983-08-31 1985-04-03 Kabushiki Kaisha Toshiba Procédé de liaison d'objets en silicium
EP0190508A2 (fr) * 1985-02-08 1986-08-13 Kabushiki Kaisha Toshiba Procédé pour fabriquer un dispositif à semi-conducteur composé
EP0300433A2 (fr) * 1987-07-24 1989-01-25 Kabushiki Kaisha Toshiba Procédé pour fabriquer un corps semi-conducteur composé
EP0364814A1 (fr) * 1988-10-14 1990-04-25 Shin-Etsu Handotai Company Limited Méthode pour inspecter le bonding des circuits semi-conducteurs
EP0367536A2 (fr) * 1988-11-01 1990-05-09 Mitsubishi Denki Kabushiki Kaisha Matériau de base sous forme de barreaux pour la production de plaquettes pour composants électroniques et méthode de fabrication de ces plaquettes
US5236118A (en) * 1992-05-12 1993-08-17 The Regents Of The University Of California Aligned wafer bonding
EP0590899A2 (fr) * 1992-09-29 1994-04-06 Shin-Etsu Handotai Company Limited Procédé pour la fabrication d'un substrat SOI
DE4404931A1 (de) * 1993-02-16 1994-08-18 Nippon Denso Co Verfahren und Vorrichtung zum Direktverbinden von zwei Körpern

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0136050A1 (fr) * 1983-08-31 1985-04-03 Kabushiki Kaisha Toshiba Procédé de liaison d'objets en silicium
EP0190508A2 (fr) * 1985-02-08 1986-08-13 Kabushiki Kaisha Toshiba Procédé pour fabriquer un dispositif à semi-conducteur composé
EP0300433A2 (fr) * 1987-07-24 1989-01-25 Kabushiki Kaisha Toshiba Procédé pour fabriquer un corps semi-conducteur composé
EP0364814A1 (fr) * 1988-10-14 1990-04-25 Shin-Etsu Handotai Company Limited Méthode pour inspecter le bonding des circuits semi-conducteurs
EP0367536A2 (fr) * 1988-11-01 1990-05-09 Mitsubishi Denki Kabushiki Kaisha Matériau de base sous forme de barreaux pour la production de plaquettes pour composants électroniques et méthode de fabrication de ces plaquettes
US5236118A (en) * 1992-05-12 1993-08-17 The Regents Of The University Of California Aligned wafer bonding
EP0590899A2 (fr) * 1992-09-29 1994-04-06 Shin-Etsu Handotai Company Limited Procédé pour la fabrication d'un substrat SOI
DE4404931A1 (de) * 1993-02-16 1994-08-18 Nippon Denso Co Verfahren und Vorrichtung zum Direktverbinden von zwei Körpern

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KASHIBA Y ET AL: "Energy-free bonding of materials with fine controlled surfaces in ultrahigh vacuum", ELECTRONIC PACKAGING MATERIALS SCIENCE SYMPOSIUM, BOSTON, MA, USA, 30 NOV.-4 DEC. 1987, ISBN 0-931837-76-6, 1988, PITTSBURGH, PA, USA, MATER. RES. SOC, USA, pages 371 - 376 *

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6180496B1 (en) 1997-08-29 2001-01-30 Silicon Genesis Corporation In situ plasma wafer bonding method
WO1999010927A1 (fr) * 1997-08-29 1999-03-04 Farrens Sharon N Procede de soudage de tranches in situ par plasma
US6908832B2 (en) 1997-08-29 2005-06-21 Silicon Genesis Corporation In situ plasma wafer bonding method
US10366962B2 (en) 1999-10-01 2019-07-30 Invensas Bonding Technologies, Inc. Three dimensional device integration method and integrated device
US9564414B2 (en) 1999-10-01 2017-02-07 Ziptronix, Inc. Three dimensional device integration method and integrated device
US9431368B2 (en) 1999-10-01 2016-08-30 Ziptronix, Inc. Three dimensional device integration method and integrated device
US7126212B2 (en) 1999-10-01 2006-10-24 Ziptronix, Inc. Three dimensional device integration method and integrated device
US10312217B2 (en) 2000-02-16 2019-06-04 Invensas Bonding Technologies, Inc. Method for low temperature bonding and bonded structure
US6946363B2 (en) 2000-03-13 2005-09-20 Sun Microsystems, Inc. Method for bonding substrates
WO2001069676A3 (fr) * 2000-03-13 2002-03-07 Sun Microsystems Inc Procede et appareil de liaison de substrats
EP1277232A1 (fr) * 2000-03-22 2003-01-22 Ziptronix, Inc. Procede d'integration tridimensionnel d'un appareil et appareil integre
US7037755B2 (en) 2000-03-22 2006-05-02 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6864585B2 (en) 2000-03-22 2005-03-08 Ziptronix, Inc. Three dimensional device integration method and integrated device
EP1277232A4 (fr) * 2000-03-22 2003-07-23 Ziptronix Inc Procede d'integration tridimensionnel d'un appareil et appareil integre
EP1209735A3 (fr) * 2000-10-24 2003-10-15 Shinko Electric Industries Co. Ltd. Dispositif semi-conducteur et son procédé de fabrication
EP1209735A2 (fr) * 2000-10-24 2002-05-29 Shinko Electric Industries Co. Ltd. Dispositif semi-conducteur et son procédé de fabrication
US6780759B2 (en) 2001-05-09 2004-08-24 Silicon Genesis Corporation Method for multi-frequency bonding
US11760059B2 (en) 2003-05-19 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Method of room temperature covalent bonding

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