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WO1995000973A1 - Boitier ameliore electriquement et thermiquement a substrat en silicium separe - Google Patents

Boitier ameliore electriquement et thermiquement a substrat en silicium separe Download PDF

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Publication number
WO1995000973A1
WO1995000973A1 PCT/US1994/006739 US9406739W WO9500973A1 WO 1995000973 A1 WO1995000973 A1 WO 1995000973A1 US 9406739 W US9406739 W US 9406739W WO 9500973 A1 WO9500973 A1 WO 9500973A1
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WO
WIPO (PCT)
Prior art keywords
integrated
silicon substrate
circuit
circuit die
top surface
Prior art date
Application number
PCT/US1994/006739
Other languages
English (en)
Inventor
Richard Groover
William Shu
Sang S. Lee
George Fujimoto
Original Assignee
Vlsi Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vlsi Technology, Inc. filed Critical Vlsi Technology, Inc.
Priority to JP50291895A priority Critical patent/JP2002515175A/ja
Priority to EP94920207A priority patent/EP0705485A1/fr
Priority to KR1019950705862A priority patent/KR960703274A/ko
Publication of WO1995000973A1 publication Critical patent/WO1995000973A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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    • H01L23/495—Lead-frames or other flat leads
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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Definitions

  • This invention relates to integrated- circuit packages and, more particularly, to techniques for cooling integrated-circuit packages.
  • power and ground planes have been added to molded-plastic and hermetically-sealed integrated-circuit packages to improve the electrical performance of these packages.
  • the added power and ground planes provided improved electrical performance by lowering the inductance of the power and ground leads.
  • Additional power and ground planes are provided by using multi-layer leadframes and/or multi-layer printed-circuit- board substrates.
  • heatsinks are added either internally or externally to the packages. Adding a heatsink to an electrically enhanced package, as described above, provides an integrated- circuit package with both improved electrical performance and with improved thermal performance.
  • Prior art thermally conductive heatsink materials such as copper, aluminum, alumina nitride, and multi-layer printed-circuit boards, are costly.
  • an integrated-circuit package assembly for an integrated-circuit die.
  • the package assembly is for various types of packages includes molded plastic packages and cavity- type packages, formed of materials such as ceramic or multi ⁇ layer printed-circuit board materials.
  • An important element of a package according to the invention is a separate and distinct silicon substrate.
  • the separate silicon substrate has a top surface and a bottom surface with the integrated-circuit die being fixed to the top surface of the separate silicon substrate.
  • the separate silicon substrate serves as a heat spreader for the integrated-circuit die to diffuse heat away from the integrated-circuit die.
  • the separate silicon substrate with the integrated- circuit die fixed to the separate silicon substrate can be packaged in several different types of package bodies, such as, for ex ⁇ imple, molded plastic packages and cavity-type packages, formed of materials such as ceramic or multi-layer printed- circuit boards.
  • the molded package body is formed around a leadframe, the integrated-circuit die, and the separate silicon substrate to which the integrated-circuit die is fixed.
  • the leadframe has leads extending inwardly towards a central region of the leadframe and bonding fingers are formed at the inward ends of the leads.
  • the bonding fingers are attached directly to the margins of the separate silicon substrate.
  • the separate silicon substrate is fixed to the bottom side of the die-attach paddle and the integrated-circuit die is fixed to the top side of the die-attach paddle.
  • one or more interposer ⁇ ireas are formed on the top surface of the silicon substrate for attachment of connection wires from the integrated-circuit die or the leadframe.
  • a portion of the interposer is formed on the top surface of the separate silicon substrate and extends between the integrated circuit die and the top surface of the silicon substrate to accommodate integrated-circuit dies of various sizes.
  • the interposer is formed, for example, on the surface of the silicon substrate as a layer of oxide which is covered with a layer of conductive materi ⁇ d.
  • the package body For the cavity-type package body with a cavity formed therein, the package body includes a mounting surface formed adjacent to the cavity.
  • the mounting surface has the separate silicon substrate fixed to the top surface thereof.
  • a method for cooling an integrated-circuit die includes fixing an integrated circuit die to the top surface of a separate silicon substrate having a top surface and a bottom surface; packaging the separate silicon substrate with the integrated-circuit die fixed to the separate silicon substrate in a package body; and conducting heat from the integrated-circuit die using a separate silicon substrate.
  • the step of packaging the separate silicon substrate with the integrated-circuit die fixed to the separate silicon substrate in a package body includes the step of molding the package body around a leadframe, the integrated-circuit die and the separate silicon substrate to which the integrated-circuit die is fixed.
  • the step of packaging the separate silicon substrate with the integrated-circuit die fixed to the separate silicon substrate in a package body includes the steps of providing a cavity in a cavity- type package with a mounting surface formed adjacent to the cavity and fixing the separate silicon substrate to the mounting surface.
  • the invention further includes the step of attaching connection wires from the integrated-circuit die or the leadframe to at least one interposer area formed on the top surface of the silicon substrate.
  • the step of attaching connection wires from the integrated-circuit die or the leadfr ⁇ ime to at least one interposer area formed on the top surface of the silicon substrate includes attaching connection wires to the at least one interposer which extends between the integrated circuit die and the top surface of the silicon substrate.
  • the method also includes the step of attaching the connection wires to a layer of conductive material which is formed over a layer of oxide formed on the surface of the silicon substrate.
  • FIGURE 1 is a sectional view of a package assembly with an integrated-circuit die mounted to a separate heat conductive silicon substrate, where the separate heat conductive silicon substrate is mounted to the die-attach pad of a lead frame.
  • FIGURE 2 is a sectional view of a package assembly with an integrated-circuit die mounted to a separate heat conductive silicon substrate, which is used as the die-attach pad portion of a lead frame.
  • FIGURE 3 is a sectional view of a package assembly similar to the assembly of Figure 2 and further including interposers, or connections areas, formed on the surface of the silicon substrate.
  • FIGURE 4 is a sectional view of a package assembly similar to the assembly of Figure 3 where the interposers extend under the integrated-circuit die.
  • FIGURE 5 is a sectional view of a package assembly similar to the assembly of Figure 4 where the interposers have more than one conductive layer formed thereon.
  • FIGURE 6 is a sectional view of a package assembly in which a separate silicon substrate is mounted within a cavity formed in a ceramic pin grid array (PGA) package body having a number of conductive layers formed therein.
  • FIGURE 7 is a sectional view of a package assembly in which a separate silicon substrate is mounted within a cavity formed in the ceramic PGA package body of Figure 6 and which further includes interposers, or connections areas, formed on the surface of the silicon substrate.
  • PGA ceramic pin grid array
  • FIGURE 8 is a sectional view of a package assembly similar to the assembly of Figure 7 where the interposers extend under the integrated-circuit die.
  • FIGURE 9 is a sectional view of a package assembly similar to the ceramic PGA package assembly of Figure 8 with the addition of multi-layer interposers being formed on the top surface of the silicon substrate.
  • FIGURE 10 is a sectional view of a PGA package assembly in which a separate silicon substrate is mounted within a cavity formed in a package body, which is fabricated as a multi-layer printed-circuit board with a number of conductive layers formed therein.
  • FIGURE 11 is a sectional view of the PGA package assembly of Figure 10 in which a separate silicon substrate is mounted within a cavity formed in a multi-layer printed circuit package body and which further includes interposers, or connections areas, formed on the surface of the silicon substrate.
  • FIGURE 12 is a sectional view of a PGA package assembly with the multi-layer printed circuit package body similar to the assembly of Figure 11 where the interposers extend under the integrated-circuit die.
  • FIGURE 13 is a sectional view of a PGA package assembly similar to the package assembly of Figure 12 with the addition of multi-layer interposers being formed on the top surface of the silicon substrate.
  • FIGURE 14 is an enlarged, sectional view of a portion of the PGA package assembly of Figure 13 showing typical interconnections between various external package pins and various conductive layers in the package body.
  • FIGURE 1 shows a package assembly 10 provided according to the invention for a package having a molded body.
  • the package assembly 10 has the bottom surface of an integrated-circuit die 12 mounted to the top surface of a separate heat conductive silicon substrate 14 using a thin layer 16 of die-attach materi ⁇ il.
  • the die-attach material is a standard epoxy die-attach material, which is thermally conductive and which is made electrically conductive by adding, for example, silver or another conductive material.
  • the separate heat conductive silicon substrate 14 is fixed with a layer of suitable adhesive material 18 to a die-attach pad 20 of a leadframe.
  • the leadframe has leads which extend inwardly towards a central region of the leadframe.
  • the leads have bonding fingers 22 formed at the inward ends thereof.
  • Bonding wires 24 extend from the wire-bonding pads 26 formed on the top surface of the integrated circuit die 12 to the bonding fingers 22, as indicated in the Figure.
  • the silicon substrate 14 is a separate piece which can have lateral dimensions greater than the lateral dimensions of the integrated-circuit die 12.
  • the separate silicon substrate 14 functions as a heat sink or heat spreader to enhance the thermal performance of the package assembly 10.
  • the separate silicon substrate 14 is also available to be used as a single or multi-layer interposer.
  • Silicon as a substrate material is inexpensive and readily available for the application described herein below as reject wafers from an integrated-circuit fabrication line. Silicon is thermally matched to the package components. The characteristics of the silicon substrate match those of the integrated-circuit die. Crystalline silicon has good temperature characteristics. Silicon also has the advantage that depositing of conductors on its surface is readily accomplished using standard integrated-circuit, multi-layer- metal technology. The the ⁇ n ⁇ d coefficient of expansion mismatches internal to a package are the same as those in current package designs. Finally, existing packaging materi ⁇ ds and technologies can be used.
  • FIGURE 2 shows another molded-package assembly 30 which includes an integrated-circuit die 32 mounted to the top surface of a separate heat conductive silicon substrate 34 using a thin layer 36 of die-attach material.
  • the die-attach material is a standard epoxy die-attach material, which is thermally conductive and which, if necessary, is made electrically conductive by adding, for example, silver or another conductive material.
  • bonding fingers 42 formed at the inward ends of leads of a leadframe are fixed with a layer 44 of substrate-attach material to the peripheral areas of the top surface of the separate heat conductive silicon substrate 34.
  • Bonding wires 46 extend from wire-bonding pads 48 formed on the top surface of the integrated-circuit die 32 to the bonding fingers 42, as indicated in the Figure.
  • FIGURE 3 shows a molded-package assembly 50, which is similar to the assembly of Figure 2 so that the same reference numerals are used for like elements.
  • This embodiment of the invention includes interposers 60, or connections areas, which are conveniently formed on the surface of the silicon substrate.
  • the interposers are formed of conductive material such as, for example, aluminum deposited on the top surface of the silicon substrate 34.
  • the interposers are formed with various shapes, including, for example, elongated strips extending from near the integrated-circuit die 32 to the peripheral areas on the top surface of the silicon substrate 34.
  • Bonding wires 62 extend from the wire-bonding pads 48 formed on the top surface of the integrated-circuit die 32 to the inner ends of the interposers 60 near the integrated-circuit die 32 as indicated in the Figure.
  • the outer ends of the interposers 60 are connected by bonding wires 64 to the bonding fingers 42, as indicated in the Figure.
  • FIGURE 4 shows a molded-package assembly 70, which is similar to the assembly of Figure 3, so that the same reference numerals are used for like elements.
  • interposers 72 are provided which extend under the integrated-circuit die 32, as shown in the Figure.
  • This arr ⁇ mgement accommodates various die sizes so that a standard package is provided for a wide range of die sizes. This type of package configuration is particularly useful in an environment where limited production runs of different die sizes are to be run. Only one or a small number of different standard package configurations must then be inventoried.
  • various sizes of integrated-circuit dies 32 are accommodated. Bonding wires 74 from the bonding pads 48 on a particular die 32 are bonded near the die 32, as indicated in the Figure.
  • the bonding location on the interposer 72 will vary, depending upon the size of the die. Thus, for a die larger than the die shown, bonding sites on the interposer 72 will be closer towards the periphery of the silicon substrate 34.
  • FIGURE 5 shows another embodiment of a molded- package assembly which is similar to the assembly of Figure 4, so that the same reference numerals are used for like elements.
  • the interposers 72 extend under the integrated-circuit die 32, as shown in the Figure to accommodate a range of various die sizes. This type of package configuration is particularly useful in an environment where limited production runs of somewhat different die sizes are to be run.
  • an insulation layer 82 is formed over the interposers 72.
  • the insulation layer is formed, for example, as a layer 82 of oxide material deposited on the surface of the silicon substrate 72.
  • the layer of oxide 82 has a layer 84 of conductive material formed on its top surface. These alternate layers of insulating material can be repeated, as desired. Various portions of conductive layers can be exposed and made available for connections.
  • a bonding wire 86 is connected between the bonding finger 42 and the interposer 72.
  • a bonding wire 88 is connected between the bonding pad 48 on the integrated- circuit die 32 ⁇ md the interposer 72.
  • a bonding wire 90 is connected between ⁇ mother bonding pad 48 on the integrated- circuit die 32 and the conductive layer 84.
  • Another bonding wire 92 is connected between the conductive layer 84 and a bonding finger 42.
  • FIGURE 6 shows a pin-grid- array (PGA) package assembly 100 in which a separate silicon substrate 102 is mounted within a cavity 104 formed in a cavity-type package body 106 formed of a ceramic material. The cavity is covered with a lid member 107 which is fixed to the ceramic package body 106 with a layer of an appropriate material.
  • the package body 106 has number of conductive layers (typically shown as 108) formed therein. Internal connections (not shown) are conventionally provided between various ones of the conductive layers 108 and respective ones of the external package pins (typically shown as 109).
  • a mounting surface 110 for the separate silicon substrate 102 is formed on the base portion of the ceramic PGA package body adjacent to the cavity 104, as indicated in the Figure.
  • the separate silicon substrate 102 is mounted to the mounting surface 104 with a thin layer 112 of suitable substrate-attachment material.
  • This material can be a standard epoxy material, which is thermally conductive and which is made electrically conductive by adding, for example, silver or another conductive material.
  • the separate silicon substrate 102 also serves as a die- attach pad for an integrated-circuit die 114 which is attached to the top surface of the separate silicon substrate 102 with a thin layer 116 of die-attach material.
  • Wire-bonded bonding wires 118, 119 typically extend from wire-bonding pads formed on the top surface of the integrated-circuit die 114 to various exposed portions of the conductive layers 108, as indicated in the Figure.
  • FIGURE 7 shows another embodiment of a PGA ceramic package assembly 120, which is similar to the assembly of Figure 6, so that the same reference numerals are used for like elements.
  • the separate silicon substrate 102 is mounted within the cavity formed within the ceramic PGA package body 106.
  • the package assembly 120 further includes interposers 122, 123, or conductive connection areas, formed on the upper surface of the silicon substrate 102, as illustrated.
  • the interposers 122, 123 provide intermediate connections areas so that shorter bonding wires can be used, in comparison to the longer bonding wires 118, 119 of Figure 6.
  • Wire-bonded bonding wires 124, 125 extend between bonding pads formed on the top surface of the integrated-circuit die 114 and various portions of the interposers 122, 123, as indicated in the Figure.
  • Shorter bonding wires 126, 127 extend respectively between from the outer areas ofthe interposers 122, 123 to v ⁇ irious exposed portions of the conductive layers 108, as indicated in the Figure.
  • FIGURE 8 shows a sectional view of another embodiment of a package assembly 130 which is very similar to the assembly of Figure 7 so that the same reference numerals are used for like elements.
  • interposers 132, 134 extend beneath the die 114, as illustrated. This permits a number of different die sizes to be accommodated by one package configuration.
  • FIGURE 9 shows a sectional view of an embodiment of a package assembly 140 which is very similar to the assembly of Figure 8 so that the same reference numerals are used for like elements.
  • the interposers have additional conductive layers 142, 143 formed over respective layers 144, 146 of oxide formed on the surface of the silicon substrate.
  • These additional conductive layers 142, 143 are used, for example, as connection areas for a bonding wire 146 from a bonding pad on the die 114 or for a bonding wire 148 from one of the conductive layers 108 ofthe package body 106.
  • Additional alternate layers of oxide and conductive material can be formed to provide additional intermediate connection areas, as required for particular applications, to provide multi-layer interposers on the top surface of the silicon substrate 102.
  • FIGURES 10-13 illustrate PGA package assemblies which use a package body 150, which is fabricated as a multi- layer printed-circuit board with a number of conductive layers 152 formed therein. These package assemblies are similar to the ceramic package assemblies illustrated in Figures 6-10.
  • FIGURE 10 illustrates a pin-grid-array (PGA) package assembly 160 in which a separate silicon substrate 162 is mounted within a cavity 164 formed in the cavity-type package body 150, which is formed as a multi-layer printed-circuit bo ⁇ ird.
  • the cavity is covered with a lid member 167 which is fixed to the ceramic package body 150 with a la ⁇ er of an appropriate material.
  • the package body 150 has the number of conductive layers (typically shown as 152) formed therein. Internal connections (not shown) are conventionally provided between various ones of the conductive layers 152 and respective ones of the external package pins (typically shown as 168).
  • a mounting surface 170 for the separate silicon substrate 162 is formed on the base portion ofthe multi-layer printed-circuit board PGA package body adjacent to the cavity 164, as indicated in the Figure.
  • the separate silicon substrate 162 is mounted to the mounting surface 170 with a thin layer 172 of suitable substrate-attachment material.
  • This material can be a standard epoxy material, which is thermally conductive and which is made electrically conductive by adding, for example, silver or another conductive material.
  • the separate silicon substrate 162 also serves as a die- attach pad for an integrated-circuit die 174 which is attached to the top surface of the separate silicon substrate 162 with a thin layer 176 of die-attach material.
  • Wire-bonded bonding wires 178, 179 typic ⁇ tlly extend from wire-bonding pads formed on the top surface of the integrated-circuit die 174 to various exposed portions of the conductive layers 152, as indicated in the Figure.
  • FIGURE 11 shows a sectional view of another embodiment of a multi-layer printed-circuit board package assembly 180 which is very similar to the assembly of Figure 10, so that the same reference numerals are used for like elements.
  • interposers 182, 183 extend beneath the die 174, as illustrated. This permits a number of different die sizes to be accommodated by one package configuration.
  • the interposers 182, 183 provide intermediate connections areas so that shorter bonding wires can be used, in comparison to the longer bonding wires 178, 179 of Figure 10.
  • Wire-bonded bonding wires 184, 185 extend between bonding pads formed on the top surface of the integrated-circuit die 174 and various portions of the interposers 182, 183, as indicated in the Figure.
  • Shorter bonding wires 186, 187 extend respectively between from the outer areas of the interposers 182, 183 to various exposed portions of the conductive layers 152, as indicated in the Figure.
  • FIGURE 12 shows a sectional view of another embodiment of a multi-layer printed circuit body package assembly 190 which is very simil ⁇ ir to the assembly of Figure 11 so that the same reference numerals are used for like elements.
  • interposers 182, 184 extend beneath the die 174, as illustrated. This permits a number of different die sizes to be accommodated by one package configuration.
  • FIGURE 13 shows a sectional view of an embodiment of a multi-layer printed circuit body package assembly 200 which is very similar to the assembly of Figure 12 so that the same reference numerals are used for like elements.
  • the interposers have additional conductive layers 202, 203 formed over respective layers 204, 205 of oxide formed on the surface of the silicon substrate.
  • These additional conductive layers 202, 203 are used, for ex ⁇ imple, as connection areas for a bonding wire 206 from a bonding pad on the die 174 or for a bonding wire 208 from one of the conductive layers 152 of the package body 150.
  • Additional alternate layers of oxide and conductive material can be formed to provide additional intermediate connection areas, as required for particular applications, to provide multi-layer interposers on the top surface of the silicon substrate 162.
  • FIGURE 14 shows a portion of the PGA package assembly 200 of Figure 13, illustrating typical interconnections between various typical external package pins 168 and various typical conductive layers 152 in the package body.
  • plated-through holes 210, 212 are typically shown extending through the body of the package to provide conductive connections between the conductive layers 1152 and the external package pins 168.
  • the interposer with the separate silicon substrate provides for assembly of a very small die in a high pincount packages.
  • the separate silicon substrate allows an integrated- circuit die to be bonded out in a standard package bond-out configuration and in a universal bond-out configuration without crossing wires.
  • the invention provides a very cost effective solution for thermal enhancement of the package.
  • the separate silicon substrate could be patterned using existing integrated-circuit fabrication and processing technology to provide an interposer.
  • the interposer reduces the wirelengths required for a die with a limited number pads in a high pincount packages.
  • the interposer uses single level metalization techniques known in the art of fabricating integrated circuits.
  • the invention could also be used to duplicate the pinout of an electrical and thermally enhanced with a standard metric quad flat pack (MQFP) package or a molded-plastic thermally enh ⁇ inced package.
  • MQFP standard metric quad flat pack
  • the invention could ⁇ ilso be used to duplicate the pinout of either an 8-layer high performance ceramic pin grid array (HPCPGA) or an 8- layer high performance plastic pin grid ⁇ irray (HPPPGA) package in a 5-layer high performance ceramic pin grid array (HPCPGA) or a 5-layer high performance plastic pin grid array HPPPGA package.
  • the separate silicon substrate according to the invention could also be patterned to allow for attachment of multiple integrated-circuit dies to the separate silicon substrate.
  • Standard techniques are employed in practicing the invention.
  • An integrated circuit die is attached to a silicon substrate with standard epoxy die-attach material, which is thermally conductive and which is made electrically conductive by adding, for example, silver.
  • PPGA plastic pin grid array
  • Silicon as a substrate material is inexpensive and readily available as reject wafers from integrated-circuit fabrication lines. Crystalline silicon has good temperature characteristics. Depositing of conductors is readily accomplished using integrated-circuit multi-layer-metal technology.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

Un ensemble boîtier de circuit intégré comporte un substrat (34) en silicium séparé auquel est fixée une puce (32) de circuit intégré. Ledit substrat (34) en silicium séparé sert de diffuseur de chaleur pour la puce (32) de circuit intégré. Le substrat (34) en silicium auquel la puce (32) de circuit intégré est fixée est mis sous boîtier dans un corps (80) de boîtier moulé ou un corps (120) de boîtier de type à cavité. Le corps (80) de boîtier moulé est moulé autour d'une grille de connexion (42), de la puce (32) de circuit intégré et du substrat (34) en silicium séparé auquel cette dernière (32) est fixée. Pour ce qui concerne le corps (80) de boîtier moulé, la grille de connexion (42) présente des pattes de connexion formées au niveau de ses extrémités en dedans fixées au substrat (34) en silicium séparé, ou peut présenter un plot (20) de connexion de la puce à laquelle est fixé le substrat (34) en silicium séparé. Pour ce qui concerne le boîtier (120) à cavité, le corps du boîtier comporte une surface de montage adjacente à une cavité formée dans celui-ci, ledit substrat en silicium séparé (102) étant fixé sur la surface supérieure de la surface de montage. Le corps (120) de type boîtier est constitué de matière céramique ou forme une carte de circuits imprimés multicouche. Une ou plusieurs zones d'interposeur (122) sont formées sur la surface supérieure du substrat (102) en silicium de manière à permettre la fixation de fils de connexion (125, 127) provenant de la puce (114) de circuit intégré ou de la grille de connexion (42). Une partie de l'interposeur (72, 122) peut s'étendre entre la puce (32, 114) de circuit intégré et la surface supérieure du substrat (34, 102) en silicium pour recevoir des puces (32, 114) de circuit intégré de tailles diverses. L'interposeur se compose d'une couche d'oxyde (82) formée à la surface du substrat (34, 102) en silicium et recouverte d'une couche de matériau conducteur (84).
PCT/US1994/006739 1993-06-23 1994-06-13 Boitier ameliore electriquement et thermiquement a substrat en silicium separe WO1995000973A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP50291895A JP2002515175A (ja) 1993-06-23 1994-06-13 別個のシリコンサブストレートを用いる電気的および熱的に向上したパッケージ
EP94920207A EP0705485A1 (fr) 1993-06-23 1994-06-13 Boitier ameliore electriquement et thermiquement a substrat en silicium separe
KR1019950705862A KR960703274A (ko) 1993-06-23 1994-06-13 분리 실리콘기판을 사용하여 전기적 열적으로 향상된 팩키지(electrically and thermally enhanced package using a separate silicon substrate)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US8212293A 1993-06-23 1993-06-23
US16961793A 1993-12-17 1993-12-17
US08/169,617 1993-12-17
US08/082,122 1993-12-17

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Cited By (1)

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US8404980B2 (en) 2005-09-30 2013-03-26 Fujitsu Semiconductor Limited Relay board and semiconductor device having the relay board

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JPS56134747A (en) * 1980-03-25 1981-10-21 Mitsubishi Electric Corp Semiconductor device
JPS6315447A (ja) * 1986-07-07 1988-01-22 Nec Corp 混成集積回路装置
EP0509825A2 (fr) * 1991-04-16 1992-10-21 Nec Corporation Structure d'empaquetage pour dispositif semi-conducteur
EP0516185A2 (fr) * 1987-04-22 1992-12-02 Hitachi, Ltd. Dispositif semi-conducteur à circuits intégrés à l'échelle d'une pastille
EP0520679A2 (fr) * 1991-06-27 1992-12-30 AT&T Corp. Procédé pour fabriquer un ensemble d'empaquetage prémoulé
FR2684803A1 (fr) * 1991-12-04 1993-06-11 Gemplus Card Int Boitier a structure renforcee pour circuit integre, et carte comprenant un tel boitier.
WO1993017455A2 (fr) * 1992-02-20 1993-09-02 Vlsi Technology, Inc. Configuration de boitier de circuit integre pour l'encapsulation d'une puce a circuit integre et procede d'encapsulation d'une puce a circuit integre
WO1993020586A1 (fr) * 1992-03-31 1993-10-14 Vlsi Technology, Inc. Grille de connexion dotee d'un ou plusieurs plans de connexion a l'alimentation ou a la masse depourvus de traversees

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JPS56134747A (en) * 1980-03-25 1981-10-21 Mitsubishi Electric Corp Semiconductor device
JPS6315447A (ja) * 1986-07-07 1988-01-22 Nec Corp 混成集積回路装置
EP0516185A2 (fr) * 1987-04-22 1992-12-02 Hitachi, Ltd. Dispositif semi-conducteur à circuits intégrés à l'échelle d'une pastille
EP0509825A2 (fr) * 1991-04-16 1992-10-21 Nec Corporation Structure d'empaquetage pour dispositif semi-conducteur
EP0520679A2 (fr) * 1991-06-27 1992-12-30 AT&T Corp. Procédé pour fabriquer un ensemble d'empaquetage prémoulé
FR2684803A1 (fr) * 1991-12-04 1993-06-11 Gemplus Card Int Boitier a structure renforcee pour circuit integre, et carte comprenant un tel boitier.
WO1993017455A2 (fr) * 1992-02-20 1993-09-02 Vlsi Technology, Inc. Configuration de boitier de circuit integre pour l'encapsulation d'une puce a circuit integre et procede d'encapsulation d'une puce a circuit integre
WO1993020586A1 (fr) * 1992-03-31 1993-10-14 Vlsi Technology, Inc. Grille de connexion dotee d'un ou plusieurs plans de connexion a l'alimentation ou a la masse depourvus de traversees

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8404980B2 (en) 2005-09-30 2013-03-26 Fujitsu Semiconductor Limited Relay board and semiconductor device having the relay board

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EP0705485A1 (fr) 1996-04-10
JP2002515175A (ja) 2002-05-21
KR960703274A (ko) 1996-06-19

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