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WO1993017455A2 - Configuration de boitier de circuit integre pour l'encapsulation d'une puce a circuit integre et procede d'encapsulation d'une puce a circuit integre - Google Patents

Configuration de boitier de circuit integre pour l'encapsulation d'une puce a circuit integre et procede d'encapsulation d'une puce a circuit integre Download PDF

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Publication number
WO1993017455A2
WO1993017455A2 PCT/US1993/001490 US9301490W WO9317455A2 WO 1993017455 A2 WO1993017455 A2 WO 1993017455A2 US 9301490 W US9301490 W US 9301490W WO 9317455 A2 WO9317455 A2 WO 9317455A2
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WO
WIPO (PCT)
Prior art keywords
bonding
die
integrated
conductive
electrically
Prior art date
Application number
PCT/US1993/001490
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English (en)
Other versions
WO1993017455A3 (fr
Inventor
Young Il Kwon
Louis H. Liang
Original Assignee
Vlsi Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vlsi Technology, Inc. filed Critical Vlsi Technology, Inc.
Priority to JP5514969A priority Critical patent/JP2691799B2/ja
Publication of WO1993017455A2 publication Critical patent/WO1993017455A2/fr
Publication of WO1993017455A3 publication Critical patent/WO1993017455A3/fr

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    • H—ELECTRICITY
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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Definitions

  • This invention relates to packaging techniques for integrated circuits and, more particularly, to techniques for mounting various sizes of integrated- circuit dies to a common leadframe and to techniques for improving the thermal
  • the integrated-circuit die is mounted to a centrally-located die-attach paddle, or pad, of the leadframe.
  • the die- attach paddle is rectangular in shape and is supported at each of its four corners by a radially extending support beam.
  • the leadframe includes a number of thin, closely- spaced conductive leads which radially extend away from the edges of the die.
  • FIGURE 1 of the drawings for the instant patent application shows a sectional view of a prior art integrated-circuit package assembly 10 which is similar to the Comstock 317 reference.
  • bonding pads 13 On the top surface of an integrated- circuit die 12 are provided bonding pads 13 to which are attached bonding wires by techniques known in the integrated-circuit packaging art.
  • the die 12 is conventionally mounted to a die-attach pad 14 which is part of a leadframe assembly for leads having bonding fingers 16, typically shown.
  • the die 12 lies within a central cavity 17 formed within an insulated bridging member, or substrate assembly 18.
  • the substrate assembly includes conductors formed on a relatively thick insulator layer 22.
  • the conductors 20 serve as intermediate connection points for a typical first bonding wire 24, which spans the gap between the bonding finger 16 and the conductors 20.
  • the conductor 20 also serves an intermediate connection point for a typical second bonding wire 26, which spans the gap between one of the bonding pads 13 of the die 12 and one of the conductors 20.
  • Encapsulating plastic epoxy material is molded around the die and the leadframe to form a body 30 for the integrated-circuit package assembly 10.
  • FIGURE 2 of the drawings for the instant patent application shows a prior art integrated-circuit package assembly 40, similar to the Greenberg 635 structure, for an integrated-circuit die 42.
  • the die 42 has bonding pads 43 on its top surface, to which are attached bonding wires by techniques known in the integrated- circuit packaging art.
  • the die 42 is conventionally mounted to a conventional die- attach pad 44 which is part of a leadframe assembly for the leads 46.
  • the package assembly 40 includes an intermediate insulated layer 52, which has very thin, fragile conductive fingers 54 formed on its top surface.
  • the conductive fingers 54 are bonded at one end to the bonding fingers 46 of the leadframe.
  • the conductive fingers 54 shorten the gap which must be covered by bonding wires 60 extending from the bonding pads of the integrated-circuit die 42.
  • the die 42 sits within a cavity 62 formed within the center region of the insulated layer 52. Note that this technique requires precise alignment and assembly of the thin, fragile conductive fingers 54 to their respective bonding fingers 46, which requires expensive fabrication
  • the distance between a bonding pad and its corresponding bonding finger varies, depending upon whether the bonding pad is located near a corner of the die or near the midpoint of the side of the die.
  • the bonding distance for a bonding pad near a corner of a die may greatly exceed 150 mils, while the bonding distance for a bonding near the midpoint of a side may be approximately 150 mils. Consequently, a need exists for an integrated-circuit packaging technique which can optionally provide an intermediate bridge point for a long bonding wire span.
  • an integrated-circuit die be electrically insulated from the die-attach pad to which the lower surface of the integrated-circuit die is attached. This may require the use of a dielectric material between the lower surface of the die and the conductive die-attach pad. Smaller dies typically require better thermal dissipation characteristics from their packaging configuration. Consequently, the need exists for an integrated-circuit technique which permits a die to be electrically insulated, but thermally connected to a die-attach pad portion of a leadframe.
  • a package design configuration for an integrated-circuit die includes a leadframe having a plurality of bonding fingers extending from a central region.
  • An electrically-insulated, heat-conductive substrate is provided which has a first surface to which the ends of the bonding fingers are bonded along its periphery.
  • the substrate is formed from a thermally conductive material such as a ceramic material.
  • the integrated-circuit die is attached to a central area of the substrate, corresponding to the central region of the leadframe.
  • a number of electrically conductive bonding islands, or conductive traces, are formed on the first surface of the electrically-insulated, heat- conductive substrate.
  • the conductive traces extend from the central area of the ceramic substrate to provide respective intermediate attachment areas for bonding wires which extend from bonding pads on the integrated-circuit die.
  • the conductive traces also provide an intermediate attachment area for attachment of shorter bonding wires between the bonding fingers of the lead frame and the conductive traces.
  • the conductive traces serving as bonding islands are formed by deposition of thin-film material using semiconductor fabrication techniques or by deposition of thick-film material using printing techniques.
  • Various shapes and configurations of the conductive traces are available, such as elongated rectangular patterns, or zigzag patterns.
  • suitable bonding-pad areas are provided
  • the invention provides the option of not having conductive traces for all of the bonding pads of the integrated-circuit die.
  • the conductive traces are provided for bonding distances greater than, for example, 150 mils, typically encountered at the corners of the die.
  • the electrically-insulated, heat-conductive pad is attached to the die-attach pad of a conventional leadframe.
  • a method of packaging an integrated-circuit die includes bonding the ends of the bonding fingers of a leadframe to the periphery of an electrically-insulated, heat-conductive substrate.
  • An integrated-circuit die is attached to a central area of the substrate. Bonding wires are attached from between bonding pads on the integrated-circuit die to respective ones of a plurality of electrically conductive traces, or bonding islands, formed on the electrically-insulated, heat-conductive substrate. Bonding wires are also attached between the bonding fingers of the leadframe and one of the plurality of electrically conductive traces.
  • the method includes the step of forming the electrically conductive traces by printing thick-films on the electrically-insulated, heat-conductive substrate or by depositing thin-films on the substrate.
  • the invention readily accommodates a variety of die sizes without changing the leadframe or the conductive traces formed on the ceramic substrate. Consequently, either standard leadframes or a common leadframe can be used according to the invention.
  • the invention permits connections to an integrated-circuit die by providing connections to the die with the conductive traces.
  • electrically-insulated ceramic die-attach substrate permits the entire die to be electrically isolated from the leadframe, while providing good thermal performance with the thermally conductive die-attach ceramic substrate.
  • the method of the invention also provides for forming the conductive traces or bonding islands only where the distance between the bonding pads on the integrated-circuit die and a corresponding bonding finger of the leadframe is greater than 150 mils.
  • the intermediate conductive traces are utilized. Connections to bonding pads on the die which require bonding-wire lengths less than 150 mils do not require use of the conductive traces. Consequently, the invention provides a flexible technique adapted to the needs of a particular die size and the wire- bonding length requirement of each bonding pad of an integrated-circuit die. Use of the standard die-attach paddle of a standard leadframe is also accommodated by the present invention.
  • FIGURE 1 is a sectional view of a prior art integrated-circuit package assembly which has a leadframe with an intermediate conductive substrate, or bridge member, fixed thereto to serve as an intermediate connection point for two shorter bonding wires.spanning the gap between a die and bonding fingers.
  • FIGURE 2 is a sectional view of another prior art integrated-circuit package assembly which has an insulating-tape layer having conductive fingers formed thereupon, where the conductive fingers extend out and are bonded to the ends of the bonding fingers of a leadframe.
  • FIGURE 3 is a sectional view of an integrated-circuit package which uses an electrically-insulated, heat-conducting substrate on which the integrated-circuit die is mounted and on which are formed conductive traces which serve as intermediate junction points for connecting integrated-circuit dies of various sizes to bonding fingers of a leadframe with two shorter bonding wires.
  • FIGURE 4 is a plan view of the integrated circuit package arrangement of Figure 3, showing the substrate and the integrated-circuit die overlying the conductive traces.
  • FIGURE 5 is a sectional view of an electrically-insulated, heat-conducting substrate to which is attached a die, the bonding fingers of a leadframe, and intermediate conductive traces.
  • FIGURE 6 is a plan, partial view of the arrangement of Figure 5, showing one pattern for the conductive traces, or bonding islands.
  • FIGURE 7 is a plan, partial view of an alternative arrangement for the conductive traces, or bonding islands of Figure 5.
  • FIGURE 8 is a sectional view showing an electrically-insulated, heat- conducting substrate having conductive traces formed thereupon which are directly connected to the bonding fingers of a leadframe.
  • FIGURE 9 is a sectional view showing an electrically-insulated, heat- conducting substrate which is mounted to a die-attach pad of a conventional leadframe.
  • FIGURE 10 is a sectional view showing an electrically-insulated, heat- conducting substrate mounted to a die-attach pad of a conventional leadframe, where the heat-conducting substrate includes conductive traces, or bonding islands, formed on its top surface and extending beneath the ceramic substrate to serve as an intermediate junction point for two shorter bonding wires for integrated-circuit dies of various sizes.
  • FIGURE 11 is a plan view of the integrated circuit package arrangement of Figure 10, showing the substrate mounted to the die-attach pad of the leadframe and showing the integrated circuit overlying the conductive traces on the substrate.
  • FIGURES 3 and 4 show an integrated-circuit package configuration 100, according to the invention.
  • This embodiment of the invention uses an electrically- insulated, heat-conducting substrate 102 as a bonding pad for an integrated-circuit die 104.
  • the electrically-insulated, heat-conducting substrate 102 is formed of a ceramic material such as alumina nitride, beryllium oxide, a very thin polymeric film, or an equivalent material having good heat conduction characteristics.
  • the ceramic substrate 102 is bonded to the bonding-finger ends of the leads, typically shown as 106, of a leadframe.
  • the ceramic substrate 102 serves as an electrically-insulated, thermally- conductive die-attach pad for the integrated-circuit die 104.
  • the leadframe is not conventional because it does not have a conventional metal die-attach pad (such as shown in Figures 1 and 2 by the reference numerals 14,44), where the leadframe is formed along with the leads
  • the leads converge from the exterior walls of a molded package toward the central region of the ceramic substrate 104.
  • Electrically conductive traces are formed on the substrate 102. These traces 110 serve as intermediate junction points for two shorter bonding wires, which are used for connecting dies of various sizes to bonding-finger ends of the leads.
  • the conductive traces 110 extend outwardly from a central area of the ceramic substrate 104 and provide intermediate attachment locations for attachment of a first shorter bonding wire 112, which extends from a bonding pad (typically shown as 114) on the integrated-circuit die 104.
  • the conductive traces 110 also provide an intermediate attachment area for attachment of a second shorter bonding wire 116, which extends to the bonding finger 106.
  • FIGURE 4 also shows an optional use arrangement to accommodate cases where the entire distance, or bond- wire length, between a wire-bonding pad on an integrated-circuit die and the bonding finger is not greater than 150 mils. This case may occur for those leads 120 which are near the midpoints of the side of a die.
  • the corresponding conductive traces 122 can alternatively not be used so that bonding wires 124 from the mid-point bonding pads 126 go directly from the bonding pads 126 on the die 104 to the bonding fingers 120.
  • the corresponding conductive traces for those positions on the die are eliminated and bonding wires 130 are connected directly between the bonding fingers and the bonding pads 134, as indicated in Figure 4.
  • the die 104 is attached to the ceramic substrate 102.
  • the ceramic substrate 102 is a particularly good conductor of heat from the die 104 to the bonding-finger ends 106 of the leadframe. Use of the heat-conducting ceramic substrate 102 consequently improves the thermal performance of the integrated-circuit package.
  • FIGURE 5 shows an alternative packaging configuration, according to the invention.
  • An electrically-insulated, heat-conducting ceramic substrate 152 has an integrated-circuit die 154 attached to its upper surface.
  • the bonding fingers 156 of a leadframe are also attached to the upper surface of the ceramic substrate 152.
  • Intermediate conductive traces, or interposers, 158 are deposited on the upper surface of the ceramic substrate 152 using, for example, thin-film deposition techniques or thick-film printing techniques. Connections are made between the die and the interposer 158 with bonding wires 160. Connections are made between the interposer 158 and the bonding fingers 156 with bonding wires 162. Note that the die 154 does not contact the interposers 158 and that dies of various size can be accommodated by this arrangement so that the length of any of the bonding wires can be maintained less than 150 mils.
  • a printing tool is provided which has a positive raised-relief of the pattern of the conductive traces formed on its surface.
  • the printing tool is dipped in a gold-filled epoxy material and the gold-filled epoxy material is imprinted on the surface of the ceramic substrate.
  • FIGURE 6 shows in plan view shows another alternative embodiment of a pattern of the generic bonding islands, or conductive traces, 158 of Figure 5.
  • Elongated strips of conductive material 170 are formed on the upper surface of a ceramic substrate 172 using either deposited thin films or printed thick-films formed on the upper surface of the electrically-insulated, heat-conductive substrate 152.
  • Short bonding wires typically shown as 174, connect between bonding pads 176 on an integrated-circuit die 178 and the inner ends 176 of the bonding pads 170.
  • the outer ends 178 of the bonding pads 170 are connected with short bonding wires 178 to inner ends of the bonding fingers 180.
  • Figure 6 shows that no intermediate bonding islands are used.
  • single bonding wires 182 connect the bonding pads 184 on the die 178 to respective bonding fingers 186.
  • the intermediate conductive traces, bonding islands, are most often needed for bonding pads near the comers of a die where the distance to its corresponding bonding finger is greater than that for a bonding pad near the midpoint of of the side of a die.
  • FIGURE 7 shows another alternative pattern of the generic bonding islands 158 of Figure 5 where the pattern includes zigzag shaped conductive strips (typically shown as 190) formed on a ceramic substrate 191.
  • a conductive strip 190 has a first bonding area 192 at its inner end.
  • a first short bonding wire 194 is connected between the bonding area 192 and a bonding pad 196 on an integrated-circuit die 198.
  • a second bonding area 200 has one end of a second short bonding wire 202 attached thereto. The other end of the second short bonding wire 202 is attached to a bonding finger 204 which is fixed to the ceramic substrate 191.
  • This figure also shows that, for bonding distances less than 150 mils, a bonding wire 206 is connected directly between a bonding pad 208 on the die 198 and a bonding finger 210.
  • FIGURE 8 is shows an electrically-insulated, heat-conducting ceramic substrate 220 with an integrated-circuit die attached to its upper surface.
  • Conductive traces 224 are formed on the ceramic substrate 220.
  • Bonding fingers 226 of a leadframe are directly connected to the conductive traces 224. This arrangement eliminates the need for two bonding wires per bonding pad on the integrated-circuit die 222.
  • Single short bonding wires 228 are shown connected between bonding pads on the die 222 and the conductive traces 224.
  • FIGURE 9 shows an electrically-insulated, heat-conducting ceramic substrate
  • Bonding fingers 236 of a leadframe are adhesively directly bonded to the electrically-insulated, heat- conducting ceramic substrate 230.
  • Wire-bond wires 238 are connected between bonding pads on the die 232 and the bonding fingers 236.
  • FIGURE 10 shows an electrically-insulated, heat-conducting ceramic substrate 5.
  • 240 mounted to a die-attach pad 242 of a conventional leadframe.
  • conductive traces 244 are formed on the top surface of the ceramic substrate
  • An integrated-circuit die 246 is mounted to the ceramic substrate 240 over the traces 244.
  • These traces 244 are designed so that different sizes of dies can be accommodated by having the traces 244 extend beneath the die, as indicated in the 0 figure.
  • the traces 244 serve as an intermediate junction point for two shorter bonding wires 248,250.
  • FIGURE 11 is a plan view of the integrated circuit package arrangement of Figure 10.
  • the ceramic substrate 240 is mounted to the die-attach pad 242 of the 5 leadframe.
  • the integrated-circuit die is shown overlying the inner ends of the conductive traces 244 located on the upper surface of the the the ceramic substrate 240.
  • Bonding wires 260,262 are shown directly bonded between die-attach pads and their corresponding bonding fingers.
  • a method for packaging an integrated- circuit die.
  • the ends of the bonding fingers of a leadframe are bonded to the periphery of an electrically-insulated, heat-conductive substrate.
  • An integrated-circuit die is 0 attached to a central area of the substrate.
  • Bonding wires are attached between bonding pads on the integrated-circuit die and one of a plurality of electrically conductive traces, or bonding islands, formed on the electrically-insulated, heat-conductive substrate. Bonding wires are attached between the bonding fingers of the leadframe and one of the plurality of electrically conductive traces, or bonding islands. 5
  • the method includes the step of forming the electrically conductive bonding traces, or bonding islands, by forming thick-films or thin-films on the electrically- insulated, heat-conductive ceramic substrate.
  • the bonding conductive trace, or bonding islands are optionally formed where the distance between the bonding pads on the integrated-circuit die and a corresponding bonding finger of the leadframe is typically greater than 150 mils.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

Un type de boîtier destiné à une puce à circuit intégré (104) comporte une grille de connexion dont les pattes de connexion (106) sont connectées à la périphérie d'un substrat (102) conducteur de chaleur, électriquement isolé, constitué par exemple d'un matériau céramique. Plusieurs trajets conducteurs électriques (110), ou îlots de liaison, servent de sites de liaison intermédiaire pour les fils de liaison plus courts (112, 116) connectant les plages de connexion (114) placées sur la puce à circuit intégré (104) aux pattes de connexion (106) de la grille de connexion. La puce à circuit intégré recouvre les trajets conducteurs tout en laissant une partie exposée qui sert respectivement de zone de rattachement intermédiaire pour chacun des fils de liaison. Les trajets électriques servant d'îlots de liaison sont créés par dépôt d'un matériau en couche mince recourant aux techniques de fabrication des semi-conducteurs ou par dépôt d'un matériau en couche épaisse recourant aux techniques d'impression.
PCT/US1993/001490 1992-02-20 1993-02-19 Configuration de boitier de circuit integre pour l'encapsulation d'une puce a circuit integre et procede d'encapsulation d'une puce a circuit integre WO1993017455A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5514969A JP2691799B2 (ja) 1992-02-20 1993-02-19 リードフレームに接合された介在ダイ取付基板を有する集積回路パッケージ設計

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US83919192A 1992-02-20 1992-02-20
US07/839,191 1992-02-20

Publications (2)

Publication Number Publication Date
WO1993017455A2 true WO1993017455A2 (fr) 1993-09-02
WO1993017455A3 WO1993017455A3 (fr) 1993-11-25

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JP (1) JP2691799B2 (fr)
WO (1) WO1993017455A2 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995000973A1 (fr) * 1993-06-23 1995-01-05 Vlsi Technology, Inc. Boitier ameliore electriquement et thermiquement a substrat en silicium separe
US5598031A (en) * 1993-06-23 1997-01-28 Vlsi Technology, Inc. Electrically and thermally enhanced package using a separate silicon substrate
GB2306775A (en) * 1995-10-24 1997-05-07 Altera Corp integrated circuit package
WO2001027996A1 (fr) * 1999-10-14 2001-04-19 Motorola Inc. Grille matricielle a billes a brochage reconfigurable
US7592694B2 (en) 2006-12-18 2009-09-22 Chipmos Technologies Inc. Chip package and method of manufacturing the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019074857A1 (fr) * 2017-10-10 2019-04-18 Zglue Inc. Ensemble de boîtiers de module flexibles et intégrés avec grilles de connexion

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5694762A (en) * 1979-12-28 1981-07-31 Fujitsu Ltd Plug-in type package
US4754317A (en) * 1986-04-28 1988-06-28 Monolithic Memories, Inc. Integrated circuit die-to-lead frame interconnection assembly and method
US4774635A (en) * 1986-05-27 1988-09-27 American Telephone And Telegraph Company At&T Bell Laboratories Semiconductor package with high density I/O lead connection
EP0351581A1 (fr) * 1988-07-22 1990-01-24 Oerlikon-Contraves AG Circuit intégré à haute densité et procédé pour sa fabrication
JP2519806B2 (ja) * 1989-09-12 1996-07-31 株式会社東芝 樹脂封止型半導体装置

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995000973A1 (fr) * 1993-06-23 1995-01-05 Vlsi Technology, Inc. Boitier ameliore electriquement et thermiquement a substrat en silicium separe
US5598031A (en) * 1993-06-23 1997-01-28 Vlsi Technology, Inc. Electrically and thermally enhanced package using a separate silicon substrate
GB2306775A (en) * 1995-10-24 1997-05-07 Altera Corp integrated circuit package
US5757070A (en) * 1995-10-24 1998-05-26 Altera Corporation Integrated circuit package
GB2306775B (en) * 1995-10-24 2000-09-20 Altera Corp Integrated circuit package
WO2001027996A1 (fr) * 1999-10-14 2001-04-19 Motorola Inc. Grille matricielle a billes a brochage reconfigurable
US7592694B2 (en) 2006-12-18 2009-09-22 Chipmos Technologies Inc. Chip package and method of manufacturing the same

Also Published As

Publication number Publication date
JPH06507276A (ja) 1994-08-11
JP2691799B2 (ja) 1997-12-17
WO1993017455A3 (fr) 1993-11-25

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