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WO1993016881A1 - Dispositif discriminateur de type et procede correspondant - Google Patents

Dispositif discriminateur de type et procede correspondant Download PDF

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Publication number
WO1993016881A1
WO1993016881A1 PCT/JP1992/000227 JP9200227W WO9316881A1 WO 1993016881 A1 WO1993016881 A1 WO 1993016881A1 JP 9200227 W JP9200227 W JP 9200227W WO 9316881 A1 WO9316881 A1 WO 9316881A1
Authority
WO
WIPO (PCT)
Prior art keywords
electronic device
data
address
type
signal
Prior art date
Application number
PCT/JP1992/000227
Other languages
English (en)
Japanese (ja)
Inventor
Ken-Ichi Wakabayashi
Chitoshi Takayama
Tadashi Shiozaki
Original Assignee
Seiko Epson Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corporation filed Critical Seiko Epson Corporation
Priority to PCT/JP1992/000227 priority Critical patent/WO1993016881A1/fr
Publication of WO1993016881A1 publication Critical patent/WO1993016881A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K17/00—Methods or arrangements for effecting co-operative working between equipments covered by two or more of main groups G06K1/00 - G06K15/00, e.g. automatic card files incorporating conveying and reading operations

Definitions

  • the present invention relates to an apparatus for determining the model of a plurality of types of electronic devices and a method for determining the model.
  • Devices based on such digital logic operations have more flexible control than simple feedback control realized only with hardware, and also change substantial functions by changing software. It has the advantage of being able to do so. Therefore, even with the same hardware, completely different control can be realized only by changing the contents of the ROM storing the processing procedure. In addition, it has the advantage that the function can be purged only by changing the software.
  • Some of such electronic devices can mount a cartridge such as an IC card in the expansion slot. If a cartridge containing data for an electronic device such as a program software is mounted on the electronic device as a cartridge, the function of the electronic device can be changed.
  • the present invention has been made to solve the above-described problems in the related art, and has as its object to provide a device for discriminating a model of a plurality of types of electronic devices and a method for discriminating the model.
  • the present invention which is made as an additional electronic device, is an additional electronic device that can be connected via a connector to a plurality of types of electronic devices having a first processor capable of performing a logical operation.
  • a first storage unit that stores a plurality of types of data applied to each of the plurality of types of electronic devices; and a first storage unit configured to store the plurality of types of data based on a signal given from the connected electronic device.
  • Discriminating means for discriminating a type and selecting at least one of the plurality of types of data stored in the first storage means according to the discriminated type and transmitting the selected data to the electronic device. .
  • the determining means determines the type of the connected electronic device and selects one of a plurality of types of data in accordance with the determined type and transmits it to the electronic device. Can be applied to a plurality of types of electronic devices.
  • the judging means switches the level of at least one predetermined bit of the address given from the first processor according to the type of the connected electronic device, and switches the switched address to the first address. It is preferable to have an address switching means for providing the storage means. With this configuration, even if the electronic device accesses the same address, data corresponding to the type of the electronic device can be read from the first storage unit.
  • each of the plurality of types of data stored in the first storage means is It preferably includes a processing procedure executed by the first processor. This makes it possible to cause different types of electronic devices to execute different types of processing according to the processing procedure read from the first storage means.
  • the determination means may include means for determining a type of the connected electronic device based on at least an address strobe signal output from the first processor. In this way, when the behavior of the address strobe signal differs depending on the type of the electronic device, the type of the electronic device can be determined.
  • the determination means may include means for determining the type of the connected electronic device based on at least a cook signal provided from the connected electronic device. In this way, when the behavior (frequency, etc.) of the clock signal differs depending on the type of the electronic device, the type of the electronic device can be determined.
  • the additional electronic device includes a printed circuit board on which at least the first storage means is mounted, has a housing for housing the printed circuit board, and is configured as a cartridge that can be handled alone. . Since this additional electronic device is configured as a cartridge that can be handled alone, its handling is extremely easy, and the usability is excellent.
  • the additional electronic device includes: a second processor that executes a process different from the first processor; and a second storage unit that stores processing steps executed by the second processor. Is preferred. According to this additional electronic device, the electronic device can be controlled by the second processor, and processing of information required by the electronic device can be realized. Therefore, new functions can be added to the electronic device, Changing or improving functions can be easily realized.
  • the electronic device is a printer that performs printing based on print data received from outside
  • the additional electronic device includes a print data input unit that inputs print data received from outside by the printer
  • the second storage means includes means for storing a processing procedure for causing the second processor to process the print data
  • the first storage means stores the processing procedure based on the data processed by the second processor.
  • the first processor further includes means for storing a print processing procedure for causing the first processor to execute the print processing. In this way, the print data processed by the additional electronic Since printing can be performed by the linter, the function of the printer can be improved by the additional electronic device.
  • the first storage means may be configured such that the electronic device reflects transfer data transferred from the electronic device to the additional control device side in an address signal, and the address signal is transmitted to the additional electronic device via the connector. It is preferable that the additional electronic device further includes a data extracting unit that extracts the transfer data from an address signal output from the electronic device. . With this configuration, even when a data bus for transmitting data from the electronic device to the additional electronic device is not provided, any data can be transmitted from the electronic device to the additional electronic device.
  • the present invention implemented as an electronic system includes: an electronic device having a first processor capable of performing a logical operation; and an additional electronic device that can be connected to the electronic device via a connector.
  • First storage means for storing a plurality of types of data applied to each of the types of electronic devices; and determining the type of the connected electronic device based on a signal given from the connected electronic device.
  • determining means for selecting at least one of the plurality of types of data stored in the first storage means and transmitting the selected data to the electronic device according to the determined type.
  • the determining means determines the type of the connected electronic device, and selects one of a plurality of types of data according to the determined type, and transmits it to the electronic device. Can be provided from the additional electronic device.
  • the present invention implemented as a model determination circuit includes a signal determination circuit that outputs a determination signal for determining a type of the connected electronic device based on a signal given from the connected electronic device; An address switching circuit that switches a level of at least one predetermined bit of an address given from the first processor based on the determination signal.
  • this model discriminating circuit the level of a predetermined bit of an address is switched based on a discriminating signal from the signal discriminating circuit.
  • the present invention performed as a model determination method includes: (a) a step of determining a type of the connected electronic device based on a signal given from the connected electronic device; (b) switching the level of at least one predetermined bit of an address given from the first processor based on the determination.
  • the level of a predetermined bit of the address is switched based on the determination of the model of the electronic device, so that the address can be converted to an address according to the model of the electronic device.
  • FIG. 1 is a block diagram showing a schematic configuration of a laser printer applied to the embodiment and a cartridge mounted on the laser printer.
  • FIG. 2 is a block diagram showing an internal configuration of a line buffer and a cartridge in the first embodiment.
  • Fig. 3 is an explanatory diagram showing the connection between the plug and the connector.
  • FIG. 4 is an explanatory diagram showing the address space of the CPU of the printer for each printer model.
  • FIG. 5 is an explanatory diagram showing data stored in the ROM of the cartridge.
  • FIG. 6 is an explanatory diagram showing the state of the memory area being skipped by the discrimination circuit.
  • FIG. 7 is a block diagram showing the internal configuration of the discrimination circuit.
  • FIG. 8 is a timing chart showing the difference between the behaviors of the two signals / A S B and / A S D b,
  • FIG. 9 is a timing chart showing the operation of the discrimination circuit.
  • FIG. 10 is a timing chart showing the operation of the discrimination circuit.
  • FIG. 11 is a block diagram showing a modification of the address inversion circuit.
  • Figure 12 is a block diagram of a circuit that determines the type of printer based on a clock signal.
  • FIG. 13 is an exploded perspective view showing the configuration of the cartridge 503 in the second embodiment
  • FIG. 14 is a plan view of the front and back of a print board on which a processor and the like are mounted
  • FIG. Explanatory drawing showing the cartridge map of the cartridge 503 viewed from the device 501 side.
  • FIG. 16 is an explanatory diagram showing an address map of the cartridge 503 viewed from the microprocessor 601 side, ll 7 is a block diagram showing the internal configuration of the cartridge 503,
  • FIG. 18 is a circuit diagram showing a configuration example of the interrupt request register 64.
  • FIG. 19 is a circuit diagram showing a configuration example of the polling / command register 643.
  • FIG. 20 is an explanatory diagram showing the contents of the status register 645.
  • FIG. 21 is a circuit diagram showing a configuration example of a read control circuit 62
  • FIG. 22 shows an electronic control unit 5 that realizes data transfer using the read control circuit 62.
  • FIG. 23 is an explanatory diagram showing the structure of data in the ROM 671
  • Fig. 24 shows a cartridge 5 that realizes data transfer using the read control circuit 62.
  • FIG. 25 is a flowchart showing a process on the electronic control unit 501 that realizes data transfer using the FIFO control circuit 623.
  • FIG. 26 is a flow chart showing the processing on the cartridge vpage 503 side for realizing data transfer using the FIFO control circuit 623.
  • FIG. 27 is a circuit diagram showing a configuration example of the double bank control circuit 624.
  • FIG. 28 is a flowchart showing a process for starting data transfer using the double bank control circuit 624.
  • FIG. 29 is a block diagram showing the response processing on the electronic control unit 501 similarly.
  • FIG. 30 is a flowchart showing processing on the electronic control unit 501 realizing data transfer using the double bank control circuit 624;
  • FIG. 31 is a flowchart showing processing on the cartridge 503 side for realizing data transfer using the double bank control circuit 624;
  • FIG. 32 is a timing chart showing the timing of printing of solid image data performed by controlling the laser engine 505. '
  • FIG. 1 is a block diagram showing a schematic configuration of a laser printer 500 applied to the embodiment and a card cartridge 50 mounted on the laser printer 500.
  • the laser printer 500 includes an electronic control unit 501 that controls the entire laser printer 500 and a laser engine 505 that forms an image on paper P.
  • the laser printer 500 is connected to the workstation 507 and has an electronic control unit.
  • the device 50 I develops image data (bit map data) based on the print data sent from the workstation 507, and feeds the developed image data to the laser engine 505 via the connector CN 10.
  • the laser engine 505 drives the xerographic unit 15 in response to this, and prints an image on the paper P.
  • a well-known CPU in this embodiment, MC 68000 manufactured by Motorola
  • a ROM 511 storing a program to be executed by the CPU 510
  • a print data and an image after development as shown in FIG. RAM 5 12 for storing data
  • data input port 514 for receiving print data from the workstation 507 as a host
  • line buffer 515 interposed in the bus line 516 for sending and receiving data to and from the cartridge 50
  • laser engine 505 Register 517 for exchanging commands and status information with the console
  • console panel I ZF 519 for interfacing with the console panel 518 of the laser printer 500
  • double buffer circuit 520 for storing image data to be transferred to the laser engine 505 , are provided.
  • the double-bap-up circuit 520 includes two RAMs 520A and 520B having a storage capacity of eight lines for printing by the laser engine 505, that is, 4K bytes. Write image data.
  • the laser engine 505 alternately reads the two RAMs 520A and 520B via the memory read controller 520D, thereby converting the image data into a video signal in synchronization with the rotation of the photosensitive drum and executing printing. can do.
  • the two RAMs 520A and 520B are provided to alternately write and read data because access from the CPU 510 and access from the laser engine 505 must be performed independently.
  • the CPU 510 After the CPU 510 damages the data in the RAM, the CPU 510 sets a flag in a predetermined bit of the register 517, and the laser engine 505 checks the flag to read the stored image data. During reading, another bit of the register 517 is set to notify the CPU 510 that reading is being performed. At this time, since the other RAM is not accessed from the laser engine 505, the CPU 510 completes the writing of the next eight lines of image data to the other RAM during this time. Laseren When reading from one RAM is completed, the gin 505 resets the flag and switches to reading from the other RAM. The speed at which data from the CPU 510 is damaged is faster than the speed at which data is read from the laser engine 505, that is, the speed at which printing is performed. Transfer of image data is reliably and easily realized.
  • FIG. 2 is a block diagram showing an internal configuration of the line buffer 515 and the cartridge 50.
  • the bus line 516 in the electronic control unit 501 is composed of an address bus 32 and a data bus 34, and the line buffer 515 has a bus driver 36 inserted in the middle of the data bus 34.
  • the bus driver 36 is a one-way buffer that transfers data only in the direction from the connector CN 11 to the CPU 510.
  • the cartridge 50 connected to the connector CN11 is a read-only device.
  • the cartridge 50 includes a plug section 52 connected to the connector CN 11, an address bus CAB and a data bus CDB connected to the plug section 52, a determination circuit 54, and a program executed by the CPU 510 of the electronic control unit 501. , A data buffer 58, and an auxiliary circuit 60 that outputs a clock signal and the like to the determination circuit 54.
  • the address bus C A B connected to the plug section 52 is connected to the ROM 56 via the determination circuit 54
  • the data bus CD B is connected to the ROM 56 via the data buffer 58.
  • the address put on the address bus 32 from the CPU 510 is sent to the ROM 56 via the address bus CAB of the cartridge 50 via the determination circuit 54 to the ROM 56.
  • Data read from ROM 56 according to this address is supplied to connector CN11 via data bus CDB, and further to CPU 510 via bus driver 36.
  • FIG. 3 is a diagram showing a connection relationship between the plug section 52 and the connector CN 11.
  • the plug portion 52 has 25 terminals formed on two surfaces (surfaces A and B) of the double-sided printed circuit board, respectively.
  • the signal corresponding to each terminal of Name is listed.
  • the symbol “ZJ” added before the signal name indicates that the signal is low active.
  • the meaning of each signal is as follows.
  • Signal ZASB Address strobe signal output by CPU510 (Motorola MC 68000).
  • This address strobe assist signal ZADS behaves differently for different types of printers when the printer is started (initialized). In this embodiment, as will be described later, the type of blinking is determined based on the behavior at the time of initialization of the address strobe auxiliary signal ZADS.
  • SIGNAL / OD TACK An artefact data acknowledgment signal for transferring data from the cartridge 50 to the electronic control unit 501 side.
  • Signal ZCTRGSEL Select signal when CPU510 reads data and instructions from ROM56.
  • Signals A1 to A20 Address signals output by CPU510.
  • Signal D 1 to D 15 Output signal from the cartridge 50 side.
  • Signal SCLK Clock signal output from an oscillator (not shown) built into laser printer 500.
  • the signal ZCTRGS given to the laser printer 500 is lowered to L level when the cartridge 50 is inserted, and the CPU 510 detects that the cartridge 50 is inserted into the connector CN 11 by this. .
  • the CPU 510 specifies a door address using the 23-bit address signals A1 to A23, and specifies an upper byte and a lower byte of each mode using signals / UDS and ZLDS. .
  • the CPU 510 can handle a 16 Mbyte address space from 00000 Oh to FFFF FFh.
  • the symbol "h" appended to the address indicates that the display is in hexadecimal.
  • the ROM 56 of the cartridge 50 is allocated to a part of an address space handled by the CPU 510 of the electronic control unit 501. The space allocated to the cartridge 50 often differs depending on the type of laser printer. FIG.
  • FIG. 4 is a diagram showing, for each model, a CPU 510 address space allocated to a ROM cartridge of a laser printer manufactured by Hered Packer.
  • a 2Mbyte space such as 200000h to 3FFFFFh or 40000 Oh to 5FFFFFh is allocated to the ROM cartridge.
  • R0M56 in the cartridge 50 in this embodiment is allocated to the first 128 Kbytes in the 2 Mbyte address space of the ROM cartridge, and the other addresses are allocated.
  • the I / O register is assigned to the space. “X” indicates the value of the four most significant bits of the address.
  • FIG. 5 is an explanatory diagram showing data stored in the ROM 56.
  • ROM56 is divided into two areas, 64K bytes from XOOOOOh to X0FFFFh contain data for type 1 printing, and 64K bytes from X10000h to XlFFFFh contain type 2 and type data.
  • 3Data for printer is stored. In this example, the same data is applied to the type 2 printer and the type 3 printer.
  • the discriminating circuit 54 discriminates the printer type based on a signal supplied from the laser printer 500, and is supplied from the CPU 510 when the printer is inserted into a type 1 printer. The address is supplied to ROM 56 as it is.
  • the discrimination circuit 54 When inserted into a type 2 or type 3 printer, the discrimination circuit 54 inverts the 16-bit address signal A 16 and supplies it to the ROM 56.
  • the address X output when the CPU 510 reads the first 64 Kbytes of data in the ROM 56 0000 Oh -XOFFFFh is given to the ROM 56 as it is in the cartridge 50 inserted in the type 1 printer, and the address X10000h to Xl FFFFh in the cartridge Vge 50 inserted in the type 2 or type 3 printer. Given to 56.
  • FIG. 6A is an explanatory diagram showing a manner in which two areas of the ROM 56 are exchanged (stepped) in the address space of the CPU 510 by the function of the determination circuit 54 described above.
  • the data for the type 1 printer is effectively assigned to addresses X0000 Oh to XOFFFFh
  • the data for the type 2 and type 3 printers is XI OOOOh ⁇ X1 Assigned to FFFFh.
  • data for the type 2 and type 3 printers is effectively assigned to the address X0000 Oh -XOFFFFh
  • the data for the type 1 printer is set to X. 1000 Oh ⁇ X 1 0 assigned to FFFFh
  • Fig. 6 (b) data for a type 1 printer is written-data (II) for a type 2 and type 3 printer is written after an evening.
  • the CPU 510 reads and uses the data for type 1 printer starting with [rPROG]. At this time, for example, data for a type 1 printer is read according to the address X0000 Oh -X0BF F Fh.
  • the CPU 510 starts the data for type 2 and type 3 printers starting with “SYST” ( In addition to reading and using I), it is also possible to read and use data (II), with the data (I) for type 2 and type 3 printers corresponding to addresses X00000h to X0FFFFh.
  • the data read (II) is read, for example, at addresses X1C00 Oh to X1FFFFh. Read out accordingly.
  • the character codes "PROG” and "SYST” are written in the first four bytes of the two 64-byte areas, respectively, when the laser printer 500 is turned on.
  • the CPU 510 sequentially specifies the addresses X0000 Oh-X00003h when the printer is initialized, thereby reading the first four bytes of the ROM 56.
  • the character code of "PRO G” is read, and when it is inserted in the type 2 or type 3 printer, the character code of "SYST" is read.
  • the CPU 510 determines that the ROM for storing the data for the type 1 printer is inserted at the time of “PR 0G”, and the ROM that stores the data for the type 2 or type 3 printer at the time of rSYST]. Is inserted If the printer type indicated by these character codes matches the user's type, the program jumps to the address in the ROM 56 specified by the program start address and is stored in the ROM 56. On the other hand, if the printer type indicated by the character code does not match the user's type, the CPU 510 executes the CPU 510 according to the program stored in the ROM 511 of the laser printer 500. Execute various processes.
  • FIG. 7 is a block diagram showing an internal configuration of the discrimination circuit 54.
  • the determination circuit 54 includes an address strobe signal ZASB, an address strobe auxiliary signal / ADS, a clock signal CLK, a reset signal ZRESET, and an address signal A 1 & (shown in the upper center in the figure). Has been given.
  • the clock signal CLK and The reset signal ZRESET is a signal given from the auxiliary circuit 60 (FIG. 2) in the cartridge 50.
  • the determination circuit 54 determines the type of the laser printer 500 based on the difference between the behaviors of the signals ZASB and ZASD, and outputs the address signal A 16 as it is to the ROM 56 in the case of the type 1 printer. On the other hand, in the case of a type 2 or type 3 blink, the address signal A 16 is inverted and applied to the ROM 56.
  • the discrimination circuit 54 includes two JK flip-flops JK1 and JK2 as main components, four D-type flip-flops FF1 to FF4, a synchronous 4-bit binary counter 70, and an address inversion circuit 72. Have. .
  • the two signals ZASB and ZADS are input to the 3-input NOR gate 80 together with the Q output of the D-type flip-flop FF4.
  • the output of the 3-input NOR gate 80 is given to the J input terminals of the two JK flip-flops JK1 and JK2, and inverted by the inverter 82 to the K input terminals of the two JK flip-flops JK1 and JK2, respectively.
  • the clock signal CLK is supplied to the clock input terminal of the first JK flip-flop JK1 and is inverted by the inverter 84 and input to the clock input terminal of the second JK flip-flop JK2. I have.
  • the Q outputs of the two JK flip-flops JK1 and JK2 are input to the OR gate 86, and the output of the OR gate 86 is applied to the clock input terminal of the D-type flip-flop FF1.
  • the D input terminal of the D-type flip-flop FF 1 is pulled up, and its Q output is supplied to the address inversion circuit 72.
  • an input terminal of the first AND gate 100 is supplied with an address signal A16 from the CPU 510 and an output of the D-type flip-flop FF1 inverted by the inverter 106.
  • the input terminal of the second AND gate 102 is supplied with an address signal A 16 ⁇ inverted by the inverter 104 and an output of the D-type flip-flop FF1.
  • the outputs of the two AND gates 100 and 102 are input to the OR gate 108, and the output of the OR gate 108 is supplied to the ROM 56 as a 16-bit address (FIG. 2).
  • the D input terminal of the second D-type flip-flop FF2 is inverted by the inverter 88.
  • the input signal ZASB is input, and the clock signal CLK is input to the clock input terminal.
  • the Q output of the D-type flip-flop FF 2 is supplied to the input terminal of an AND gate 90, and the other input terminal of the AND gate 90 is supplied with the clock signal CLK inverted by the inverter 92. .
  • the output of the AND gate 90 is given to the clock input terminal of the third D-type flip-flop FF3.
  • the D input terminal of the third D-type flip-flop FF3 is pulled up, and its Q output is input to the count enable terminal P of the counter 70.
  • the clock signal CLK is input to the clock input terminal of the counter 70, and the four data input terminals are grounded.
  • the output of the fourth bit of the counter 70 is supplied to the clock input terminal of the fourth D-type flip-flop FF4.
  • the D input terminal of this D-type flip-flop FF4 is pulled up.
  • the Q output of the D-type flip-flop FF4 is input to the OR gate 94 together with the reset signal ZRESET.
  • the output of the OR gate 94 is provided to the clear input terminal of the first D-type flip-flop FF1.
  • the Q output of the D-type flip-flop F F 4 is also supplied to the 3-input NOR gate 80 (upper left in the figure) as described above.
  • the reset signal / RESET is also input to the clear input terminals of the two JK flip-flops JK1 and JK2, the three D-type flip-flops FF2, FF3 and FF4, and the counter 70.
  • the reset signal ZRESET is a signal for resetting the six flip-flops in the discriminating circuit 54 and the counter 70 after a predetermined time (for example, 100 ms) after the power of the laser printer 500 is turned on, and going to the L level. is there.
  • a predetermined time for example, 100 ms
  • the discrimination circuit 54 is reset by the reset signal ZRESET, the Q output of the D-type flip-flop FF1 becomes L level, and the address inversion circuit 72 outputs an address corresponding to the type 1 printer. That is, the address A 16 given from the CPU 510 is output to the ROM 56 as it is.
  • the determination circuit 54 determines that the printer is a type 2 or type 3 printer based on the behavior of the signals ZASB and ZASD, the Q output of the D-type flip-flop FF1 goes high. At this time, the address A 16 is inverted by the address inversion circuit 72 and input to the ROM 56. In the address signals A1 to A20 transferred from the laser printer 500 to the cartridge 50, address signals other than the address A16 of the 16th bit are directly supplied to the ROM 56.
  • the discriminating circuit 54 discriminates the type of the laser printer 500 based on the difference in the behavior of the two signals / ASB and ZASD given from the CPU 510 of the laser printer 500.
  • FIG. 8 is a timing chart showing the behavior of the two signals / ASB and ZASD at the time of initialization after IS when the power of the laser printer 500 is turned on. As shown in FIG. 8 (a), in the type 1 printer, the signal / ASD is kept at the H level even when the signal / ASB level changes. On the other hand, as shown in FIG. 8B, in the type 2 and type 3 printers, the level of the signal ZASD also changes in accordance with the level change of the signal / ASB.
  • FIG. 9 is a timing chart showing the operation of the discrimination circuit 54 when the printer is initialized, and is a diagram showing an example in which the cartridge 50 is inserted into the type 1 printer.
  • FF 1 to 4 indicate the Q output of each 0-type flip-flop
  • Q70 indicates the output of the fourth bit of the counter 70.At time t10, when the signal / ASB falls, the following The output of the D-type flip-flop FF2 rises at the rise of the clock signal CLK, and the output of the D-type flip-flop FF3 rises at the next fall of the clock signal CLK (time t11).
  • the output of the D-type flip-flop FF 1 remains at the L level because the signal ZADS remains at the H level even when the signal / ASB level changes.
  • the output of the fourth bit of the counter 70 rises, and the output of the D-type flip-flop FF4 rises accordingly.
  • the output of the D-type flip-flop FF 4 is input to the 3-input NOR gate 80 together with the two signals / ASB and / ADS.
  • And ZADS both go low, the output of D-type flip-flop FF 1 goes low. (Time t13).
  • the address A16 input to the cartridge 50 from the laser printer 500 is given to the ROM 56 as it is.
  • FIG. 10 is a timing chart showing the operation of the discrimination circuit 54 when the cartridge 50 is inserted into a type 2 or type 3 printer.
  • the discrimination circuit 54 uses the fact that the behavior of the signals / ASB and / ADS differs between the type 1 printer and the type 2 and type 3 printers to determine the type of the printer. ing.
  • the Q output of the D-type flip-flop FF1 may be directly provided as the address of the 16th bit of the ROM 56 by omitting the address inversion circuit 72 in the determination circuit 54. In this way, in the case of a type 1 printer, the first 64K bits of data in the ROM 58 are always read, and in the case of type 2 and type 3 printers, the latter 64 K bits of data are always read.
  • the address inversion circuit 72 is provided to skip the memory area as in the above embodiment, there is an advantage that the memory area of the ROM 56 can be more effectively utilized as described above. . 'In the above embodiment, the memory area is divided into two, but generally, the memory area may be divided into a plurality.
  • the address inversion circuit 72a shown in FIG. 11 may be used instead of the address inversion circuit 72 in FIG.
  • the address inverting circuit 72a is a circuit that can be mounted as either a 1-Mbit (128K-byte) element or a 4-Mbit (512K-byte) element as the ROM 56.
  • the address inverting circuit 72a receives, in addition to the output of the D-type flip-flop FF1 and the addresses A16 and A18, the enable Z disable signal E / D, the model selection signal L2, and the element selection signal CHGMEM. ing. Each signal has the following functions.
  • Enable / Disable signal EZD A signal that specifies whether or not the address inversion circuit 72a is to be operated.
  • the address inverting circuit 72a functions only when the signal EZD is at the H level, and inverts the address A16 or A18 depending on the type of the printer. When the signal EZD is at the L level, the addresses A16 and A18 are directly supplied to the ROM 56.
  • Model selection signal L2 Selects the evening of the printer, and is valid only when the E / D signal is at the L level. Fix to L level when using a cartridge exclusively for Type 1 printers, and fix to H level when using cartridges exclusively for Type 2 and Type 3 printers. That is, when the signal L2 is at the L level, the addresses A16 and A18 are directly supplied to the ROM 56 irrespective of the levels of other signals, and when the signal L2 is at the H level, the addresses A16 and A16 are regardless of the levels of the other signals. A 18 is inverted and applied to ROM56.
  • Element selection signal CHGMEM A signal that indicates whether a 1-Mbit ROM or a 4-Mbit ROM is installed.
  • the signal CHGMEM is fixed to the H level using a jumper wire when mounting a 1 Mbit ROM, and is fixed to the L level when mounting a 4 Mbit ROM.
  • the address A16 is inverted according to the printer type
  • the signal CHGMEM is fixed at the L level
  • the address A18 is inverted according to the printer type.
  • a detailed description of the configuration of the address inversion circuit 72a is omitted.
  • the level of each of the signals EZD and L2 may be fixed inside the cartridge when the cartridge is manufactured, or the signal level may be switched by providing a dip switch or the like in the cartridge 50. Good.
  • the type of the blink was determined based on the difference in the behavior of the signals / ASB and ZADS.
  • the type of the printer can be determined based on some signal given from the printer. I just need. For example, when the frequency of the clock signal applied to the cartridge side differs depending on the type of the printer, the type of the printer can be determined based on the clock signal.
  • FIG. 12 is a block diagram showing two types of circuit configurations for determining the type of the printer based on the clock signal SCLK supplied from the printer to the cartridge.
  • the clock signal SCLK is input to the clock input terminal of the counter 140, and the output of the fourth bit of the counter 140 is applied to the D input terminal of the D-type flip-flop FF5. I have.
  • the clock signal SCLK is also input to the monostable multivibrator 142.
  • the output of the monostable multivibrator is kept at the L level for a certain period from the rising edge of the clock signal SCLK. Then, the output of the fourth bit of the counter 140 when the output of the monostable multivibrator 142 returns to the H level is latched by the D-type flip-prop FF5.
  • the output of the D-type flip-flop FF5 can be set to a level corresponding to the type of the printer. Then, if the output of the D-type flip-flop FF 5 is given to, for example, the clock input terminal of the D-type flip-flop FF 1 in FIG. 7, the address A 16 can be switched according to the type of the printer. . 'In the circuit of FIG. 12 (b), the clock signal SCLK is given to the fV converter 150, and the f / V converter 150 outputs a signal of a voltage level corresponding to the frequency of the clock signal SCLK.
  • the output of the f / V converter 150 is input to the comparator 152, and is compared with a predetermined level of the reference voltage Vref.
  • the reference voltage By keeping Vref to a particular printer type, the output of comparator 152 can be at a level that is IS dependent on the type of printer. If the output of the comparator 152 is given to, for example, the address inversion circuit 72 in FIG. 7, the address A16 can be switched according to the type of the printer.
  • the discrimination circuit 54 can have various configurations. Generally, the discrimination circuit 54 has a function of discriminating a different type of printer based on a signal given from the printer to the cartridge, and a function of selecting data used for jg for the discriminated type from the memory. Good.
  • the program for the CPU 510 is stored in the ROM 56 in the cartridge 50.
  • the ROM 56 may store other data such as font data.
  • a cartridge only needs to have a memory for storing a plurality of types of data applied to each of a plurality of types of printers.
  • the cartridge 503 of the second embodiment has a multilayer printed circuit board 550 (hereinafter simply referred to as “printing”) between a concave upper case 521 U and a plate-shaped lower case 521 L. ) Is inserted, and a cap 540 is fitted on the connector side of the printed circuit board 550.
  • a circuit element such as a microprocessor 601 described later is attached to the printed circuit board 550.
  • Both upper case 521U and lower case 521L are made of aluminum. Aluminum has high thermal conductivity, so it can efficiently transmit heat from the internal elements to the outside and emit it.
  • the lower case 521L has two pieces to secure the ground connection to the printer body.
  • the grounding spring members 5 2 2 are fixed with rivets 5 2 4 respectively, and the cylindrical pressing silicone rubber 5 2 6 which comes into contact with the printed circuit board 5 50 from below is the rubber on the inner surface of the lower case. It is fitted into the holding section 5 2 8.
  • the pressing silicone rubber 526 is provided at a position directly below the microprocessor 601. Between the upper surface of the microprocessor 601 and the inner surface of the upper case 521U, a sheet-like heat-dissipating silicone rubber 552 for improving adhesion and heat conductivity is interposed.
  • FIG. 14A is a plan view showing the upper surface side of the printed circuit board 550
  • FIG. 14B is a plan view showing the lower surface side of the printed circuit board 550.
  • a microprocessor 600 is attached to one end of the upper surface side of the printed circuit board 550, and a plurality of other ends for connecting to a connector of the printer body are provided at the other end.
  • An insertion plug section 551 is formed in which the electrodes are arranged in parallel.
  • ROMs 606 to 609 each storing a control program for the microprocessor 601 are arranged.
  • four tri-state buffers 617 are arranged in a square shape adjacent to the microphone processor 601.
  • R AM611-614 are arranged in parallel. Note that, for convenience of illustration, a wiring pattern formed on the surface of the printed board 550 is omitted.
  • the microprocessor 601 is a pin grid array (PGA) type device, and the others are SO J type, SOP type or QFP type devices.
  • PGA pin grid array
  • the microphone processor 601 for example, an Am29030 (clock frequency 25 MHz) manufactured by AMD, which is a RISC processor, is used.
  • a plug portion 551 is also formed at one end on the lower surface side of the printed circuit board 550.
  • the pin 601P of the microprocessor 601 is projected as it is.
  • On each side of the microprocessor 601, two tri-state buffers 619 are provided.
  • An ASIC (application-specific LSI) 603 including a control circuit and a register for the micro-sigma sensor 601 is arranged in the center of the printed circuit board 550 and slightly near the plug 551.
  • the configuration of the printer body (parameters related to the operation of the printer, such as the number of prints, the size of the printer, margins, fonts, and communication parameters) is recorded.
  • EEPROM670 is located. Further, adjacent to the EEPROM 670, an R0M618 storing a program for operating the microphone opening processor of the printer main body is arranged.
  • the first oscillator 661 is a circuit for transmitting a signal serving as a base of a clock signal for the microprocessor 601 and, for example, transmits a 50 MHz clock signal.
  • the second oscillator 665 is a circuit for transmitting a close signal used for an interval timer processing unit described later, and transmits a 5 MHz clock signal, for example.
  • a reset element 637, a FIFO memory 621, and a NAND gate 680 are arranged along the side edge of the printed circuit board 550.
  • Sa In addition, five tri-state buffers 684-688 are arranged in parallel with the plug section 551.
  • the longitudinal direction of the rectangular element is aligned with the insertion direction of the cartridge 3.
  • Such an arrangement facilitates the flow of air from the plug 551 toward the microprocessor 601 as indicated by the arrow, and contributes to the cooling of the microprocessor 601.
  • the cartridge 3 is inserted into the cartridge insertion slot for the printer in the printer body.
  • a normal font cartridge is just a ROM containing font data.
  • the cartridge 3 of this embodiment includes a microprocessor 601, ROMs 606 to 609 storing processing programs of the microprocessor 601, and a ROM 618 storing processing programs of a processor in the printer main body. And a control circuit including the AS IC 603.
  • the cartridge 503 is allocated to a part of an address space handled by the CPU 510 of the electronic control unit 501.
  • CPU510 can handle 16M bytes of address space from OOOOOOh to FFFF F Fh, and a part of it is allocated for ROM cartridges.
  • the space allocated to the cartridge 503 varies depending on the type of laser printer. Space is normal.
  • the microprocessor 601 provided inside the cartridge 503 of this embodiment is AMD29030-25MHz manufactured by AMD, and the address space that can be handled is 4 Gbytes from 0000000 Oh to FFFFFFFFh.
  • the address space not only ROM and RAM, but also various registers used for exchanging data with the electronic control unit 501 on the printer side are allocated. This Is shown in FIG.
  • the electrical configuration inside the cartridge 503 will be described together with the assignment of address spaces for both microprocessors.
  • Fig. 17 shows the internal configuration of the cartridge 503.
  • the cartridge 503 mainly includes a microprocessor 601 for controlling the entire system.
  • the cartridge 503 is mainly composed of a memory unit 602 including ROM, RAM and its peripheral circuits, and an electronic control unit 501. It comprises a data transfer control unit 603 that controls all the data exchange and other circuits.
  • the memory unit 602 receives a total of 2 Mbytes of ROMs 606 to 609 for storing a program to be executed by the microprocessor 601, a selector 610 for using the ROMs 606 to 609 for bank switching, and an electronic control unit 501. It consists of a total of 2 Mbytes of RAM 611 to 614, which store print data and image data after expansion.
  • the ROMs 606 and 607, and the ROMs 608 and 609 each constitute a bank, and a set of two banks constitutes a 32-bit data bus.
  • the ROMs 606 to 609 and the microprocessor 601 are connected by an address bus AAB and a control signal bus.
  • the data bus IDB of the ROMs 606 to 609 is connected to the data bus DB 29 via the data selector 610, through which the microprocessor 601 can read data from the ROMs 606 to 609.
  • R0M606 and 607 and R0M608 and 609 receive all address signals except the least significant three bits (AO, A1, ⁇ 2) 'of the address bus AAB from the microprocessor 601.
  • the address A2 since the address A2 is not assigned, when reading data in a predetermined area, four RQM 606 through 609 will output data at the same time.
  • the data selector 610 adjusts the data output at the same time.
  • a 2 Mbyte memory can be further installed.
  • an extended RAM interface 615 is provided.
  • This extended RAM interface 615 is allocated from 2020000 Oh to 203FFFFFFh in the address space.
  • the extended RAM interface 615 can accommodate up to 2 Mbytes of RAM of the SIMM type.
  • the extended RAM need not be limited to the SIMM type, but may be provided in the form of a memory card with a built-in semiconductor memory or in the form of a laser card that stores data by the magneto-optical effect.
  • the data lines of the RAMs 61 1 to 614 and the extended RAM interface 615 are directly connected to the data bus DB 29 of the microprocessor 601, and the address lines of the data buses of the microprocessor 601 are transmitted via the data transfer control unit 603.
  • Adress bus is married to AAB.
  • I / O of various registers and the like described later are allocated from 8000000 Oh in the address space.
  • a ROM is allocated to the first 128K bytes as shown in the right column of FIG. That is, the cartridge 503 also has a built-in program executed by the PU 510 of the electronic control unit 501.
  • the CPU 510 of the electronic control unit 501 has an initial setting when the cartridge 503 is mounted. After completion of the conversion process, a jump instruction to a predetermined address of the ROM is executed. After that, CPU5 10 operates in accordance with the processing procedure longed for in the ROM.
  • the CPU 510 accesses the space of 128 Kbytes from the beginning of the space of 2 Mbytes allocated to the cartridge 503, it is output via the address buffer 617 provided in the connector-side address bus CAB of the cartridge 503.
  • the ROM 618 is accessed by the address signal, and instructions and data stored in the ROM 618 are sent to the CPU 510 of the electronic control device 501 via the data buffer 619 provided on the data bus CDB of the connector.
  • the address signal is supplied to the discriminating circuit 680 before being supplied to the ROM 618, and the address signal corrected according to the type of the blinking signal is supplied from the discriminating circuit 680 to the ROM 618.
  • the discriminating circuit 680 is a circuit having the same function as the discriminating circuit 54 in the first embodiment, and the details are omitted here.
  • addresses other than those to which ROM and RAM are assigned contain various control registers and status registers. Since these registers are realized by the data transfer control unit 603, the data transfer control unit 603 will be described next. Although the explanation of the circuit is the main, refer to the address map (Figs. 15 and 16) as appropriate.
  • the data transfer control unit 603 shown in FIG. 17 is realized by the ASIC of the usable gate 7900. This ASIC is a standard cell of model number SSC 3630, manufactured by Seiko Epson, and is a small power-dissipating device made by a CMOS process.
  • the data transfer control unit 603 was designed using the CAD system “ASDS design system“ LADSNET ”manufactured by Seiko Epson Corporation. This CAD system prepares elements such as latches, flip-flops, counters, and programmable logic arrays used in the design of logic circuits in the form of a library. After designing the necessary logic circuits using these, the AS IC The pattern as can be automatically generated.
  • the data transfer control unit 603 implemented as an AS IC operates with the cartridge 503 attached to the connector CN11 of the printer 500, It controls data exchange between the CPU 510 of the control device 501 and the microprocessor 601 of the cartridge 503. Data exchange between the two is performed by a read control circuit 620 for transmitting data from the electronic control device 501 to the cartridge 503 via a read-only data bus, and a part of the read control circuit 620.
  • a FI FO control circuit 623 that transfers data via the FI FO memory 621 using a FO, and a double bank control circuit 624 that allows the data prepared by the cartridge 503 to be read from the electronic control unit 501 side.
  • the FIFO memory 621 is a RAM that stores and reads out data in a first-in-first-out procedure. In this embodiment, M66252 FP manufactured by Mitsubishi Electric Corporation was used.
  • the data transfer control unit 603 has a signal line with the electronic control unit 501 side.
  • the address bus CAB is connected to the electronic control unit 501 via the address buffer 617
  • the data bus CDB is connected to the electronic control unit 501 via the data buffer 619.
  • the data transfer control unit 603 includes a first decoder 631 that receives the address bus CAB signal and the cartridge select signal CSEL and outputs a selection signal to each unit in the data transfer control unit 603. I have.
  • an address bus AAB and a control signal CCC from the microprocessor 601 are also connected to the data transfer control unit 603.
  • the data transfer control unit 603 receives the address bus AAB, and receives signals from the internal circuits.
  • a second decoder 632 that outputs a selection signal to the second decoder is configured. Further, a bus controller 635 that receives the address bus AAB and the control signal CCC and outputs an address signal and a control signal to the ROMs 606 to 609, the RAMs 611 to 614, and the extended RAM interface 615 is also configured.
  • various registers are configured in the data transfer control unit 603. Reading and writing to the registers are performed not only by a normal read / write operation but also automatically when a specific process is performed. There are not a few things that are written to. The configuration of these special registers will be described later.
  • a register that can be written from the electronic control device 501 performs a read operation from a predetermined address. It is configured to be hurt by doing so. That is, by specifying a predetermined address, a selection signal is output from the first decoder 631, and data is written to the register by this signal. Reading from the register is performed by a normal read cycle.
  • registers are drawn with a read on the readable bus, and the write operations are indicated by simple arrows.
  • Such registers include an interrupt request register 640, a polling and command register 643, a status register (register STATUS) 645 in FIG. 15, a transfer flag register (register BPOLL) 647 in FIG. 16, a PROM control register 649, and a control register 650.
  • registers other than the status register 645 and the transfer flag register 647 are the registers of a plurality of registers assigned as memory-mapped I / O to the CPU 510 of the electronic control unit 501 or the microprocessor 601 of the cartridge 503. It is a generic term. Multiple registers are not necessarily assigned to contiguous addresses.
  • the registers AMDINT0,1,2 and the registers AMDCLR0,1,2 shown in FIGS. 15 and 16 belong to the interrupt request register 640.
  • the polling command register 643 includes a register P COL and a register MCONTCS.
  • the registers EEPCS, EEPSK, and EEPDI belong to the PROM control register 649.
  • the control register 650 is a register that does not belong to the read control circuit 620, the FIFO control circuit 623, and the double bank control circuit 624, and all registers not mentioned in the above description belong to the control register 650. These are the registers ADDMUXA, ADDMUXB, CLKD IV, RTCVAL, RTCON, RTCSEL, RTCCLR, and SYSKEEP shown in FIGS.
  • each of the areas EWWRL and EWWRH of 512 bytes is written from the electronic control unit 501 to the first and second latches 651 and 652 of the read control circuit 620.
  • the register EWR D is equivalent to the register 651, 652 as one word when viewed from the microprocessor 601 side.
  • the registers FI RCLK, RDCLK, FI FORD, and RD RST correspond to the FIF 0 read register 655 of the FIF 0 control circuit 623.
  • the FIFO control circuit 623 is also provided with a latch 657 for holding data to be written to the FIFO memory 621 by using a part of the function of the read control circuit 620.
  • the areas indicated by the symbols DPRAMA and DPR AMB in FIG. 15 are buffers having a capacity of 32 bytes, and the first and second buffers 658 and 659 of the double bank control circuit 624 are viewed from the electronic control device 501 side. Equivalent to Banks DPWROA and DPWROB shown in FIG. 16 show these buffers 658 and 659 from the microprocessor 601 side.
  • the predetermined bits d 1 and d 2 of the status register 645 are also used for data exchange via the double bank control circuit 624, the details of which will be described later.
  • the interrupt request register 640 is a register that generates an interrupt request from the electronic control unit 501 to the microprocessor 601 and holds the interrupt request. Three levels of interrupts from the electronic control unit 501 to the microprocessor 601 are provided, and three registers (AMD ITO, 1, 2) are provided as shown in FIG. By reading any of the interrupt request registers 640 from the electronic control unit 501, an interrupt request to the microprocessor 601 is generated. The setting of this register is performed by a read operation from the electronic control unit 501. However, the read data has no meaning and is not related to the generation of the interrupt request.
  • FIG. 18 shows a specific configuration example of the interrupt request register 640.
  • These registers are composed of D-type flip-flops.
  • the output terminals Q of a, b, and c are set to active low, and interrupt signals / INTO, 1, 2 are output.
  • the sign “/” added before the signal indicates that the signal is active (the same applies hereinafter).
  • the read registers are assigned to predetermined addresses as three read-only registers (AMD CLRO, 1, 2). Therefore, when the microprocessor 601 performs a read operation for each address to which this register is assigned, the second decoder 632 outputs the signals / INTCLR0, 1, 2 respectively, and the corresponding flip-flops are reset. Is
  • the microprocessor 601 determines the priority order and performs processing to respond to the interrupt request. Do. In this case, the microprocessor 601 clears the corresponding interrupt request register 640a, b, c.
  • a signal starting with the symbol rPUPJ such as the signal PUP2 is a signal output from the reset signal output circuit 637, and is a signal that goes low at the time of reset or the like.
  • Signal PUP 2 shown in FIG. 18 is a signal for clearing three interrupt requests at once.
  • the polling command register 643 is a register that transfers a command from the microprocessor 601 to the electronic control device 501, and is a register that can be written from the microprocessor 601 and readable from the electronic control device 501.
  • FIG. 19 shows an example of the configuration of this register on hardware.
  • the polling command register 643 is composed of two octal D-type flip ports, knobs 643a and b, and one D-type flip flop 643c, which constitute a 16-bit width data latch. Can be.
  • the data bus DB 29 (16-bit bus width) from the microprocessor 601 is connected to the data input terminals 1D to 8D of the octal D-type flip-flop, y-643a and b, and the output terminal thereof. 1Q to 8Q are connected to the data bus DB 68 (bus width 16 bits) from the electronic control unit 501 side.
  • the clock terminal CK of the Otaru D-type flip-flops 643 a and b has a signal ZMC ONTCS output from the second decoder 632 when the microprocessor 601 accesses the polling command register 643 ( Figure 16, register MCONTCS).
  • the signal ZMCONTC S and the signal / POLL are connected to the D-type flip-flop port, the clock terminal C and the bliss and the y-terminal PR of the Sop 643c, and the signal CMDRD from the output terminal Q is octal.
  • the signal is set to a high level.
  • this data is read from the electronic control unit 501 (signal / POLL is low). , Is reset to low level.
  • the CMDRD which is the output signal of the D-type flip-flop 643c, is a predetermined bit d3 (hereinafter, also referred to as a flag CMDRD) of the status register 645 that can be read from the electronic control unit 501 side. Therefore, by reading the status register 645 from the electronic control device 501, the electronic control device 501 can know that a command has been set to the polling / command register 643 from the microprocessor 601.
  • the electronic control unit 501 When the electronic control unit 501 sees the flag CMDRD, which is bit d3 of the status register 645, and knows that the command has been set, it polls by a normal read cycle. Read the command sent from 601. The contents of the command include an instruction to start the transfer of print data to the data transfer control unit 603, an instruction to start a mark, and a display of a message on the console panel 518.
  • the electronic control unit 501 reads the contents of the bowling command register 643, as shown in FIG. 19, the output signal CMDRD of the D-type flip-flop 643c is inverted to a high level by the signal / POLL. I do.
  • the microprocessor 601 can know whether or not the command output by itself is read by the electronic control device 501 by monitoring the predetermined bit d2 of the transfer flag register 647.
  • the status register 645 holds the information shown in FIG. 20 in addition to the above-mentioned information indicating whether or not a command has been set from the microprocessor 601. The contents of each bit will be described.
  • the bit dO is set to a low level by a signal EWRDY generated in the read control circuit 620 when data is written from the electronic control device 501 to a read control circuit 620 described later, and the data is stored in the read control circuit 620.
  • EWRDY generated in the read control circuit 620
  • Bits d1 and d2 indicate whether the double bank control # 1 circuit 624 is accessible from the electronic control unit 501 or the microprocessor 601 side, and are called flags ADDMUXA and ADDMUXB, respectively.
  • the two bits correspond to each of the two transfer banks included in the double bank control circuit 624.
  • These bits d1 and d2 are set and reset by the microprocessor 601 writing data to bit d0 of the registers ADDMUXA and ADDMUXAB included in the control register 650, as shown in FIG. It is. Therefore, the microprocessor 601 sets this flag to low level before writing data to one bank of the double bank control circuit 624, resets this flag to high level after writing is completed, and sets the electronic control unit.
  • Bit d3 (flag CMDRD) has already been described.
  • Bit d5 is a flag CLK DIV that is set based on the operation clock of the microprocessor 601.
  • the clock CLK output from the first oscillator 661 using the external crystal oscillator CRC 1 is used as the operating clock of the microprocessor 601, but the microprocessor 601 uses the control register 650 register CLKD IV
  • the operation clock CLK of the microprocessor 601 becomes 25 MHz
  • the operation clock becomes 12.5 MHz.
  • the flag CLKD IV of the register 645 is set to low level when the clock CLK is 25 MHz, and is set to high level when the clock CLK is 12.5 M.
  • the electronic control unit 501 checks this bit of the status register 645 when it is necessary to know the operation clock frequency, that is, the operation speed of the microphone processor 601 in order to adjust the timing of data transfer and the like.
  • Bit d6 is a flag ADMON that is set to a high level when the microprocessor 601 is operating and is set to a low level when the sleeve mode is entered.
  • the microprocessor 601 receives the page description language from the electronic control unit 501 and performs processing for expanding the page description language into image data. Therefore, the page description language to be processed is transmitted from the electronic control unit 501 side. If the predetermined time has elapsed without being received, the microprocessor 601 first sets the operating frequency to 1Z2, that is, 12.5 MHz, in order to save power. Enter mode. At this time, the microprocessor 601 writes the value 0 to the register ADMON of the control register 650. As a result, when viewed from the electronic control unit 501 side, this bit d6 of the status register 645 becomes low level, and by checking this bit from the electronic control unit 501 side, the operation mode of the microprocessor 601 can be known. is there.
  • a real-time clock incorporated in the data transfer control unit 603 is used for such time measurement and the like.
  • the clock RCLK for the real-time clock a clock from a second oscillator 667 configured using an external crystal oscillator 665 is used.
  • the real-time clock is configured in the bus control unit 635, and measures an elapse of a predetermined time in response to an instruction from the microprocessor 601.
  • the two sets of crystal oscillators and oscillators are provided so that the operation clock CLK of the microprocessor 601 can be changed independently of the operation clock RCLK of the real-time clock.
  • the real-time clock can specify four types of interval timers by setting the dl bit of the registers RT CVAL and RTCSEL belonging to the control register 650 to low or high, and the predetermined bit d of the register RT CON can be specified.
  • the timer can be started by writing a value of 1 to 0.
  • the started timer outputs an interrupt request signal to the microprocessor 601 at a predetermined interval until the timer is stopped because the value d0 of the register RTCON is damaged.
  • the microprocessor 601 Upon receiving this interrupt request signal, the microprocessor 601 reads the register RTCCLR and clears the interrupt request. The output of these interval timers is used for counting user time in page description language processing.
  • the PROM control register 649 includes the three registers EEPCS, EEPSK, and EPDDI shown in FIG. 16, and these registers are memories built in the cartridge 503 and electrically erase data. Used to exchange data with the rewritable EE PROM 670.
  • the cartridge 503 of this embodiment stores various variables (configuration) necessary for the operation of the laser printer 500 in the EEPROM 670.
  • This EEPR OM670 is of a type in which data is read, erased, and written by serial transfer.
  • NMC93C66X3 manufactured by National Semiconductor is used.
  • This 10 ⁇ 1670 has a capacity of 16 bits ⁇ 256 bytes (the number of registers) as a storage capacity, and can read, erase, and write the contents of any specified register.
  • the EEPROM 670 is selected by the chip select signal CS, the data of “0” and “1” sent to the serial data input terminal Din is captured in synchronization with the serial data clock SL.
  • bits are interpreted as an instruction to the EEPROM, and the next eight bits are interpreted as the register number where the data is read, erased or written.
  • data to be stored is supplied to the data input terminal Din in synchronization with the serial data clock SL in accordance with these instructions and register specification.
  • the register EEPCS switches the chip select signal.
  • the microprocessor 601 writes the value 1 to bit d0 of this register, the EEPROM 670 is in the selected state.
  • Register EEPSK is the serial data clock
  • the microprocessor 601 generates a serial data clock for the EEPROM 670 by alternately writing a value 0 and a value 1 to this register.
  • the register EEPD I is a register for holding 1-bit data to be written to the EEPROM 670.
  • the microprocessor 601 rewrites the register EEPSK to synchronize with the generation of the serial data clock SK. Then, the predetermined bit d0 of the register EEPDI is rewritten according to the data to be written.
  • the data output terminal D out of the EE PROM 670 is the predetermined bit d 0 of the transfer flag register 647 described above, and the microprocessor 601 outputs the data read command and the register number to be read to the EE PR0M670. Thereafter, by reading bit d0 of transfer flag register 647 in synchronization with serial data clock SK, the contents of the specified register can be read.
  • Ki ⁇ the EE PROM 670 since also stored as power off, immediately after turning on the power to the laser printer 500, reads out the contents of EEPROM670, the configurator Igureshi s down the power-off state immediately before Can be returned to.
  • the read control circuit 620 outputs data necessary for transfer, as well as the 8-bit X2 first and second latches 651 and 652, the R0M671, 3-input AND gate 672, and the status register 645. It has a D-type flip-prop 674 that generates the same flag EWRDY (bit d0).
  • the latches 651 and 652 correspond to two registers EWWRL and EWWRH that transfer data in 8-bit units as shown in FIG.
  • the first and second latches 651 and 652 correspond to the register EWRD shown in FIG. 16 when viewed from the microprocessor 601 side. That is, both latches 651 and 652 can be read as one word from the microprocessor 601 via the data bus DB290.
  • the ROM 671 of the read control circuit 620 is a ROM that stores 256 bytes of data, and can be realized by, for example, a fuse ROM, a small-capacity PROM, or the like. Of course, it may be realized as a part of ROM with a large storage capacity. When using RAM, the same function can be realized by transferring data in advance.
  • the lower eight bits (AC1 to AC8) of the address line from the connector-side address bus CAB are connected to the address terminals AO to A7 of the ROM 671, and the data terminals 00 to 07 are connected to the first terminals.
  • the output of R0M671 is also output to FI F0 control circuit 623 as data buses Z0 to Z7 for FI F0 control circuit 623.
  • the output sides of the first latch 651 and the second latch 652 are connected to the data bus DB 29 and can be read from the microprocessor 601 as a register EWRD.
  • the output signal / EWROM of the 3-input AND gate 672 is input to the chip select CE and the art bit enable 0E of the R0M671, and the signal / EWWRH, / FIFO WR, When any of ZEWWRL becomes active low, it becomes active. At this time, R0M671 outputs the data of the address specified by the lower 8 bits of the connector-side address bus CAB.
  • the signal / EWWRH is a signal that goes low when the transfer of the upper byte by the read control circuit 620 is specified
  • the signal / EWWRL is a signal that goes low when the transfer of the byte is specified
  • the signal / FI FOWR is a signal that goes low when the data transfer by the FI FO control circuit 623 is specified. Since the signal ZEWWRL and the signal / EWWRH are input to the clock terminal CK of the first lapuchi 651 and the second latch 652, respectively, when these signals become active and data is output from the ROM 671, The data is held in a first latch 651 and a second latch 652.
  • the microprocessor 601 performs a read operation on the register EWRD.
  • the signal ZEWR D becomes low active, and this signal is first supplied to the output side of the first latch 651 and the second latch 652 connected to the art-bubble enable terminal, that is, to the data bus DB 29 first.
  • the retained data is output. Since this signal / EWRD is connected to the preset terminal PR of the D-type flip-flop 674, the data of the first latch 651 and the second latch 652 are read from the microprocessor 601 side at the same time.
  • the signal EWRD Y which is the Q output of the D flip-flop 674 is inverted to a high level. That is, the flag dWR of the status register 645 and the flag EWRDY which is the bit d1 of the transfer flag register 647 are set to a value of 1.
  • the electronic control unit 501 and the microprocessor 601 transfer data from the electronic control unit 501 to the microprocessor 601 in the following procedure.
  • Data transferred from the electronic control device 501 to the microprocessor 601 side a print data the electronic control device 501 has received from the workstation shea a down 5 07, with microprocessor Se Uz support 601 of the cartridges 503 side, It is a page description language program to be processed.
  • the data transfer by the read control circuit 620 is performed by a data transfer processing routine to the cartridge (FIG. 22) executed by the CPU 510 of the electronic control unit 501 and data read by the microprocessor 601 of the cartridge 503 side. This is performed by the interrupt processing routine (Fig. 24).
  • the CPU 510 starts the process shown in the flowchart of FIG. 22 and first performs the process of reading the flag EWRDY (bit dO) of the status register 645. (Step S700).
  • the flag EWRDY is set to the first latch 651 and the second latch 651 of the read control circuit 620.
  • the value becomes 0, and when the data is read by the microprocessor 601, the value is set to 1; therefore, it is determined whether the flag EW RDY is the value 1 or not. A determination is made (step S705).
  • the process waits until the flag EWRDY becomes the value 1, and when the value becomes 1, the process of reading the address of (the start address of the area EWWRH + the data DX2 to be transferred) is performed (step S710).
  • read processing is performed on the area EWWRH, data is read from the ROM 671.
  • 256 data from 0 Oh to FFh are sequentially written into the ROM 671 at a private address from the first address EWWRH.
  • the reason why data is not placed at odd addresses is that data access by the CPU 510 is basically performed in one word (16 bits), and access in code units starting from odd addresses is not possible (causes an address bus error). It is.
  • read processing is performed for an address separated by DX2 from the head of the area EWWRH, data D is read from the ROM 671, and this is latched by the second latch 652 as shown in FIG.
  • Step S720 When the upper byte of the data to be transferred is transferred (the second latch 652 holds the data), the CPU 510 similarly transfers the lower byte (the first latch 651 holds the data) (Step S715). As a result of the above processing, assuming that the data for one mode has been held in the first and second ruptures 651 and 652, the CPU 510 sets one of the interrupt request registers (in this embodiment, AMDINT0). (Step S720).
  • CPU 510 continues to execute the transfer processing routine shown in FIG. 22 in a loop, but when data is held by first latch 651, flag EWRDY is set to low level as shown in FIG. Therefore, the next data transfer processing is not performed until this flag EWR DY becomes high level (value 1) (steps S700, 705). '
  • the microphone processor 601 accepts this interrupt request and starts the data read interrupt processing routine shown in FIG. This process is started immediately after data is held in the first and second latches 651 and 652 of the read control circuit 620.
  • the microprocessor 601 reads 1-word data prepared by the electronic control unit 501 (step S730). Thereafter, the microprocessor 601 transfers the read data to a predetermined area of the RAMs 611 to 614 (step S735).
  • the electronic control device 501 can transfer data to the cartridge 503 which is merely connected to the data bus CDB which is a read-only line.
  • the microprocessor 601 can efficiently take in data. Note that here, the case of transferring one word of data has been described as an example; the data transfer does not need to be performed in word units, but may be performed in byte units. In that case, only the transfer using the area EWWRL side is performed, and the upper-order 8-bit data may be discarded on the microphone processor 601 side.
  • the FI FO control circuit 623 includes a latch 657 for latching data to be written to the FI FO memory 621, a FI F0 write register 653 for controlling writing of data to the FI FO memory 621, and a FI FO read register for controlling reading similarly. It has 655.
  • the FIFO memory 621 can store 2048 bytes of data, and internally has a write address counter and a read counter.
  • the FI F0 memory 621 has a reset terminal for writing, a reset terminal for reading, an 8-bit data bus for writing, and an 8-bit data bus for reading, which reset these counters, respectively.
  • a clock terminal for writing and a clock terminal for reading are provided.
  • the CPU 510 of the electronic control device 501 can use the FIFO control circuit 623 to transfer data to the microprocessor 601.
  • Data transfer using the read control circuit 620 is performed on a byte-by-byte basis, and an interrupt request signal is issued to the microprocessor 601 every time data is transferred on a byte-by-byte basis to notify the microprocessor 601 of this.
  • Data transfer using the FO control circuit 623 using the function of the FI FO memory 621, collects multiple bytes. Can be done.
  • the CPU 510 of the electronic control unit 501 executes the transfer processing routine shown in FIG. 25, and the microprocessor 601 of the cartridge 503 executes the processing routine shown in FIG. Are executed respectively.
  • the processing routine shown in the flowchart of FIG. 25 will be described.
  • step S765 a process of reading the register FIFOREQ of the FIFO control circuit 623 and transferring the data D held in the burner 657 to the FIFO memory 621 is performed (step S765).
  • a write clock is output to the clock terminal on the write side of the FI FO memory 621, and the data D held in the latch 657 is stored at the address indicated by the address counter on the write side of the FI FO memory 621.
  • the contents of the write-side address counter in the FIFO memory 621 are incremented by one.
  • step S770 When one byte of data is written, the variable N indicating the number of transferred data is incremented by 1 (step S770), and whether or not the variable N has become equal to the total number of bytes X of the data to be transferred is determined. (Step S775). Therefore, the processing of the above-described steps S760 to S775 is repeated until the number N of bytes of the tilled data matches the total number X of data.
  • the CPU 510 sets one of the interrupt request registers (AMDINT1) and notifies the microprocessor that the data transfer has been completed. Notify the 601 side (step S780), exit to "NEXT", and end this processing routine.
  • AMDINT1 interrupt request registers
  • the microprocessor 601 receives this interrupt request AMDINT1, and activates a data reception interrupt routine shown in the flowchart of FIG.
  • the microprocessor 601 first reads the register RDRST belonging to the FIFO read register 655 of the FI F0 control circuit 623, and performs processing to reset the address counter on the read side of the FIFO memory 621 (step S800). Then, a process of setting a value 0 to a variable M for counting the number of received data is performed (step S805).
  • step S810 a process of reading the register FIRCLK belonging to the FIF0 read register 655 is performed (step S810), and a process of transferring the read data to a predetermined area of the RAMs 611 to 614 is performed (step S815).
  • a read clock is output to the clock terminal on the read side of the FIFO memory 621, and the data D at the address indicated by the read-side address counter at that time is read.
  • the content of the read address counter in the FIFO memory 621 is incremented by one.
  • the data transferred via the FI F0 control circuit 623 is a program in a page description language, so the received data is immediately transferred to a predetermined area of the RAM to prepare for the development of image data. It is done.
  • step S820 When one byte of data is received, the variable M is incremented by 1 (step S820), and it is determined whether or not this variable M is equal to the total number of bytes X (step S825). Therefore, the processes in steps S810 to S825 described above are repeated until the number of bytes M of the received data matches the total number X of data.
  • the microprocessor 601 When it is determined that the reception of all data has been completed, the microprocessor 601 performs a process of writing a command indicating the completion of data reading into the polling command register 643 (step S630). By reading the contents of the polling / command register 643, the CPU 510 of the electronic control device 501 can know the completion of data reception by the FI F0 control circuit 623.
  • the microphone processor 601 exits to the RNTJ and ends the processing routine.
  • the transferred data is stored in a predetermined area of the RAMs 61 1 to 61 4 of the data transfer control unit 603, and waits for processing by the microprocessor 61.
  • the microprocessor 601 receives all print data (program written in a page description language) to be developed from the electronic control unit 501, the microprocessor 601 stores the page description stored in the ROM 606 to 609. Activate the language interpreter and process the print data stored in a predetermined area of the RAM 611 to 614.
  • the image is developed by such processing, and the developed result is stored as image data in a predetermined area of the RAMs 611 to 614.
  • the image data obtained by completing the image development is then transferred to the electronic control unit 501, stored in the RAM 512, and printed by the laser engine 505 at a predetermined timing. Will be.
  • the double bank control circuit 624 transfers such image data.
  • the double-bank control circuit 624 transfers the data from the micro-processor 601 to the electronic control unit 501, and has a bank for storing 32 bytes (16 words) of data. There are two sets, which are called A bank and B bank, but since the rain is completely the same as hardware, only the configuration example on bank A is shown in Fig. 27.
  • Each puncture has a configuration in which the address and data buses can be switched between the microprocessor 61 side and the electronic control unit 501 side, and an address line is selected as shown in the figure.
  • Data selector 6 8 1, 6 8 2, 2 Used to select a data bus (16 bit width) 2 sets Total 4 octal drivers.
  • Sofa 6 8 4 to 6 8 7, 3 2 It is composed of RAMs 691 and 692, each of which has a storage capacity of bytes, OR gates 694, 695, which are other constituent gates, and Imba 6966.
  • FIG. 27 a configuration is used in which two memory chips each having a storage capacity of 32 bytes are used. However, it can be realized by switching the upper address of a single memory chip.
  • the data selector 681 is located at the bottom of the address bus CB on the electronic control unit 501 side. 4 bits (AC 1 to AC4) and the lower 4 bits (A2 to A5) of the address bus AAB of the microprocessor 601 are selected and output. Is performed by the signal ADDMU XA (bit dO of register ADD MUX A) connected to the select terminal S.
  • the data selector 682 switches the read / write signals of the RAMs 691 and 692 in accordance with the selection of the address bus. Similarly, one of the signals is connected to the signal 69 or 692 by the signal ADDMUXA connected to the select terminal S. Is connected to the chip select terminals CE 1 and 2 and the output enable terminal OE.
  • Octal line buffer 684, 685 is a 3-state type line buffer with data bus DB 29 interposed.When the gate terminals 1G, 2G are at the mouth level, the data bus on the microprocessor 601 side Connect DB 29 to the data bus of RAM 691, 692, and enable the microprocessor 601 to write data to RAM 691, 692.
  • the gate terminals 1G and 2G of the Otaru line buffers 684 and 685 are connected to the output of the OR gate 694 that receives the signal / DPWR0A and the signal ADDM UX A.
  • the signal ZDPW R0A is a signal that goes low when the microprocessor 601 attempts to write data to bank A.
  • the octal line buffers 686 and 687 connect the data bus DB68 of the electronic control unit 501 to the data buses of the RAMs 691 and 692 when the gate terminals 1G and 2G become low level. Data can be read from the electronic control unit 501.
  • the gate terminals 1 G and 2 G of the octal line buffers 686 and 687 receive the output of the OR gate 695 that inputs the signal ZDPOE 1 A and the signal obtained by inverting the signal ADDMUX A with the inverter 696. It is connected.
  • the signal ZDPOE 1 A is a signal that goes to a low level when the electronic control unit 501 attempts to read data from the A bank.
  • FIG. 28 is a flowchart showing a processing routine for starting transfer of image data performed by the microprocessor 601. As shown, the microprocessor 601 sets a transfer start command in the polling command register 643 prior to the transfer of image data (step S850).
  • the CPU 510 of the electronic control unit 501 reads the command of the polling / command register 643 and executes a response processing routine shown in FIG. That is, the electronic control unit 501 determines whether the laser printer 500 is in a printable state (step S60). If the electronic control unit 501 determines that the laser printer 500 is in a printable state, the electronic control unit 501 checks the interrupt request register. (AMD INT 2) is set (step S865), and "NEXTJ is exited once.
  • AMD INT 2 is set (step S865), and "NEXTJ is exited once.
  • step S870 The state in which printing is not possible means that printing cannot be performed even when image data is transferred, for example, a state in which the laser engine 505 has not been warmed up or a paper jam has occurred. To tell.
  • the microphone port processor 601 Upon receiving an interrupt request signal AMDINT2 from the electronic control unit 501, the microphone port processor 601 starts an image data transfer interrupt processing routine shown in FIG. When this process is started, the microprocessor 601 first performs a process of writing a value 1 to the bit d0 of the register ADD MUX A (step S900). If bit d0 of this register ADDMUXA has a value of 1, the data bus of RAMs 691 and 692 that make up bank A is It is connected to the data bus DB 29 side of the microprocessor 601 side, and cannot be accessed from the electronic control unit 501 side.
  • the microprocessor 601 performs processing for transferring data of 16 words (32 bytes) to the A bank DPWR0A (step S902).
  • the signal ZD PWR OA shown in FIG. 27 goes low, and the data is written to the RAMs 691 and 692 via the OTTAL line buffers 684 and 685.
  • the microprocessor 601 writes the value 1 to the bit dO of the register ADDMUXA (step S904), and transfers the data bus of the RAMs 691 and 692 constituting the A bank to the data of the electronic control unit 501. Connect to bus DB 68.
  • the microprocessor 601 performs a process of writing command data indicating the completion of the transfer to the bank A into the polling / command register 643 (step S906).
  • the process of transferring the data to the bank A is completed, and the microprocessor 601 subsequently executes the same process as that described above for the bank B (step S910).
  • the microprocessor 601 writes command data to the polling / command register 643 similarly indicating that the transfer has been completed. In this way, the transfer of 32 bytes (64 bytes) of data for banks A and B from cartridge 503 is completed.
  • the CPU 510 of the electronic control unit 501 executes an image data reception processing routine shown in FIG. 31 in response to the processing of the microprocessor ⁇ -processor 601 described above. That is, the CPU 510 first reads bit d3 of the status register 645, that is, the flag CMDRD (step S920), and determines whether or not this value is 0 (step S925). When command data is harmed to the polling command register 643 from the microprocessor 601 side, the flag CMDRD is set to a value of 0. At this time, the CPU 510 sets the command of the polling command register 643. The read data is read (step S930).
  • the read command data is checked, and it is determined whether or not the command data indicates that the data transfer of the A bank has been completed (step S935). If not, other processing is executed (step S940). If the command data of the boring and command register 643 indicates the completion of the data transfer of the A bank, the electronic control unit 501 performs a process of reading 16 words of the A bank DP RAMA (see FIG. 15). In step S945, the read data is transferred to the RAM 512 (step S950).
  • the electronic control unit 501 sets one of the interrupt request registers (AMD I Set NT 2). Then, the processing of steps S920 to S955 described above is executed for bank B. That is, when it is determined from the command data of the command register 643 that the transfer of the data from the microprocessor 601 to the bank B has been completed by one byte, the 16-word data of the bank B DPRAMB is read, and this is stored in the RAM 512. After the transfer, one of the interrupt request registers is set, and an interrupt request is made to the microprocessor 601.
  • the microprocessor 601 executes the interrupt processing routine shown in FIG. 30 again, so that the microprocessor 601 and the CPU 510 execute both routines (FIGS. 30 and 31). This completes the transfer of all image data.
  • the microprocessor 601 writes the value 1 to the register CLKD IV of the control register 650 when the predetermined time has passed, and It switches its own operating frequency to 12.5MHz, which is half, to reduce power consumption and, consequently, calorific value.
  • the electronic control unit 501 that has received the transfer of all the image data performs printing using the image data while exchanging signals with the laser engine 505 using the double buffer circuit 520 and the register 517 described above.
  • the exchange of signals between the electronic control unit 501 and the laser engine 505 is schematically shown in FIG. The outline of printing will be described with reference to this figure.
  • the electronic control unit 501 Upon receiving the developed image data from the cartridge 503, the electronic control unit 501 inquires whether or not the laser engine 505 is in a printable state. If it is determined that there is a print signal, the print signal shown in FIG. 32 is output to the laser engine 505 via the register 517. Upon receiving this signal, the laser engine 505 immediately activates the paper transport motor. In synchronization with this, the rotation of the photosensitive drum, the charging process and the like are started.
  • the laser engine 505 detects the leading end of the sheet and outputs a signal VREQ to the electronic control unit 501 via the register 517.
  • the electronic control unit 501 receives the signal VREQ, the electronic control unit 501 waits for a predetermined time, that is, a time required for the photosensitive drum to rotate to a position where the formation of a latent image by the laser beam is started, and then outputs the signal VSY. Output NC through register 517.
  • the laser engine 505 receives this signal VS YNC and outputs a horizontal synchronization signal H SYNC of the laser beam via the register 517.
  • this signal HSYNC corresponds to a signal instructing the start of reading one line of image data
  • the laser engine 505 reads the image data from one of the RAMs 520A or 520B of the double buffer circuit 520 in synchronization with this signal. .
  • control is performed to ignore the signal VSYNC by the number of lines corresponding to the top margin. This control is the same for the platform that forms the bottom margin.
  • CPU 510 transfers necessary image data to RAM 520 A or RAM 520 B of double bath sofa circuit 520 while counting this signal.
  • the CPU 510 determines whether the image data is The transfer to the double buffer circuit 520 ends.
  • the same effects as in the first embodiment can be obtained.
  • the circuit can be reduced in size and simplified.
  • the data transfer from the electronic control unit 501 to the data transfer control unit 603 is provided in two systems of the read control circuit 620 and the FIFO control circuit 623, the data to be tilled is provided. Efficient data transfer can be achieved by properly using these depending on the type. Also, if one system fails, the other system can compensate for it.
  • the microprocessor 601 of the cartridge 503 since the electronic control unit 501 uses an interrupt to notify the transfer of data to the cartridge 503, the microprocessor 601 of the cartridge 503 always has the electronic control unit 5 There is no need to monitor the operation of the 01 side, and the microprocessor 61 can operate efficiently.
  • the present invention is not limited to application to a printer, but may be applied to, for example, a warp ⁇ , a personal computer, or a work station. Can be.
  • such computer-related equipment has often become capable of mounting not only expansion slots but also cartridge-type expansion devices such as IC cards.
  • the additional electronic device of the present invention is mounted here, and the processing of the processor of the main unit is built in the additional electronic device by a monitor command or the like. If information is processed together with the processor provided in the additional electronic device, the information processing function can be easily improved if the processing is shifted to the processing that is stored in the memory.
  • the content of the processing can be changed in any way, so that the functions of already sold devices can be changed or improved, and software for various dedicated machines such as word processors can be used. It is possible to achieve a barge-up of eight.
  • the present invention is applicable to all devices using a processor, such as electronic components mounted on a vehicle, a facsimile, a telephone, an electronic organizer, an electronic musical instrument, an electronic camera, a translator, a handicap copy, a cash dispenser, a remote control device, and a calculator.
  • the connector can be used for any information processing device to which an additional electronic device can be connected.
  • the processor on the main body side has a function of recognizing the additional electronic device and shifting the processing to an address prepared in the additional electronic device, the additional electronic device of the present invention can be used. It is easy to realize the device and the information processing device. Even if such a function is not provided, various methods for shifting the main processor to processing stored in the additional electronic device can be considered.
  • the 680, 6000 system processor outputs data (slave) to determine whether data on the data bus is established when reading data from a predetermined address. Judge by the signal DTACK which responds to the processor. Therefore, when the processor of the main unit tries to execute the jump instruction to the absolute address while executing the processing stored in the ROM provided in the main unit, the execution of the jump instruction to the absolute address is added.
  • the configuration may be such that the execution address is output to the data bus, the signal DTACK is returned to the processor on the main unit side, and the process is forcibly shifted to a predetermined address or later in the additional electronic device.
  • the processor on the main unit executes the jump instruction to the absolute address.However, focusing on the fact that the jump instruction itself is read from the ROM on the main unit, It can and reads the installation Torakushi s emissions from, before the reading of ⁇ I Nsu Torakushi a down, can be configured and child to return the signal DTACK with placing the codes corresponding to the jump instruction to the data bus from the additional electronic apparatus It is. These techniques may cause a problem of signal DTACK contention, but can be realized by analyzing the timing of the bus in detail.
  • the additional electronic device is configured as a cartridge in which the printed circuit board is housed in the housing and can be handled alone, but the additional electronic device may be configured as a single board mounted on the expansion slot. Absent.
  • a single additional electronic device may be realized by occupying a plurality of connectors.
  • a case in which the housing itself is configured as a printed circuit board can also be realized as one embodiment of the present invention.
  • the present invention is not limited to the above-described embodiments.
  • a cartridge with a built-in font receives data such as the number of character points from the printer, generates a bit image of the specified number of characters, and transfers it to the printer. It goes without saying that the present invention can be implemented in various modes without departing from the gist of the present invention, such as a configuration of a printer.
  • the present invention is based on a connector using any device using a processor, such as electrical components mounted on a vehicle, a facsimile, a telephone, an electronic organizer, an electronic musical instrument, an electronic camera, a translator, a handy copy, a cash dispenser, a remote control device, and a calculator.
  • the present invention can be applied to any information processing device to which the additional electronic device can be connected. When applied to these, the functions of electronic devices can be improved, added or changed, and can be used in a wide range of industrial fields, including the effective use of existing devices.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Record Information Processing For Printing (AREA)
  • Accessory Devices And Overall Control Thereof (AREA)

Abstract

Dans la présente invention, une cartouche (50) adaptée à un dispositif électronique est équipée d'un circuit discriminateur (54) et d'une mémoire morte (ROM) (56). Le circuit discriminateur établit une discrimination entre les types de dispositifs électroniques pour déterminer celui dans lequel la cartouche est introduite, en se servant du fait que le comportement d'un signal d'échantillonnage d'adresse fournie par une unité centrale (CPU) (510) dans le dispositif électronique varie en fonction du type de dispositif électronique. Un bit d'adresse prédéterminé fourni par l'unité centrale est transformé en fonction du type de dispositif électronique et est introduit dans la mémoire ROM (56). Il en résulte qu'une donnée déterminée par le type de dispositif électronique est extraite de la mémoire ROM (56) et fournie au dispositif électronique.
PCT/JP1992/000227 1992-02-26 1992-02-26 Dispositif discriminateur de type et procede correspondant WO1993016881A1 (fr)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS621181A (ja) * 1985-06-26 1987-01-07 Ricoh Co Ltd メモリパツク
JPS625875A (ja) * 1985-07-03 1987-01-12 Hitachi Ltd 印字装置
JPS6214689A (ja) * 1985-07-13 1987-01-23 株式会社リコー 文字出力制御装置
JPS62111776A (ja) * 1985-11-12 1987-05-22 Oki Electric Ind Co Ltd プリンタの制御方法
JPS62182795A (ja) * 1986-02-05 1987-08-11 ミノルタ株式会社 フォントカートリッジとそのデータ管理方法
JPH0322160A (ja) * 1989-06-20 1991-01-30 Fuji Electric Co Ltd 計算機システムにおけるアダプタ制御プログラムの組込方式

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS621181A (ja) * 1985-06-26 1987-01-07 Ricoh Co Ltd メモリパツク
JPS625875A (ja) * 1985-07-03 1987-01-12 Hitachi Ltd 印字装置
JPS6214689A (ja) * 1985-07-13 1987-01-23 株式会社リコー 文字出力制御装置
JPS62111776A (ja) * 1985-11-12 1987-05-22 Oki Electric Ind Co Ltd プリンタの制御方法
JPS62182795A (ja) * 1986-02-05 1987-08-11 ミノルタ株式会社 フォントカートリッジとそのデータ管理方法
JPH0322160A (ja) * 1989-06-20 1991-01-30 Fuji Electric Co Ltd 計算機システムにおけるアダプタ制御プログラムの組込方式

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