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WO1992015960A1 - Systeme d'ordinateur electronique et elements processeurs utilises pour ce systeme - Google Patents

Systeme d'ordinateur electronique et elements processeurs utilises pour ce systeme Download PDF

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Publication number
WO1992015960A1
WO1992015960A1 PCT/JP1991/000296 JP9100296W WO9215960A1 WO 1992015960 A1 WO1992015960 A1 WO 1992015960A1 JP 9100296 W JP9100296 W JP 9100296W WO 9215960 A1 WO9215960 A1 WO 9215960A1
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Prior art keywords
data
memory
processor
cell
written
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PCT/JP1991/000296
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English (en)
Japanese (ja)
Inventor
Hajime Seki
Original Assignee
Hajime Seki
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Hajime Seki filed Critical Hajime Seki
Priority to PCT/JP1991/000296 priority Critical patent/WO1992015960A1/fr
Publication of WO1992015960A1 publication Critical patent/WO1992015960A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4494—Execution paradigms, e.g. implementations of programming paradigms data driven

Definitions

  • the present invention relates to a computer system having a novel configuration and a processor element used therein.
  • the present invention has been proposed in order to solve the above problems.
  • the purpose of the present invention is to execute operations in individual processors, transfer data between processors, and the like.
  • the computer system of the present invention has a hardware configuration that includes a control processor and a plurality of processor elements capable of mutually transferring data through a bucket communication network (hereinafter referred to as the present invention).
  • the control processor is written as CP and the processor element is written as PE.
  • Each PE is sent from the CP based on the principle of Single Instruction stream Multiple Data stream (SIMD).
  • SIMD Single Instruction stream Multiple Data stream
  • An execution unit having a function of executing data transfer between PEs through a communication network is configured.
  • the CP should send instructions to the control unit of the PE and execute them based on the data structure in the execution unit.
  • the content can be set, and the operation based on the data movement in the execution unit is performed in parallel with the setting of the execution unit.
  • the execution unit of the PE has a function of executing calculation of variable data indicated by a program statement based on data driving, and a variable as soon as variable data corresponding to a variable name to be transferred is obtained. It can be configured to have a function of sending a packet including name and variable data to the execution unit of the destination PE.
  • the proposed processor element has an associative memory function in which the variable name and variable data are written in each cell, and the variable names are collated and the variable data is written in the matching cell.
  • Data memory with storage function, variable name indicating the storage location of the calculation result, immediate data, and data memory in which the calculation result is written, stack memory, and individual memory for each cell Equipped with an instruction memory in which the contents of the operation are written and an operation unit that executes the operation, and configures the program statements from the PE control unit to the operation execution unit based on the instructions of the CP.
  • the stack memory is operated and the contents of the calculation indicated by the program statement are stored in the data memory with associative memory function and The contents of calculations to be executed based on data activation by converting the data stored in the data memory cells into the form of a set of individual operations that are used as operands and writing them to the instruction memory.
  • the configuration is such that the operation shown is executed.
  • the instructions for setting the execution unit in the local memory of each PE and the setting method are described.
  • the contents are stored and the CP sends instructions to execute the contents in the local memory of each PE, so that the MIMD (Multiple Instruction stream Multiple Data strea) ( A similar operation can be performed.
  • MIMD Multiple Instruction stream Multiple Data strea
  • the CP assigns an activity number to a set of contents ⁇ for setting the execution part of the PE; Section indicates the limit of the activity number of the setting that is waiting to be executed or is being executed by the CP.
  • the control unit controls the flow of commands sent to the control unit.
  • each PE indicates the limit of the activity number of the setting contents that are waiting or being executed by the execution unit to any controller at the lowest layer.
  • Each controller is waiting for or executing all the PEs connected to the lower layer, and presents the upper limit controller with the upper limit of the activity number of the setting contents.
  • the control unit may be configured to indicate to the CP the limit of the activity number of the setting contents that are waiting to be executed or are being executed across all the PEs.
  • a variable refers to a data item of a fixed word length having a storage area in one of the local memories provided in each PE, and each variable name represents a local memory for storing data. It consists of the address of the provided PE and the address of the word in the local memory.
  • Each program element represents either a variable name, immediate data, or an operator that indicates an operation such as an arithmetic logic operation or data storage.
  • a program statement is a sequence of program elements that make sense based on reverse Polish notation, and begins with a program element that indicates a variable name that indicates the storage location of the calculation result. Should end with a program element that represents.
  • the program element representing the variable name in the program statement is used to represent the storage area for operand data or the address where the calculation results are stored.
  • FIG. 1 is a block diagram showing a basic configuration of the system of the present invention
  • FIG. 2 is a block diagram showing a detailed configuration of a processor element of the present invention
  • FIG. 3 is a detailed configuration of an execution control memory described later.
  • 4 is an explanatory diagram showing the detailed configuration of the data memory with associative memory
  • FIG. 5 is an explanatory diagram showing the detailed configuration of the instruction memory
  • FIG. 6 is a data diagram.
  • FIG. 7 is an explanatory diagram showing a detailed configuration of the transfer control memory.
  • FIG. 7 is a stack memory, a data memory with an associative memory function, a key memory, and an inductance when a calculation operation is performed in the processor element of the present invention.
  • FIG. 7 is a stack memory, a data memory with an associative memory function, a key memory, and an inductance when a calculation operation is performed in the processor element of the present invention.
  • FIG. 8 is a diagram specifically showing a change in the content of the memory
  • FIG. 8 is a diagram showing the content of a matrix-vector product assumed to specifically explain the operation of the system of the present invention
  • FIG. The figure is shown in Figure 8
  • Matrix is a diagram that shows the table in binary tree.
  • FIG. 1 is a block diagram showing a basic hardware configuration of the system of the present invention, wherein 1 is a control processor (hereinafter, referred to as a CP), 21 is a broadcast network, and 22 is packet communication. Network, 3!-3 n are processor elements ('PE is shown below), and 28!-28 are clusters described later.
  • the - ⁇ -control device 29 represents a global control device described later.
  • each of the control units includes a control unit having a function of executing a flow of an instruction sent from the CP based on the principle of the SIMD method and an execution unit operating based on the data active.
  • the execution unit further includes an operation execution unit configured to execute calculation of variable data indicated by a program statement based on data driving, and a variable name to be transferred.
  • the control unit of the PE executes the flow of instructions sent from the CP, so that the execution unit can set the contents to be executed based on the data movement in the execution unit. For the operations such as, the program elements that make up the program statement are delivered one by one to the operation execution unit, and for the data transfer between PEs, the variable name to be transferred and the destination PE are sent to the communication execution unit. The address is handed over, and the contents to be executed are set based on the key movement.
  • an activity number is given by CP to each program sent to the operation execution unit of PE. It is not necessary to give different activity numbers between different program statements, but it is assumed to be a number to which a non-negative increment is added each time it is delivered to the execution unit of PE. (If the activity numbers are wrapped around, the order set in the calculation execution part of the PE does not always match the magnitude relationship.)
  • the local The instruction for setting the execution unit and the contents to be set are stored in the memory, and the CP sends the instruction to execute the contents in the local memory of each PE, so that it can be transmitted to the MIMD computer system. Similar operations can be performed. Next, each component and operation of the invention system of this embodiment will be described.
  • the CP can broadcast commands to all PEs via the broadcast network 21.
  • This instruction is directed directly to the control unit of each PE, and is executed based on the SIMD principle.However, the execution unit performs operations and data transfer between PEs based on data active. Can be set as follows.
  • the CP assigns an activity number to each program statement and notifies the control section of the PE when issuing an instruction to the control section of the PE in order to set the calculation content indicated by the program statement in the operation execution section.
  • the same activity number is given to a program sentence to a calculation execution unit in a plurality of PEs at the same time.
  • the CP Since the lower limit of the activity number of the program statement waiting or executing in the PE group is provided to the CP from the global controller described later, the CP must not lose the consistency of the data dependency. It controls the flow of commands sent to the PEs. In other words, variables that are subject to calculation in a program statement given an activity number equal to or lower than the lower limit of the activity number presented to the CP by the global controller, wait for execution or execution of variable data calculation in the PE execution unit. It is not possible to directly access the variable data by the instruction sent by the CP because it may be in the middle, and refrain from changing the variable data through the setting of the operation execution unit to maintain the integrity of the calculation. Must-have.
  • any of the PEs will be described later. If any of the execution control memory, the data memory with associative memory function, the data memory, the integration memory, and the key transfer control memory described later is about to overflow, the global memory described later is used. Since the CP is notified through the control mechanism, the CP suspends the instruction flow to set up the execution unit of the PE. When the above condition is resolved, the PE is notified again to the CP via the global control mechanism, and the CP can resume the setting of the execution unit of the PE.
  • FIG. 2 is a block diagram showing a detailed configuration of the processor element 3 i used in this embodiment.
  • the processor element 3 i has a control unit 30 i, an execution unit 31 i, and a local memory 35 i, and the execution unit 31 i comprises an operation execution unit 32 i and a communication execution unit 33 i Is done.
  • the control unit 30 i includes an execution control memory 4 i to be described later, and the arithmetic execution unit 32 i includes a stack memory 6 i, a data memory with an associative memory function 7 i, a data memory 8 i, and an installation. It has a function memory 9i and an operation unit 39i.
  • the communication execution unit 33 i includes a data transfer control memory 5 i described later.
  • the control unit 30 i is connected to the broadcast network 21 coming from the CP 1, and can directly access the oral memory 35 i. Data communication is possible between the PEs via the packet communication network 22, but the sender of the packet is a communication execution unit, and the recipient is an operation execution unit.
  • each PE control unit is configured to be able to process a single instruction flow sent from the CP at the same time, but each PE control unit It has a function to select whether to execute or ignore an instruction depending on the internal state.
  • control unit of the PE By executing the instruction flow sent from the CP, the control unit of the PE operates based on the data execution of the arithmetic execution unit and the communication execution unit. It can be set as follows.
  • the PE's control unit performs the operation on the local memory in accordance with the explicit instructions from the CP based on the SIMD principle, and the asynchronous execution with the operation based on the data organization principle in the execution unit. It can be accessed independently and in parallel in two systems.
  • the control unit of the PE controls the flow of the command sent from the CP to the control unit of the PE, the setting operation of the execution unit in the PE, and the operation based on the decoder active in the execution unit.
  • the execution control memory (hereafter referred to as the execution control memory) stores the activity number and the variable name indicating the storage location of the calculation result for each of the program statements waiting to be executed or being executed in the operation execution unit. ECM).
  • FIG. 3 is an explanatory diagram showing a detailed configuration of the ECM.
  • E CM4 i is composed of cells 4 1 i, 42 i ⁇ , each of which has an activity number column 4 1 1 i, 4 2 1 i ⁇ and a variable name column 4 1 2 i, 422 i ⁇ , and the control builders 4 13 i, 4 23 i ⁇ .
  • the ECM has an associative memory function using the variable name column as a collation field.
  • the control field of the ECM is a storage area for control information such as whether or not each cell is in use and whether variable data needs to be transferred to the communication execution unit.
  • Each PE is configured to always present the lower limit of the activity number of the program statement waiting to be executed or being executed by the operation execution unit, that is, the lower limit of the activity number written in the ECM, to the cluster controller described later. You. (If the activity number is wrapped around, the lower limit is not necessarily the minimum value.)
  • the control unit hands over the program elements that make up the program statement to the operation execution unit one by one, and sets so that the operation is executed based on data activation. can do.
  • the control unit passes one program statement to the operation execution unit based on the instruction of the CP, the variable name indicating the storage location of the calculation result and the activity number given to the program statement are vacant in the ECM. Writes to cells.
  • variable name indicated as the storage destination of the calculation result in the program statement is the local memory of the PE executing the calculation indicated in the program statement. It must belong to In each program statement, it is assumed that the same variable name as the variable name indicating the storage location of the calculation result does not appear as an operand.
  • the control unit hands over the variable name to be transferred and the address of the PE that is the destination to the communication execution unit, and makes settings so that the data transfer between PEs is executed based on the switch active. be able to.
  • variable name to be transferred is compared by the associative memory function in the ECM, and if there is no cell in which the same variable name is written, the local memory is immediately accessed and the The variable data fetched with the name is sent to the communication execution unit. Conversely, if there is an ECM cell in which the same variable name as the above transfer target is written, the control field of that cell is calculated by the arithmetic execution unit for that variable. Is completed and the control unit stores the variable data in the local memory Is set to send variable data along with the variable name to the communication execution unit.
  • variable to be transferred in the data transfer executed by the communication execution unit, the variable to be transferred must have a storage area in the local memory of the PE that is the sender of the bucket. Shall be. Further, in the present embodiment, even when variable data is transferred to the operation execution unit of the same PE based on data driving, the address of the own PE is set as the destination of the dry transfer, and the communication execution unit is used. It is assumed that the bucket is transferred from the to the operation execution unit of the same PE through the bucket communication network.
  • the operation execution part of the processor element has a stack memory, data memory with associative memory function, data memory, instruction memory, and operation unit, and can be handed over from the control part. It has a function to execute the calculation indicated in the program statement based on data drive.
  • the stack memory (hereinafter referred to as SM) 6 i is a structure in which the address of the cell of the data memory 7 i with associative memory function or the data memory 8 i is written to each cell.
  • FIG. 4 is an explanatory diagram showing a detailed configuration of a data memory with an associative memory function (hereinafter referred to as ADM) 7i.
  • the ADM 7 i is composed of cells 7 1 i and 72 i, each of which has a variable name ⁇ 7 lli, 72 1 i ⁇ , and a column for variable data 7 1 2 i, 722 i ⁇ , And control fields 7 13 i, 723 i ⁇ .
  • the ADM has an associative memory function in which a variable name is collated in the column of a variable name, and data is written into the variable data of the matching cell.
  • the control field of the ADM is used to control whether each cell is in use or not. This is a storage area for control information.
  • the data memory (in the following, denoted by DM) 8i is configured to write the variable name indicating the storage location of the calculation result, immediate data, and the operation result.
  • the instruction memory (hereinafter referred to as IM) 9i stores the contents of a program statement described based on the reverse Polish notation in the ADM and DM cells as storage areas for operand data and operation results. It is stored in the form of a set of individual operations to be performed.
  • FIG. 5 is an explanatory diagram showing a detailed configuration of the IM.
  • ⁇ ⁇ 9 ⁇ is composed of cells of 91 i and 92 i, and each cell is an operation field 911 i and 92 1:! ⁇ , 1st Operand Field 912i, 922i ⁇ , 2nd Operand Field 913i, 923i ⁇ , Destination Field 914i, 9 24 i ⁇ , and control fields 9 15 i, 9 25 i ⁇ .
  • the IM control field is used to identify each cell, such as whether the cell is in use and whether data has been written to the ADM or DM cell indicated in the operand field. This is a storage area for control information.
  • the operation unit 39 i is a part for executing the operation perfumed in M.
  • the arithmetic unit can be configured such that the arithmetic units are pipelined, or that a plurality of arithmetic units are provided and they can operate in parallel.
  • An unused cell of the ADM is assigned to the program element, and the variable name of the operand is written in ⁇ of the variable name of the cell, and the address of the written ADM cell is pushed into SM.
  • Allocate cells that do not use DM as the storage destination of operation results, secure cells that do not use IM, and store operation codes in their operation fields, and the number of operands used for calculations from SM in the operand field.
  • Write the address of the ADM or DM cell that was just extracted into the destination field and write the address of the DM cell that was assigned as the destination for the above-mentioned operation result in the destination field, and assigned it as the storage destination for the operation result. Press the address of the DM cell into the SM.
  • a cell in which IM is not used is secured, and the operation code is used in the operation field and the operation field is used for calculation from SM in the operand field.
  • variable data When variable data is transmitted along with the variable name to the operation execution unit of the processor element through the bucket communication network, the variable name is collated by the associative memory function in the ADM and the variable name is matched. Data is written to the cell variable data column.
  • IM In IM, as soon as a cell is detected in which arithmetic and logical operations, etc. are written and all operand data has been written to ADM or DM, the operation indicated in that cell is executed in the arithmetic unit. Then, the operation result is written to the DM cell indicated in the destination field.
  • the storage of data is the contents of writing, and as soon as a cell in which all of the operand data has been written to ADM or DM is detected, the storage of the data indicated in that cell is sent to the control unit. Ask.
  • a cell in which the ADM is not used is allocated every time a program element representing a variable name of an operand is delivered. If there is a cell in which the same variable name is written in the variable name column, the cell can be assigned.
  • FIG. 7 is an explanatory diagram specifically showing the operation of the arithmetic execution unit of the processor element of the present embodiment, and the detailed operation will be described below based on this diagram.
  • the configurations of ADM and IM in FIG. 7 are the same as those in FIGS. 4 and 5, respectively, except that the control field is omitted.
  • the dotted line indicates that the cell is not used. Means that. (Here, each time the execution step progresses, a hyphen and a number corresponding to the step are appended to the end of the code of each part to indicate the content of each component at that time.)
  • the cell at address DM8-4 at address 3> is assigned as the storage destination of the operation result (other unused DM cells). ), And reserve a cell at address 1 of IM 9-4 (or another unused IM cell) in order to record the contents of the operation.
  • * And are taken from SM as two addresses (operators, * and are binary operators) extracted from SM. ⁇ 2> is written into the destination field, and the address of the DM cell assigned as the storage location of the above operation result is written to the destination field, and the SM is addressed to the SM. Press in as in 6—4.
  • the associative memory function is used to enter the variable data of the cell with the variable name [ ⁇ ] written in the ADM 7-6 variable name.
  • the operation indicated in the cell at address 1 of ⁇ ⁇ 9-6 can be executed, and the operation is executed in the operation unit 39.
  • the writing to the cell at address 1 of ⁇ , the cell at ADM address ⁇ 1 >>, and the cell at DM address 2 are invalidated.
  • the data '10' of the operation result is written to the DM address 3) cell indicated by the destination field. .
  • the storage of the data indicated in the cell at address 2 of IM 9-7 becomes executable, and the control unit controls the storage of the data and 10 'in the data storage area indicated by the variable name [A]. To ask. At this time, writing to the cell at the address 2 of the IM and the two cells at the addresses 1> and 3> of the DM are invalidated.
  • the communication execution part of the processor element performs bucket communication based on active data. It performs data communication between PEs via a network.
  • the communication execution unit has a data transfer control memory described below. This data transfer control memory stores the name of the variable to be transferred and the address of the PE as the destination. As soon as the variable data corresponding to the above variable name is received, it can be transmitted to the destination.
  • Fig. 6 is an explanatory diagram showing the detailed configuration of the data transfer control memory (hereinafter referred to as TCM).
  • TCM5 i is composed of cells 5 1 i, 5 2 i ⁇ , and each cell is a destination ⁇ 5 1 1 i, 5 21 i ⁇ , a transmission variable name ⁇ 5 1 2 i, 522i ⁇ , transfer data # 513i, 523i ⁇ , and control blocks 514i, 524i ⁇ .
  • the TCM has an associative memory function in which data is written to the ⁇ ⁇ of the transfer data of the cell having the same variable name using the column of the transfer variable name as a collation field.
  • the TCM zen build of TCM is a storage area for control information such as the next to the transfer variable name and the presence or absence of writing of the transfer data tree for each cell. Next, the operation of the communication execution unit will be described.
  • a cell in which the TCM is not used is secured, and the variable name to be transferred transferred from the control unit and the address of the PE which is the destination passed from the control unit are respectively entered in the fields of ⁇ ⁇ and the destination of the transfer variable name.
  • the address By writing the address, data transfer between PEs can be set to be executed based on data movement.
  • the transmission data corresponding to the transfer variable name is sent to the communication execution unit asynchronously with the variable name after the above setting.
  • the TCM uses the associative memory function to write the variable data to the transfer channel of the cell with the matching variable name.
  • the contents of the cell for which the transfer data has been written are sent to the bucket communication network. At this time, the cell holding the contents of the transmitted packet is released.
  • the variable data is transferred from the communication execution unit through the bucket communication network.
  • the global control mechanism has the function of integrating control information from all PEs and presenting or notifying them to the CP.
  • the global control mechanism connects a plurality of control devices in a hierarchical manner, thereby reducing the number of PEs or control devices directly connected to each control device.
  • the configuration can be limited.
  • a two-layer control mechanism including a plurality of cluster control devices (hereinafter referred to as CCU) 28i to 28m and one global control device (hereinafter referred to as GCU) 29 is provided. It is assumed that each PE is directly connected to one of the CCUs, and all CCUs are directly connected to the G CU.
  • Each PE always presents the lower limit of the activity number written to the execution control memory to the directly connected CCU, and each CCU is presented by all directly connected PEs.
  • the lower limit of the activity numbers assigned to the CCU is always presented to the G CU, and the G CU always presents the lower limit of the activity numbers presented by all the CCUs to the CP. In this way, the CP can know the lower limit of the activity number of the program statement waiting or executing through all the PEs.
  • any of execution control memory, data transfer control memory, data memory with associative memory function, chip memory, and installation memory is likely to overflow.
  • the CP is notified via the global control mechanism, and the CP interrupts the execution of instructions to set the execution unit of the PE.
  • the PE is notified to the CP again through the global control mechanism, and the CP can resume the setting of the execution unit of the PE.
  • the global control mechanism is not limited to the above-described control information, and can be used to integrate various control information and present or notify the CP. Let us explain concretely the operation of the invention system in this example using the product of a sparse matrix and a vector as an example.
  • the memory efficiency can be improved by expressing each of the rows and columns in a rillie structure. That is, consider a tree structure in which one route is provided for each row and column, and leaves corresponding to non-zero matrix elements are connected to this route by pointers. In this embodiment, a binary tree is used, and a fan-out node is required to connect two or more leaves to the root.
  • a certain area of the oral memory of one PE is allocated to the nodes ⁇ constituting the tree, and each area is called a record.
  • the records corresponding to the root, leaf, and fan-out nodes are called record, leaf record, and fan-out record, respectively.
  • the pointer from the root to the leaf is the forward pointer, and the leaf to the root.
  • the forward pointer is called the back pointer. At most two forward pointers for the record, one back pointer for the leaf record, and the forward pointer for the fan-out record, along with various data. Two and one backpointer are listed.
  • FIG. 9 shows the tree representation of the sparse matrix.
  • C1 to C4 are the routes provided for columns 1 to 4
  • R1 to R4 are the routes provided for rows 1 to 4, respectively
  • C3a and R2a are fans.
  • Art nodes, aH to a44 represent leaves corresponding to matrix elements (aij corresponds to matrix elements of i rows and j columns), and one record is assigned to each of the above .
  • [C 1] designates a record corresponding to node C 1
  • [C 1] designates a variable name that stores the k-th word in record [C 1] as a data storage area.
  • PE [C 1] represents a PE having a local memory in which the record [C 1] is stored. Also, in each record, the first word identifies whether the record is in use or unused, and identifies the record in use between the root / fanart Z leaf, An indication of the type and number of pointers used, and a storage area for information such as identification of a row or column in a row or fan record, such as the second or fourth. The word is used as the storage area of the pointer, and the fifth and subsequent words are used as the storage area or the work area of the data body.
  • the CP sends an instruction to the PEs based on the principle of the SIMD method, and in each PE, the control unit controls the first word of the record.
  • the execution unit can be set as follows.
  • CALC [R 4] aa 3 i + [a 4 4 3> where k ⁇ 5, and [C 1] t to [C 4] t are 2, 0, -1, 1 It is assumed that data has been written in advance. In addition, 1 to ® are in the order set according to the instructions of the CP, and it is not always necessary to follow this order, but if you do so randomly, the consistency of the calculation will be lost. Those with the same number are set at the same time according to the principle of the SIMD method. In the setting of 1, the value of the matrix element written in each leaf record is read and used.
  • the data transfer indicated by SEND is executed through the bucket communication network immediately after setting.
  • the calculations following CALC (1) and (2) can be executed sequentially except for a part, and when the calculation is completed, the calculation result is changed to the k-th record of each record.
  • the data transfer indicated by SEND becomes executable in the same PE. Thereafter, similarly, the setting contents of 5 to 11 are executed sequentially as soon as necessary data is collected, and finally, each record is
  • efficient calculation can be performed by operating a plurality of PEs in parallel.
  • each PE operates independently by data movement, the control structure of the PE group is simple, and there is an advantage that there is no need to give much control to this control structure during programming. is there.

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Abstract

Système d'ordinateur électronique comprenant un processeur de commande (1) et un ensemble d'éléments processeurs (31-3n) qui s'échangent des données par l'intermédiaire d'un réseau de transmission par paquets (22). Chacun des éléments processeurs (31-3n) possède une unité de commande (30i) qui exécute le flux d'instructions envoyées par le processeur de commande (1) selon le principe du système SIMD, et une unité d'exécution (31i) qui exécute des opérations en fonction de l'unité de commande de données et qui exécute le transfert de données entre les éléments processeurs (31-3n) via le réseau de transmission par paquets (22). Le processeur de commande (1) envoie une instruction à l'unité de commande (30i) de chacun des éléments processeurs (31-3n), de manière à déterminer le contenu devant être exécuté par l'unité d'exécution (31i) en fonction de l'unité de commande de données. L'unité d'exécution (31i) opère en fonction de l'unité de commande de données en parallèle avec le réglage de l'unité d'exécution (31i).
PCT/JP1991/000296 1991-03-05 1991-03-05 Systeme d'ordinateur electronique et elements processeurs utilises pour ce systeme WO1992015960A1 (fr)

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GB2410350A (en) * 2001-02-14 2005-07-27 Clearspeed Technology Plc Data processing architectures

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JPH01195540A (ja) * 1988-01-29 1989-08-07 Sharp Corp データのロードおよびダンプ方式
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GB2374443B (en) * 2001-02-14 2005-06-08 Clearspeed Technology Ltd Data processing architectures
GB2410350A (en) * 2001-02-14 2005-07-27 Clearspeed Technology Plc Data processing architectures
GB2410350B (en) * 2001-02-14 2005-11-09 Clearspeed Technology Plc Data processing architectures
US7856543B2 (en) 2001-02-14 2010-12-21 Rambus Inc. Data processing architectures for packet handling wherein batches of data packets of unpredictable size are distributed across processing elements arranged in a SIMD array operable to process different respective packet protocols at once while executing a single common instruction stream
US7917727B2 (en) 2001-02-14 2011-03-29 Rambus, Inc. Data processing architectures for packet handling using a SIMD array
US8127112B2 (en) 2001-02-14 2012-02-28 Rambus Inc. SIMD array operable to process different respective packet protocols simultaneously while executing a single common instruction stream

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