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WO1992002885A1 - Unites de traitement pour un systeme d'ordinateur numerique a processeurs multiples - Google Patents

Unites de traitement pour un systeme d'ordinateur numerique a processeurs multiples Download PDF

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Publication number
WO1992002885A1
WO1992002885A1 PCT/US1990/004376 US9004376W WO9202885A1 WO 1992002885 A1 WO1992002885 A1 WO 1992002885A1 US 9004376 W US9004376 W US 9004376W WO 9202885 A1 WO9202885 A1 WO 9202885A1
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WO
WIPO (PCT)
Prior art keywords
memory
host
bus
data
cpu
Prior art date
Application number
PCT/US1990/004376
Other languages
English (en)
Inventor
Roy Emerson Murphy
Original Assignee
Epic Industries Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Epic Industries Incorporated filed Critical Epic Industries Incorporated
Priority to PCT/US1990/004376 priority Critical patent/WO1992002885A1/fr
Publication of WO1992002885A1 publication Critical patent/WO1992002885A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Definitions

  • the present invention relates generally to the technical field of digital computers and, more particularly, to multi ⁇ processor digital computers adapted to perform engineering and scientific computations swiftly.
  • the exact sequence in which particular pairs of numbers from the row vector of matrix A and from the column vector of matrix B are multiplied together is irrelevant to accurate computation so long as the results of that multiplication can be stored properly in the appropriate entry in the matrix C.
  • one technique that is employed to reduce the time required to perform a computation is to have multiple processors operate in parallel with each processor simultaneously processing a different portion of the same computation, i.e. parallel processing.
  • PE processing element
  • FPU floating point unit
  • current microprocessors such as Motorola's MC68040 and Intel's 80486 include a FPU integrated into the same chip as the central processing unit (“CPU") itself.
  • both Motorola's MC68020 and MC68030 have been designed to simultaneously control the operation of several co-processor chips.
  • Motorola's MC68030 has been designed to simultaneously control a combination of up to 8 co-processor chips such as Motorola's MC68882 FPU and/or Motorola's MC68451 memory management unit (“MMU") .
  • MMU memory management unit
  • a common difficulty in parallel multi-processor digital computing systems is the need to share data among the several processors.
  • any one of the several processors may require access to a value that was computed at an earlier time by another one of the processors.
  • this data sharing problem has been recognized by those working in the field of parallel multi-processor digital computing systems for many years and while various different solutions to the problem have been proposed and even implemented, thus far there exists no generally recognized solution to the problem.
  • a system in which several processors share a single memory suffers from the problem of "contention among the various processors for access to the shared memory.
  • each processor includes its own local memory to avoid contending for a shared resource, then the results of its computations must be shared among all the other processors.
  • a common bus is used to interconnect the local memories in the several processors, there is a problem with processors contending for access to the bus.
  • postbox One particular attempt at solving the preceding problems in multi-processor systems is known as a "postbox" system.
  • a postbox system a single, multi-port memory is shared between or among the multi-processors. To access this shared memory, a port on the memory is assigned to each of the processors.
  • One processor commences a data transfer to another processor by accessing the memory through its port and storing the data into a memory location in the shared memory. Subsequently, another processor needing those data will access the shared memory through its port to fetch the data from the memory location into which it has been stored by the first processor.
  • a postbox system employs only a single, shared, multi- port memory, the memory must arbitrate memory accesses occurring simultaneously through two or more memory ports. If the shared memory employs a hierarchial arbitration circuit, it is possible for processors assigned the highest priority to block accesses to the shared memory by the lower priority processors.
  • An object of the present invention is to provide an effective way of adapting a personal computer to efficiently perform scientific or engineering computations.
  • Another object of the present invention is to provide a multi-processor that may be expanded modularly to include a plurality of processing elements.
  • Another object of the present invention is to provide a multi-processor which adapts a single CPU to effectively control the operation of a plurality of FPUs.
  • Another object of the present invention is to provide a multi-processor system in which one processor may not block another processor.
  • Yet another object of the present invention is to provide a multi-processor that is cost effective, and easy and economical to manufacture.
  • the present invention adapts a personal computer for performing engineering or scientific computations by incorporating one or more PEs into a conventional personal computer.
  • Each of these PEs that may be incorporated into a host personal computer, includes a pair of multi-port memories.
  • Each PE also includes an inter-memory bus that interconnects shared ports of the two multi-port memories for exchanging data between the two memories.
  • a host port of the first of these two multi-port memories exchanges data with a bus in the host personal computer over which the CPU and host computer memory exchange data.
  • a bus within the PE couples a PE port of the second of the two multi-port memories with a central processing unit included in the PE itself ("PE CPU").
  • the PE's CPU and the second multi-port memory exchange data over this PE bus.
  • the PE also includes a memory control means for controlling exchanges of data between the host bus and the first multi-port memory, between the two multi-port memories, and between the second multi-port memory and the PE bus. In controlling these various exchanges of data, the PE's memory control means responds to signals received from the host CPU and from the PE CPU.
  • the first and second multi-port memories are video ram ("VRAM") integrated circuits.
  • VRAM video ram
  • one port of such VRAM integrated circuits operates to store or to retrieve data in the same way as conventional single port random access memories (“RAM"). It is this port of the two VRAMs included in the preferred embodiment of the PE which respectively exchange data with the host bus and with the PE bus.
  • a second, or serial, port of a VRAM integrated circuit either receives data for storage or transmits stored data.
  • These second, or serial, ports of the VRAM are the shared ports of the PE and are interconnected by the inter-memory bus.
  • Signals supplied to the first and second VRAM cause one of them to transmit data over the inter-memory bus from its shared port while the other VRAM receives such transmitted data from the inter-memory bus for storage within the VRAM.
  • data written into one of the VRAMs by either the host CPU or by the PE CPU transfers automatically and/or simultaneously from the written VRAM into the other VRAM thereby making them directly addressable for further processing by the other CPU.
  • either or both CPUs can access their respective VRAM memories without interference from the other CPU while data are being transferred between the VRAM memories.
  • FIG. 1 is a block diagram depicting a personal computer incorporating a PE in accordance with the present invention that illustrates the PE's memories, the control for those memories, the control and status registers, and the various buses interconnecting the memories with the host bus, with the inter-memory bus, and with the PE bus;
  • FIG. 2 is a block diagram depicting the organization of FIGs. 2a-2d into a single composite diagram;
  • FIGs. 2a-2d form a composite block diagram depicting, at the integrated circuit package and signal line level, the memories, memory control, registers, and buses within the PE;
  • FIG. 3 is a memory allocation diagram depicting the assignment of memory address space for the host personal computer and for the PE in accordance with the present invention.
  • FIG. 4 is a diagram depicting the two registers by which the host personal computer and the PE exchange control and status information.
  • FIG. 1 depicts a personal computer that is enclosed within a dashed line and referred to by the general reference character 20.
  • the personal computer 20 includes a CPU 22, a RAM memory 24, a disk controller 26 for controlling the operation of a hard disk 28, a video display adapter.32 for controlling the operation of a video monitor 34, and a keyboard 36.
  • a host bus 38 within the personal computer 20 interconnects the CPU 22, the RAM memory 24, the disk controller 26, the video display adapter 32 and the keyboard 36 for transferring data among those various items. Since the preferred embodiment of the host personal computer 20 is an IBM PC AT, the host bus 38 conforms to the Industry Standard Architecture ("ISA") bus of an IBM PC AT personal computer.
  • ISA Industry Standard Architecture
  • FIG. 1 also depicts a plurality of PEs in accordance with the present invention that are illustrated by dashed outlines and referred to by the general reference character 40.
  • FIG. 1 depicts the block diagram for only one of the PEs 40 while the remaining PEs 40 are illustrated only by their dashed outlines because they are obscured by one or more of the other PEs 40.
  • Each of the PEs 40 includes a PE ISA bus 42 that adapts the PE 40 to plug into the ISA host bus 38 and to be
  • the PE ISA bus 42 extends the host bus 38 onto the PE 40 which includes the particular bus 42. Inclusion of the PE ISA bus 42 in each PE 40 permits it to exchange control and status signals and data with the CPU 22 and RAM memory 24 included in the personal
  • FIG. 1 depicts a total of fifteen PEs 40, as few as one PE 40 or more than 15 PEs 40 may be connected to the host bus 38.
  • the PE 40 of the present invention allows assembly of a computer system for use in performing engineering and scientific computations that is
  • each of the PEs 40 includes a first multi-port VRAM 44 and a second multi-port VRAM 46.
  • Each PE 40 also includes an inter-memory bus 48 that interconnects serial data in/data out shared ports 52 of the two VRAMs 44 and
  • the VRAMs 44 and 46 exchange data via the inter-memory bus 48.
  • the first VRAM 44 includes a random-access data in/data out host port 54 to which a PE host bus 56 connects.
  • the first VRAM 44 exchanges data with the host bus 38 in the personal computer 20 via the PE
  • a first VRAM control and address bus 66 connects the first VRAM 44 to a first VRAM control circuit 68 which also connects to the PE bus 64 and to the PE-host interface circuit 58 via the PE host bus 56.
  • a second VRAM control and address bus 72 connects the second VRAM 46 to the first VRAM control circuit 68 and to a second VRAM control circuit 74, which itself also connects to the PE bus 64.
  • the PE bus 64 also connects directly to the PE-host interface circuit 58.
  • a VRAM synchronization signal bus 76 connects the second VRAM control 74 to the first VRAM control 68. Responsive to signals that the PE-host interface circuit 58 receives both from the PE bus 64 and from the host bus 38 via the PE ISA bus 42, to signals that the first VRAM control circuit 68 receives from the PE-host interface circuit 58, from the PE bus 64, and from the second VRAM control circuit 74, and to signals that the second VRAM control circuit 74 receives from the PE bus 64, the combined PE-host interface circuit 58, the first VRAM control circuit 68, and the second VRAM control circuit 74 operate to control exchanges of data between the host bus 38 and the first VRAM 44, between the first VRAM 44 and the second VRAM 46, and between the second VRAM 46 and the PE bus 64.
  • each of the VRAMs 44 and 46 responds independently to memory accesses respectively over either the host bus 38 or over the PE bus 64, an access on one of the buses 38 or 64 to the shared multi-port memory provided by the combined VRAMs 44 and 46 cannot block a simultaneous access to the multi-port memory on the other bus 64 or 38.
  • each PE 40 includes a PE CPU 82 which connects to the PE bus 64 and can exchange data with the VRAM 46 via the bus 64. Also included in the PE 40 and connected to the PE bus 64 may be one or more FPUs 84, four of which are illustrated in FIG. 1.
  • the PE CPU 82 transmits signals to the one or more FPUs 84 for controlling their operation via a FPU control signal bus 86.
  • the PE CPU 82 includes a Motorola MC68020 and the PE 40 includes at least one Motorola MC68882 FPU as its FPU 84. Because the PE 40 includes the Motorola MC68020 CPU and MC68882 FPU, the PE BUS 64 includes signals normally present in a computer system employing both a Mo.torola 68020 CPU and MC68882 FPU.
  • PE memory 92 Also connected to PE bus 64 is PE memory 92 that includes a stack and cache memory 94a.
  • the stack and cache memory 94a is relatively small, fast static RAM in which stacks created by a computer program executed by the PE CPU 82 are stored and in which temporary and intermediate results may also be stored.
  • the stack and cache memory 94a is provided by two Hitachi 6264P eight bit static RAM integrated circuits that are connected to the PE bus 64 for storing and retrieving sixteen bit words.
  • the PE memory 92 also includes an erasable programmable read only memory (“EPROM”) program memory 94b.
  • the program memory 94b includes two Texas Instruments 2764, 27128 or 27256 EPROM integrated circuits that are connected to the PE bus 64 for retrieving 16 bit words.
  • the program memory 94b stores programs that are executed by the PE CPU 82 including those program that it executes for communicating with the host personal computer 20 and for controlling the operation of the PE 40.
  • the memory 92 includes a Texas Instruments 20L8 Programmable Array Logic ("PAL") integrated circuit UA0 94c for controlling the operation of the stack and cache memory 94a and program memory 94b, and for transmitting a signal to the PE CPU 82 indicating when the stack and cache memory 94a, the program memory 94b and the second multi-port VRAM 46 ready to exchange data.
  • PAL Programmable Array Logic
  • the following table sets forth the pin numbers for the PAL UAO 94c together with the names of the signals either received by or transmitted from each pin.
  • the input signals FC0, FC1, A20-A23, AS* and R/W* come to the PAL UAO 94c from the Motorola MC68020 included in the PE CPU 82. (In the following and all subsequent signal names, the symbol "*" indicates the logical negation of the signal whose name immediately precedes the symbol.)
  • the input signals UDS* and LDS* come to the PAL UAO 94c from the PE CPU 82.
  • the input signal PE-MCS* and BDTACK* come to the PAL UAO 94c from the second multi-port VRAM 46.
  • the output signal BRAM* from the PAL UAO 94c is only used internally within the PAL in generating other output signals.
  • the PAL UAO 94c supplies its output signals READ*, WRITE* and SRAM* respectively to the OE*, WE* and CS* input terminals of the two 6264P eight bit static RAM integrated circuits in the stack and cache memory 92.
  • the PAL UAO 94c supplies its output signal PROM* to the E* input terminal of the two EPROMs in the program memory 94b.
  • the PAL UAO 94c supplies its output signal DTACK* to the PE CPU 82.
  • the PAL UAO 94c supplies its output signal HIF* to the PE-host interface circuit 58.
  • An address from the PE CPU 82 that lies in the range 200000H-3FFFFFH causes the PAL UAO 94c to assert its output signal BRAM*.
  • An address from the PE CPU 82 that lies in the range 000000H-0FFFFFH causes the PAL UAO 94c to assert its output signal PROM*.
  • An address from the PE CPU 82 that lies in the range 100000H-1FFFFFH causes the PAL UAO 94c to assert its output signal SRAM*.
  • An address from the PE CPU 82 that lies in the range 400000H-4FFFFFH causes the PAL UAO 94c to assert Its output signal HIF*.
  • the DTACK* signal indicates that the memory 92 and the second multi-port VRAM 46 are capable of exchanging data with the PE
  • All write operations to the memory 92 are performed early without wait states.
  • the PE CPU 82 can experience wait states during accesses to the second multi-port VRAM 46.
  • the PE CPU 82 includes a circuit for generating various synchronous clock signals used throughout the PE 40. Thus, the PE CPU 82 generates a 20 MHz SCLK signal which it supplies to the first VRAM control circuit 68, and another 20 MHz FFP-CLK signal which it supplies directly to the FPUs 84.
  • the PE CPU 82 generates a 20 MHz SCLK signal which it supplies to the first VRAM control circuit 68, and another 20 MHz FFP-CLK signal which it supplies directly to the FPUs 84.
  • the PE CPU 82 also generates a jumper selectable 10 or 20 MHz PCLK clock signal that is applied internally within the PE CPU 82 to the Motorola MC68020.
  • the PE CPU 82 generates a 10 MHZ PCLK* signal which it supplies to the second VRAM control circuit 74 for synchronization functions.
  • the PE CPU 82 also generates a jumper selectable 10 or 20 MHz PCLK clock signal that is applied internally within the PE CPU 82 to the Motorola MC68020.
  • the PE CPU 82 generates a 10 MHZ PCLK* signal which it supplies to the second VRAM control circuit 74 for synchronization functions.
  • the PE CPU 82 also generates a jumper selectable 10 or 20 MHz PCLK clock signal that is applied internally within the PE CPU 82 to the Motorola MC68020.
  • the PE CPU 82 generates a 10 MHZ PCLK* signal which it supplies to the second VRAM control circuit 74 for synchronization functions.
  • the PE CPU 82 also generates a jump
  • the PE CPU 82 also includes a reset circuit which automatically holds the MC68020 and all of the MC68882s reset for a time interval immediately following application of power
  • the reset circuit included in the PE CPU 82 may also be triggered by a signal from the PE-host interface circuit 58 that is generated in response to signals from the host personal computer 20. Within the PE CPU 82, a five volt positive signal is continuously applied through individual
  • PE CPU 82 of the preferred embodiment is a PAL UB9, not ⁇ illustrated in FIG. 1, for producing the control signals which the PE CPU 82 transmits to
  • the ⁇ PAL included in the PE CPU 82 for controlling the PE FPU is a 20L8 integrated circuit and is connected to the MC68020 and the one or more MC68882s and is programmed in accordance with the description set forth in the "MC68020 32-Bit Microprocessor User's Manual", Third Edition, 1989, 1988 by Motorola Inc., MC68020UM/AD REV 2, particularly as depicted in Figures 11-5 and 11-6 on pages 11-7 and 11-8 thereof, together with the text accompanying those figures. Accordingly, the "MC68020 32-Bit Microprocessor User's Manual" identified above is incorporated by reference as though fully set forth here.
  • the PE CPU 82 also includes a second 20L8 CPU control signal PAL UB10, not illustrated in FIG. 1, that adapts control signals present on the PE bus 64 from those for a Motorola MC68000 to those for a Motorola MC68020.
  • the adaptation of the PE 40 to use different microprocessors from the same family of Motorola microprocessors merely by the addition of the single PAL UB10 indicates the flexibility, adaptability and generality of the present invention.
  • the PAL UB10 receives as input signals from the MC68020 its address signals A0 and Al, its SIZO and SIZ1 signals, its address strobe signal AS*, its data strobe signal DS*, its read/write signal R/W*, and its external cycle start signal ECS*.
  • the PAL UB10 also receives interrupt signals IAV4*, IAV5*, IAV6* and IAV7* that originate in the PE-host interface circuit 58. While the PAL UB10 provides an input terminal for an interrupt signal IAV3*, that terminal is merely connected to a positive five volt potential through a resistor. Lastly, the PAL UB10 receives the signal DTACK* that originates in the PE Memory Controller PAL UAO 94c.
  • the PAL UB10 supplies to the Motorola MC68020
  • it supplies a UDS* and a LDS* signal to the PAL UAO 94c, and respectively to G* inputs of the two EPROM integrated circuits included in the program memory 94b.
  • the DSACK1* signal indicates completion of a data transfer requested by the Motorola MC68020. Because the memories stack and cache memory 94a and program memory 94b as well as the second multi-port VRAM 46 exchange only 16 bit words with the MC68020, a high logic level signal is continuously supplied to the DSACKO* input terminal of the MC68020.
  • the following table sets forth the pin numbers for the PAL UB10 toget r with the names of the signals either received by or transmitted from each pin.
  • IPL2* IAV7* & IAV6 & IAV5 & IAV4 & IAV3
  • the PE 40 includes a host-PE register 96 and a PE-host register 98.
  • the personal computer 20 transmits certain control signals to the PE CPU 82- by storing them into " the host-PE register 96 via the PE-host interface circuit 58 from which they may be subsequently fetched by the PE CPU 82.
  • the PE CPU transmits certain control signals to the personal computer 20 by storing them into the PE-host register 98 from which they may be subsequently fetched by the host personal computer 20 via the PE-host interface circuit 58.
  • FIGs. 2a-2d when assembled as illustrated in FIG. 2, form a detailed block diagram depicting, at the integrated circuit level, the VRAMs 44 and 46, the VRAM control circuits 68 and 74,. the PE-host interface circuit 58, and the registers 96 and 98. Also depicted down the left hand edge of the combined FIGs. are the ISA host bus 38 and its interface to the PE ISA bus 42.
  • FIG. 2b of the composite diagram depicts that the first multi-port VRAM 44 includes four Texas Instruments TMS4461 262,144 Bit Multiport VRAM integrated circuits 442a-442d. Similarly, FIG.
  • FIG. 2d of the composite diagram depicts that the second multi-port VRAM 46 also includes four TMS4461 262,144 Bit Multiport VRAM integrated circuits 462a-462d organized as 4 x 65,536 bits. That FIG. also depicts sixteen resistors 482a-482p having a resistance in the range of fifty to one- hundred ohms one of which is respectively located in each of the signal lines of the inter-memory bus 48 intermediate to the serial data in/data out shared port 52 of the first multi-port VRAM 44 and the serial data in/data out shared port 52 of the second multi-port VRAM 46.
  • the resistors 482a-482p provide isolation and termination resistances between the terminals of the VRAM integrated circuits 442a-442d that connect to the inter-memory bus 48 and the corresponding terminals of the VRAM integrated circuits 462a-462d that also connect to the inter- memory bus 48.
  • FIGs. 2a and 2b of the composite diagram show that the PE host bus 56 includes a host control signal section 562, a host buffered address section 564, and a host buffered data section 566.
  • FIGs. 2c and 2d of the composite diagram show that the PE bus 64 includes a PE control signal section 642, a PE address section 644, and a PE data section 646.
  • FIG. 2b of the composite diagram shows that the first VRAM control and address bus 66 includes a first VRAM control signal section 662 and a first VRAM address section 664.
  • the first VRAM control circuit 68 includes three 20L8 PAL integrated circuits UA5 682a, UA6 682b, UA7 682c, a Texas Instruments TMS 34061 Video System Controller (“VSC") 684, a 74F74 flip-flop 686, and two 74F04 inverters 688a and 688b.
  • FIG. 2d of the composite diagram shows that the second VRAM control and address bus 72 includes a second VRAM control signal section 722 and a second VRAM address section 724.
  • the second VRAM control circuit 74 includes a single 20L8 PAL integrated circuit UA13 742, a TMS 34061 VSC 744, two 74F113 flip-flops 746a and 746b, and a 74F04 inverter 748.
  • the PE ISA bus 42 supplies an electrical ground 782 and a positive five volt potential 784 from the host personal computer 20 to the electrical circuits of the PE 40.
  • FIGs. 2a and 2c which depict the PE-host interface circuit 58 shows that it includes a first pair of 74F245 data transceivers 802a and 802b and a second pair of 74F245 register transceivers 804a and 804b.
  • a first set of bidirectional signal terminals for the data transceivers 802a and 802b and a corresponding first set of bidirectional signal terminals for the register transceivers 804a and 804b connect to a SD section 806 of the PE ISA bus 42.
  • the SD section 806 of the PE ISA bus 42 receives data signals SD00-SD15 from the host bus 38 and conducts those signals to the transceivers 802a-b and 804a-b.
  • a second set of bidirectional signal terminals for the data transceivers 802a and 802b connect to the host buffered data section 566 of the PE host bus 56 while a second set of bidirectional signal terminals for the register transceivers 804a and 804b connect to a register bus 808.
  • signals present on the SD00-SD15 signal lines of the host bus 38 are transferred to the host buffered data section 566 of the PE-host bus 56, or conversely.
  • signals present on the SD00-SD15 signal lines of the host bus 38 are transferred to the register bus 808 or conversely.
  • the PE-host interface circuit 58 controls the operation of the transceivers 802a-b and 804a-b to transfer SD00-SD15 signals present on the host bus 38 to the host buffered data section 566 and to the register bus 808 during either memory write or I/O write operations. Conversely, the host interface circuit 58 controls the transceivers 802a-b and 804a-b to transfer signals both from the host buffered data section 566 and from the register bus 808 to the SD00-SD15 signal lines of the host bus 38 during either a memory read or I/O read operation on the ISA host bus 38.
  • FIGs. 2a and 2c which depict the PE-host interface circuit 58 also shows that it includes a pair of series connected 74F04 inverters 812a and 812b, a pair of 74LS541 buffers 814a and 814b and a 74F373 latch 816.
  • Output terminals of the inverter 812b, the buffers 814a and 814b, and the latch 816 all connect to the host buffered address section 564 of the PE host bus 56.
  • Input terminals of the inverter 812a and the buffers 814a and 814b connect to a SA section 818 of the PE ISA bus 42.
  • the SA section 818 of the PE ISA bus 42 receives address signals SA00-SA16 from the host bus 38 and conducts those signals to the input terminal of the inverter 812a and to the input terminals of the buffers 814a and 814b. Control signals applied to the pair of buffers 814a and 814b enable them together with the series connected inverters 812a and 812b to continuously transfer address signals present on the SA section 818 of the PE ISA bus 42 to the host buffered address section 564 of the PE host bus 56. Input terminals of the latch 816 are connected to a LA section 822 of the PE ISA bus 42.
  • the LA section 822 of the PE ISA bus 42 receives address signals LA17-LA23 from the host bus 38 and conducts those signals to the input terminals of the latch 816.
  • a control signal input terminal of the latch 816 connects to a BALE signal line 824 included in the host control signal section 562 of the PE host bus 56.
  • the BALE signal line 824 receives a BALE control signal from the host bus 38. While the host personal computer 20 is operating, valid address signals SA00-SA16 are always present on the host bus 38. Therefore, the pair of inverters 812a and 812b and the pair of buffers 814a and 814b continuously receive such valid address signals from the SA section 818 and transfer those address signals to the host buffered address section 564 of the PE host bus 56.
  • the latch 816 responds to the signal present on the BALE signal line 824 to accept the LA17-LA23 address signals from the host bus 38 and to transfer those signals to the host buffered address section 564 of the PE host bus 56.
  • the latch 816 stores the valid address signals that it received most recently and continues supplying the host buffered address section 564 of the PE host bus 56 with the stored address signals.
  • the inverters 812a and 812b, the buffers 814a and 814b, and the latch 816 continuously supply the host buffered address section 564 of the PE host bus 56 with a set of address signals H-AO through H-A23 that correspond exactly to the address signals on the host bus 38.
  • FIGs. 2a and 2c which depict the PE-host interface circuit 58 also shows that it includes a first AM25LS2521 selector 832.
  • a first set of input terminals to the selector 832 connects individually to a portion of the signal lines present in the host buffered address bus 564 of the PE host bus 56 to receive the address signals H-A12 through H-A19.
  • a second set of input terminals to the selector 832 connect individually via a set of jumper lines 834 to one-half of a set of jumpers pins 836. The other half of the jumper pins 836 connect to electrical ground 782.
  • the jumper lines 834 also connect individually through resistors 838 to the positive five volt potential 784.
  • the positive five volt potential is applied through the individual resistors 838 and jumper lines 834 to all terminals in the second set of input terminals to the selector 832. If a jumper is installed between a pair of jumper pins 836, then ground potential is applied to the corresponding input terminal of the second set of input terminals to the selector 832.
  • the selector 832 continuously compares the signals present at its first set of input terminals with those present afe its second set of input terminals.
  • the selector 832 transmits a signal indicating the occurrence of the matching condition onto a H-CSEL* signal line 842 included in the host control signal section 562 of the PE host bus 56.
  • the host control signal section 562 of the PE host bus 56 transmits the signal on the H-CSEL* signal line to the PAL UA7 682c included in the first VRAM control circuit 68.
  • the signal present on the H-CSEL* signal line controls whether or not the VSC 684 will respond to address signals on the host buffered address section 564 of the PE host bus 56 for exchanging data with the host personal computer 20 via the host buffered data section 566 of the PE host bus 56.
  • the installation or removal of jumpers from the jumper pins 836 permits setting an address range on the host bus 38 throughout which the host personal computer 20 may store data into or retrieve data from the VSC 684. This address range is 00 0XXXH to OF FXXXH with the address usually being set to 0D CXXXH.
  • the PE-host interface circuit 58 also includes a second AM25LS2521 selector 852.
  • selector 852 some of its first set of input terminals connect to the host buffered address section 564 of the PE host bus 56 to receive address signals H-A20 through H-A23.
  • a second set of input terminals of the selector 852 i.e. those input terminals which are compared with the terminals of the first set of input terminals that receive the signals H-A20 through H-A23, connect via jumper lines 854 to one-half of a set of jumpers pins 856 and also connect through resistors 858 to the positive five volt potential 784.
  • the input terminals of the selector 852 which do not receive either an address signal or a signal from the jumper lines 854 are connected to electrical ground 782. If the set of input signals H-A20 through H-A23 supplied to the first set of input terminals of the selector 852 match the set of input signals supplied by the jumper lines 854 to the second set of input terminals, then the selector transmits a signal indicating that matching condition onto H-MSEL* signal line 862 included in the host control signal section 562 of the PE host bus 56. The host control signal section 562 of the PE host bus 56 transmits the signal on the H-MSEL* signal line to the PAL UA7 682c included in the first VRAM control circuit 68.
  • the signal present on the H-MSEL* signal line controls whether or not the VSC 684 included in the first VRAM control circuit 68 will respond to address signals on the host buffered address section 564 of the PE host bus 56 for addressing the first multi-port VRAM 44 for exchanging data between the VRAM 44 and the host personal computer 20 via the host buffered data section 566 of the PE host bus 56.
  • the installation or removal of jumpers from the jumper pins 856 permits setting the address range on the host bus 38 at which the host personal computer 20 may store data into or retrieve data from the VRAM 44. This address range is OX XXXXH to FX XXXH with the address usually being set to 50 0000H.
  • the PE-host interface circuit 58 includes a set of interrupt selection jumper pins 872.
  • One side of the jumper pins 872 connects to individual lines for IAV4*, IAV5*, IAV6* and IAV7* signals in the PE control signal section 642 of the PE bus 64.
  • the other side of the jumper pins 872 all connect in parallel to a PC-INT* signal line 874 in an interface circuit bus 882. Installation of a jumper between a particular pair of jumper pins 872 selects a particular priority level for interrupt signals that are applied to the Motorola MC68020 included in the PE CPU 82.
  • the PE-host interface circuit 58 includes a pair of 74F04 inverters 892 and 894. Inputs of the inverters 892 and 894 respectively receive the signals PE-WTD* and H-WTD* from the interface circuit bus 882. The outputs of the inverters 892 and 894 respectively transmit the signals PE-WTD and H-WTD back to the interface circuit bus 882.
  • the PE-host interface circuit 58 also includes a 74F74 host-PE flip-flop 902 having a CP input which receives the H-WTD signal from the inverter 894. The D and SD inputs of the host-PE flip-flop 902 receive the positive five volt potential 784 through a resistor 904.
  • the RD input of the host-PE flip- flop 902 receives a PE-RDD* signal from the interface circuit bus 882. Responsive to these input signals, one state of the host-PE flip-flop 902 indicates that the host personal computer 20 has stored data in the host-PE register 96 and that the PE CPU 82 has not yet read the data stored there. The other state of the host-PE flip-flop 902 indicates that the PE CPU 82 has read any previously stored data from the host-PE register 96, and that the host personal computer 20 may therefore store new data into the register 96.
  • the PE-host interface circuit 58 also includes a 74F74 PE-host flip-flop 906.
  • the D and CP inputs of the PE-host flip-flop 906 receive the positive five volt potential 784 through the resistor 904.
  • the SD input of the PE-host flip- flop 906 receives the PE-WTD* signal from the interface circuit bus 882 while its RD input receives a H-RDD* signal from the bus 882.
  • the state of the PE-host flip-flop 906 indicates whether the PE CPU 82 has stored data for the host personal computer 20 into the PE-host register 98, or whether the host personal computer 20 has already read the last such data stored there and that, therefore, the PE CPU 82 may store new data into the PE-host register 98.
  • the PE-host interface circuit 58 includes three 20L8 PALs UA35 912a, UA36 912b and UA37 912c.
  • the first of these PALs, UA35 912a receives, via the SA section 818 of the PE ISA bus 42, the SAOO-SAll address signals from the host bus 38 of the host personal computer 20.
  • the PAL UA35 912a also receives, via the interface circuit bus 882, a IO-SEL* signal and a HI* signal from the PAL UA37 912c.
  • the PAL UA35 912a Responsive to these input signals, the PAL UA35 912a transmits H-DSEL*, H-SSEL*, FUNCT-A, FUNCT-B, PC-INT*, and PORT-EQ* signals via the interface circuit bus 882.
  • the PAL UA35 912a also transmits a PETRGRST signal to the PE CPU 82 via the PE control signal section 642 of the PE bus 64 for resetting the Motorola MC68020 and MC68882 ⁇ s) included in the PE CPU 82 together with the VSC(s) 684 and 744, and the flip-flops described above.
  • the following table sets forth the pin numbers for the PAL UA35 912a together with the names of the signals either received by or transmitted from each of its pins.
  • An address on the SAOO-SAll signal lines from the host personal computer 20 that lies in the range 0304H-0307H causes the PAL UA35 912a to assert its output signal H-DSEL*.
  • An address on the SAOO-SAll signal lines from the host personal computer 20 that lies in the range 0300H-0303H causes the PAL UA35 912a to assert its output signal H-SSEL*.
  • An address on the SAOO-SAll signal lines from the host personal computer 20 5 that lies in the range 0308H-030BH causes the PAL UA35 912a to assert its output signal PETRGRST thereby resetting the Motorola MC68020 included in the PE CPU 82.
  • An address on the SAOO-SAll signal lines from the host personal computer 20 that lies in the range 0314H-0317H causes the PAL UA35 912a to
  • the PAL UA36912b receives input signals Al, A2, RESET*, and R/W* from the Motorola MC68020 included in the PE CPU 82.
  • the PAL UA36 912b receives the input signal HIF* from the PAL UAO 94c in the memory 92.
  • the PAL UA36 912b receives input signals H-DA and H-DU from the host-PE flip-flop 902.
  • the PAL UA36 912b receives input signals PE-DA and PE-DU from the PE-host flip-flop 906.
  • the PAL UA36 912b receives input
  • the PAL UA36 912b receives input signals BIOW* and BIOR* from the PAL UA37 912c.
  • the PAL UA36 912b transmits signals D16 and D17 to the Motorola MC68020 included in the PE CPU 82. (With regard to nomenclature for the data signal lines of the Motorola MC68020,
  • the PAL UA36 912b supplies signals H-RDD* and PE-WTD* to the host-PE flip-flop
  • the PAL UA36 912b supplies the signals IO-D00 and IO-D01 to the transceiver 804a via the register bus 808 for transmission to the host bus 38 of-the personal computer 20 as data bits SD00 and SD01.
  • the following table sets forth the pin numbers for the PAL UA36 912b together with the names of the signals either received by or transmitted from each of its pins.
  • Equations for the output signals from the PAL UA36 912b which specify the logical relationships that exist between the input signals to the PAL UA36 912b and its output signals.
  • the 20L8 PAL integrated circuit used for the PAL UA36 912b has tri-state output drivers that may be set to a high impedance state by an input signal applied to an input terminal of the PAL.
  • the phrase "IF(signal name)" indicates that the output driver for the signal whose equation follows the phrase is enabled to transmit an output signal only upon the occurrence of the specified condition.
  • H-RDD* H-DSEL* & BIOR* + RESET* H-WTD* H-DSEL* & BIOW*
  • the PAL UA37 912c receives input signals MEMW*, MEMR*, IOW*, IOR*, SMEMW*, SMEMR*, AEN and SBHE* from the host bus 38 in the personal computer 20 via the PE ISA bus 42 and the host control signal section 562 of the PE host bus 56.
  • An input terminal of the PAL UA37 912c connects to a SA00 address line 922 in the SA section 818 of the PE ISA bus 42 to receive the SA00 address signal from the host bus 38.
  • the PAL UA37 912c receives the PORT-EQ* signal from the PAL UA35 912a via the interface circuit bus 882.
  • the PAL UA37 912c supplies output signals HI* and IO-SEL* to the PAL UA35 912a via the interface circuit bus 882.
  • the PAL UA37 912c supplies output signals BIOW* and BIOR* to the PAL UA36 912b via the interface circuit bus 882.
  • the PAL UA37 912c also supplies the output signal BIOR* to the SR* input terminals of the transceivers 802a-b and 804a-b.
  • the PAL UA37 912c supplies output signals LO-E* and HI-E* respectively to the CE* input terminals of the transceivers 802a and 802a, and to the CE input terminals of the transceivers 802b and 804b.
  • the following table sets forth the pin numbers for the PAL UA37 912c together with the names of the signals either received by or transmitted from each of its pins.
  • IO-SEL* IOW* & AEN* & PORT-EQ*
  • HI-E* IOR* & PORT-EQ* & AEN* & SBHE* + IOW* & PORT-EQ* & AEN* & SBHE*
  • the host-PE register 96 includes two 74F373 latches 962a and 962b for storing a sixteen bit data word of control and status signals that the host personal computer 20 may transmit to the PE CPU 82.
  • the OE* input terminal of the latches 962a and 962b receives the PE-RDD* signal from the PAL UA36 912b via the interface circuit bus 882.
  • the E input terminal of the 962a and 962b receives the H-WTD signal from the inverter 894 via the interface circuit bus 882.
  • the 96 includes two 74F373 latches 982a and 982b for storing a sixteen bit data word of control and status signals that the PE CPU 82 may transmit to the host personal computer 20.
  • the OE* input terminal of the latches 982a and 982b receives the H-RDD* signal from the PAL UA36912b via the interface circuit bus 882.
  • the E input terminal of the 982a and 982b receives the PE-WTD signal from the inverter 892 via the interface circuit bus 882.
  • the host personal computer 20 exchanges data signals SD00-SD03 of the host bus 38 with DQ0-DQ3 terminals of the VRAM integrated circuit 442a included in the first multi-port VRAM 44 via the PE ISA bus 42, the transceiver 802a, and data signal lines H-D0 through H-D31002a of the host buffered data section 566 of the PE host bus 56.
  • host personal computer 20 exchanges data signals SD04-SD07 with the VRAM integrated circuit 442b on data signal lines H-D4 through .H-D7 1002b of the host buffered data section 566.
  • the host personal computer 20 exchanges data signals SD08-SD11 with the VRAM integrated circuit 442c on data signal lines H-D8 through H-Dll 5 1002c of the host buffered data section 566 except that the signals pass through the transceiver 802b rather than the transceiver 802a.
  • host personal computer 20 exchanges data signals SD12-SD15 with the VRAM integrated circuit 442b on data signal lines H-D12 through H-D15 1002d of
  • the SDQ0-SDQ3 terminals of the VRAM integrated circuit 442a included in the first multi-port VRAM 44 exchange data with the SDQ0-SDQ3 terminals of the VRAM integrated circuit 462a included in the second multi-port VRAM 46 via IM0-IM3 5 signal lines 1004a in the inter memory bus 48.
  • the VRAMs 442b and 462b exchange data via IM4-IM7 signal lines 1004b in the inter memory bus 48
  • the VRAMs 442c and 462c exchange data via IM8-IM11 signal lines 1004c
  • the VRAMs 442d and 462d exchange data via IM12-IM15 signal lines 1004d.
  • A0-A7 terminals of each of the four VRAM integrated circuits 442a-442d receive address signals from the VSC 684 included in the first VRAM control circuit 68 on address lines H-MA0 through H-MA7 1006. Via the first VRAM
  • a RAS* terminal of each of the four VRAM integrated circuits 442a-442d receives a H-RAS0* signal from the VSC 684
  • a TRG* terminal receives a H-TRG* signal from the VSC 684.
  • a CAS* terminal of each of the VRAMs 442a and 442b receives a
  • H-CASLO* signal from the VSC 684 via the first VRAM control section 662 of the first VRAM control and address bus 66 while the CAS* terminals of each of the VRAMs 442c and 442d receives a H-CASHI* signal from the VSC 684.
  • a SE* terminal of each of the VRAMs 442a-442d receives a H-SOE* signal from the PAL UA5
  • a W* terminal of each of the VRAMs 442a and 442b receives a H-WLO* signal from the PAL UA6 682b via the first VRAM control section 662 of the first VRAM control and address bus 66 while the W* terminals of each of the VRAMs 442c and 442d receives a H-WHI* signal from the PAL UA6 682b.
  • VRAMs 442a-442c Analogous to the VRAMs 442a-442c, via data signal lines D16 through D19 1012a in the PE data section 646 of the PE bus 64, DQ0-DQ3 terminals of the VRAM 462a included in the second multi-port memory 46 respectively receive data signals D16 through D19 from the Motorola MC68020 included in the PE CPU 82.
  • DQ0-DQ3 terminals of the VRAM 462a included in the second multi-port memory 46 respectively receive data signals D16 through D19 from the Motorola MC68020 included in the PE CPU 82.
  • data signal lines D20 through D23 1012b the VRAM 462b receives data signals D20 through D23 from the Motorola MC68020
  • data signal lines D24 through D27 1012c the VRAM 462c receives data signals D24 through D27
  • signal lines D28 through D31 1012d the VRAM 462d receives data signals D28 through D31.
  • A0-A7 terminals of each of the four VRAM integrated circuits 462a-462d receive address signals from the VSC 744 included in the second VRAM control circuit 74 on address lines PE-MAO through PE-MA71016.
  • a RAS* terminal of each of the four VRAM integrated circuits 462a-462d receives a PE-RAS0* signal from the VSC 744, and a TRG* terminal receives a PE-TRG* signal from the VSC 744.
  • a CAS* terminal of each of the VRAMs 462a and 462b receives a PE-CASL0* signal from the VSC 744 via the second VRAM control section 722 of the second VRAM control and address bus 72 while the CAS* terminals of each of the VRAMs 462c and 462d receives a PE-CASHI* signal from the VSC 744.
  • a SE* terminal of each of the VRAMs 462a-462d receives a PE-SOE* signal from the PAL UA5 682a via the second VRAM control section 722 of the second VRAM control and address bus 72 while a SC terminal of each of the VRAMs 462a-462d receives a XSCLK signal from the PAL UA5 682a.
  • a W* terminal of each of the VRAMs 462a and 462b receives a PE-WLO* signal from the PAL UA6 682b via the second VRAM control section 722 of the second VRAM control and address bus 72 while the W* terminals of each of the VRAMs 462c and 462d receives a PE-WHI* signal from the PAL UA6 682b.
  • the host personal computer 20 exchanges data signals SD00-SD07 of the host bus 38 with D0-D7 terminals of the VSC 5 684 included in the first VRAM control circuit 68, via the data signal lines H-DO through H-D3 1002a and H-D4 through H-D7 1002b of the host buffered data section 566 of the PE host bus 56, that also respectively connect to the VRAM integrated circuits 442a and 442b in the first multi-port VRAM 44.
  • the host personal computer 20 exchanges data signals SD00-SD07 of the host bus 38 with D0-D7 terminals of the VSC 5 684 included in the first VRAM control circuit 68, via the data signal lines H-DO through H-D3 1002a and H-D4 through H-D7 1002b of the host buffered data section 566 of the PE host bus 56, that also respectively connect to the VRAM integrated circuits 442a and 442b in the first multi-port VRAM 44.
  • host personal computer 20 supplies address signals SA1-SA8 of the host bus 38 to CA0-CA7 terminals of the VSC 684, via H-Al through H-A8 signal lines 1022a included in the host buffered address section 564 of the PE host bus 56.
  • the host personal computer 20 also supplies address signals SA9-SA16 of the host
  • HSYNC*, VSYNC* and RESET* terminals of the VSC 684 respectively, receive signals from the HSYNC*, VSYNC* and
  • VSC 744 20 RESET* terminals of the VSC 744, via the VRAM synchronization signal bus 76.
  • Supplying these three signals from the VSC 744 to the VSC 684 slaves the operation of the SDQ0-SDQ3 terminals of the VRAM integrated circuits 442a-442d to the operation of the SDQ0-SDQ3 terminals of the VRAM integrated circuits
  • the inverter 688a receives the CLK signal from the riost bus 38 of the personal computer 20 via the host control signal section 562 of the PE host bus 56.
  • the output signal from the inverter 688a which is the logical inverse of the CLK signal of the host personal computer 20, is supplied as an input signal to the inverter 688b and to the CP input of the flip- flop 686.
  • the inverter 688a supplies an output signal, H-SYSCLK, to a SYSCLK terminal of the VSC 684 via the first VRAM control signal section 662 of the first VRAM control and address bus 66.
  • the H-SYSCLK signal is the same as the CLK signal of the host personal computer 20 delayed by the transmission delays of the inverters 688a and 688b.
  • the D input of the flip-flop 686 receives a H-ALE* signal from the PAL UA6 682b.
  • the Q output of the flip-flop 686 supplies a H-XALE* to an ALE terminal of the VSC 684 via the first VRAM control signal section 662.
  • the flip-flop 686 Since the flip-flop 686 operates synchronously with the CLK signal of the host personal computer 20, its operation synchronizes the H-ALE* signal from the PAL UA6 682b to the CLK signal of the host personal computer 20 before transmitting the H-ALE* signal to the ALE terminal of the VSC 684 as the H-XALE* signal.
  • Input terminals CEH* and CEL* of the VSC 684 receive H-CEH* and H-CEL* signals from the PAL UA5 682a via the first VRAM control signal section 662 of the first VRAM control and address bus 66.
  • Input terminals FS0, FS1, FS2, and CS* of the VSC 684 respectively, receive H-FS0, H-FS1 and H-FS2 signals from the PAL UA7 682c via the first VRAM control signal section 662.
  • a R/W* input terminal of the VSC 684 receives the MEMW* signal from the host bus 38 of the personal computer 20 via the host control signal section of the 562 of the PE host bus 56.
  • a VDCLK input terminal of the VSC 684 receives the 5 MHZ BCLK signal from the CPU 82 via the PE control signal section 642 of the PE bus 64.
  • Input terminals HOLDACK*, RS0 and RSI of the VSC 684 are connected to electrical ground potential 782.
  • a BLANK* output terminal of the VSC 684 transmits a SGATE* signal to the PAL UA5 682a via the first VRAM control signal section 662.
  • 15 terminals of the VSC 684 respectively transmit a H-RDY* signal and a H-W* signal to the PAL UA6 682b via the first VRAM control signal section 662.
  • the PAL UA5 682a receives, as an input signal, the A15 address signal from the Motorola MC68020 included in the PE CPU 82.
  • the PAL UA5 682a receives as an input signal the 20 MHz SCLK signal from the PE CPU 82.
  • the SA00, SA09 and SA10 address signals from the host bus 38 of the personal computer 20 are supplied as input signals HA-00, HA-09 and HA-10 to the PAL UA5 682a via the host buffered address section 564 of the PE host bus 56.
  • the PAL UA5 Via the host control section 562 of the PE host bus 56, the PAL UA5
  • the PAL UA5 682a receives as an input signal the SBHE control signal from the host bus 38. Via the first VRAM control section 662 of the first VRAM control and address bus 66, the PAL UA5 682a receives as an input signal the SGATE* signal from the VSC 684. Via the first VRAM control section 662, the PAL UA5 682a
  • the PAL UA5 682a receives as input signals PE-FSO, PE-FS1 and PE-FS2 from ' the
  • the PAL UA5 682a transmits the CEL* and CEH* signals to the VSC 684 via the first VRAM control signal section 662 of the first VRAM control and address bus 66.
  • the PAL UA5 682a transmits the XSCLK signal to the VRAM integrated circuits
  • the PAL UA5 682a transmits the H-SOE* signal to the VRAMs 442a-442d, and to a
  • H-CEL* H-MCS* & H-A0*
  • H-CEH* H-MCS* & SBHE*
  • H-XSOE* H-FSO* & H-FSl* & H-FS2 & H-A9 & H-A10
  • PE-XSOE* PE-FSO* & PE-FS1* & PE-FS2 & A15
  • PE-SOE* PE-XSOE
  • the PAL UA6 Via the first VRAM control signal section 662 of the first VRAM control and address bus 66, the PAL UA6 682b receives input signals H-CASLO*, H-CASHI*, H-W*, H-TRG* and H-RDY* from the VSC 684 included in the first VRAM control circuit 68. Via the second VRAM control signal section 722 of the second VRAM control and address bus 72, the PAL UA6 682b receives input signals PE-CASLO*, PE-CASHI*, PE-W* and PE-TRG* from the VSC 684 included in the first VRAM control circuit 68.
  • the PAL UA6 682b receives input signals H-FSO, H-FSl and H-FS2 from the PAL UA7 682c.
  • the personal computer 20 supplies signals MEMR*, MEMW* and AEN of the host bus 38 to the PAL UA6 682b.
  • the PAL UA6 682b transmits signals H-WHI* and H-WLO* to the VRAM integrated circuits 442a-442d, via the first VRAM control signal section 662 of the first VRAM control and address bus 66 as described above. Via a second VRAM control signal section 722 of the second VRAM control and address bus 72, the PAL UA6 682b transmits signals PE-WHI* and PE-WLO* respectively to a W* input terminal of VRAM integrated circuits 462c and 462d, included in the second multi-port VRAM 46, and to a W* input terminal of the VRAM integrated circuits 462a and 462b.
  • the PAL UA6 682b transmits a H-ALE* signal to the flip- flop 686 via the second VRAM control signal section 622 as described above. Via the host control signal section 562 of the PE host bus 56, the PAL UA6 682b transmits the IOCHRDY signal to the host bus 38 of the personal computer 20.
  • the following table sets forth the pin numbers for the PAL UA6 682b together with the names of the signals either received by or transmitted from each of its pins.
  • H-ALE* AEN* & H-FSO* & MEMR* + AEN* & H-FSO* & MEMW*
  • H-WLO* H-W* & H-CASLO* + H-W* & H-TRG*
  • H-WHI* H-W* & H-CASHI* + H-W* & H-TRG*
  • PE-WLO* PE-W* & PE-CASLO* + PE-W* & PE-TRG*
  • PE-WHI* PE-W* & PE-CASHI* + PE-W* & PE-TRG*
  • the personal computer 20 supplies signals DACKO*, MEMR* and MEMW* of the host bus 38 as input signals to the PAL UA7 682c.
  • the PAL UA6682c also receives input signals H-MSEL* and H-CSEL* via the host control signal section 562 from the selectors 832 and 852.
  • the pe'rsonal computer 20 supplies address signals SA09-SA15 as input signals to the PAL UA7 682c.
  • the PAL UA6 682c transmits output signals H-FSO, H-FSl, H-FS2, and H-MCS* to the PALs UA5 682a and UA6 682b, and to the VSC 684 included in the first VRAM control circuit 68.
  • the following table sets forth the pin numbers for the PAL UA7 682c together with the names of the signals either received by or transmitted from each of its pins.
  • H-S2R* H-CSEL* & DACKO & MEMR* & H-A15* & H-A14*
  • H-R2S* H-CSEL* & DACKO & MEMR* & H-A15* & H-A14*
  • H-REGS* H-CSEL* & DACKO & MEMR* & H-A15* & H-A14*
  • H-XY* H-CSEL* & DACKO & MEMR* & H-A15* & H-A14*
  • H-FSO H-S2R* + H-REGS*
  • H-FSl H-R2S* + H-S2R* + H-REGS* + H-XY*
  • H-FS2 H-REGS* + H-XY*
  • H-MCS* H-MSEL* & DACKO & MEMR* + H-MSEL* & DACKO & MEMW* + H-R2S* + H-S2R* + H-REGS*
  • the PE CPU 82 exchanges data signals D16-D23 with DO- D7 terminals of the VSC 744, included in the second VRAM control circuit 74, via the data signal lines D16 through D19 1012a and D20 through D23 1012b of the PE data section 646 of the PE bus 64, that also respectively connect to the VRAM integrated circuits 462a and 462b in the second multi-port VRAM 46.
  • the PE CPU 82 supplies address signals A1-A8 to CA0-CA7 input terminals of the VSC 744 via Al through A8 signal lines 1032a included in the PE address section 644 of the PE bus 64.
  • the PE CPU 82 also supplies address signals A9-A16 to RA0-RA7 terminals of the VSC 744 via A9 and A8 signal lines 1032b included in the PE address section 644.
  • RSO and RSI input terminals of the VSC 744 receive address signals A22 and A23 via A22 and A23 signal lines 1032c included in the PE address section 644.
  • HSYNC*, VSYNC* and RESET* terminals of the VSC 744 respectively transmit signals to the HSYNC*, VSYNC* and RESET* terminals of the VSC 684 via the VRAM synchronization signal bus 76 as described above.
  • Input terminals ALE, FS0, FS1, FS2, CEH*, CEL*, and CS* of the VSC 744 respectively receive PE-ALE, PE-FSO, PE-FS1, PE-FS2, PE-CEH*, PE-CEL* and PE-MCS* signals from the PAL UA13 742 via the second VRAM control signal section 722 of the second VRAM control and address bus 72.
  • a R/W* input terminal of the VSC 744 receives the R/W* signal from the Motorola MC68020 included in the PE CPU 82 via the PE control signal section 642 of the PE bus 64.
  • a VDCLK input terminal of the VSC 744 receives the 5 MHZ BCLK signal from the CPU 82 via the PE control signal section 642 of the PE bus 64; while a SYSCLK input terminal of the VSC 744 receives the PCLK signal from the CPU 82.
  • Input terminals HOLDACK* of the VSC 744 connects to the positive five volt potential 784 through a resistor 1034.
  • Output terminals MA0-MA7 of the VSC 744 supply address signals to the VRAM integrated circuits 462a-462d via the address lines PE-MAO through PE-MA7 1016.
  • Output signals from terminals CASHI*, CASLO*, TR*/QE*, and RASO* of the VSC 744 respectively transmit PECASHI*, PECASLO*, PE-TRG* and PE-RAS0* signals to the VRAM integrated circuits 462a-462d, via the second VRAM control signal section 722 of the second VRAM control and address bus 72, as described in greater detail above.
  • the output signals from terminals CASHI*, CASLO*, TR*/QE*, and W* of the VSC 744 respectively transmit the PECASHI*, PECASLO*, PE-TRG* and a PE-W* signals to the PAL UA6 682b via second VRAM control section 722 of the second VRAM control and address bus 72.
  • a RDY*/HLD* output terminal of the VSC 744 transmits a PE-RHD* signal to the input of the inverter 748 via the second VRAM control signal section 722 of the second VRAM control and address bus 72.
  • the second VRAM control circuit 74 includes a circuit for synchronizing a PE-ALE signal to the PCLK supplied within the PE CPU 82 to the Motorola MC 68020.
  • the PCLK signal is supplied, via a PCLK signal line 1036 in the PE control signal section 642 of the PE bus 64, to the CP input terminal of the flip-flop 746a.
  • the Jl input terminal of the flip-flop 746a connects to electrical ground 782, while its Kl input terminal connects to the positive five volt potential 784 through a resistor 1042.
  • the PAL UA13 742 supplies a PE-DS signal to the SD1 input terminal of the flip-flop 746a.
  • the flip-flop 746a transmits a VAD signal from its Ql output terminal to the PAL UA13 742 via the second VRAM control signal section 722 of the second VRAM control and address bus 72.
  • the CP input terminal of the flip-flop 746b receives the PCLK signal.
  • the VSC 744 supplies a PE-RDH* signal to the input terminal of the inverter 748, that also connects to the positive five volt potential 784 through a resistor 1044.
  • the inverter 748 supplies a PE-RDH signal to the SD1 input terminal of the flip-flop 746b.
  • the flip-flop 746b transmits a BDTACK* signal from its Q2 output terminal to the PAL UAO 94c, via the second VRAM control signal section 722 of the second VRAM control and address bus 72.
  • the PAL UA13 742 receives input address signals A16- A23 from the Motorola MC68020 included in the PE CPU 82 via the
  • the PAL UA13 742 Via the PE control signal section 642 of the PE bus 64, the PAL UA13 742 also receives a DS input signal from the Motorola MC68020 together with PE-LDS* and a PE-UDS* signals- from the PAL UB10 included in the PE CPU 82.
  • the PAL UA13 742 receives a VAD input signal from the flip-flop 746a.
  • the PAL UA13 742 transmits signals PE-ALE, PE-FSO, PE-FSl, PE-FS2, PE-CEH*, PE-CEL*, and PE-MCS* to the VSC 744.
  • the PAL UA13 742 also transmits signals PE-FSO, PE-FSl and PE-FS2 to the PAL UA5 682a included in the first VRAM control circuit 68.
  • the PAL UA13 742 transmits a PE-DS signal to the inverter 748.
  • the following table sets forth the pin numbers for the PAL UA13 .742 together with the names of the signals either received by or transmitted from each of its pins.
  • PE-CEL* DS* & VAD*
  • PE-CEH* DS* & VAD*
  • PE-ALE* DS* & VAD*
  • PE-DS DS*
  • FIG. 3 depicts the allocation of memory address space in the host personal computer 20 on the left hand side of the FIG. and in the PE 40 on the right hand side.
  • the host addresses for the first multi-port VRAM 44 begins at 50 0000H.
  • the host usually addresses the registers that are in the VSC 68 beginning at 0D 0000H.
  • the host-PE register 96 and the PE-host register 98 are usually addressed in the I/O address space of the host digital computer 20 beginning at location 300H.
  • the EPROM of the program memory 94b begins at address 0000:0400H immediately above the area reserved for the Motorola MC68020's start up and exception vectors.
  • Addresses for the static RAM of the stack and cache memory 94a begin at 001O:O000H.
  • Addresses for the second multi-port VRAM 46 begin at 0020:0000H.
  • the host addresses the registers that are in the VSC 74 beginning at 0030:0000H.
  • the host-PE register 96 and the PE-host register 98 are addressed beginning at location 0040:0000H.
  • the host-PE register 96 and the PE-host register 98 Depicted in FIG. 4 are the host-PE register 96 and the PE-host register 98. If either of the registers 96 or 98 are presently transmitting data respectively from the host personal computer 20 to the PE 40 or conversely, all bits in the registers are used for 16 or 8 bit data words. If either of the registers 96 or 98 are presently transmitting status information, then only bits bO and bl are used. When transmitting status information to the host personal computer 20, the PAL UA36 912b transmits the H-DU signal from the flip- flop 902 and the PE-DA signal- from the flip-flop * 904 respectively as bits bO and bl of the PE-host register 98.
  • a value of zero in bO bit of the PE-host register 98 indicates that a data word from the PE to be fetched by the host is presently stored in the latches 982a and 982b.
  • a value of zero in the bl bit of the PE-host register 98 indicates that the PE 40 has fetched the previous data word stored by the host personal computer in the latches 962a and 962b.
  • the PAL UA36 912b transmits complementary information to the PE CPU 82 via the DO and Dl signal lines of the PE data section 646 included in the PE.bus 64.
  • the CPU 22 of the personal computer 20 and the PE CPU 82 execute complementary routines set forth below in computer programs UTIL.C and PE01UTIL.017.
  • a computer program, FUNCTION.C set forth below invokes the routines in the computer program UTIL.C to provide all the communication and supervisory functions required to perform particular mathematical computations requested by program calls to FUNCTION.C.
  • FUNCTION.C For example, if the program calling FUNCTION.C wanted to solve a set of linear equations for which the data were already available, that program would make two subroutine calls to FUNCTION.C. The first of these subroutine calls would invoke a mathematical function described in the book "LINPAK Users' Guide,” copyrighted 1979 by the Society for Industrial and Applied Mathematics, to cause the PE to factor the matrix of coefficients for the linear equations. The second subroutine call would then invoke another mathematical function described in that book to cause the PE to solve the triangular matrix resulting from the factorization.
  • the PE CPU 82 executes a supervisory computer program, PE01IOS.011 also set forth below, to supervises the overall operation of the PE 40.
  • the computer program PE01IOS.011 invokes routines in the computer program PE01UTIL.017 to look for requests from the personal computer 20 and to respond to such requests to the extent they involve communication between the PE 40 and the host personal computer 20.
  • a request involves performing a mathematical computation on data that is already present in the second multi-port VRAM 46 as the result of inter-processor communication effected by routines in the computer program UTIL.C in the personal computer 20 and by routines in the computer program PE01UTIL.017 in the PE CPU 82, then the computer program PE01IOS.011 invokes another computer program PE01MATH.
  • the computer program PE01MATH is an assembly language program that implements the mathematical algorithms described in the "LINPAK Users' Guide.” Accordingly, the "LINPAK Users' Guide" is incorporated by reference as though fully set forth here.
  • a computer program executed by the host personal computer 20 first loads the data into the first multi-port VRAM 44. After having loaded the data into the VRAM 44, the computer program executed by the host personal computer 20 supplies signals to the PE 40 which cause it to transfer the data over the inter-memory bus 48 from the VRAM 44 to the second multi-port VRAM 46. Once the data is present in the VRAM 46, the computer program executed by the host personal computer 20 then directs the PE CPU 82 to perform the desired mathematical computation.
  • the personal computer 20 may be preparing the data for a succeeding computation and storing it in the first multi-port VRAM 44 free from contention with memory exchanges occurring between the PE CPU 82 and the second multi-port VRAM 46.
  • the PE CPU 82 finishes the mathematical computation, it transmits signals to the host computer 20 indicating that fact.
  • the computer program executed by the host personal computer 20 then supplies additional signals to the PE 40 that cause the results of the computation to be transferred back over the inter-memory bus 48 from the VRAM 46 to the VRAM 44.
  • UTIL.C The following computer program called UTIL.C, contains routines executed by the host personal computer 20 to effect different types of interprocessor communications between the personal computer 20 and the PE 40.
  • PE_Mode TX; return(IOMode) ; ⁇
  • H_Mode TX; return(IOMode) ;
  • Signal CheckPE(PE); /* get signal from host */ if(Signal EQ ACK) return TRUE; return FALSE;
  • int H2PE_LB2H(PE,Data) int PE unsigned long Data
  • char HexString[20] char *p
  • int i Length, Signal, Status
  • HexStringfO] hex_digit[ (*(unsigned long *)&Data) » 28) & OxOOOOOOOf];
  • HexString[l] hex_digit[ (*(unsigned long *)&Data) » 24) & OxOOOOOOOf];
  • HexString[2] hex_digit[ (*(unsigned long *)&Data) » 20) & OxOOOOOOOf];
  • HexString[5] hex_digit[ (*(unsigned long *)&Data) » 8 ) & OxOOOOOOOf];
  • HexString[6] hex_digit[ (*(unsigned long *)&Data) » 4 ) & OxOOOOOOOf];
  • HexString[7] hex_digit[ (*(unsigned long *)&Data) ) & OxOOOOOOOf];
  • H2PE(PE,Token) /* send selected Token */
  • PE Buffer has been cleared by internal code ");*/ return(TRUE);
  • Data PE2H(PE); printf(" ⁇ n End Row: %02X ⁇ n",Data) ; wgoto(12,2) ; if(Data NE EndRow) return(FALSE) ;
  • SCLK gate /* Start writing to PE buffer from PE SAM V*/ H2PE(PE, 'h* ); /* send Token to PE to start auto update */ if(PE2H(PE) NE 'h') return(FALSE); /* PE is deaf V if(CheckPE(PE) NE ACK) return(FALSE) ; /* PE is screwed up
  • Rows-per-Buffer Calculate new(VSB) from new( rows_per_buffer ) and old(VEB) Units are lines which equal rows since we set 1 row per line.
  • VSB Size + buf fer_back_porch + buf fer_sync_width -
  • VES 4; put_byte(VES & 0x00FF,HOST_REGS,VES_LSB) ; /* send LSB to register
  • V Byte VES » 8; /* shift MSB to LSB location */ put_byte(Byte&0x00FF,HOST_REGS,VES_MSB); /* send MSB to register
  • VEB 6; put_byte(VEB & 0x00FF,HOST_REGS,VEB_LSB) ; /* send LSB to register
  • V Byte VEB » 8; /* shift MSB to LSB location */ put_byte(Byte&0x00FF,HOST_REGS,VEB_MSB) ; /* send MSB to register */
  • VT VSB+2 ; put_byte ( VT & 0x00FF,HOST_REGS ,VT_LSB ) ; /* send LSB to register
  • V put_byte ( VT & 0x00FF,HOST_REGS ,VI_LSB) ; /* send it to register
  • V new_data atoi(entry); /* convert it to integer */ printf("%3d ",new_data); /* show it and erase entry */ ⁇ return(new_data) ; ⁇ text_window(cmd,stringl,string2) /* show main working screen window */ int cmd; char stringl[20], string2[20]; if(cmd EQ CLEAR) wclean(BLACK_BACK); /* erase if required
  • Data PE2H(PE); if(Data GE ' • ) printf("%c",Data); if(Data EQ OxOD) printf(" ⁇ n") ; while(Data NE EOS); return Signal;
  • 0x10; /* bit 8 in CRI to high */ put_byte(Byte,HOST_REGS,CRl_MSB); return(TRUE); if(Processor GT HOST)
  • Bytej Number; /* set bits 12, 13, and 14 of Byte to value of State */ put_byte(Byte,HOST_REGS,CR1_MSB) ; return(TRUE); if(Processor GT HOST)
  • Number; /* set bits 12, 13, and 14 of Byte to value of State */ put_byte(Byte,HOST_REGS,CR2_MSB) ; return(TRUE) ; ⁇ else
  • VIDCLKs Therefore the number of VIDCLKs in HSB must be:
  • V HSB 73
  • HES 4; put_byte(HES&0x00FF,0x0D0C0 f 0) ; /* send LSB to register */
  • HT Size/4 + row_front_porch + row-back-porch + sync width - 1
  • HT 78; put_byte(HT & OxOOFF,OxODOCO,24) ; /* send LSB to register */
  • Byte HT » 8; /* shift MSB to LSB location */ put_byte(Byte&OxOOFF,OxODOCO,28) ; /* send MSB to register */ return(TRUE) ; ⁇ return(FALSE) ;
  • VIDCLKs Therefore the number of VIDCLKs in HSB must be:
  • HSB words_per_row/4 + row_back_porch + row_sync_width - 1
  • V HSB 70
  • HES 4; put_byte(HES&0x00FF,0x0D0C0,0); /* send LSB to register */
  • HT Size/4 + row_front_porch + row-back-porch + sync width - 1
  • templ PE2H(PE); if (not isxdigit(tempi) ) printf("PE2H_H2F returning 0"); return FALSE;
  • ExtAddress 0x500000L; return ExtAddress; ⁇ int PE2H(int PE) /* get data from PE */ int Data;
  • PE_DAWait(PE) /* Host waits for PE to send it */
  • V return Data; /* to meter out data ⁇ void H2PE(PE,Data) int PE,Data; /* assuming Host has data (H_DA TRUE) ⁇ /* send it to PE */
  • FP_OFF(ptr) offset; return *ptr; ⁇ int get_byte(seg,offset) int seg,offset;
  • PE01UTIL.017 contains assembly language routines executed by the PE CPU 82 to effect various different types of interprocessor communications between the PE 40 and the host personal computer
  • SAM2RAM * Switch Buffer controls to Receive Mode move.l #$248000,aO ; address for PseudoSAM2RAM
  • TXRowL move.l #HSB_LSB,a0 ; point to lsb of HSB move.w #70, (aO) ; put it into LSB of Vert.
  • RXRowL move.l #HSB_LSB,aO ; point to lsb of HSB move.w #73, (aO) ; put it into LSB of Vert.
  • BufLength: movem.l d0-d2/a0,-(a7) move.w d2,dl get length add.w #6,dl compute VSB * 262 256+5+2-1 move.l #VSB_LSB,a0 point to lsb of VSB move.w dl,(a0) move.l #VSB MSB,a0 point to MSB of Vert.
  • H2PEd ************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************ jsr H2PEs ; push first 32 bits
  • H2PEhex * read hex number from input port, return in dO******************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
  • PE2Hhex * PE sends 32 bit binary number as 8 hex characters to * Host
  • PEXfrOn movem.l d0/a0,-(a7) ; push registers point to LSB crl
  • Second buffer interrupt should turn transfer off, here
  • PE2RX * Function e: Host to TX mode calls this function******************************************* movem.l d0-d3,-(a7) ; push registers * Calculate number of rows to send
  • PE is set to "slave sync" mode, bsr SyncOff
  • Compute bRAM address of rows sub.w d2,d3 compute number of chunks to load less 1 move.w d3,d0 add.w #l,d0
  • BuffClear clr.w (a6)+ move word into bRAM and bump * pointer sub.w #l,d2 bne BuffClear rts ShowBuffer: move.l #vram,a6 ; bRAM bank 0 address move.w #$0FFF,d3 ; loop count - 1 (16 rows of 256 words ) get word from PE-RAM to d2 copy into dO shift MSB to lower byte send MSB to host get word again send LSB to host
  • FUNCTION.C The following computer program called FUNCTION.C, that the CPU 22 of the host personal computer 20 executes, illustrates the use of the various functions provided by the routines in the program UTIL.C for exchanging data between the host personal computer 20 and the PE 40.
  • V N (unsigned long)(n);
  • PE */ answer question( " ⁇ nSGEFA: Show contents of PE buffer after computation") ; if(answer EQ YES) DumpPE(PE,0,36) ; /* Transfer PE buffer A to Host buffer A */
  • BufPnt_t *pnt unsigned long HBuf, PEBuf, Offset_A, Offset_p, Offset_i,
  • Offset_b unsigned long N,Chunks_A, Chunks_p, Chunks_i, Chunks_b;
  • N (unsigned long)(n);
  • Chunks_A (pnt->Offset_A/512)+1;
  • Chunks_b (pnt->Offset_b/512)+1;
  • PE 0x300
  • PEError(8) ; /* Send matrix size, N, twice */ if(H2PE_B2H(PE,n) EQ FALSE) PEError(8); if(H2PE_B2H(PE,n) EQ FALSE) PEError(8);
  • PE01IOS.011 contains assembly language routines executed by the PE CPU 82 in supervising the overall operation of the PE 40.
  • Mode 0 Bit 0 is Mode
  • * Register Usage: * aO is used for scratch, e.g., message pointers mainly * al is used at i/o base register * a2 is SRAM pointer (not used) * a3 is a pointer to the Function List * a4 is the code pointer * a5 * a6 is the bRAM pointer * a7 is stack pointer * dO carries data byte to and from pio module * dl carries status byte for pio module * d2 is used by ShowString * d3 is the token in list * d4 is the token commanded
  • Dsr (a4) then use it to go and execute the code bra.s Command ; get next command token srch; dc.b 'Searching for Token' ,cr,If,eos ex: dc.b 1 Executing Token' ,cr,If,eos err: dc.b 'Token not in List' ,cr,lf,eos
  • the first multi-port VRAM 44 is primarily intended to be used in transmitting data between the host personal computer 20 and the PE CPU 82, when the PE 40 is not being used to perform computations, the first multi-port VRAM 44 is available to the personal computer 20 to be used in the same manner as any extended memory installed in an IBM PC AT.
  • a PE 40 in accordance with the present invention may be constructed for use with many other different types of presently existing digital computers including IBM PC clones using either the ISA or EISA bus, the IBM P/S2, Sun digital computers and Digital Equipment Corporation ("DEC") computers.
  • the presently preferred embodiment of the program memory 94b is an EPROM memory
  • a PE 40 in accordance with the present invention may used other types of memories for the program memory 94b including EEPROM integrated circuits such as "FLASH" EEPROMs.

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Abstract

Le domaine technique de cette invention se rapporte en général à des ordinateurs numériques à processeurs multiples adaptés à effectuer rapidement des calculs scientifiques et relatifs à l'ingénierie. Selon la présente invention, un ordinateur personnel est adapté à effectuer des calculs scientifiques ou d'ingénierie grâce à l'inclusion d'une ou plusieurs unités de traitement (UT) (40) dans l'ordinateur personnel (20). Chacune de ces UT (40) comprend une paire de mémoires à accès multiples (44 et 46) accouplées par un bus d'entre-mémoire (48). La première de ces mémoires à accès multiples (44) échange des données avec un bus (38) situé dans l'ordinateur personnel (28). De même, la seconde mémoire à accès multiples (46) échange des données avec un bus (64) d'UT. L'UT (40) comprend aussi un élément de commande de mémoire (58, 68 et 74) servant à commander des échanges de données entre le bus (38) de l'ordinateur central et la première mémoire à accès multiples (46), entre les deux mémoires à accès multiples (44 et 46) par l'intermédiaire du bus d'entre-mémoire (48), et entre la seconde mémoire à accès multiples (46) et le bus (64) de l'UT. En réponse à des signaux de déclenchement émanant de l'ordinateur central (20), des données introduites dans l'une des mémoires (44 ou 46) sont automatiquement transférées de la mémoire où elles ont été inscrites (44 ou 46) vers l'autre mémoire (46 ou 44), dans laquelle ces données sont directement accessibles pour être ultérieurement traitées par l'autre unité centrale (82 ou 22). De plus, soit une soit les deux unités centrales (82 ou 22) peuvent avoir accès à leurs mémoires respectives (46 ou 44) sans qu'il y ait d'interférence avec l'autre unité centrale (22 ou 82) alors que des données sont en train d'être transférées entre les mémoires (44 et 46).
PCT/US1990/004376 1990-08-06 1990-08-06 Unites de traitement pour un systeme d'ordinateur numerique a processeurs multiples WO1992002885A1 (fr)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1033722A2 (fr) * 1999-02-12 2000-09-06 Hiroshima University Mémoire partagée
US6563163B1 (en) 1999-05-18 2003-05-13 Hiroshima University Nonvolatile memory using deep level capture of carrier at corner structure of oxide film
WO2007149317A2 (fr) * 2006-06-16 2007-12-27 Bono Vincent P Systèmes et procédés de fourniture d'une mémoire système non volatile à un ordinateur personnel

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4570217A (en) * 1982-03-29 1986-02-11 Allen Bruce S Man machine interface

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4570217A (en) * 1982-03-29 1986-02-11 Allen Bruce S Man machine interface

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1033722A2 (fr) * 1999-02-12 2000-09-06 Hiroshima University Mémoire partagée
EP1033722A3 (fr) * 1999-02-12 2001-05-23 Hiroshima University Mémoire partagée
US6874068B1 (en) 1999-02-12 2005-03-29 Hiroshima University Shared memory
US6563163B1 (en) 1999-05-18 2003-05-13 Hiroshima University Nonvolatile memory using deep level capture of carrier at corner structure of oxide film
WO2007149317A2 (fr) * 2006-06-16 2007-12-27 Bono Vincent P Systèmes et procédés de fourniture d'une mémoire système non volatile à un ordinateur personnel
WO2007149317A3 (fr) * 2006-06-16 2008-09-12 Vincent P Bono Systèmes et procédés de fourniture d'une mémoire système non volatile à un ordinateur personnel
US7886099B2 (en) * 2006-06-16 2011-02-08 Superspeed Llc Systems and methods for providing a personal computer with non-volatile system memory

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