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WO1992002885A1 - Processing element for a multi-processor digital computing system - Google Patents

Processing element for a multi-processor digital computing system Download PDF

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Publication number
WO1992002885A1
WO1992002885A1 PCT/US1990/004376 US9004376W WO9202885A1 WO 1992002885 A1 WO1992002885 A1 WO 1992002885A1 US 9004376 W US9004376 W US 9004376W WO 9202885 A1 WO9202885 A1 WO 9202885A1
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WO
WIPO (PCT)
Prior art keywords
memory
host
bus
data
cpu
Prior art date
Application number
PCT/US1990/004376
Other languages
French (fr)
Inventor
Roy Emerson Murphy
Original Assignee
Epic Industries Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Epic Industries Incorporated filed Critical Epic Industries Incorporated
Priority to PCT/US1990/004376 priority Critical patent/WO1992002885A1/en
Publication of WO1992002885A1 publication Critical patent/WO1992002885A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Definitions

  • the present invention relates generally to the technical field of digital computers and, more particularly, to multi ⁇ processor digital computers adapted to perform engineering and scientific computations swiftly.
  • the exact sequence in which particular pairs of numbers from the row vector of matrix A and from the column vector of matrix B are multiplied together is irrelevant to accurate computation so long as the results of that multiplication can be stored properly in the appropriate entry in the matrix C.
  • one technique that is employed to reduce the time required to perform a computation is to have multiple processors operate in parallel with each processor simultaneously processing a different portion of the same computation, i.e. parallel processing.
  • PE processing element
  • FPU floating point unit
  • current microprocessors such as Motorola's MC68040 and Intel's 80486 include a FPU integrated into the same chip as the central processing unit (“CPU") itself.
  • both Motorola's MC68020 and MC68030 have been designed to simultaneously control the operation of several co-processor chips.
  • Motorola's MC68030 has been designed to simultaneously control a combination of up to 8 co-processor chips such as Motorola's MC68882 FPU and/or Motorola's MC68451 memory management unit (“MMU") .
  • MMU memory management unit
  • a common difficulty in parallel multi-processor digital computing systems is the need to share data among the several processors.
  • any one of the several processors may require access to a value that was computed at an earlier time by another one of the processors.
  • this data sharing problem has been recognized by those working in the field of parallel multi-processor digital computing systems for many years and while various different solutions to the problem have been proposed and even implemented, thus far there exists no generally recognized solution to the problem.
  • a system in which several processors share a single memory suffers from the problem of "contention among the various processors for access to the shared memory.
  • each processor includes its own local memory to avoid contending for a shared resource, then the results of its computations must be shared among all the other processors.
  • a common bus is used to interconnect the local memories in the several processors, there is a problem with processors contending for access to the bus.
  • postbox One particular attempt at solving the preceding problems in multi-processor systems is known as a "postbox" system.
  • a postbox system a single, multi-port memory is shared between or among the multi-processors. To access this shared memory, a port on the memory is assigned to each of the processors.
  • One processor commences a data transfer to another processor by accessing the memory through its port and storing the data into a memory location in the shared memory. Subsequently, another processor needing those data will access the shared memory through its port to fetch the data from the memory location into which it has been stored by the first processor.
  • a postbox system employs only a single, shared, multi- port memory, the memory must arbitrate memory accesses occurring simultaneously through two or more memory ports. If the shared memory employs a hierarchial arbitration circuit, it is possible for processors assigned the highest priority to block accesses to the shared memory by the lower priority processors.
  • An object of the present invention is to provide an effective way of adapting a personal computer to efficiently perform scientific or engineering computations.
  • Another object of the present invention is to provide a multi-processor that may be expanded modularly to include a plurality of processing elements.
  • Another object of the present invention is to provide a multi-processor which adapts a single CPU to effectively control the operation of a plurality of FPUs.
  • Another object of the present invention is to provide a multi-processor system in which one processor may not block another processor.
  • Yet another object of the present invention is to provide a multi-processor that is cost effective, and easy and economical to manufacture.
  • the present invention adapts a personal computer for performing engineering or scientific computations by incorporating one or more PEs into a conventional personal computer.
  • Each of these PEs that may be incorporated into a host personal computer, includes a pair of multi-port memories.
  • Each PE also includes an inter-memory bus that interconnects shared ports of the two multi-port memories for exchanging data between the two memories.
  • a host port of the first of these two multi-port memories exchanges data with a bus in the host personal computer over which the CPU and host computer memory exchange data.
  • a bus within the PE couples a PE port of the second of the two multi-port memories with a central processing unit included in the PE itself ("PE CPU").
  • the PE's CPU and the second multi-port memory exchange data over this PE bus.
  • the PE also includes a memory control means for controlling exchanges of data between the host bus and the first multi-port memory, between the two multi-port memories, and between the second multi-port memory and the PE bus. In controlling these various exchanges of data, the PE's memory control means responds to signals received from the host CPU and from the PE CPU.
  • the first and second multi-port memories are video ram ("VRAM") integrated circuits.
  • VRAM video ram
  • one port of such VRAM integrated circuits operates to store or to retrieve data in the same way as conventional single port random access memories (“RAM"). It is this port of the two VRAMs included in the preferred embodiment of the PE which respectively exchange data with the host bus and with the PE bus.
  • a second, or serial, port of a VRAM integrated circuit either receives data for storage or transmits stored data.
  • These second, or serial, ports of the VRAM are the shared ports of the PE and are interconnected by the inter-memory bus.
  • Signals supplied to the first and second VRAM cause one of them to transmit data over the inter-memory bus from its shared port while the other VRAM receives such transmitted data from the inter-memory bus for storage within the VRAM.
  • data written into one of the VRAMs by either the host CPU or by the PE CPU transfers automatically and/or simultaneously from the written VRAM into the other VRAM thereby making them directly addressable for further processing by the other CPU.
  • either or both CPUs can access their respective VRAM memories without interference from the other CPU while data are being transferred between the VRAM memories.
  • FIG. 1 is a block diagram depicting a personal computer incorporating a PE in accordance with the present invention that illustrates the PE's memories, the control for those memories, the control and status registers, and the various buses interconnecting the memories with the host bus, with the inter-memory bus, and with the PE bus;
  • FIG. 2 is a block diagram depicting the organization of FIGs. 2a-2d into a single composite diagram;
  • FIGs. 2a-2d form a composite block diagram depicting, at the integrated circuit package and signal line level, the memories, memory control, registers, and buses within the PE;
  • FIG. 3 is a memory allocation diagram depicting the assignment of memory address space for the host personal computer and for the PE in accordance with the present invention.
  • FIG. 4 is a diagram depicting the two registers by which the host personal computer and the PE exchange control and status information.
  • FIG. 1 depicts a personal computer that is enclosed within a dashed line and referred to by the general reference character 20.
  • the personal computer 20 includes a CPU 22, a RAM memory 24, a disk controller 26 for controlling the operation of a hard disk 28, a video display adapter.32 for controlling the operation of a video monitor 34, and a keyboard 36.
  • a host bus 38 within the personal computer 20 interconnects the CPU 22, the RAM memory 24, the disk controller 26, the video display adapter 32 and the keyboard 36 for transferring data among those various items. Since the preferred embodiment of the host personal computer 20 is an IBM PC AT, the host bus 38 conforms to the Industry Standard Architecture ("ISA") bus of an IBM PC AT personal computer.
  • ISA Industry Standard Architecture
  • FIG. 1 also depicts a plurality of PEs in accordance with the present invention that are illustrated by dashed outlines and referred to by the general reference character 40.
  • FIG. 1 depicts the block diagram for only one of the PEs 40 while the remaining PEs 40 are illustrated only by their dashed outlines because they are obscured by one or more of the other PEs 40.
  • Each of the PEs 40 includes a PE ISA bus 42 that adapts the PE 40 to plug into the ISA host bus 38 and to be
  • the PE ISA bus 42 extends the host bus 38 onto the PE 40 which includes the particular bus 42. Inclusion of the PE ISA bus 42 in each PE 40 permits it to exchange control and status signals and data with the CPU 22 and RAM memory 24 included in the personal
  • FIG. 1 depicts a total of fifteen PEs 40, as few as one PE 40 or more than 15 PEs 40 may be connected to the host bus 38.
  • the PE 40 of the present invention allows assembly of a computer system for use in performing engineering and scientific computations that is
  • each of the PEs 40 includes a first multi-port VRAM 44 and a second multi-port VRAM 46.
  • Each PE 40 also includes an inter-memory bus 48 that interconnects serial data in/data out shared ports 52 of the two VRAMs 44 and
  • the VRAMs 44 and 46 exchange data via the inter-memory bus 48.
  • the first VRAM 44 includes a random-access data in/data out host port 54 to which a PE host bus 56 connects.
  • the first VRAM 44 exchanges data with the host bus 38 in the personal computer 20 via the PE
  • a first VRAM control and address bus 66 connects the first VRAM 44 to a first VRAM control circuit 68 which also connects to the PE bus 64 and to the PE-host interface circuit 58 via the PE host bus 56.
  • a second VRAM control and address bus 72 connects the second VRAM 46 to the first VRAM control circuit 68 and to a second VRAM control circuit 74, which itself also connects to the PE bus 64.
  • the PE bus 64 also connects directly to the PE-host interface circuit 58.
  • a VRAM synchronization signal bus 76 connects the second VRAM control 74 to the first VRAM control 68. Responsive to signals that the PE-host interface circuit 58 receives both from the PE bus 64 and from the host bus 38 via the PE ISA bus 42, to signals that the first VRAM control circuit 68 receives from the PE-host interface circuit 58, from the PE bus 64, and from the second VRAM control circuit 74, and to signals that the second VRAM control circuit 74 receives from the PE bus 64, the combined PE-host interface circuit 58, the first VRAM control circuit 68, and the second VRAM control circuit 74 operate to control exchanges of data between the host bus 38 and the first VRAM 44, between the first VRAM 44 and the second VRAM 46, and between the second VRAM 46 and the PE bus 64.
  • each of the VRAMs 44 and 46 responds independently to memory accesses respectively over either the host bus 38 or over the PE bus 64, an access on one of the buses 38 or 64 to the shared multi-port memory provided by the combined VRAMs 44 and 46 cannot block a simultaneous access to the multi-port memory on the other bus 64 or 38.
  • each PE 40 includes a PE CPU 82 which connects to the PE bus 64 and can exchange data with the VRAM 46 via the bus 64. Also included in the PE 40 and connected to the PE bus 64 may be one or more FPUs 84, four of which are illustrated in FIG. 1.
  • the PE CPU 82 transmits signals to the one or more FPUs 84 for controlling their operation via a FPU control signal bus 86.
  • the PE CPU 82 includes a Motorola MC68020 and the PE 40 includes at least one Motorola MC68882 FPU as its FPU 84. Because the PE 40 includes the Motorola MC68020 CPU and MC68882 FPU, the PE BUS 64 includes signals normally present in a computer system employing both a Mo.torola 68020 CPU and MC68882 FPU.
  • PE memory 92 Also connected to PE bus 64 is PE memory 92 that includes a stack and cache memory 94a.
  • the stack and cache memory 94a is relatively small, fast static RAM in which stacks created by a computer program executed by the PE CPU 82 are stored and in which temporary and intermediate results may also be stored.
  • the stack and cache memory 94a is provided by two Hitachi 6264P eight bit static RAM integrated circuits that are connected to the PE bus 64 for storing and retrieving sixteen bit words.
  • the PE memory 92 also includes an erasable programmable read only memory (“EPROM”) program memory 94b.
  • the program memory 94b includes two Texas Instruments 2764, 27128 or 27256 EPROM integrated circuits that are connected to the PE bus 64 for retrieving 16 bit words.
  • the program memory 94b stores programs that are executed by the PE CPU 82 including those program that it executes for communicating with the host personal computer 20 and for controlling the operation of the PE 40.
  • the memory 92 includes a Texas Instruments 20L8 Programmable Array Logic ("PAL") integrated circuit UA0 94c for controlling the operation of the stack and cache memory 94a and program memory 94b, and for transmitting a signal to the PE CPU 82 indicating when the stack and cache memory 94a, the program memory 94b and the second multi-port VRAM 46 ready to exchange data.
  • PAL Programmable Array Logic
  • the following table sets forth the pin numbers for the PAL UAO 94c together with the names of the signals either received by or transmitted from each pin.
  • the input signals FC0, FC1, A20-A23, AS* and R/W* come to the PAL UAO 94c from the Motorola MC68020 included in the PE CPU 82. (In the following and all subsequent signal names, the symbol "*" indicates the logical negation of the signal whose name immediately precedes the symbol.)
  • the input signals UDS* and LDS* come to the PAL UAO 94c from the PE CPU 82.
  • the input signal PE-MCS* and BDTACK* come to the PAL UAO 94c from the second multi-port VRAM 46.
  • the output signal BRAM* from the PAL UAO 94c is only used internally within the PAL in generating other output signals.
  • the PAL UAO 94c supplies its output signals READ*, WRITE* and SRAM* respectively to the OE*, WE* and CS* input terminals of the two 6264P eight bit static RAM integrated circuits in the stack and cache memory 92.
  • the PAL UAO 94c supplies its output signal PROM* to the E* input terminal of the two EPROMs in the program memory 94b.
  • the PAL UAO 94c supplies its output signal DTACK* to the PE CPU 82.
  • the PAL UAO 94c supplies its output signal HIF* to the PE-host interface circuit 58.
  • An address from the PE CPU 82 that lies in the range 200000H-3FFFFFH causes the PAL UAO 94c to assert its output signal BRAM*.
  • An address from the PE CPU 82 that lies in the range 000000H-0FFFFFH causes the PAL UAO 94c to assert its output signal PROM*.
  • An address from the PE CPU 82 that lies in the range 100000H-1FFFFFH causes the PAL UAO 94c to assert its output signal SRAM*.
  • An address from the PE CPU 82 that lies in the range 400000H-4FFFFFH causes the PAL UAO 94c to assert Its output signal HIF*.
  • the DTACK* signal indicates that the memory 92 and the second multi-port VRAM 46 are capable of exchanging data with the PE
  • All write operations to the memory 92 are performed early without wait states.
  • the PE CPU 82 can experience wait states during accesses to the second multi-port VRAM 46.
  • the PE CPU 82 includes a circuit for generating various synchronous clock signals used throughout the PE 40. Thus, the PE CPU 82 generates a 20 MHz SCLK signal which it supplies to the first VRAM control circuit 68, and another 20 MHz FFP-CLK signal which it supplies directly to the FPUs 84.
  • the PE CPU 82 generates a 20 MHz SCLK signal which it supplies to the first VRAM control circuit 68, and another 20 MHz FFP-CLK signal which it supplies directly to the FPUs 84.
  • the PE CPU 82 also generates a jumper selectable 10 or 20 MHz PCLK clock signal that is applied internally within the PE CPU 82 to the Motorola MC68020.
  • the PE CPU 82 generates a 10 MHZ PCLK* signal which it supplies to the second VRAM control circuit 74 for synchronization functions.
  • the PE CPU 82 also generates a jumper selectable 10 or 20 MHz PCLK clock signal that is applied internally within the PE CPU 82 to the Motorola MC68020.
  • the PE CPU 82 generates a 10 MHZ PCLK* signal which it supplies to the second VRAM control circuit 74 for synchronization functions.
  • the PE CPU 82 also generates a jumper selectable 10 or 20 MHz PCLK clock signal that is applied internally within the PE CPU 82 to the Motorola MC68020.
  • the PE CPU 82 generates a 10 MHZ PCLK* signal which it supplies to the second VRAM control circuit 74 for synchronization functions.
  • the PE CPU 82 also generates a jump
  • the PE CPU 82 also includes a reset circuit which automatically holds the MC68020 and all of the MC68882s reset for a time interval immediately following application of power
  • the reset circuit included in the PE CPU 82 may also be triggered by a signal from the PE-host interface circuit 58 that is generated in response to signals from the host personal computer 20. Within the PE CPU 82, a five volt positive signal is continuously applied through individual
  • PE CPU 82 of the preferred embodiment is a PAL UB9, not ⁇ illustrated in FIG. 1, for producing the control signals which the PE CPU 82 transmits to
  • the ⁇ PAL included in the PE CPU 82 for controlling the PE FPU is a 20L8 integrated circuit and is connected to the MC68020 and the one or more MC68882s and is programmed in accordance with the description set forth in the "MC68020 32-Bit Microprocessor User's Manual", Third Edition, 1989, 1988 by Motorola Inc., MC68020UM/AD REV 2, particularly as depicted in Figures 11-5 and 11-6 on pages 11-7 and 11-8 thereof, together with the text accompanying those figures. Accordingly, the "MC68020 32-Bit Microprocessor User's Manual" identified above is incorporated by reference as though fully set forth here.
  • the PE CPU 82 also includes a second 20L8 CPU control signal PAL UB10, not illustrated in FIG. 1, that adapts control signals present on the PE bus 64 from those for a Motorola MC68000 to those for a Motorola MC68020.
  • the adaptation of the PE 40 to use different microprocessors from the same family of Motorola microprocessors merely by the addition of the single PAL UB10 indicates the flexibility, adaptability and generality of the present invention.
  • the PAL UB10 receives as input signals from the MC68020 its address signals A0 and Al, its SIZO and SIZ1 signals, its address strobe signal AS*, its data strobe signal DS*, its read/write signal R/W*, and its external cycle start signal ECS*.
  • the PAL UB10 also receives interrupt signals IAV4*, IAV5*, IAV6* and IAV7* that originate in the PE-host interface circuit 58. While the PAL UB10 provides an input terminal for an interrupt signal IAV3*, that terminal is merely connected to a positive five volt potential through a resistor. Lastly, the PAL UB10 receives the signal DTACK* that originates in the PE Memory Controller PAL UAO 94c.
  • the PAL UB10 supplies to the Motorola MC68020
  • it supplies a UDS* and a LDS* signal to the PAL UAO 94c, and respectively to G* inputs of the two EPROM integrated circuits included in the program memory 94b.
  • the DSACK1* signal indicates completion of a data transfer requested by the Motorola MC68020. Because the memories stack and cache memory 94a and program memory 94b as well as the second multi-port VRAM 46 exchange only 16 bit words with the MC68020, a high logic level signal is continuously supplied to the DSACKO* input terminal of the MC68020.
  • the following table sets forth the pin numbers for the PAL UB10 toget r with the names of the signals either received by or transmitted from each pin.
  • IPL2* IAV7* & IAV6 & IAV5 & IAV4 & IAV3
  • the PE 40 includes a host-PE register 96 and a PE-host register 98.
  • the personal computer 20 transmits certain control signals to the PE CPU 82- by storing them into " the host-PE register 96 via the PE-host interface circuit 58 from which they may be subsequently fetched by the PE CPU 82.
  • the PE CPU transmits certain control signals to the personal computer 20 by storing them into the PE-host register 98 from which they may be subsequently fetched by the host personal computer 20 via the PE-host interface circuit 58.
  • FIGs. 2a-2d when assembled as illustrated in FIG. 2, form a detailed block diagram depicting, at the integrated circuit level, the VRAMs 44 and 46, the VRAM control circuits 68 and 74,. the PE-host interface circuit 58, and the registers 96 and 98. Also depicted down the left hand edge of the combined FIGs. are the ISA host bus 38 and its interface to the PE ISA bus 42.
  • FIG. 2b of the composite diagram depicts that the first multi-port VRAM 44 includes four Texas Instruments TMS4461 262,144 Bit Multiport VRAM integrated circuits 442a-442d. Similarly, FIG.
  • FIG. 2d of the composite diagram depicts that the second multi-port VRAM 46 also includes four TMS4461 262,144 Bit Multiport VRAM integrated circuits 462a-462d organized as 4 x 65,536 bits. That FIG. also depicts sixteen resistors 482a-482p having a resistance in the range of fifty to one- hundred ohms one of which is respectively located in each of the signal lines of the inter-memory bus 48 intermediate to the serial data in/data out shared port 52 of the first multi-port VRAM 44 and the serial data in/data out shared port 52 of the second multi-port VRAM 46.
  • the resistors 482a-482p provide isolation and termination resistances between the terminals of the VRAM integrated circuits 442a-442d that connect to the inter-memory bus 48 and the corresponding terminals of the VRAM integrated circuits 462a-462d that also connect to the inter- memory bus 48.
  • FIGs. 2a and 2b of the composite diagram show that the PE host bus 56 includes a host control signal section 562, a host buffered address section 564, and a host buffered data section 566.
  • FIGs. 2c and 2d of the composite diagram show that the PE bus 64 includes a PE control signal section 642, a PE address section 644, and a PE data section 646.
  • FIG. 2b of the composite diagram shows that the first VRAM control and address bus 66 includes a first VRAM control signal section 662 and a first VRAM address section 664.
  • the first VRAM control circuit 68 includes three 20L8 PAL integrated circuits UA5 682a, UA6 682b, UA7 682c, a Texas Instruments TMS 34061 Video System Controller (“VSC") 684, a 74F74 flip-flop 686, and two 74F04 inverters 688a and 688b.
  • FIG. 2d of the composite diagram shows that the second VRAM control and address bus 72 includes a second VRAM control signal section 722 and a second VRAM address section 724.
  • the second VRAM control circuit 74 includes a single 20L8 PAL integrated circuit UA13 742, a TMS 34061 VSC 744, two 74F113 flip-flops 746a and 746b, and a 74F04 inverter 748.
  • the PE ISA bus 42 supplies an electrical ground 782 and a positive five volt potential 784 from the host personal computer 20 to the electrical circuits of the PE 40.
  • FIGs. 2a and 2c which depict the PE-host interface circuit 58 shows that it includes a first pair of 74F245 data transceivers 802a and 802b and a second pair of 74F245 register transceivers 804a and 804b.
  • a first set of bidirectional signal terminals for the data transceivers 802a and 802b and a corresponding first set of bidirectional signal terminals for the register transceivers 804a and 804b connect to a SD section 806 of the PE ISA bus 42.
  • the SD section 806 of the PE ISA bus 42 receives data signals SD00-SD15 from the host bus 38 and conducts those signals to the transceivers 802a-b and 804a-b.
  • a second set of bidirectional signal terminals for the data transceivers 802a and 802b connect to the host buffered data section 566 of the PE host bus 56 while a second set of bidirectional signal terminals for the register transceivers 804a and 804b connect to a register bus 808.
  • signals present on the SD00-SD15 signal lines of the host bus 38 are transferred to the host buffered data section 566 of the PE-host bus 56, or conversely.
  • signals present on the SD00-SD15 signal lines of the host bus 38 are transferred to the register bus 808 or conversely.
  • the PE-host interface circuit 58 controls the operation of the transceivers 802a-b and 804a-b to transfer SD00-SD15 signals present on the host bus 38 to the host buffered data section 566 and to the register bus 808 during either memory write or I/O write operations. Conversely, the host interface circuit 58 controls the transceivers 802a-b and 804a-b to transfer signals both from the host buffered data section 566 and from the register bus 808 to the SD00-SD15 signal lines of the host bus 38 during either a memory read or I/O read operation on the ISA host bus 38.
  • FIGs. 2a and 2c which depict the PE-host interface circuit 58 also shows that it includes a pair of series connected 74F04 inverters 812a and 812b, a pair of 74LS541 buffers 814a and 814b and a 74F373 latch 816.
  • Output terminals of the inverter 812b, the buffers 814a and 814b, and the latch 816 all connect to the host buffered address section 564 of the PE host bus 56.
  • Input terminals of the inverter 812a and the buffers 814a and 814b connect to a SA section 818 of the PE ISA bus 42.
  • the SA section 818 of the PE ISA bus 42 receives address signals SA00-SA16 from the host bus 38 and conducts those signals to the input terminal of the inverter 812a and to the input terminals of the buffers 814a and 814b. Control signals applied to the pair of buffers 814a and 814b enable them together with the series connected inverters 812a and 812b to continuously transfer address signals present on the SA section 818 of the PE ISA bus 42 to the host buffered address section 564 of the PE host bus 56. Input terminals of the latch 816 are connected to a LA section 822 of the PE ISA bus 42.
  • the LA section 822 of the PE ISA bus 42 receives address signals LA17-LA23 from the host bus 38 and conducts those signals to the input terminals of the latch 816.
  • a control signal input terminal of the latch 816 connects to a BALE signal line 824 included in the host control signal section 562 of the PE host bus 56.
  • the BALE signal line 824 receives a BALE control signal from the host bus 38. While the host personal computer 20 is operating, valid address signals SA00-SA16 are always present on the host bus 38. Therefore, the pair of inverters 812a and 812b and the pair of buffers 814a and 814b continuously receive such valid address signals from the SA section 818 and transfer those address signals to the host buffered address section 564 of the PE host bus 56.
  • the latch 816 responds to the signal present on the BALE signal line 824 to accept the LA17-LA23 address signals from the host bus 38 and to transfer those signals to the host buffered address section 564 of the PE host bus 56.
  • the latch 816 stores the valid address signals that it received most recently and continues supplying the host buffered address section 564 of the PE host bus 56 with the stored address signals.
  • the inverters 812a and 812b, the buffers 814a and 814b, and the latch 816 continuously supply the host buffered address section 564 of the PE host bus 56 with a set of address signals H-AO through H-A23 that correspond exactly to the address signals on the host bus 38.
  • FIGs. 2a and 2c which depict the PE-host interface circuit 58 also shows that it includes a first AM25LS2521 selector 832.
  • a first set of input terminals to the selector 832 connects individually to a portion of the signal lines present in the host buffered address bus 564 of the PE host bus 56 to receive the address signals H-A12 through H-A19.
  • a second set of input terminals to the selector 832 connect individually via a set of jumper lines 834 to one-half of a set of jumpers pins 836. The other half of the jumper pins 836 connect to electrical ground 782.
  • the jumper lines 834 also connect individually through resistors 838 to the positive five volt potential 784.
  • the positive five volt potential is applied through the individual resistors 838 and jumper lines 834 to all terminals in the second set of input terminals to the selector 832. If a jumper is installed between a pair of jumper pins 836, then ground potential is applied to the corresponding input terminal of the second set of input terminals to the selector 832.
  • the selector 832 continuously compares the signals present at its first set of input terminals with those present afe its second set of input terminals.
  • the selector 832 transmits a signal indicating the occurrence of the matching condition onto a H-CSEL* signal line 842 included in the host control signal section 562 of the PE host bus 56.
  • the host control signal section 562 of the PE host bus 56 transmits the signal on the H-CSEL* signal line to the PAL UA7 682c included in the first VRAM control circuit 68.
  • the signal present on the H-CSEL* signal line controls whether or not the VSC 684 will respond to address signals on the host buffered address section 564 of the PE host bus 56 for exchanging data with the host personal computer 20 via the host buffered data section 566 of the PE host bus 56.
  • the installation or removal of jumpers from the jumper pins 836 permits setting an address range on the host bus 38 throughout which the host personal computer 20 may store data into or retrieve data from the VSC 684. This address range is 00 0XXXH to OF FXXXH with the address usually being set to 0D CXXXH.
  • the PE-host interface circuit 58 also includes a second AM25LS2521 selector 852.
  • selector 852 some of its first set of input terminals connect to the host buffered address section 564 of the PE host bus 56 to receive address signals H-A20 through H-A23.
  • a second set of input terminals of the selector 852 i.e. those input terminals which are compared with the terminals of the first set of input terminals that receive the signals H-A20 through H-A23, connect via jumper lines 854 to one-half of a set of jumpers pins 856 and also connect through resistors 858 to the positive five volt potential 784.
  • the input terminals of the selector 852 which do not receive either an address signal or a signal from the jumper lines 854 are connected to electrical ground 782. If the set of input signals H-A20 through H-A23 supplied to the first set of input terminals of the selector 852 match the set of input signals supplied by the jumper lines 854 to the second set of input terminals, then the selector transmits a signal indicating that matching condition onto H-MSEL* signal line 862 included in the host control signal section 562 of the PE host bus 56. The host control signal section 562 of the PE host bus 56 transmits the signal on the H-MSEL* signal line to the PAL UA7 682c included in the first VRAM control circuit 68.
  • the signal present on the H-MSEL* signal line controls whether or not the VSC 684 included in the first VRAM control circuit 68 will respond to address signals on the host buffered address section 564 of the PE host bus 56 for addressing the first multi-port VRAM 44 for exchanging data between the VRAM 44 and the host personal computer 20 via the host buffered data section 566 of the PE host bus 56.
  • the installation or removal of jumpers from the jumper pins 856 permits setting the address range on the host bus 38 at which the host personal computer 20 may store data into or retrieve data from the VRAM 44. This address range is OX XXXXH to FX XXXH with the address usually being set to 50 0000H.
  • the PE-host interface circuit 58 includes a set of interrupt selection jumper pins 872.
  • One side of the jumper pins 872 connects to individual lines for IAV4*, IAV5*, IAV6* and IAV7* signals in the PE control signal section 642 of the PE bus 64.
  • the other side of the jumper pins 872 all connect in parallel to a PC-INT* signal line 874 in an interface circuit bus 882. Installation of a jumper between a particular pair of jumper pins 872 selects a particular priority level for interrupt signals that are applied to the Motorola MC68020 included in the PE CPU 82.
  • the PE-host interface circuit 58 includes a pair of 74F04 inverters 892 and 894. Inputs of the inverters 892 and 894 respectively receive the signals PE-WTD* and H-WTD* from the interface circuit bus 882. The outputs of the inverters 892 and 894 respectively transmit the signals PE-WTD and H-WTD back to the interface circuit bus 882.
  • the PE-host interface circuit 58 also includes a 74F74 host-PE flip-flop 902 having a CP input which receives the H-WTD signal from the inverter 894. The D and SD inputs of the host-PE flip-flop 902 receive the positive five volt potential 784 through a resistor 904.
  • the RD input of the host-PE flip- flop 902 receives a PE-RDD* signal from the interface circuit bus 882. Responsive to these input signals, one state of the host-PE flip-flop 902 indicates that the host personal computer 20 has stored data in the host-PE register 96 and that the PE CPU 82 has not yet read the data stored there. The other state of the host-PE flip-flop 902 indicates that the PE CPU 82 has read any previously stored data from the host-PE register 96, and that the host personal computer 20 may therefore store new data into the register 96.
  • the PE-host interface circuit 58 also includes a 74F74 PE-host flip-flop 906.
  • the D and CP inputs of the PE-host flip-flop 906 receive the positive five volt potential 784 through the resistor 904.
  • the SD input of the PE-host flip- flop 906 receives the PE-WTD* signal from the interface circuit bus 882 while its RD input receives a H-RDD* signal from the bus 882.
  • the state of the PE-host flip-flop 906 indicates whether the PE CPU 82 has stored data for the host personal computer 20 into the PE-host register 98, or whether the host personal computer 20 has already read the last such data stored there and that, therefore, the PE CPU 82 may store new data into the PE-host register 98.
  • the PE-host interface circuit 58 includes three 20L8 PALs UA35 912a, UA36 912b and UA37 912c.
  • the first of these PALs, UA35 912a receives, via the SA section 818 of the PE ISA bus 42, the SAOO-SAll address signals from the host bus 38 of the host personal computer 20.
  • the PAL UA35 912a also receives, via the interface circuit bus 882, a IO-SEL* signal and a HI* signal from the PAL UA37 912c.
  • the PAL UA35 912a Responsive to these input signals, the PAL UA35 912a transmits H-DSEL*, H-SSEL*, FUNCT-A, FUNCT-B, PC-INT*, and PORT-EQ* signals via the interface circuit bus 882.
  • the PAL UA35 912a also transmits a PETRGRST signal to the PE CPU 82 via the PE control signal section 642 of the PE bus 64 for resetting the Motorola MC68020 and MC68882 ⁇ s) included in the PE CPU 82 together with the VSC(s) 684 and 744, and the flip-flops described above.
  • the following table sets forth the pin numbers for the PAL UA35 912a together with the names of the signals either received by or transmitted from each of its pins.
  • An address on the SAOO-SAll signal lines from the host personal computer 20 that lies in the range 0304H-0307H causes the PAL UA35 912a to assert its output signal H-DSEL*.
  • An address on the SAOO-SAll signal lines from the host personal computer 20 that lies in the range 0300H-0303H causes the PAL UA35 912a to assert its output signal H-SSEL*.
  • An address on the SAOO-SAll signal lines from the host personal computer 20 5 that lies in the range 0308H-030BH causes the PAL UA35 912a to assert its output signal PETRGRST thereby resetting the Motorola MC68020 included in the PE CPU 82.
  • An address on the SAOO-SAll signal lines from the host personal computer 20 that lies in the range 0314H-0317H causes the PAL UA35 912a to
  • the PAL UA36912b receives input signals Al, A2, RESET*, and R/W* from the Motorola MC68020 included in the PE CPU 82.
  • the PAL UA36 912b receives the input signal HIF* from the PAL UAO 94c in the memory 92.
  • the PAL UA36 912b receives input signals H-DA and H-DU from the host-PE flip-flop 902.
  • the PAL UA36 912b receives input signals PE-DA and PE-DU from the PE-host flip-flop 906.
  • the PAL UA36 912b receives input
  • the PAL UA36 912b receives input signals BIOW* and BIOR* from the PAL UA37 912c.
  • the PAL UA36 912b transmits signals D16 and D17 to the Motorola MC68020 included in the PE CPU 82. (With regard to nomenclature for the data signal lines of the Motorola MC68020,
  • the PAL UA36 912b supplies signals H-RDD* and PE-WTD* to the host-PE flip-flop
  • the PAL UA36 912b supplies the signals IO-D00 and IO-D01 to the transceiver 804a via the register bus 808 for transmission to the host bus 38 of-the personal computer 20 as data bits SD00 and SD01.
  • the following table sets forth the pin numbers for the PAL UA36 912b together with the names of the signals either received by or transmitted from each of its pins.
  • Equations for the output signals from the PAL UA36 912b which specify the logical relationships that exist between the input signals to the PAL UA36 912b and its output signals.
  • the 20L8 PAL integrated circuit used for the PAL UA36 912b has tri-state output drivers that may be set to a high impedance state by an input signal applied to an input terminal of the PAL.
  • the phrase "IF(signal name)" indicates that the output driver for the signal whose equation follows the phrase is enabled to transmit an output signal only upon the occurrence of the specified condition.
  • H-RDD* H-DSEL* & BIOR* + RESET* H-WTD* H-DSEL* & BIOW*
  • the PAL UA37 912c receives input signals MEMW*, MEMR*, IOW*, IOR*, SMEMW*, SMEMR*, AEN and SBHE* from the host bus 38 in the personal computer 20 via the PE ISA bus 42 and the host control signal section 562 of the PE host bus 56.
  • An input terminal of the PAL UA37 912c connects to a SA00 address line 922 in the SA section 818 of the PE ISA bus 42 to receive the SA00 address signal from the host bus 38.
  • the PAL UA37 912c receives the PORT-EQ* signal from the PAL UA35 912a via the interface circuit bus 882.
  • the PAL UA37 912c supplies output signals HI* and IO-SEL* to the PAL UA35 912a via the interface circuit bus 882.
  • the PAL UA37 912c supplies output signals BIOW* and BIOR* to the PAL UA36 912b via the interface circuit bus 882.
  • the PAL UA37 912c also supplies the output signal BIOR* to the SR* input terminals of the transceivers 802a-b and 804a-b.
  • the PAL UA37 912c supplies output signals LO-E* and HI-E* respectively to the CE* input terminals of the transceivers 802a and 802a, and to the CE input terminals of the transceivers 802b and 804b.
  • the following table sets forth the pin numbers for the PAL UA37 912c together with the names of the signals either received by or transmitted from each of its pins.
  • IO-SEL* IOW* & AEN* & PORT-EQ*
  • HI-E* IOR* & PORT-EQ* & AEN* & SBHE* + IOW* & PORT-EQ* & AEN* & SBHE*
  • the host-PE register 96 includes two 74F373 latches 962a and 962b for storing a sixteen bit data word of control and status signals that the host personal computer 20 may transmit to the PE CPU 82.
  • the OE* input terminal of the latches 962a and 962b receives the PE-RDD* signal from the PAL UA36 912b via the interface circuit bus 882.
  • the E input terminal of the 962a and 962b receives the H-WTD signal from the inverter 894 via the interface circuit bus 882.
  • the 96 includes two 74F373 latches 982a and 982b for storing a sixteen bit data word of control and status signals that the PE CPU 82 may transmit to the host personal computer 20.
  • the OE* input terminal of the latches 982a and 982b receives the H-RDD* signal from the PAL UA36912b via the interface circuit bus 882.
  • the E input terminal of the 982a and 982b receives the PE-WTD signal from the inverter 892 via the interface circuit bus 882.
  • the host personal computer 20 exchanges data signals SD00-SD03 of the host bus 38 with DQ0-DQ3 terminals of the VRAM integrated circuit 442a included in the first multi-port VRAM 44 via the PE ISA bus 42, the transceiver 802a, and data signal lines H-D0 through H-D31002a of the host buffered data section 566 of the PE host bus 56.
  • host personal computer 20 exchanges data signals SD04-SD07 with the VRAM integrated circuit 442b on data signal lines H-D4 through .H-D7 1002b of the host buffered data section 566.
  • the host personal computer 20 exchanges data signals SD08-SD11 with the VRAM integrated circuit 442c on data signal lines H-D8 through H-Dll 5 1002c of the host buffered data section 566 except that the signals pass through the transceiver 802b rather than the transceiver 802a.
  • host personal computer 20 exchanges data signals SD12-SD15 with the VRAM integrated circuit 442b on data signal lines H-D12 through H-D15 1002d of
  • the SDQ0-SDQ3 terminals of the VRAM integrated circuit 442a included in the first multi-port VRAM 44 exchange data with the SDQ0-SDQ3 terminals of the VRAM integrated circuit 462a included in the second multi-port VRAM 46 via IM0-IM3 5 signal lines 1004a in the inter memory bus 48.
  • the VRAMs 442b and 462b exchange data via IM4-IM7 signal lines 1004b in the inter memory bus 48
  • the VRAMs 442c and 462c exchange data via IM8-IM11 signal lines 1004c
  • the VRAMs 442d and 462d exchange data via IM12-IM15 signal lines 1004d.
  • A0-A7 terminals of each of the four VRAM integrated circuits 442a-442d receive address signals from the VSC 684 included in the first VRAM control circuit 68 on address lines H-MA0 through H-MA7 1006. Via the first VRAM
  • a RAS* terminal of each of the four VRAM integrated circuits 442a-442d receives a H-RAS0* signal from the VSC 684
  • a TRG* terminal receives a H-TRG* signal from the VSC 684.
  • a CAS* terminal of each of the VRAMs 442a and 442b receives a
  • H-CASLO* signal from the VSC 684 via the first VRAM control section 662 of the first VRAM control and address bus 66 while the CAS* terminals of each of the VRAMs 442c and 442d receives a H-CASHI* signal from the VSC 684.
  • a SE* terminal of each of the VRAMs 442a-442d receives a H-SOE* signal from the PAL UA5
  • a W* terminal of each of the VRAMs 442a and 442b receives a H-WLO* signal from the PAL UA6 682b via the first VRAM control section 662 of the first VRAM control and address bus 66 while the W* terminals of each of the VRAMs 442c and 442d receives a H-WHI* signal from the PAL UA6 682b.
  • VRAMs 442a-442c Analogous to the VRAMs 442a-442c, via data signal lines D16 through D19 1012a in the PE data section 646 of the PE bus 64, DQ0-DQ3 terminals of the VRAM 462a included in the second multi-port memory 46 respectively receive data signals D16 through D19 from the Motorola MC68020 included in the PE CPU 82.
  • DQ0-DQ3 terminals of the VRAM 462a included in the second multi-port memory 46 respectively receive data signals D16 through D19 from the Motorola MC68020 included in the PE CPU 82.
  • data signal lines D20 through D23 1012b the VRAM 462b receives data signals D20 through D23 from the Motorola MC68020
  • data signal lines D24 through D27 1012c the VRAM 462c receives data signals D24 through D27
  • signal lines D28 through D31 1012d the VRAM 462d receives data signals D28 through D31.
  • A0-A7 terminals of each of the four VRAM integrated circuits 462a-462d receive address signals from the VSC 744 included in the second VRAM control circuit 74 on address lines PE-MAO through PE-MA71016.
  • a RAS* terminal of each of the four VRAM integrated circuits 462a-462d receives a PE-RAS0* signal from the VSC 744, and a TRG* terminal receives a PE-TRG* signal from the VSC 744.
  • a CAS* terminal of each of the VRAMs 462a and 462b receives a PE-CASL0* signal from the VSC 744 via the second VRAM control section 722 of the second VRAM control and address bus 72 while the CAS* terminals of each of the VRAMs 462c and 462d receives a PE-CASHI* signal from the VSC 744.
  • a SE* terminal of each of the VRAMs 462a-462d receives a PE-SOE* signal from the PAL UA5 682a via the second VRAM control section 722 of the second VRAM control and address bus 72 while a SC terminal of each of the VRAMs 462a-462d receives a XSCLK signal from the PAL UA5 682a.
  • a W* terminal of each of the VRAMs 462a and 462b receives a PE-WLO* signal from the PAL UA6 682b via the second VRAM control section 722 of the second VRAM control and address bus 72 while the W* terminals of each of the VRAMs 462c and 462d receives a PE-WHI* signal from the PAL UA6 682b.
  • the host personal computer 20 exchanges data signals SD00-SD07 of the host bus 38 with D0-D7 terminals of the VSC 5 684 included in the first VRAM control circuit 68, via the data signal lines H-DO through H-D3 1002a and H-D4 through H-D7 1002b of the host buffered data section 566 of the PE host bus 56, that also respectively connect to the VRAM integrated circuits 442a and 442b in the first multi-port VRAM 44.
  • the host personal computer 20 exchanges data signals SD00-SD07 of the host bus 38 with D0-D7 terminals of the VSC 5 684 included in the first VRAM control circuit 68, via the data signal lines H-DO through H-D3 1002a and H-D4 through H-D7 1002b of the host buffered data section 566 of the PE host bus 56, that also respectively connect to the VRAM integrated circuits 442a and 442b in the first multi-port VRAM 44.
  • host personal computer 20 supplies address signals SA1-SA8 of the host bus 38 to CA0-CA7 terminals of the VSC 684, via H-Al through H-A8 signal lines 1022a included in the host buffered address section 564 of the PE host bus 56.
  • the host personal computer 20 also supplies address signals SA9-SA16 of the host
  • HSYNC*, VSYNC* and RESET* terminals of the VSC 684 respectively, receive signals from the HSYNC*, VSYNC* and
  • VSC 744 20 RESET* terminals of the VSC 744, via the VRAM synchronization signal bus 76.
  • Supplying these three signals from the VSC 744 to the VSC 684 slaves the operation of the SDQ0-SDQ3 terminals of the VRAM integrated circuits 442a-442d to the operation of the SDQ0-SDQ3 terminals of the VRAM integrated circuits
  • the inverter 688a receives the CLK signal from the riost bus 38 of the personal computer 20 via the host control signal section 562 of the PE host bus 56.
  • the output signal from the inverter 688a which is the logical inverse of the CLK signal of the host personal computer 20, is supplied as an input signal to the inverter 688b and to the CP input of the flip- flop 686.
  • the inverter 688a supplies an output signal, H-SYSCLK, to a SYSCLK terminal of the VSC 684 via the first VRAM control signal section 662 of the first VRAM control and address bus 66.
  • the H-SYSCLK signal is the same as the CLK signal of the host personal computer 20 delayed by the transmission delays of the inverters 688a and 688b.
  • the D input of the flip-flop 686 receives a H-ALE* signal from the PAL UA6 682b.
  • the Q output of the flip-flop 686 supplies a H-XALE* to an ALE terminal of the VSC 684 via the first VRAM control signal section 662.
  • the flip-flop 686 Since the flip-flop 686 operates synchronously with the CLK signal of the host personal computer 20, its operation synchronizes the H-ALE* signal from the PAL UA6 682b to the CLK signal of the host personal computer 20 before transmitting the H-ALE* signal to the ALE terminal of the VSC 684 as the H-XALE* signal.
  • Input terminals CEH* and CEL* of the VSC 684 receive H-CEH* and H-CEL* signals from the PAL UA5 682a via the first VRAM control signal section 662 of the first VRAM control and address bus 66.
  • Input terminals FS0, FS1, FS2, and CS* of the VSC 684 respectively, receive H-FS0, H-FS1 and H-FS2 signals from the PAL UA7 682c via the first VRAM control signal section 662.
  • a R/W* input terminal of the VSC 684 receives the MEMW* signal from the host bus 38 of the personal computer 20 via the host control signal section of the 562 of the PE host bus 56.
  • a VDCLK input terminal of the VSC 684 receives the 5 MHZ BCLK signal from the CPU 82 via the PE control signal section 642 of the PE bus 64.
  • Input terminals HOLDACK*, RS0 and RSI of the VSC 684 are connected to electrical ground potential 782.
  • a BLANK* output terminal of the VSC 684 transmits a SGATE* signal to the PAL UA5 682a via the first VRAM control signal section 662.
  • 15 terminals of the VSC 684 respectively transmit a H-RDY* signal and a H-W* signal to the PAL UA6 682b via the first VRAM control signal section 662.
  • the PAL UA5 682a receives, as an input signal, the A15 address signal from the Motorola MC68020 included in the PE CPU 82.
  • the PAL UA5 682a receives as an input signal the 20 MHz SCLK signal from the PE CPU 82.
  • the SA00, SA09 and SA10 address signals from the host bus 38 of the personal computer 20 are supplied as input signals HA-00, HA-09 and HA-10 to the PAL UA5 682a via the host buffered address section 564 of the PE host bus 56.
  • the PAL UA5 Via the host control section 562 of the PE host bus 56, the PAL UA5
  • the PAL UA5 682a receives as an input signal the SBHE control signal from the host bus 38. Via the first VRAM control section 662 of the first VRAM control and address bus 66, the PAL UA5 682a receives as an input signal the SGATE* signal from the VSC 684. Via the first VRAM control section 662, the PAL UA5 682a
  • the PAL UA5 682a receives as input signals PE-FSO, PE-FS1 and PE-FS2 from ' the
  • the PAL UA5 682a transmits the CEL* and CEH* signals to the VSC 684 via the first VRAM control signal section 662 of the first VRAM control and address bus 66.
  • the PAL UA5 682a transmits the XSCLK signal to the VRAM integrated circuits
  • the PAL UA5 682a transmits the H-SOE* signal to the VRAMs 442a-442d, and to a
  • H-CEL* H-MCS* & H-A0*
  • H-CEH* H-MCS* & SBHE*
  • H-XSOE* H-FSO* & H-FSl* & H-FS2 & H-A9 & H-A10
  • PE-XSOE* PE-FSO* & PE-FS1* & PE-FS2 & A15
  • PE-SOE* PE-XSOE
  • the PAL UA6 Via the first VRAM control signal section 662 of the first VRAM control and address bus 66, the PAL UA6 682b receives input signals H-CASLO*, H-CASHI*, H-W*, H-TRG* and H-RDY* from the VSC 684 included in the first VRAM control circuit 68. Via the second VRAM control signal section 722 of the second VRAM control and address bus 72, the PAL UA6 682b receives input signals PE-CASLO*, PE-CASHI*, PE-W* and PE-TRG* from the VSC 684 included in the first VRAM control circuit 68.
  • the PAL UA6 682b receives input signals H-FSO, H-FSl and H-FS2 from the PAL UA7 682c.
  • the personal computer 20 supplies signals MEMR*, MEMW* and AEN of the host bus 38 to the PAL UA6 682b.
  • the PAL UA6 682b transmits signals H-WHI* and H-WLO* to the VRAM integrated circuits 442a-442d, via the first VRAM control signal section 662 of the first VRAM control and address bus 66 as described above. Via a second VRAM control signal section 722 of the second VRAM control and address bus 72, the PAL UA6 682b transmits signals PE-WHI* and PE-WLO* respectively to a W* input terminal of VRAM integrated circuits 462c and 462d, included in the second multi-port VRAM 46, and to a W* input terminal of the VRAM integrated circuits 462a and 462b.
  • the PAL UA6 682b transmits a H-ALE* signal to the flip- flop 686 via the second VRAM control signal section 622 as described above. Via the host control signal section 562 of the PE host bus 56, the PAL UA6 682b transmits the IOCHRDY signal to the host bus 38 of the personal computer 20.
  • the following table sets forth the pin numbers for the PAL UA6 682b together with the names of the signals either received by or transmitted from each of its pins.
  • H-ALE* AEN* & H-FSO* & MEMR* + AEN* & H-FSO* & MEMW*
  • H-WLO* H-W* & H-CASLO* + H-W* & H-TRG*
  • H-WHI* H-W* & H-CASHI* + H-W* & H-TRG*
  • PE-WLO* PE-W* & PE-CASLO* + PE-W* & PE-TRG*
  • PE-WHI* PE-W* & PE-CASHI* + PE-W* & PE-TRG*
  • the personal computer 20 supplies signals DACKO*, MEMR* and MEMW* of the host bus 38 as input signals to the PAL UA7 682c.
  • the PAL UA6682c also receives input signals H-MSEL* and H-CSEL* via the host control signal section 562 from the selectors 832 and 852.
  • the pe'rsonal computer 20 supplies address signals SA09-SA15 as input signals to the PAL UA7 682c.
  • the PAL UA6 682c transmits output signals H-FSO, H-FSl, H-FS2, and H-MCS* to the PALs UA5 682a and UA6 682b, and to the VSC 684 included in the first VRAM control circuit 68.
  • the following table sets forth the pin numbers for the PAL UA7 682c together with the names of the signals either received by or transmitted from each of its pins.
  • H-S2R* H-CSEL* & DACKO & MEMR* & H-A15* & H-A14*
  • H-R2S* H-CSEL* & DACKO & MEMR* & H-A15* & H-A14*
  • H-REGS* H-CSEL* & DACKO & MEMR* & H-A15* & H-A14*
  • H-XY* H-CSEL* & DACKO & MEMR* & H-A15* & H-A14*
  • H-FSO H-S2R* + H-REGS*
  • H-FSl H-R2S* + H-S2R* + H-REGS* + H-XY*
  • H-FS2 H-REGS* + H-XY*
  • H-MCS* H-MSEL* & DACKO & MEMR* + H-MSEL* & DACKO & MEMW* + H-R2S* + H-S2R* + H-REGS*
  • the PE CPU 82 exchanges data signals D16-D23 with DO- D7 terminals of the VSC 744, included in the second VRAM control circuit 74, via the data signal lines D16 through D19 1012a and D20 through D23 1012b of the PE data section 646 of the PE bus 64, that also respectively connect to the VRAM integrated circuits 462a and 462b in the second multi-port VRAM 46.
  • the PE CPU 82 supplies address signals A1-A8 to CA0-CA7 input terminals of the VSC 744 via Al through A8 signal lines 1032a included in the PE address section 644 of the PE bus 64.
  • the PE CPU 82 also supplies address signals A9-A16 to RA0-RA7 terminals of the VSC 744 via A9 and A8 signal lines 1032b included in the PE address section 644.
  • RSO and RSI input terminals of the VSC 744 receive address signals A22 and A23 via A22 and A23 signal lines 1032c included in the PE address section 644.
  • HSYNC*, VSYNC* and RESET* terminals of the VSC 744 respectively transmit signals to the HSYNC*, VSYNC* and RESET* terminals of the VSC 684 via the VRAM synchronization signal bus 76 as described above.
  • Input terminals ALE, FS0, FS1, FS2, CEH*, CEL*, and CS* of the VSC 744 respectively receive PE-ALE, PE-FSO, PE-FS1, PE-FS2, PE-CEH*, PE-CEL* and PE-MCS* signals from the PAL UA13 742 via the second VRAM control signal section 722 of the second VRAM control and address bus 72.
  • a R/W* input terminal of the VSC 744 receives the R/W* signal from the Motorola MC68020 included in the PE CPU 82 via the PE control signal section 642 of the PE bus 64.
  • a VDCLK input terminal of the VSC 744 receives the 5 MHZ BCLK signal from the CPU 82 via the PE control signal section 642 of the PE bus 64; while a SYSCLK input terminal of the VSC 744 receives the PCLK signal from the CPU 82.
  • Input terminals HOLDACK* of the VSC 744 connects to the positive five volt potential 784 through a resistor 1034.
  • Output terminals MA0-MA7 of the VSC 744 supply address signals to the VRAM integrated circuits 462a-462d via the address lines PE-MAO through PE-MA7 1016.
  • Output signals from terminals CASHI*, CASLO*, TR*/QE*, and RASO* of the VSC 744 respectively transmit PECASHI*, PECASLO*, PE-TRG* and PE-RAS0* signals to the VRAM integrated circuits 462a-462d, via the second VRAM control signal section 722 of the second VRAM control and address bus 72, as described in greater detail above.
  • the output signals from terminals CASHI*, CASLO*, TR*/QE*, and W* of the VSC 744 respectively transmit the PECASHI*, PECASLO*, PE-TRG* and a PE-W* signals to the PAL UA6 682b via second VRAM control section 722 of the second VRAM control and address bus 72.
  • a RDY*/HLD* output terminal of the VSC 744 transmits a PE-RHD* signal to the input of the inverter 748 via the second VRAM control signal section 722 of the second VRAM control and address bus 72.
  • the second VRAM control circuit 74 includes a circuit for synchronizing a PE-ALE signal to the PCLK supplied within the PE CPU 82 to the Motorola MC 68020.
  • the PCLK signal is supplied, via a PCLK signal line 1036 in the PE control signal section 642 of the PE bus 64, to the CP input terminal of the flip-flop 746a.
  • the Jl input terminal of the flip-flop 746a connects to electrical ground 782, while its Kl input terminal connects to the positive five volt potential 784 through a resistor 1042.
  • the PAL UA13 742 supplies a PE-DS signal to the SD1 input terminal of the flip-flop 746a.
  • the flip-flop 746a transmits a VAD signal from its Ql output terminal to the PAL UA13 742 via the second VRAM control signal section 722 of the second VRAM control and address bus 72.
  • the CP input terminal of the flip-flop 746b receives the PCLK signal.
  • the VSC 744 supplies a PE-RDH* signal to the input terminal of the inverter 748, that also connects to the positive five volt potential 784 through a resistor 1044.
  • the inverter 748 supplies a PE-RDH signal to the SD1 input terminal of the flip-flop 746b.
  • the flip-flop 746b transmits a BDTACK* signal from its Q2 output terminal to the PAL UAO 94c, via the second VRAM control signal section 722 of the second VRAM control and address bus 72.
  • the PAL UA13 742 receives input address signals A16- A23 from the Motorola MC68020 included in the PE CPU 82 via the
  • the PAL UA13 742 Via the PE control signal section 642 of the PE bus 64, the PAL UA13 742 also receives a DS input signal from the Motorola MC68020 together with PE-LDS* and a PE-UDS* signals- from the PAL UB10 included in the PE CPU 82.
  • the PAL UA13 742 receives a VAD input signal from the flip-flop 746a.
  • the PAL UA13 742 transmits signals PE-ALE, PE-FSO, PE-FSl, PE-FS2, PE-CEH*, PE-CEL*, and PE-MCS* to the VSC 744.
  • the PAL UA13 742 also transmits signals PE-FSO, PE-FSl and PE-FS2 to the PAL UA5 682a included in the first VRAM control circuit 68.
  • the PAL UA13 742 transmits a PE-DS signal to the inverter 748.
  • the following table sets forth the pin numbers for the PAL UA13 .742 together with the names of the signals either received by or transmitted from each of its pins.
  • PE-CEL* DS* & VAD*
  • PE-CEH* DS* & VAD*
  • PE-ALE* DS* & VAD*
  • PE-DS DS*
  • FIG. 3 depicts the allocation of memory address space in the host personal computer 20 on the left hand side of the FIG. and in the PE 40 on the right hand side.
  • the host addresses for the first multi-port VRAM 44 begins at 50 0000H.
  • the host usually addresses the registers that are in the VSC 68 beginning at 0D 0000H.
  • the host-PE register 96 and the PE-host register 98 are usually addressed in the I/O address space of the host digital computer 20 beginning at location 300H.
  • the EPROM of the program memory 94b begins at address 0000:0400H immediately above the area reserved for the Motorola MC68020's start up and exception vectors.
  • Addresses for the static RAM of the stack and cache memory 94a begin at 001O:O000H.
  • Addresses for the second multi-port VRAM 46 begin at 0020:0000H.
  • the host addresses the registers that are in the VSC 74 beginning at 0030:0000H.
  • the host-PE register 96 and the PE-host register 98 are addressed beginning at location 0040:0000H.
  • the host-PE register 96 and the PE-host register 98 Depicted in FIG. 4 are the host-PE register 96 and the PE-host register 98. If either of the registers 96 or 98 are presently transmitting data respectively from the host personal computer 20 to the PE 40 or conversely, all bits in the registers are used for 16 or 8 bit data words. If either of the registers 96 or 98 are presently transmitting status information, then only bits bO and bl are used. When transmitting status information to the host personal computer 20, the PAL UA36 912b transmits the H-DU signal from the flip- flop 902 and the PE-DA signal- from the flip-flop * 904 respectively as bits bO and bl of the PE-host register 98.
  • a value of zero in bO bit of the PE-host register 98 indicates that a data word from the PE to be fetched by the host is presently stored in the latches 982a and 982b.
  • a value of zero in the bl bit of the PE-host register 98 indicates that the PE 40 has fetched the previous data word stored by the host personal computer in the latches 962a and 962b.
  • the PAL UA36 912b transmits complementary information to the PE CPU 82 via the DO and Dl signal lines of the PE data section 646 included in the PE.bus 64.
  • the CPU 22 of the personal computer 20 and the PE CPU 82 execute complementary routines set forth below in computer programs UTIL.C and PE01UTIL.017.
  • a computer program, FUNCTION.C set forth below invokes the routines in the computer program UTIL.C to provide all the communication and supervisory functions required to perform particular mathematical computations requested by program calls to FUNCTION.C.
  • FUNCTION.C For example, if the program calling FUNCTION.C wanted to solve a set of linear equations for which the data were already available, that program would make two subroutine calls to FUNCTION.C. The first of these subroutine calls would invoke a mathematical function described in the book "LINPAK Users' Guide,” copyrighted 1979 by the Society for Industrial and Applied Mathematics, to cause the PE to factor the matrix of coefficients for the linear equations. The second subroutine call would then invoke another mathematical function described in that book to cause the PE to solve the triangular matrix resulting from the factorization.
  • the PE CPU 82 executes a supervisory computer program, PE01IOS.011 also set forth below, to supervises the overall operation of the PE 40.
  • the computer program PE01IOS.011 invokes routines in the computer program PE01UTIL.017 to look for requests from the personal computer 20 and to respond to such requests to the extent they involve communication between the PE 40 and the host personal computer 20.
  • a request involves performing a mathematical computation on data that is already present in the second multi-port VRAM 46 as the result of inter-processor communication effected by routines in the computer program UTIL.C in the personal computer 20 and by routines in the computer program PE01UTIL.017 in the PE CPU 82, then the computer program PE01IOS.011 invokes another computer program PE01MATH.
  • the computer program PE01MATH is an assembly language program that implements the mathematical algorithms described in the "LINPAK Users' Guide.” Accordingly, the "LINPAK Users' Guide" is incorporated by reference as though fully set forth here.
  • a computer program executed by the host personal computer 20 first loads the data into the first multi-port VRAM 44. After having loaded the data into the VRAM 44, the computer program executed by the host personal computer 20 supplies signals to the PE 40 which cause it to transfer the data over the inter-memory bus 48 from the VRAM 44 to the second multi-port VRAM 46. Once the data is present in the VRAM 46, the computer program executed by the host personal computer 20 then directs the PE CPU 82 to perform the desired mathematical computation.
  • the personal computer 20 may be preparing the data for a succeeding computation and storing it in the first multi-port VRAM 44 free from contention with memory exchanges occurring between the PE CPU 82 and the second multi-port VRAM 46.
  • the PE CPU 82 finishes the mathematical computation, it transmits signals to the host computer 20 indicating that fact.
  • the computer program executed by the host personal computer 20 then supplies additional signals to the PE 40 that cause the results of the computation to be transferred back over the inter-memory bus 48 from the VRAM 46 to the VRAM 44.
  • UTIL.C The following computer program called UTIL.C, contains routines executed by the host personal computer 20 to effect different types of interprocessor communications between the personal computer 20 and the PE 40.
  • PE_Mode TX; return(IOMode) ; ⁇
  • H_Mode TX; return(IOMode) ;
  • Signal CheckPE(PE); /* get signal from host */ if(Signal EQ ACK) return TRUE; return FALSE;
  • int H2PE_LB2H(PE,Data) int PE unsigned long Data
  • char HexString[20] char *p
  • int i Length, Signal, Status
  • HexStringfO] hex_digit[ (*(unsigned long *)&Data) » 28) & OxOOOOOOOf];
  • HexString[l] hex_digit[ (*(unsigned long *)&Data) » 24) & OxOOOOOOOf];
  • HexString[2] hex_digit[ (*(unsigned long *)&Data) » 20) & OxOOOOOOOf];
  • HexString[5] hex_digit[ (*(unsigned long *)&Data) » 8 ) & OxOOOOOOOf];
  • HexString[6] hex_digit[ (*(unsigned long *)&Data) » 4 ) & OxOOOOOOOf];
  • HexString[7] hex_digit[ (*(unsigned long *)&Data) ) & OxOOOOOOOf];
  • H2PE(PE,Token) /* send selected Token */
  • PE Buffer has been cleared by internal code ");*/ return(TRUE);
  • Data PE2H(PE); printf(" ⁇ n End Row: %02X ⁇ n",Data) ; wgoto(12,2) ; if(Data NE EndRow) return(FALSE) ;
  • SCLK gate /* Start writing to PE buffer from PE SAM V*/ H2PE(PE, 'h* ); /* send Token to PE to start auto update */ if(PE2H(PE) NE 'h') return(FALSE); /* PE is deaf V if(CheckPE(PE) NE ACK) return(FALSE) ; /* PE is screwed up
  • Rows-per-Buffer Calculate new(VSB) from new( rows_per_buffer ) and old(VEB) Units are lines which equal rows since we set 1 row per line.
  • VSB Size + buf fer_back_porch + buf fer_sync_width -
  • VES 4; put_byte(VES & 0x00FF,HOST_REGS,VES_LSB) ; /* send LSB to register
  • V Byte VES » 8; /* shift MSB to LSB location */ put_byte(Byte&0x00FF,HOST_REGS,VES_MSB); /* send MSB to register
  • VEB 6; put_byte(VEB & 0x00FF,HOST_REGS,VEB_LSB) ; /* send LSB to register
  • V Byte VEB » 8; /* shift MSB to LSB location */ put_byte(Byte&0x00FF,HOST_REGS,VEB_MSB) ; /* send MSB to register */
  • VT VSB+2 ; put_byte ( VT & 0x00FF,HOST_REGS ,VT_LSB ) ; /* send LSB to register
  • V put_byte ( VT & 0x00FF,HOST_REGS ,VI_LSB) ; /* send it to register
  • V new_data atoi(entry); /* convert it to integer */ printf("%3d ",new_data); /* show it and erase entry */ ⁇ return(new_data) ; ⁇ text_window(cmd,stringl,string2) /* show main working screen window */ int cmd; char stringl[20], string2[20]; if(cmd EQ CLEAR) wclean(BLACK_BACK); /* erase if required
  • Data PE2H(PE); if(Data GE ' • ) printf("%c",Data); if(Data EQ OxOD) printf(" ⁇ n") ; while(Data NE EOS); return Signal;
  • 0x10; /* bit 8 in CRI to high */ put_byte(Byte,HOST_REGS,CRl_MSB); return(TRUE); if(Processor GT HOST)
  • Bytej Number; /* set bits 12, 13, and 14 of Byte to value of State */ put_byte(Byte,HOST_REGS,CR1_MSB) ; return(TRUE); if(Processor GT HOST)
  • Number; /* set bits 12, 13, and 14 of Byte to value of State */ put_byte(Byte,HOST_REGS,CR2_MSB) ; return(TRUE) ; ⁇ else
  • VIDCLKs Therefore the number of VIDCLKs in HSB must be:
  • V HSB 73
  • HES 4; put_byte(HES&0x00FF,0x0D0C0 f 0) ; /* send LSB to register */
  • HT Size/4 + row_front_porch + row-back-porch + sync width - 1
  • HT 78; put_byte(HT & OxOOFF,OxODOCO,24) ; /* send LSB to register */
  • Byte HT » 8; /* shift MSB to LSB location */ put_byte(Byte&OxOOFF,OxODOCO,28) ; /* send MSB to register */ return(TRUE) ; ⁇ return(FALSE) ;
  • VIDCLKs Therefore the number of VIDCLKs in HSB must be:
  • HSB words_per_row/4 + row_back_porch + row_sync_width - 1
  • V HSB 70
  • HES 4; put_byte(HES&0x00FF,0x0D0C0,0); /* send LSB to register */
  • HT Size/4 + row_front_porch + row-back-porch + sync width - 1
  • templ PE2H(PE); if (not isxdigit(tempi) ) printf("PE2H_H2F returning 0"); return FALSE;
  • ExtAddress 0x500000L; return ExtAddress; ⁇ int PE2H(int PE) /* get data from PE */ int Data;
  • PE_DAWait(PE) /* Host waits for PE to send it */
  • V return Data; /* to meter out data ⁇ void H2PE(PE,Data) int PE,Data; /* assuming Host has data (H_DA TRUE) ⁇ /* send it to PE */
  • FP_OFF(ptr) offset; return *ptr; ⁇ int get_byte(seg,offset) int seg,offset;
  • PE01UTIL.017 contains assembly language routines executed by the PE CPU 82 to effect various different types of interprocessor communications between the PE 40 and the host personal computer
  • SAM2RAM * Switch Buffer controls to Receive Mode move.l #$248000,aO ; address for PseudoSAM2RAM
  • TXRowL move.l #HSB_LSB,a0 ; point to lsb of HSB move.w #70, (aO) ; put it into LSB of Vert.
  • RXRowL move.l #HSB_LSB,aO ; point to lsb of HSB move.w #73, (aO) ; put it into LSB of Vert.
  • BufLength: movem.l d0-d2/a0,-(a7) move.w d2,dl get length add.w #6,dl compute VSB * 262 256+5+2-1 move.l #VSB_LSB,a0 point to lsb of VSB move.w dl,(a0) move.l #VSB MSB,a0 point to MSB of Vert.
  • H2PEd ************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************ jsr H2PEs ; push first 32 bits
  • H2PEhex * read hex number from input port, return in dO******************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
  • PE2Hhex * PE sends 32 bit binary number as 8 hex characters to * Host
  • PEXfrOn movem.l d0/a0,-(a7) ; push registers point to LSB crl
  • Second buffer interrupt should turn transfer off, here
  • PE2RX * Function e: Host to TX mode calls this function******************************************* movem.l d0-d3,-(a7) ; push registers * Calculate number of rows to send
  • PE is set to "slave sync" mode, bsr SyncOff
  • Compute bRAM address of rows sub.w d2,d3 compute number of chunks to load less 1 move.w d3,d0 add.w #l,d0
  • BuffClear clr.w (a6)+ move word into bRAM and bump * pointer sub.w #l,d2 bne BuffClear rts ShowBuffer: move.l #vram,a6 ; bRAM bank 0 address move.w #$0FFF,d3 ; loop count - 1 (16 rows of 256 words ) get word from PE-RAM to d2 copy into dO shift MSB to lower byte send MSB to host get word again send LSB to host
  • FUNCTION.C The following computer program called FUNCTION.C, that the CPU 22 of the host personal computer 20 executes, illustrates the use of the various functions provided by the routines in the program UTIL.C for exchanging data between the host personal computer 20 and the PE 40.
  • V N (unsigned long)(n);
  • PE */ answer question( " ⁇ nSGEFA: Show contents of PE buffer after computation") ; if(answer EQ YES) DumpPE(PE,0,36) ; /* Transfer PE buffer A to Host buffer A */
  • BufPnt_t *pnt unsigned long HBuf, PEBuf, Offset_A, Offset_p, Offset_i,
  • Offset_b unsigned long N,Chunks_A, Chunks_p, Chunks_i, Chunks_b;
  • N (unsigned long)(n);
  • Chunks_A (pnt->Offset_A/512)+1;
  • Chunks_b (pnt->Offset_b/512)+1;
  • PE 0x300
  • PEError(8) ; /* Send matrix size, N, twice */ if(H2PE_B2H(PE,n) EQ FALSE) PEError(8); if(H2PE_B2H(PE,n) EQ FALSE) PEError(8);
  • PE01IOS.011 contains assembly language routines executed by the PE CPU 82 in supervising the overall operation of the PE 40.
  • Mode 0 Bit 0 is Mode
  • * Register Usage: * aO is used for scratch, e.g., message pointers mainly * al is used at i/o base register * a2 is SRAM pointer (not used) * a3 is a pointer to the Function List * a4 is the code pointer * a5 * a6 is the bRAM pointer * a7 is stack pointer * dO carries data byte to and from pio module * dl carries status byte for pio module * d2 is used by ShowString * d3 is the token in list * d4 is the token commanded
  • Dsr (a4) then use it to go and execute the code bra.s Command ; get next command token srch; dc.b 'Searching for Token' ,cr,If,eos ex: dc.b 1 Executing Token' ,cr,If,eos err: dc.b 'Token not in List' ,cr,lf,eos
  • the first multi-port VRAM 44 is primarily intended to be used in transmitting data between the host personal computer 20 and the PE CPU 82, when the PE 40 is not being used to perform computations, the first multi-port VRAM 44 is available to the personal computer 20 to be used in the same manner as any extended memory installed in an IBM PC AT.
  • a PE 40 in accordance with the present invention may be constructed for use with many other different types of presently existing digital computers including IBM PC clones using either the ISA or EISA bus, the IBM P/S2, Sun digital computers and Digital Equipment Corporation ("DEC") computers.
  • the presently preferred embodiment of the program memory 94b is an EPROM memory
  • a PE 40 in accordance with the present invention may used other types of memories for the program memory 94b including EEPROM integrated circuits such as "FLASH" EEPROMs.

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Abstract

The technical field of the invention generally concerns multi-processor digital computers adapted to perform engineering and scientific computations swiftly. The present invention adapts a personal computer for performing engineering or scientific computations by incorporating one or more PEs (40) into a personal computer (20). Each of these PEs (40) includes a pair of multi-port memories (44 and 46) coupled together by an inter-memory bus (48). The first of these two multi-port memories (44) exchanges data with a bus (38) in the personal computer (28). Similarly, the second multi-port memory (46) exchanges data with a PE bus (64). The PE (40) also includes a memory control means (58, 68 and 74) for controlling exchanges of data between the host bus (38) and the first multi-port memory (46), between the two multi-port memories (44 and 46) via the inter-memory bus (48), and between the second multi-port memory (46) and the PE bus (64). Responsive to initiation signals from the host computer (20), data written into one of the memories (44 or 46) transfers automatically from the written memory (44 or 46) into the other memory (46 or 44) in which that data is directly addressable for further processing by the other CPU (82 or 22). Moreover, either or both CPUs (82 or 22) can access their respective memories (46 or 44) without interference from the other CPU (22 or 82) while data are being transferred between the memories (44 and 46).

Description

PROCESSING ELEMENT FOR A MULTI-PROCESSOR DIGITAL COMPUTING SYSTEM
Technical Field The present invention relates generally to the technical field of digital computers and, more particularly, to multi¬ processor digital computers adapted to perform engineering and scientific computations swiftly.
Background Art
Modern engineering practice relies heavily upon digital computers for analysis and simulation. Many engineering and scientific computations can be decomposed into a sequence of floating point vector products. For example, a matrix multiplication, written symbolically as AB = C, can be decomposed into a sequence of vector products in which each row vector of the matrix A is multiplied together with a column vector of the matrix B with the results of each vector product being stored into an entry in the matrix C. In computing such vector products, the exact sequence in which particular pairs of numbers from the row vector of matrix A and from the column vector of matrix B are multiplied together is irrelevant to accurate computation so long as the results of that multiplication can be stored properly in the appropriate entry in the matrix C. Consequently, one characteristic of a scientific or engineering computation is that generally it is possible to have multiple independent computers operate simultaneously on different parts of the computation. Another characteristic of computer programs used in science and engineering is that they generally execute a relatively large number of floating point instructions in comparison with other types of computer programs.
Because the precise sequence of computation is generally irrelevant in scientific and engineering computation, one technique that is employed to reduce the time required to perform a computation is to have multiple processors operate in parallel with each processor simultaneously processing a different portion of the same computation, i.e. parallel processing. Typically one processing element ("PE") in such a parallel computer controls the operation of a single floating point unit ("FPU"). For example, current microprocessors such as Motorola's MC68040 and Intel's 80486 include a FPU integrated into the same chip as the central processing unit ("CPU") itself. Earlier models of microprocessors such as Motorola's MC68000, MC68020 and MC68030, and of Intel's 80186, 80286 and 80386 employ separate integrated circuit chips for the CPU and the FPU. Execution of floating point instructions by a FPU, even the fastest ones, requires substantially longer than the time required for the CPU to load into and to unload processed data from the FPU. For example, when controlling the operation of Motorola's MC68882 FPU, Motorola's MC68030 CPU spends most of the time waiting for the FPU to complete executing one instruction before the CPU can prepare the FPU to execute the next one. Consequently, it is possible to increase CPU utilization and to shorten the time required to execute a scientific or engineering computer program by having a single CPU control the operation of a plurality of FPUs. Recognizing the possibility for these efficiencies, both Motorola's MC68020 and MC68030 have been designed to simultaneously control the operation of several co-processor chips. For example, Motorola's MC68030 has been designed to simultaneously control a combination of up to 8 co-processor chips such as Motorola's MC68882 FPU and/or Motorola's MC68451 memory management unit ("MMU") .
A common difficulty in parallel multi-processor digital computing systems is the need to share data among the several processors. At any particular time, any one of the several processors may require access to a value that was computed at an earlier time by another one of the processors. While this data sharing problem has been recognized by those working in the field of parallel multi-processor digital computing systems for many years and while various different solutions to the problem have been proposed and even implemented, thus far there exists no generally recognized solution to the problem. For example, a system in which several processors share a single memory suffers from the problem of "contention among the various processors for access to the shared memory. Alternatively, if each processor includes its own local memory to avoid contending for a shared resource, then the results of its computations must be shared among all the other processors. Generally, if a common bus is used to interconnect the local memories in the several processors, there is a problem with processors contending for access to the bus.
One particular attempt at solving the preceding problems in multi-processor systems is known as a "postbox" system. In a postbox system, a single, multi-port memory is shared between or among the multi-processors. To access this shared memory, a port on the memory is assigned to each of the processors. One processor commences a data transfer to another processor by accessing the memory through its port and storing the data into a memory location in the shared memory. Subsequently, another processor needing those data will access the shared memory through its port to fetch the data from the memory location into which it has been stored by the first processor. Because a postbox system employs only a single, shared, multi- port memory, the memory must arbitrate memory accesses occurring simultaneously through two or more memory ports. If the shared memory employs a hierarchial arbitration circuit, it is possible for processors assigned the highest priority to block accesses to the shared memory by the lower priority processors.
While computing on personal computers is relatively inexpensive and while high computational speed is theoretically possible if one assembles a multi-processor by combining a plurality of personal computers or microcomputers, the problems described above for multi-processor systems generally prevent such a system from approaching its theoretical capabilities. In particular the memories in personal computers together with the buses by which data are stored into and retrieved from such memories are unsuitable for transferring data at the rates required to perform scientific or engineering computations swiftly. Disclosure of Invention
An object of the present invention is to provide an effective way of adapting a personal computer to efficiently perform scientific or engineering computations. Another object of the present invention is to provide a multi-processor that may be expanded modularly to include a plurality of processing elements.
Another object of the present invention is to provide a multi-processor which adapts a single CPU to effectively control the operation of a plurality of FPUs.
Another object of the present invention is to provide a multi-processor in which a plurality of FPUs operating under the control of a single CPU efficiently process data simultaneously. Another object of the present invention is to provide an effective means by which a plurality of processors may share data.
Another object of the present invention is to provide a multi-processor system in which one processor may not block another processor.
Yet another object of the present invention is to provide a multi-processor that is cost effective, and easy and economical to manufacture.
Briefly, the present invention adapts a personal computer for performing engineering or scientific computations by incorporating one or more PEs into a conventional personal computer. Each of these PEs, that may be incorporated into a host personal computer, includes a pair of multi-port memories.
Each PE also includes an inter-memory bus that interconnects shared ports of the two multi-port memories for exchanging data between the two memories. A host port of the first of these two multi-port memories exchanges data with a bus in the host personal computer over which the CPU and host computer memory exchange data. Similarly, a bus within the PE couples a PE port of the second of the two multi-port memories with a central processing unit included in the PE itself ("PE CPU").
The PE's CPU and the second multi-port memory exchange data over this PE bus. The PE also includes a memory control means for controlling exchanges of data between the host bus and the first multi-port memory, between the two multi-port memories, and between the second multi-port memory and the PE bus. In controlling these various exchanges of data, the PE's memory control means responds to signals received from the host CPU and from the PE CPU.
In the preferred embodiment of the invention, the first and second multi-port memories are video ram ("VRAM") integrated circuits. In response to one set of control signals, one port of such VRAM integrated circuits operates to store or to retrieve data in the same way as conventional single port random access memories ("RAM"). It is this port of the two VRAMs included in the preferred embodiment of the PE which respectively exchange data with the host bus and with the PE bus. In response to a second set of control signals, a second, or serial, port of a VRAM integrated circuit either receives data for storage or transmits stored data. These second, or serial, ports of the VRAM are the shared ports of the PE and are interconnected by the inter-memory bus. Signals supplied to the first and second VRAM cause one of them to transmit data over the inter-memory bus from its shared port while the other VRAM receives such transmitted data from the inter-memory bus for storage within the VRAM. Responsive to initiation signals from the host computer, data written into one of the VRAMs by either the host CPU or by the PE CPU transfers automatically and/or simultaneously from the written VRAM into the other VRAM thereby making them directly addressable for further processing by the other CPU. Moreover, either or both CPUs can access their respective VRAM memories without interference from the other CPU while data are being transferred between the VRAM memories.
These and other features, objects and advantages will be understood or apparent to those of ordinary skill in the art from the following detailed description of the preferred embodiment as illustrated in the various drawing figures. Brief Description of Drawings
FIG. 1 is a block diagram depicting a personal computer incorporating a PE in accordance with the present invention that illustrates the PE's memories, the control for those memories, the control and status registers, and the various buses interconnecting the memories with the host bus, with the inter-memory bus, and with the PE bus;
FIG. 2 is a block diagram depicting the organization of FIGs. 2a-2d into a single composite diagram; FIGs. 2a-2d form a composite block diagram depicting, at the integrated circuit package and signal line level, the memories, memory control, registers, and buses within the PE;
FIG. 3 is a memory allocation diagram depicting the assignment of memory address space for the host personal computer and for the PE in accordance with the present invention; and
FIG. 4 is a diagram depicting the two registers by which the host personal computer and the PE exchange control and status information.
Best Mode for Carrying Out the Invention
Host Personal Computer The block diagram of FIG. 1 depicts a personal computer that is enclosed within a dashed line and referred to by the general reference character 20. The personal computer 20 includes a CPU 22, a RAM memory 24, a disk controller 26 for controlling the operation of a hard disk 28, a video display adapter.32 for controlling the operation of a video monitor 34, and a keyboard 36. A host bus 38 within the personal computer 20 interconnects the CPU 22, the RAM memory 24, the disk controller 26, the video display adapter 32 and the keyboard 36 for transferring data among those various items. Since the preferred embodiment of the host personal computer 20 is an IBM PC AT, the host bus 38 conforms to the Industry Standard Architecture ("ISA") bus of an IBM PC AT personal computer. The terminology used hereafter to identify particular aspects of the ISA bus such as signal names will be those set forth in "AT Bus Design" by Edward Solari, Copyright 1990 Annabooks, which is incorporated by reference as though fully set forth here.
Processing Element 40
FIG. 1 also depicts a plurality of PEs in accordance with the present invention that are illustrated by dashed outlines and referred to by the general reference character 40.
10 FIG. 1 depicts the block diagram for only one of the PEs 40 while the remaining PEs 40 are illustrated only by their dashed outlines because they are obscured by one or more of the other PEs 40. Each of the PEs 40 includes a PE ISA bus 42 that adapts the PE 40 to plug into the ISA host bus 38 and to be
15 electrically connected thereto. Thus, the PE ISA bus 42 extends the host bus 38 onto the PE 40 which includes the particular bus 42. Inclusion of the PE ISA bus 42 in each PE 40 permits it to exchange control and status signals and data with the CPU 22 and RAM memory 24 included in the personal
20 computer 20. While FIG. 1 depicts a total of fifteen PEs 40, as few as one PE 40 or more than 15 PEs 40 may be connected to the host bus 38. By this modularity, the PE 40 of the present invention allows assembly of a computer system for use in performing engineering and scientific computations that is
25 matched to a particular computing requirement.
As depicted in FIG. 1, each of the PEs 40 includes a first multi-port VRAM 44 and a second multi-port VRAM 46. Each PE 40 also includes an inter-memory bus 48 that interconnects serial data in/data out shared ports 52 of the two VRAMs 44 and
30 46. During operation of the PE 40, the VRAMs 44 and 46 exchange data via the inter-memory bus 48. The first VRAM 44 includes a random-access data in/data out host port 54 to which a PE host bus 56 connects. The first VRAM 44 exchanges data with the host bus 38 in the personal computer 20 via the PE
35 host bus 56, a PE-host interface circuit 58, and the PE ISA bus 42. Similarly, a random-access data in/data out PE port 62 of the second VRAM 46 connects to a PE bus 64 included in each PE 40. A first VRAM control and address bus 66 connects the first VRAM 44 to a first VRAM control circuit 68 which also connects to the PE bus 64 and to the PE-host interface circuit 58 via the PE host bus 56. Similarly, a second VRAM control and address bus 72 connects the second VRAM 46 to the first VRAM control circuit 68 and to a second VRAM control circuit 74, which itself also connects to the PE bus 64. The PE bus 64 also connects directly to the PE-host interface circuit 58. A VRAM synchronization signal bus 76 connects the second VRAM control 74 to the first VRAM control 68. Responsive to signals that the PE-host interface circuit 58 receives both from the PE bus 64 and from the host bus 38 via the PE ISA bus 42, to signals that the first VRAM control circuit 68 receives from the PE-host interface circuit 58, from the PE bus 64, and from the second VRAM control circuit 74, and to signals that the second VRAM control circuit 74 receives from the PE bus 64, the combined PE-host interface circuit 58, the first VRAM control circuit 68, and the second VRAM control circuit 74 operate to control exchanges of data between the host bus 38 and the first VRAM 44, between the first VRAM 44 and the second VRAM 46, and between the second VRAM 46 and the PE bus 64. Because the random-access data in/data out ports of each of the VRAMs 44 and 46 responds independently to memory accesses respectively over either the host bus 38 or over the PE bus 64, an access on one of the buses 38 or 64 to the shared multi-port memory provided by the combined VRAMs 44 and 46 cannot block a simultaneous access to the multi-port memory on the other bus 64 or 38.
Included in each PE 40 is a PE CPU 82 which connects to the PE bus 64 and can exchange data with the VRAM 46 via the bus 64. Also included in the PE 40 and connected to the PE bus 64 may be one or more FPUs 84, four of which are illustrated in FIG. 1. The PE CPU 82 transmits signals to the one or more FPUs 84 for controlling their operation via a FPU control signal bus 86. In the preferred embodiment of the invention, the PE CPU 82 includes a Motorola MC68020 and the PE 40 includes at least one Motorola MC68882 FPU as its FPU 84. Because the PE 40 includes the Motorola MC68020 CPU and MC68882 FPU, the PE BUS 64 includes signals normally present in a computer system employing both a Mo.torola 68020 CPU and MC68882 FPU.
Also connected to PE bus 64 is PE memory 92 that includes a stack and cache memory 94a. The stack and cache memory 94a is relatively small, fast static RAM in which stacks created by a computer program executed by the PE CPU 82 are stored and in which temporary and intermediate results may also be stored. In the preferred embodiment of the PE 40, the stack and cache memory 94a is provided by two Hitachi 6264P eight bit static RAM integrated circuits that are connected to the PE bus 64 for storing and retrieving sixteen bit words. The PE memory 92 also includes an erasable programmable read only memory ("EPROM") program memory 94b. The program memory 94b includes two Texas Instruments 2764, 27128 or 27256 EPROM integrated circuits that are connected to the PE bus 64 for retrieving 16 bit words. The program memory 94b stores programs that are executed by the PE CPU 82 including those program that it executes for communicating with the host personal computer 20 and for controlling the operation of the PE 40. Lastly, the memory 92 includes a Texas Instruments 20L8 Programmable Array Logic ("PAL") integrated circuit UA0 94c for controlling the operation of the stack and cache memory 94a and program memory 94b, and for transmitting a signal to the PE CPU 82 indicating when the stack and cache memory 94a, the program memory 94b and the second multi-port VRAM 46 ready to exchange data.
PAL UAO 94c
The following table sets forth the pin numbers for the PAL UAO 94c together with the names of the signals either received by or transmitted from each pin. The input signals FC0, FC1, A20-A23, AS* and R/W* come to the PAL UAO 94c from the Motorola MC68020 included in the PE CPU 82. (In the following and all subsequent signal names, the symbol "*" indicates the logical negation of the signal whose name immediately precedes the symbol.) The input signals UDS* and LDS* come to the PAL UAO 94c from the PE CPU 82. The input signal PE-MCS* and BDTACK* come to the PAL UAO 94c from the second multi-port VRAM 46. The output signal BRAM* from the PAL UAO 94c is only used internally within the PAL in generating other output signals. The PAL UAO 94c supplies its output signals READ*, WRITE* and SRAM* respectively to the OE*, WE* and CS* input terminals of the two 6264P eight bit static RAM integrated circuits in the stack and cache memory 92. The PAL UAO 94c supplies its output signal PROM* to the E* input terminal of the two EPROMs in the program memory 94b. The PAL UAO 94c supplies its output signal DTACK* to the PE CPU 82. Lastly, the PAL UAO 94c supplies its output signal HIF* to the PE-host interface circuit 58.
Figure imgf000012_0001
Figure imgf000012_0002
An address from the PE CPU 82 that lies in the range 200000H-3FFFFFH causes the PAL UAO 94c to assert its output signal BRAM*. An address from the PE CPU 82 that lies in the range 000000H-0FFFFFH causes the PAL UAO 94c to assert its output signal PROM*. An address from the PE CPU 82 that lies in the range 100000H-1FFFFFH causes the PAL UAO 94c to assert its output signal SRAM*. An address from the PE CPU 82 that lies in the range 400000H-4FFFFFH causes the PAL UAO 94c to assert Its output signal HIF*. Set forth below are equations for the remainder of the output signals from the PAL UAO 94c which specify the logical relationships that exist between the input signals to the PAL UAO 94c and its output signals. In these and all subsequent logic equations, the symbol "&" indicates the "ANDing" of logic terms while the symbol "+" indicates the "ORing" of logic terms.
READ* = UDS* & R/W + LDS* & R/W WRITE* = UDS* & R/W* +. LDS* & R/W*
DTACK* = UDS* & PE-MCS
+ LDS* & PE-MCS
5 + AS* & R/W* & PE-MCS
+ BDTACK* & PE-MCS*
The DTACK* signal indicates that the memory 92 and the second multi-port VRAM 46 are capable of exchanging data with the PE
CPU 82. For data transfers outside of the address range which
10 causes assertion of the BRAM* signal, no wait states occur.
All write operations to the memory 92 are performed early without wait states. The PE CPU 82 can experience wait states during accesses to the second multi-port VRAM 46.
15 The PE CPU 82 includes a circuit for generating various synchronous clock signals used throughout the PE 40. Thus, the PE CPU 82 generates a 20 MHz SCLK signal which it supplies to the first VRAM control circuit 68, and another 20 MHz FFP-CLK signal which it supplies directly to the FPUs 84. The PE CPU
20 82 also generates a jumper selectable 10 or 20 MHz PCLK clock signal that is applied internally within the PE CPU 82 to the Motorola MC68020. The PE CPU 82 generates a 10 MHZ PCLK* signal which it supplies to the second VRAM control circuit 74 for synchronization functions. Finally, the PE CPU 82
25 generates a 5 MHz BCLK signal which it supplies to both the first and the second VRAM control circuits 68 and 74.
The PE CPU 82 also includes a reset circuit which automatically holds the MC68020 and all of the MC68882s reset for a time interval immediately following application of power
30 to the PE 40. The reset circuit included in the PE CPU 82 may also be triggered by a signal from the PE-host interface circuit 58 that is generated in response to signals from the host personal computer 20. Within the PE CPU 82, a five volt positive signal is continuously applied through individual
35 resistors to the CDIS*, AVEC*, BR*, BGACK* and BERR* input terminals of the Motorola MC68020.
Included within the PE CPU 82 of the preferred embodiment is a PAL UB9, not ^illustrated in FIG. 1, for producing the control signals which the PE CPU 82 transmits to
40 the FPUs 84 via the FPU control signal bus 86 and by which the PE CPU 82 controls the operation, of the FPUs 84. The~ PAL included in the PE CPU 82 for controlling the PE FPU is a 20L8 integrated circuit and is connected to the MC68020 and the one or more MC68882s and is programmed in accordance with the description set forth in the "MC68020 32-Bit Microprocessor User's Manual", Third Edition, 1989, 1988 by Motorola Inc., MC68020UM/AD REV 2, particularly as depicted in Figures 11-5 and 11-6 on pages 11-7 and 11-8 thereof, together with the text accompanying those figures. Accordingly, the "MC68020 32-Bit Microprocessor User's Manual" identified above is incorporated by reference as though fully set forth here.
The PE CPU 82 also includes a second 20L8 CPU control signal PAL UB10, not illustrated in FIG. 1, that adapts control signals present on the PE bus 64 from those for a Motorola MC68000 to those for a Motorola MC68020. The adaptation of the PE 40 to use different microprocessors from the same family of Motorola microprocessors merely by the addition of the single PAL UB10 indicates the flexibility, adaptability and generality of the present invention. The PAL UB10 receives as input signals from the MC68020 its address signals A0 and Al, its SIZO and SIZ1 signals, its address strobe signal AS*, its data strobe signal DS*, its read/write signal R/W*, and its external cycle start signal ECS*. The PAL UB10 also receives interrupt signals IAV4*, IAV5*, IAV6* and IAV7* that originate in the PE-host interface circuit 58. While the PAL UB10 provides an input terminal for an interrupt signal IAV3*, that terminal is merely connected to a positive five volt potential through a resistor. Lastly, the PAL UB10 receives the signal DTACK* that originates in the PE Memory Controller PAL UAO 94c. In addition to the output signals IPL0*, IPL1*, IPL2* and DSACK1* which the PAL UB10 supplies to the Motorola MC68020, it supplies a UDS* and a LDS* signal to the PAL UAO 94c, and respectively to G* inputs of the two EPROM integrated circuits included in the program memory 94b. The DSACK1* signal indicates completion of a data transfer requested by the Motorola MC68020. Because the memories stack and cache memory 94a and program memory 94b as well as the second multi-port VRAM 46 exchange only 16 bit words with the MC68020, a high logic level signal is continuously supplied to the DSACKO* input terminal of the MC68020.
PAL UB10
The following table sets forth the pin numbers for the PAL UB10 toget r with the names of the signals either received by or transmitted from each pin.
Figure imgf000015_0001
Figure imgf000015_0002
Set forth below are equations for the PAL UB10 which specify the logical relationships that exist between the input signals to the PAL UB10 and its output signals.
UDS* = A0* & DS*;
Figure imgf000015_0003
IPL2*= IAV7* & IAV6 & IAV5 & IAV4 & IAV3
+ IAV7 & IAV6* & IAV5 & IAV4 & IAV3
+ IAV7 & IAV6 & IAV5* & IAV4 & IAV3
+ IAV7 & IAV6 & IAV5 & IAV4* & IAV3
The PE 40 includes a host-PE register 96 and a PE-host register 98. The personal computer 20 transmits certain control signals to the PE CPU 82- by storing them into" the host-PE register 96 via the PE-host interface circuit 58 from which they may be subsequently fetched by the PE CPU 82. Similarly, the PE CPU transmits certain control signals to the personal computer 20 by storing them into the PE-host register 98 from which they may be subsequently fetched by the host personal computer 20 via the PE-host interface circuit 58.
FIGs. 2a-2d, when assembled as illustrated in FIG. 2, form a detailed block diagram depicting, at the integrated circuit level, the VRAMs 44 and 46, the VRAM control circuits 68 and 74,. the PE-host interface circuit 58, and the registers 96 and 98. Also depicted down the left hand edge of the combined FIGs. are the ISA host bus 38 and its interface to the PE ISA bus 42. FIG. 2b of the composite diagram depicts that the first multi-port VRAM 44 includes four Texas Instruments TMS4461 262,144 Bit Multiport VRAM integrated circuits 442a-442d. Similarly, FIG. 2d of the composite diagram depicts that the second multi-port VRAM 46 also includes four TMS4461 262,144 Bit Multiport VRAM integrated circuits 462a-462d organized as 4 x 65,536 bits. That FIG. also depicts sixteen resistors 482a-482p having a resistance in the range of fifty to one- hundred ohms one of which is respectively located in each of the signal lines of the inter-memory bus 48 intermediate to the serial data in/data out shared port 52 of the first multi-port VRAM 44 and the serial data in/data out shared port 52 of the second multi-port VRAM 46. The resistors 482a-482p provide isolation and termination resistances between the terminals of the VRAM integrated circuits 442a-442d that connect to the inter-memory bus 48 and the corresponding terminals of the VRAM integrated circuits 462a-462d that also connect to the inter- memory bus 48.
FIGs. 2a and 2b of the composite diagram show that the PE host bus 56 includes a host control signal section 562, a host buffered address section 564, and a host buffered data section 566. FIGs. 2c and 2d of the composite diagram show that the PE bus 64 includes a PE control signal section 642, a PE address section 644, and a PE data section 646. FIG. 2b of the composite diagram shows that the first VRAM control and address bus 66 includes a first VRAM control signal section 662 and a first VRAM address section 664. As also illustrated in that FIG., the first VRAM control circuit 68 includes three 20L8 PAL integrated circuits UA5 682a, UA6 682b, UA7 682c, a Texas Instruments TMS 34061 Video System Controller ("VSC") 684, a 74F74 flip-flop 686, and two 74F04 inverters 688a and 688b. FIG. 2d of the composite diagram shows that the second VRAM control and address bus 72 includes a second VRAM control signal section 722 and a second VRAM address section 724. Also illustrated in the FIG., the second VRAM control circuit 74 includes a single 20L8 PAL integrated circuit UA13 742, a TMS 34061 VSC 744, two 74F113 flip-flops 746a and 746b, and a 74F04 inverter 748. As depicted in FIGs. 2a and 2c, the PE ISA bus 42 supplies an electrical ground 782 and a positive five volt potential 784 from the host personal computer 20 to the electrical circuits of the PE 40.
PE-Host Interface Circuit 58
The portion of FIGs. 2a and 2c which depict the PE-host interface circuit 58 shows that it includes a first pair of 74F245 data transceivers 802a and 802b and a second pair of 74F245 register transceivers 804a and 804b. A first set of bidirectional signal terminals for the data transceivers 802a and 802b and a corresponding first set of bidirectional signal terminals for the register transceivers 804a and 804b connect to a SD section 806 of the PE ISA bus 42. The SD section 806 of the PE ISA bus 42 receives data signals SD00-SD15 from the host bus 38 and conducts those signals to the transceivers 802a-b and 804a-b. A second set of bidirectional signal terminals for the data transceivers 802a and 802b connect to the host buffered data section 566 of the PE host bus 56 while a second set of bidirectional signal terminals for the register transceivers 804a and 804b connect to a register bus 808. Depending upon a directional control signal applied to the transceivers 802a and 802b, signals present on the SD00-SD15 signal lines of the host bus 38 are transferred to the host buffered data section 566 of the PE-host bus 56, or conversely. Similarly, depending upon that same directional control signal, signals present on the SD00-SD15 signal lines of the host bus 38 are transferred to the register bus 808 or conversely. Responding to the memory read or write signals and the I/O read or write signals present on the ISA host bus 38, the PE-host interface circuit 58 controls the operation of the transceivers 802a-b and 804a-b to transfer SD00-SD15 signals present on the host bus 38 to the host buffered data section 566 and to the register bus 808 during either memory write or I/O write operations. Conversely, the host interface circuit 58 controls the transceivers 802a-b and 804a-b to transfer signals both from the host buffered data section 566 and from the register bus 808 to the SD00-SD15 signal lines of the host bus 38 during either a memory read or I/O read operation on the ISA host bus 38.
The portion of FIGs. 2a and 2c which depict the PE-host interface circuit 58 also shows that it includes a pair of series connected 74F04 inverters 812a and 812b, a pair of 74LS541 buffers 814a and 814b and a 74F373 latch 816. Output terminals of the inverter 812b, the buffers 814a and 814b, and the latch 816 all connect to the host buffered address section 564 of the PE host bus 56. Input terminals of the inverter 812a and the buffers 814a and 814b connect to a SA section 818 of the PE ISA bus 42. The SA section 818 of the PE ISA bus 42 receives address signals SA00-SA16 from the host bus 38 and conducts those signals to the input terminal of the inverter 812a and to the input terminals of the buffers 814a and 814b. Control signals applied to the pair of buffers 814a and 814b enable them together with the series connected inverters 812a and 812b to continuously transfer address signals present on the SA section 818 of the PE ISA bus 42 to the host buffered address section 564 of the PE host bus 56. Input terminals of the latch 816 are connected to a LA section 822 of the PE ISA bus 42. the LA section 822 of the PE ISA bus 42 receives address signals LA17-LA23 from the host bus 38 and conducts those signals to the input terminals of the latch 816. A control signal input terminal of the latch 816 connects to a BALE signal line 824 included in the host control signal section 562 of the PE host bus 56. The BALE signal line 824 receives a BALE control signal from the host bus 38. While the host personal computer 20 is operating, valid address signals SA00-SA16 are always present on the host bus 38. Therefore, the pair of inverters 812a and 812b and the pair of buffers 814a and 814b continuously receive such valid address signals from the SA section 818 and transfer those address signals to the host buffered address section 564 of the PE host bus 56. With regard to the LA17-LA23 signal lines, only during certain time intervals, as indicated by the state of the BALE signal, do the signals present on those signal lines represent a valid address. During the time intervals in which the LA17-LA23 signals represent a valid address, the latch 816 responds to the signal present on the BALE signal line 824 to accept the LA17-LA23 address signals from the host bus 38 and to transfer those signals to the host buffered address section 564 of the PE host bus 56. During the time intervals in which the LA17- LA23 signals on the host bus 38 do not represent a valid address, the latch 816 stores the valid address signals that it received most recently and continues supplying the host buffered address section 564 of the PE host bus 56 with the stored address signals. Thus, the inverters 812a and 812b, the buffers 814a and 814b, and the latch 816 continuously supply the host buffered address section 564 of the PE host bus 56 with a set of address signals H-AO through H-A23 that correspond exactly to the address signals on the host bus 38.
The portion of FIGs. 2a and 2c which depict the PE-host interface circuit 58 also shows that it includes a first AM25LS2521 selector 832. A first set of input terminals to the selector 832 connects individually to a portion of the signal lines present in the host buffered address bus 564 of the PE host bus 56 to receive the address signals H-A12 through H-A19. A second set of input terminals to the selector 832 connect individually via a set of jumper lines 834 to one-half of a set of jumpers pins 836. The other half of the jumper pins 836 connect to electrical ground 782. In addition to connecting to the jumper pins 836, the jumper lines 834 also connect individually through resistors 838 to the positive five volt potential 784. If no jumpers are installed on the jumper pins 836, then the positive five volt potential is applied through the individual resistors 838 and jumper lines 834 to all terminals in the second set of input terminals to the selector 832. If a jumper is installed between a pair of jumper pins 836, then ground potential is applied to the corresponding input terminal of the second set of input terminals to the selector 832. The selector 832 continuously compares the signals present at its first set of input terminals with those present afe its second set of input terminals. Thus, if the set of input signals H-A12 through H-A19 supplied to the first set of input terminals of the selector 832 match the set of input signals supplied by the jumper lines 834 to the second set of input terminals, then the selector 832 transmits a signal indicating the occurrence of the matching condition onto a H-CSEL* signal line 842 included in the host control signal section 562 of the PE host bus 56. The host control signal section 562 of the PE host bus 56 transmits the signal on the H-CSEL* signal line to the PAL UA7 682c included in the first VRAM control circuit 68. Within the first VRAM control circuit 68, the signal present on the H-CSEL* signal line, in combination with other signals supplied to the PAL UA7 682c, controls whether or not the VSC 684 will respond to address signals on the host buffered address section 564 of the PE host bus 56 for exchanging data with the host personal computer 20 via the host buffered data section 566 of the PE host bus 56. Thus, the installation or removal of jumpers from the jumper pins 836 permits setting an address range on the host bus 38 throughout which the host personal computer 20 may store data into or retrieve data from the VSC 684. This address range is 00 0XXXH to OF FXXXH with the address usually being set to 0D CXXXH.
The PE-host interface circuit 58 also includes a second AM25LS2521 selector 852. For the selector 852, some of its first set of input terminals connect to the host buffered address section 564 of the PE host bus 56 to receive address signals H-A20 through H-A23. Similar to the selector 832, a second set of input terminals of the selector 852, i.e. those input terminals which are compared with the terminals of the first set of input terminals that receive the signals H-A20 through H-A23, connect via jumper lines 854 to one-half of a set of jumpers pins 856 and also connect through resistors 858 to the positive five volt potential 784. The input terminals of the selector 852 which do not receive either an address signal or a signal from the jumper lines 854 are connected to electrical ground 782. If the set of input signals H-A20 through H-A23 supplied to the first set of input terminals of the selector 852 match the set of input signals supplied by the jumper lines 854 to the second set of input terminals, then the selector transmits a signal indicating that matching condition onto H-MSEL* signal line 862 included in the host control signal section 562 of the PE host bus 56. The host control signal section 562 of the PE host bus 56 transmits the signal on the H-MSEL* signal line to the PAL UA7 682c included in the first VRAM control circuit 68. Within the first VRAM control circuit 68, the signal present on the H-MSEL* signal line, in combination with other signals supplied to the PAL UA7 682c, controls whether or not the VSC 684 included in the first VRAM control circuit 68 will respond to address signals on the host buffered address section 564 of the PE host bus 56 for addressing the first multi-port VRAM 44 for exchanging data between the VRAM 44 and the host personal computer 20 via the host buffered data section 566 of the PE host bus 56. Thus, the installation or removal of jumpers from the jumper pins 856 permits setting the address range on the host bus 38 at which the host personal computer 20 may store data into or retrieve data from the VRAM 44. This address range is OX XXXXH to FX XXXXH with the address usually being set to 50 0000H.
The PE-host interface circuit 58 includes a set of interrupt selection jumper pins 872. One side of the jumper pins 872 connects to individual lines for IAV4*, IAV5*, IAV6* and IAV7* signals in the PE control signal section 642 of the PE bus 64. The other side of the jumper pins 872 all connect in parallel to a PC-INT* signal line 874 in an interface circuit bus 882. Installation of a jumper between a particular pair of jumper pins 872 selects a particular priority level for interrupt signals that are applied to the Motorola MC68020 included in the PE CPU 82.
The PE-host interface circuit 58 includes a pair of 74F04 inverters 892 and 894. Inputs of the inverters 892 and 894 respectively receive the signals PE-WTD* and H-WTD* from the interface circuit bus 882. The outputs of the inverters 892 and 894 respectively transmit the signals PE-WTD and H-WTD back to the interface circuit bus 882. The PE-host interface circuit 58 also includes a 74F74 host-PE flip-flop 902 having a CP input which receives the H-WTD signal from the inverter 894. The D and SD inputs of the host-PE flip-flop 902 receive the positive five volt potential 784 through a resistor 904. The RD input of the host-PE flip- flop 902 receives a PE-RDD* signal from the interface circuit bus 882. Responsive to these input signals, one state of the host-PE flip-flop 902 indicates that the host personal computer 20 has stored data in the host-PE register 96 and that the PE CPU 82 has not yet read the data stored there. The other state of the host-PE flip-flop 902 indicates that the PE CPU 82 has read any previously stored data from the host-PE register 96, and that the host personal computer 20 may therefore store new data into the register 96. The Q and Q* output terminals of the host-PE flip-flop 902, which indicate its present state, respectively connect to H-DA and H-DU signal lines in the interface circuit bus 882.
The PE-host interface circuit 58 also includes a 74F74 PE-host flip-flop 906. The D and CP inputs of the PE-host flip-flop 906 receive the positive five volt potential 784 through the resistor 904. The SD input of the PE-host flip- flop 906 receives the PE-WTD* signal from the interface circuit bus 882 while its RD input receives a H-RDD* signal from the bus 882. Similar to the host-PE flip-flop 902, the state of the PE-host flip-flop 906 indicates whether the PE CPU 82 has stored data for the host personal computer 20 into the PE-host register 98, or whether the host personal computer 20 has already read the last such data stored there and that, therefore, the PE CPU 82 may store new data into the PE-host register 98. The Q and Q* output terminals of the PE-host flip-flop 906, which indicate its present state, respectively connect to PE-DA and PE-DU signal lines in the interface circuit bus 882.
PAL UA35
The PE-host interface circuit 58 includes three 20L8 PALs UA35 912a, UA36 912b and UA37 912c. The first of these PALs, UA35 912a, receives, via the SA section 818 of the PE ISA bus 42, the SAOO-SAll address signals from the host bus 38 of the host personal computer 20. The PAL UA35 912a also receives, via the interface circuit bus 882, a IO-SEL* signal and a HI* signal from the PAL UA37 912c. Responsive to these input signals, the PAL UA35 912a transmits H-DSEL*, H-SSEL*, FUNCT-A, FUNCT-B, PC-INT*, and PORT-EQ* signals via the interface circuit bus 882. The PAL UA35 912a also transmits a PETRGRST signal to the PE CPU 82 via the PE control signal section 642 of the PE bus 64 for resetting the Motorola MC68020 and MC68882{s) included in the PE CPU 82 together with the VSC(s) 684 and 744, and the flip-flops described above. The following table sets forth the pin numbers for the PAL UA35 912a together with the names of the signals either received by or transmitted from each of its pins.
Figure imgf000023_0001
Figure imgf000023_0002
An address on the SAOO-SAll signal lines from the host personal computer 20 that lies in the range 0304H-0307H causes the PAL UA35 912a to assert its output signal H-DSEL*. An address on the SAOO-SAll signal lines from the host personal computer 20 that lies in the range 0300H-0303H causes the PAL UA35 912a to assert its output signal H-SSEL*. An address on the SAOO-SAll signal lines from the host personal computer 20 5 that lies in the range 0308H-030BH causes the PAL UA35 912a to assert its output signal PETRGRST thereby resetting the Motorola MC68020 included in the PE CPU 82. An address on the SAOO-SAll signal lines from the host personal computer 20 that lies in the range 0314H-0317H causes the PAL UA35 912a to
10 assert its output signal PC-INT* which, if a jumper is installed on any of the pairs of jumper pins 872, interrupts the operation of the Motorola MC68020 included in the PE CPU 82. An address on the SAOO-SAll signal lines from the host personal computer 20 that lies in the range 0300H-031FH causes
15 the PAL UA35 912a to assert its output signal PORT-EQ*.
PAL OA36
The PAL UA36912b receives input signals Al, A2, RESET*, and R/W* from the Motorola MC68020 included in the PE CPU 82.
20 The PAL UA36 912b receives the input signal HIF* from the PAL UAO 94c in the memory 92. The PAL UA36 912b receives input signals H-DA and H-DU from the host-PE flip-flop 902. The PAL UA36 912b receives input signals PE-DA and PE-DU from the PE-host flip-flop 906. The PAL UA36 912b receives input
25 signals H-SSEL* and H-DSEL* from PAL UA35 912a. The PAL UA36 912b receives input signals BIOW* and BIOR* from the PAL UA37 912c. The PAL UA36 912b transmits signals D16 and D17 to the Motorola MC68020 included in the PE CPU 82. (With regard to nomenclature for the data signal lines of the Motorola MC68020,
30 it is important to note that in the sixteen bit external data mode it receives and transmits sixteen bit words on data signal lines D16 through D31, not on data signal lines DO through D15.) Via the interface circuit bus 882, the PAL UA36 912b supplies signals H-RDD* and PE-WTD* to the host-PE flip-flop
35 902, the signal PE-RDD* to the PE-host flip-flop 906, and the signals PE-WTD* and H-WTD* respectively to the inverters 892 and 894. The PAL UA36 912b supplies the signals IO-D00 and IO-D01 to the transceiver 804a via the register bus 808 for transmission to the host bus 38 of-the personal computer 20 as data bits SD00 and SD01. The following table sets forth the pin numbers for the PAL UA36 912b together with the names of the signals either received by or transmitted from each of its pins.
Figure imgf000025_0001
Figure imgf000025_0002
Set forth below are equations for the output signals from the PAL UA36 912b which specify the logical relationships that exist between the input signals to the PAL UA36 912b and its output signals. The 20L8 PAL integrated circuit used for the PAL UA36 912b has tri-state output drivers that may be set to a high impedance state by an input signal applied to an input terminal of the PAL. In the following logic equations, the phrase "IF(signal name)" indicates that the output driver for the signal whose equation follows the phrase is enabled to transmit an output signal only upon the occurrence of the specified condition.
IF(HIF*)D0 = Al* & A2* & HIF* & PE-RW & PE-DU IF(HIF*)D1 = Al* & A2* & HIF* & PE-RW & H-DA PE-WTD* = Al & A2* & HIF* & R/W* PE-RDD* = Al & A2* & HIF* & R/W + RESET*
IF(H-SSEL*)IO-D00 = H-SSEL* & BIOR* & H-DU IF(H-SSEL*)IO-D01 = H-SSEL* & BIOR* & PE-DA
H-RDD* = H-DSEL* & BIOR* + RESET* H-WTD* H-DSEL* & BIOW*
PAL UA37 The PAL UA37 912c receives input signals MEMW*, MEMR*, IOW*, IOR*, SMEMW*, SMEMR*, AEN and SBHE* from the host bus 38 in the personal computer 20 via the PE ISA bus 42 and the host control signal section 562 of the PE host bus 56. An input terminal of the PAL UA37 912c connects to a SA00 address line 922 in the SA section 818 of the PE ISA bus 42 to receive the SA00 address signal from the host bus 38. The PAL UA37 912c receives the PORT-EQ* signal from the PAL UA35 912a via the interface circuit bus 882. The PAL UA37 912c supplies output signals HI* and IO-SEL* to the PAL UA35 912a via the interface circuit bus 882. The PAL UA37 912c supplies output signals BIOW* and BIOR* to the PAL UA36 912b via the interface circuit bus 882. The PAL UA37 912c also supplies the output signal BIOR* to the SR* input terminals of the transceivers 802a-b and 804a-b. The PAL UA37 912c supplies output signals LO-E* and HI-E* respectively to the CE* input terminals of the transceivers 802a and 802a, and to the CE input terminals of the transceivers 802b and 804b. The following table sets forth the pin numbers for the PAL UA37 912c together with the names of the signals either received by or transmitted from each of its pins.
Pin Signal
No. Name
Figure imgf000026_0001
Figure imgf000026_0002
Set forth below are equations for the output signals from the PAL UA37 912c which specify the logical relationships that exist between the input signals to the PAL UA37 912c and its output signals.
IO-SEL* = IOW* & AEN* & PORT-EQ*
+ IOR* & AEN* & PORT-EQ*
BIOW* = IOW*
BIOR* = IOR* LO-E* = IOR* & PORT-EQ* & AEN* & SA00*
+ IOW* & PORT-EQ* & AEN* & SA00*
HI-E* = IOR* & PORT-EQ* & AEN* & SBHE* + IOW* & PORT-EQ* & AEN* & SBHE*
HI* = SBHE*
As depicted in FIG. 2a, the host-PE register 96 includes two 74F373 latches 962a and 962b for storing a sixteen bit data word of control and status signals that the host personal computer 20 may transmit to the PE CPU 82. The OE* input terminal of the latches 962a and 962b receives the PE-RDD* signal from the PAL UA36 912b via the interface circuit bus 882. The E input terminal of the 962a and 962b receives the H-WTD signal from the inverter 894 via the interface circuit bus 882. Similarly, the 96 includes two 74F373 latches 982a and 982b for storing a sixteen bit data word of control and status signals that the PE CPU 82 may transmit to the host personal computer 20. The OE* input terminal of the latches 982a and 982b receives the H-RDD* signal from the PAL UA36912b via the interface circuit bus 882. The E input terminal of the 982a and 982b receives the PE-WTD signal from the inverter 892 via the interface circuit bus 882.
VRAMs 44 and 46
The host personal computer 20 exchanges data signals SD00-SD03 of the host bus 38 with DQ0-DQ3 terminals of the VRAM integrated circuit 442a included in the first multi-port VRAM 44 via the PE ISA bus 42, the transceiver 802a, and data signal lines H-D0 through H-D31002a of the host buffered data section 566 of the PE host bus 56. In the same way, host personal computer 20 exchanges data signals SD04-SD07 with the VRAM integrated circuit 442b on data signal lines H-D4 through .H-D7 1002b of the host buffered data section 566. The host personal computer 20 exchanges data signals SD08-SD11 with the VRAM integrated circuit 442c on data signal lines H-D8 through H-Dll 5 1002c of the host buffered data section 566 except that the signals pass through the transceiver 802b rather than the transceiver 802a. In the same way, host personal computer 20 exchanges data signals SD12-SD15 with the VRAM integrated circuit 442b on data signal lines H-D12 through H-D15 1002d of
10 the host buffered data section 566.
The SDQ0-SDQ3 terminals of the VRAM integrated circuit 442a included in the first multi-port VRAM 44 exchange data with the SDQ0-SDQ3 terminals of the VRAM integrated circuit 462a included in the second multi-port VRAM 46 via IM0-IM3 5 signal lines 1004a in the inter memory bus 48. In the same way, the VRAMs 442b and 462b exchange data via IM4-IM7 signal lines 1004b in the inter memory bus 48, the VRAMs 442c and 462c exchange data via IM8-IM11 signal lines 1004c, and the VRAMs 442d and 462d exchange data via IM12-IM15 signal lines 1004d.
20 Via the first VRAM address section 664 of the first VRAM control and address bus 66, A0-A7 terminals of each of the four VRAM integrated circuits 442a-442d receive address signals from the VSC 684 included in the first VRAM control circuit 68 on address lines H-MA0 through H-MA7 1006. Via the first VRAM
25 control section 662 of the first VRAM control and address bus 66, a RAS* terminal of each of the four VRAM integrated circuits 442a-442d receives a H-RAS0* signal from the VSC 684, and a TRG* terminal receives a H-TRG* signal from the VSC 684. A CAS* terminal of each of the VRAMs 442a and 442b receives a
30 H-CASLO* signal from the VSC 684 via the first VRAM control section 662 of the first VRAM control and address bus 66 while the CAS* terminals of each of the VRAMs 442c and 442d receives a H-CASHI* signal from the VSC 684. A SE* terminal of each of the VRAMs 442a-442d receives a H-SOE* signal from the PAL UA5
35 682a via the first VRAM control section 662 of the first VRAM control and address bus 66 while a SC terminal of each of the VRAMs 442a-442d receives a XSCLK signal from the PAL UA5 682a. A W* terminal of each of the VRAMs 442a and 442b receives a H-WLO* signal from the PAL UA6 682b via the first VRAM control section 662 of the first VRAM control and address bus 66 while the W* terminals of each of the VRAMs 442c and 442d receives a H-WHI* signal from the PAL UA6 682b. Analogous to the VRAMs 442a-442c, via data signal lines D16 through D19 1012a in the PE data section 646 of the PE bus 64, DQ0-DQ3 terminals of the VRAM 462a included in the second multi-port memory 46 respectively receive data signals D16 through D19 from the Motorola MC68020 included in the PE CPU 82. In the same way, via data signal lines D20 through D23 1012b the VRAM 462b receives data signals D20 through D23 from the Motorola MC68020, via data signal lines D24 through D27 1012c the VRAM 462c receives data signals D24 through D27, and via signal lines D28 through D31 1012d the VRAM 462d receives data signals D28 through D31.
Via the second VRAM address section 724 of the second VRAM control and address bus 72, A0-A7 terminals of each of the four VRAM integrated circuits 462a-462d receive address signals from the VSC 744 included in the second VRAM control circuit 74 on address lines PE-MAO through PE-MA71016. Via the second VRAM control section 722 of the second VRAM control and address bus 72, a RAS* terminal of each of the four VRAM integrated circuits 462a-462d receives a PE-RAS0* signal from the VSC 744, and a TRG* terminal receives a PE-TRG* signal from the VSC 744. A CAS* terminal of each of the VRAMs 462a and 462b receives a PE-CASL0* signal from the VSC 744 via the second VRAM control section 722 of the second VRAM control and address bus 72 while the CAS* terminals of each of the VRAMs 462c and 462d receives a PE-CASHI* signal from the VSC 744. A SE* terminal of each of the VRAMs 462a-462d receives a PE-SOE* signal from the PAL UA5 682a via the second VRAM control section 722 of the second VRAM control and address bus 72 while a SC terminal of each of the VRAMs 462a-462d receives a XSCLK signal from the PAL UA5 682a. A W* terminal of each of the VRAMs 462a and 462b receives a PE-WLO* signal from the PAL UA6 682b via the second VRAM control section 722 of the second VRAM control and address bus 72 while the W* terminals of each of the VRAMs 462c and 462d receives a PE-WHI* signal from the PAL UA6 682b. VRAM Control Circuits 68 and 74
The host personal computer 20 exchanges data signals SD00-SD07 of the host bus 38 with D0-D7 terminals of the VSC 5 684 included in the first VRAM control circuit 68, via the data signal lines H-DO through H-D3 1002a and H-D4 through H-D7 1002b of the host buffered data section 566 of the PE host bus 56, that also respectively connect to the VRAM integrated circuits 442a and 442b in the first multi-port VRAM 44. The
10 host personal computer 20 supplies address signals SA1-SA8 of the host bus 38 to CA0-CA7 terminals of the VSC 684, via H-Al through H-A8 signal lines 1022a included in the host buffered address section 564 of the PE host bus 56. The host personal computer 20 also supplies address signals SA9-SA16 of the host
15 bus 38 to RA0-RA7 terminals of the VSC 684 via H-A9 through H-A8 signal lines 1022b included in the host buffered address section 564.
HSYNC*, VSYNC* and RESET* terminals of the VSC 684, respectively, receive signals from the HSYNC*, VSYNC* and
20 RESET* terminals of the VSC 744, via the VRAM synchronization signal bus 76. Supplying these three signals from the VSC 744 to the VSC 684 slaves the operation of the SDQ0-SDQ3 terminals of the VRAM integrated circuits 442a-442d to the operation of the SDQ0-SDQ3 terminals of the VRAM integrated circuits
25 462a-462d; as their operation is controlled by the VSC 744 included in the second VRAM control circuit 74. Slaving the operation of the VRAMs 442a-442d to the operation of the VRAMs 462a-462d so the first multi-port VRAM 44 operates in response to signals from the second multi-port VRAM 46 synchronizes
30 their operation to insure that data transfers properly between the VRAMs 44 and 46 over the inter-memory bus 48. The choice of which multi-port VRAM 44 or 46 transmits the synchronization signals via the VRAM synchronization signal bus 76, and which of the multi-port VRAM 46 or 44 receives those signals is
35 arbitrary. Consequently, rather than the first multi-port VRAM 44 responding to synchronization signals from the second multi- port VRAM 46, the second multi-port VRAM 46 could respond to synchronization signals from the first multi-port VRAM 44. The inverter 688a receives the CLK signal from the riost bus 38 of the personal computer 20 via the host control signal section 562 of the PE host bus 56. The output signal from the inverter 688a, which is the logical inverse of the CLK signal of the host personal computer 20, is supplied as an input signal to the inverter 688b and to the CP input of the flip- flop 686. The inverter 688a supplies an output signal, H-SYSCLK, to a SYSCLK terminal of the VSC 684 via the first VRAM control signal section 662 of the first VRAM control and address bus 66. The H-SYSCLK signal is the same as the CLK signal of the host personal computer 20 delayed by the transmission delays of the inverters 688a and 688b. In addition to receiving the output signal from the inverter 688a, the D input of the flip-flop 686 receives a H-ALE* signal from the PAL UA6 682b. The Q output of the flip-flop 686 supplies a H-XALE* to an ALE terminal of the VSC 684 via the first VRAM control signal section 662. Since the flip-flop 686 operates synchronously with the CLK signal of the host personal computer 20, its operation synchronizes the H-ALE* signal from the PAL UA6 682b to the CLK signal of the host personal computer 20 before transmitting the H-ALE* signal to the ALE terminal of the VSC 684 as the H-XALE* signal.
Input terminals CEH* and CEL* of the VSC 684, respectively, receive H-CEH* and H-CEL* signals from the PAL UA5 682a via the first VRAM control signal section 662 of the first VRAM control and address bus 66. Input terminals FS0, FS1, FS2, and CS* of the VSC 684, respectively, receive H-FS0, H-FS1 and H-FS2 signals from the PAL UA7 682c via the first VRAM control signal section 662. A R/W* input terminal of the VSC 684 receives the MEMW* signal from the host bus 38 of the personal computer 20 via the host control signal section of the 562 of the PE host bus 56. A VDCLK input terminal of the VSC 684 receives the 5 MHZ BCLK signal from the CPU 82 via the PE control signal section 642 of the PE bus 64. Input terminals HOLDACK*, RS0 and RSI of the VSC 684 are connected to electrical ground potential 782.
Detailed explanations of how all these various input signals supplied to the VSC 684 influence its operation is set forth in a "TMS34061 User's Guide-," Copyright 1986 by Texas Instruments Incorporated, SPPU014A. Accordingly, the "TMS34061 User's Guide" is incorporated by reference as though fully set forth here. 5 Output terminals MA0-MA7 of the VSC 684 supply address signals to the VRAM integrated circuits 442a-442d via the address lines H-MAO through H-MA7 1006. Output signals from terminals CASHI*, CASLO*, TR*/QE*, and RASO* of the VSC 684 are respectively transmitted to the VRAM integrated circuits
10 442a-442d, via the first VRAM control signal section 662 of the first VRAM control and address bus 66 as described in greater detail above. A BLANK* output terminal of the VSC 684 transmits a SGATE* signal to the PAL UA5 682a via the first VRAM control signal section 662. A RDY*/HLD* and a W* output
15 terminals of the VSC 684 respectively transmit a H-RDY* signal and a H-W* signal to the PAL UA6 682b via the first VRAM control signal section 662.
PAL UA5
20 Via PE address section 644 of the PE bus 64, the PAL UA5 682a receives, as an input signal, the A15 address signal from the Motorola MC68020 included in the PE CPU 82. Via the PE control section 642 of the PE bus 64, the PAL UA5 682a receives as an input signal the 20 MHz SCLK signal from the PE CPU 82.
25 The SA00, SA09 and SA10 address signals from the host bus 38 of the personal computer 20 are supplied as input signals HA-00, HA-09 and HA-10 to the PAL UA5 682a via the host buffered address section 564 of the PE host bus 56. Via the host control section 562 of the PE host bus 56, the PAL UA5
30 682a receives as an input signal the SBHE control signal from the host bus 38. Via the first VRAM control section 662 of the first VRAM control and address bus 66, the PAL UA5 682a receives as an input signal the SGATE* signal from the VSC 684. Via the first VRAM control section 662, the PAL UA5 682a
35 receives as input signals H-FSO, H-FSl, H-FS2 and H-MCS* from the PAL UA7 682c. Via the second VRAM control section 722 of the second VRAM control and address bus 72, the PAL UA5 682a receives as input signals PE-FSO, PE-FS1 and PE-FS2 from' the
PAL UA13 742, included in the second VRAM control circuit 74.
The PAL UA5 682a transmits the CEL* and CEH* signals to the VSC 684 via the first VRAM control signal section 662 of the first VRAM control and address bus 66. The PAL UA5 682a transmits the XSCLK signal to the VRAM integrated circuits
442a-442d included in the first multi-port VRAM 44, and to a
SC input terminal of the VRAM integrated circuits 462a-462d included in the second multi-port VRAM 46. The PAL UA5 682a transmits the H-SOE* signal to the VRAMs 442a-442d, and to a
SE* input terminal of the VRAMs 462a-462d.
The following table sets forth the pin numbers for the
PAL UA5 682a together with the names of the signals either received by or transmitted from each of its pins. Pin Signal Pin Signal
No. Name No. Name
Figure imgf000033_0001
Figure imgf000033_0002
Set forth below are equations for the output signals from the PAL UA5 682a which specify the logical relationships that exist between the input signals to the PAL UA5 682a and its output signals.
H-CEL* = H-MCS* & H-A0*
H-CEH* = H-MCS* & SBHE* H-XSOE* = H-FSO* & H-FSl* & H-FS2 & H-A9 & H-A10
H-SOE* = H-XSOE
PE-XSOE* = PE-FSO* & PE-FS1* & PE-FS2 & A15
PE-SOE* = PE-XSOE
XSCLKX* = SGATE & PE-SCLK XSCLK = XSCLK*
PAL UA6 Via the first VRAM control signal section 662 of the first VRAM control and address bus 66, the PAL UA6 682b receives input signals H-CASLO*, H-CASHI*, H-W*, H-TRG* and H-RDY* from the VSC 684 included in the first VRAM control circuit 68. Via the second VRAM control signal section 722 of the second VRAM control and address bus 72, the PAL UA6 682b receives input signals PE-CASLO*, PE-CASHI*, PE-W* and PE-TRG* from the VSC 684 included in the first VRAM control circuit 68. Via the first VRAM control signal section 622, the PAL UA6 682b receives input signals H-FSO, H-FSl and H-FS2 from the PAL UA7 682c. Via the host control signal section 562 of the PE host bus 56, the personal computer 20 supplies signals MEMR*, MEMW* and AEN of the host bus 38 to the PAL UA6 682b.
The PAL UA6 682b transmits signals H-WHI* and H-WLO* to the VRAM integrated circuits 442a-442d, via the first VRAM control signal section 662 of the first VRAM control and address bus 66 as described above. Via a second VRAM control signal section 722 of the second VRAM control and address bus 72, the PAL UA6 682b transmits signals PE-WHI* and PE-WLO* respectively to a W* input terminal of VRAM integrated circuits 462c and 462d, included in the second multi-port VRAM 46, and to a W* input terminal of the VRAM integrated circuits 462a and 462b. The PAL UA6 682b transmits a H-ALE* signal to the flip- flop 686 via the second VRAM control signal section 622 as described above. Via the host control signal section 562 of the PE host bus 56, the PAL UA6 682b transmits the IOCHRDY signal to the host bus 38 of the personal computer 20.
The following table sets forth the pin numbers for the PAL UA6 682b together with the names of the signals either received by or transmitted from each of its pins.
Figure imgf000035_0001
Set forth below are equations for the output signals from the PAL UA6 682b which specify the logical relationships that exist between the input signals to the PAL UA6 682b and its output signals.
H-ALE* = AEN* & H-FSO* & MEMR* + AEN* & H-FSO* & MEMW*
+ AEN* & H-FSl* & MEMR* + AEN* & H-FSl* & MEMW* + AEN* & H-FS2* & MEMR* + AEN* & H-FS2* & MEMW*
H-WLO* = H-W* & H-CASLO* + H-W* & H-TRG*
H-WHI* = H-W* & H-CASHI* + H-W* & H-TRG*
PE-WLO* = PE-W* & PE-CASLO* + PE-W* & PE-TRG*
PE-WHI* = PE-W* & PE-CASHI* + PE-W* & PE-TRG*
IF(H-RDY*)IOCHRDY* = H-ALE*
PAL UA7
Via the host control signal section 562 of the PE host bus 56, the personal computer 20 supplies signals DACKO*, MEMR* and MEMW* of the host bus 38 as input signals to the PAL UA7 682c. The PAL UA6682c also receives input signals H-MSEL* and H-CSEL* via the host control signal section 562 from the selectors 832 and 852. Via the host buffered address section 564 of the PE host bus 56, the pe'rsonal computer 20 supplies address signals SA09-SA15 as input signals to the PAL UA7 682c.
Via the first VRAM control section 662 of the PE port 62, the PAL UA6 682c transmits output signals H-FSO, H-FSl, H-FS2, and H-MCS* to the PALs UA5 682a and UA6 682b, and to the VSC 684 included in the first VRAM control circuit 68.
The following table sets forth the pin numbers for the PAL UA7 682c together with the names of the signals either received by or transmitted from each of its pins.
Figure imgf000036_0001
Figure imgf000036_0002
Set forth below are equations for the output signals from the PAL UA7 682c which specify the logical relationships that exist between the input signals to the PAL UA6 682c and its output signals.
H-S2R* = H-CSEL* & DACKO & MEMR* & H-A15* & H-A14*
& H-A13* & H-A12* & H-All* & H-A10 + H-CSEL* & DACKO & MEMW* & H-A15* & H-A14*
& H-A13* & H-A12* & H-All* & H-A10 + H-CSEL* & DACKO & SMEMR* & H-A15* & H-A14*
& H-A13* & H-A12* & H-All* & H-A10 + H-CSEL* & DACKO & SMEMW* & H-A15* & H-A14*
& H-A13* & H-A12* & H-All* & H-A10
H-R2S* = H-CSEL* & DACKO & MEMR* & H-A15* & H-A14*
& H-A13* & H-A12* & H-All & H-A10* + H-CSEL* & DACKO & MEMW* & H-A15* & H-A14*
& H-A13* & H-A12* & H-All & H-A10* + H-CSEL* & DACKO & SMEMR* & H-A15* & H-A14*
& H-A13* & H-A12* & H-All & H-A10* + H-CSEL* & DACKO & SMEMW* & H-A15* & H-A14*
& H-A13* & H-A12* & H-All & H-A10* H-REGS* = H-CSEL* & DACKO & MEMR* & H-A15* & H-A14*
& H-A13* & H-A12* & H-All & H-A10 & H-A9* + H-CSEL* & DACKO & MEMW* & H-A15* & H-A14*
& H-A13* & H-A12* & H-All & H-A10 & H-A9* + H-CSEL* & DACKO & SMEMR* & H-A15* & H-A14*
& H-A13* & H-A12* & H-All & H-A10 & H-A9*
+ H-CSEL* & DACKO & SMEMW* & H-A15* & H-A14*
& H-A13* & H-A12* & H-All & H-A10 & H-A9* H-XY* = H-CSEL* & DACKO & MEMR* & H-A15* & H-A14*
& H-A13* & H-A12* & H-All & H-A10 & H-A9 + H-CSEL* & DACKO & MEMW* & H-A15* & H-A14*
& H-A13* & H-A12* & H-All & H-A10 & H-A9
+ H-CSEL* & DACKO & SMEMR* & H-A15* & H-A14*
& H-A13* & H-A12* & H-All & H-A10 & H-A9 + H-CSEL* & DACKO & SMEMW* & H-A15* & H-A14* & H-A13* & H-A12* & H-All & H-A10
& H-A9
H-FSO = H-S2R* + H-REGS*
H-FSl = H-R2S* + H-S2R* + H-REGS* + H-XY*
H-FS2 = H-REGS* + H-XY*
+ H-MSEL* & DACKO & MEMR* + H-MSEL* & DACKO & MEMW*
H-MCS* = H-MSEL* & DACKO & MEMR* + H-MSEL* & DACKO & MEMW* + H-R2S* + H-S2R* + H-REGS*
+ H-XY*
The PE CPU 82 exchanges data signals D16-D23 with DO- D7 terminals of the VSC 744, included in the second VRAM control circuit 74, via the data signal lines D16 through D19 1012a and D20 through D23 1012b of the PE data section 646 of the PE bus 64, that also respectively connect to the VRAM integrated circuits 462a and 462b in the second multi-port VRAM 46. The PE CPU 82 supplies address signals A1-A8 to CA0-CA7 input terminals of the VSC 744 via Al through A8 signal lines 1032a included in the PE address section 644 of the PE bus 64. The PE CPU 82 also supplies address signals A9-A16 to RA0-RA7 terminals of the VSC 744 via A9 and A8 signal lines 1032b included in the PE address section 644. RSO and RSI input terminals of the VSC 744 receive address signals A22 and A23 via A22 and A23 signal lines 1032c included in the PE address section 644. HSYNC*, VSYNC* and RESET* terminals of the VSC 744 respectively transmit signals to the HSYNC*, VSYNC* and RESET* terminals of the VSC 684 via the VRAM synchronization signal bus 76 as described above.
Input terminals ALE, FS0, FS1, FS2, CEH*, CEL*, and CS* of the VSC 744 respectively receive PE-ALE, PE-FSO, PE-FS1, PE-FS2, PE-CEH*, PE-CEL* and PE-MCS* signals from the PAL UA13 742 via the second VRAM control signal section 722 of the second VRAM control and address bus 72. A R/W* input terminal of the VSC 744 receives the R/W* signal from the Motorola MC68020 included in the PE CPU 82 via the PE control signal section 642 of the PE bus 64. A VDCLK input terminal of the VSC 744 receives the 5 MHZ BCLK signal from the CPU 82 via the PE control signal section 642 of the PE bus 64; while a SYSCLK input terminal of the VSC 744 receives the PCLK signal from the CPU 82. Input terminals HOLDACK* of the VSC 744 connects to the positive five volt potential 784 through a resistor 1034.
Output terminals MA0-MA7 of the VSC 744 supply address signals to the VRAM integrated circuits 462a-462d via the address lines PE-MAO through PE-MA7 1016. Output signals from terminals CASHI*, CASLO*, TR*/QE*, and RASO* of the VSC 744 respectively transmit PECASHI*, PECASLO*, PE-TRG* and PE-RAS0* signals to the VRAM integrated circuits 462a-462d, via the second VRAM control signal section 722 of the second VRAM control and address bus 72, as described in greater detail above. The output signals from terminals CASHI*, CASLO*, TR*/QE*, and W* of the VSC 744 respectively transmit the PECASHI*, PECASLO*, PE-TRG* and a PE-W* signals to the PAL UA6 682b via second VRAM control section 722 of the second VRAM control and address bus 72. A RDY*/HLD* output terminal of the VSC 744 transmits a PE-RHD* signal to the input of the inverter 748 via the second VRAM control signal section 722 of the second VRAM control and address bus 72. Similar to the first VRAM control circuit 68, the second VRAM control circuit 74 includes a circuit for synchronizing a PE-ALE signal to the PCLK supplied within the PE CPU 82 to the Motorola MC 68020. Thus, the PCLK signal is supplied, via a PCLK signal line 1036 in the PE control signal section 642 of the PE bus 64, to the CP input terminal of the flip-flop 746a. The Jl input terminal of the flip-flop 746a connects to electrical ground 782, while its Kl input terminal connects to the positive five volt potential 784 through a resistor 1042. The PAL UA13 742 supplies a PE-DS signal to the SD1 input terminal of the flip-flop 746a. The flip-flop 746a transmits a VAD signal from its Ql output terminal to the PAL UA13 742 via the second VRAM control signal section 722 of the second VRAM control and address bus 72. In addition to being supplied to the CP input terminal of the flip-flop 746a, the CP input terminal of the flip-flop 746b receives the PCLK signal. Similar to the flip-flop 746a, the Jl input terminal of the flip-flop 746b cc nects to electrical ground 782, while its Kl input terminal connects to the positive five volt potential 784 through the resistor 1042. The VSC 744 supplies a PE-RDH* signal to the input terminal of the inverter 748, that also connects to the positive five volt potential 784 through a resistor 1044. The inverter 748 supplies a PE-RDH signal to the SD1 input terminal of the flip-flop 746b. The flip-flop 746b transmits a BDTACK* signal from its Q2 output terminal to the PAL UAO 94c, via the second VRAM control signal section 722 of the second VRAM control and address bus 72.
PAL UA13
The PAL UA13 742 receives input address signals A16- A23 from the Motorola MC68020 included in the PE CPU 82 via the
PE address section 644 of the PE bus 64. Via the PE control signal section 642 of the PE bus 64, the PAL UA13 742 also receives a DS input signal from the Motorola MC68020 together with PE-LDS* and a PE-UDS* signals- from the PAL UB10 included in the PE CPU 82. The PAL UA13 742 receives a VAD input signal from the flip-flop 746a.
The PAL UA13 742 transmits signals PE-ALE, PE-FSO, PE-FSl, PE-FS2, PE-CEH*, PE-CEL*, and PE-MCS* to the VSC 744. The PAL UA13 742 also transmits signals PE-FSO, PE-FSl and PE-FS2 to the PAL UA5 682a included in the first VRAM control circuit 68. The PAL UA13 742 transmits a PE-DS signal to the inverter 748. The following table sets forth the pin numbers for the PAL UA13 .742 together with the names of the signals either received by or transmitted from each of its pins.
Figure imgf000040_0002
Set forth below are equations for the output signals from the PAL UA137 742 which specify the logical relationships that exist between the input signals to the PAL UA13 742c and its output signals.
& A21 & A20* & A19* & A18* & A17* & A16 & A21 & A20* & A19* & A18 & A17* & A16*
& A21 & A20* & A19* & A18* & A17* & A16 & A21 & A20* & A19* & A18* & A17 & A16* & A21 & A20* & A19* & A18* & A17 & A16 & A21 & A20* & A19* & A18 & A17* & A16*
& A21 & A20* & A19* & A18* & A17* & A16 & A21 & A20* & A19* & A18* & A17 & A16*
Figure imgf000040_0003
& A21 & A20 PE-MCS* = A23* & A22* & A21 & A20*- & A19* & A18* & A17* & A16
+ A23* & A22* & A21 & A20* & A19* & A18* & A17 & A16*
+ A23* & A22* & A21 & A20* & A19* & A18* & A17 & A16
+ A23* & A22* & A21 & A20* & A19* & A18 & A17* & A16* + A23* & A22* & A21 & A20
PE-CEL* = DS* & VAD*
PE-CEH* = DS* & VAD*
PE-ALE* = DS* & VAD*
PE-DS = DS*
Operation of the PE 40
FIG. 3 depicts the allocation of memory address space in the host personal computer 20 on the left hand side of the FIG. and in the PE 40 on the right hand side. As depicted in FIG. 3, normally the host addresses for the first multi-port VRAM 44 begins at 50 0000H. The host usually addresses the registers that are in the VSC 68 beginning at 0D 0000H. Also, the host-PE register 96 and the PE-host register 98 are usually addressed in the I/O address space of the host digital computer 20 beginning at location 300H. In the PE 40, the EPROM of the program memory 94b begins at address 0000:0400H immediately above the area reserved for the Motorola MC68020's start up and exception vectors. Addresses for the static RAM of the stack and cache memory 94a begin at 001O:O000H. Addresses for the second multi-port VRAM 46 begin at 0020:0000H. The host addresses the registers that are in the VSC 74 beginning at 0030:0000H. The host-PE register 96 and the PE-host register 98 are addressed beginning at location 0040:0000H.
Depicted in FIG. 4 are the host-PE register 96 and the PE-host register 98. If either of the registers 96 or 98 are presently transmitting data respectively from the host personal computer 20 to the PE 40 or conversely, all bits in the registers are used for 16 or 8 bit data words. If either of the registers 96 or 98 are presently transmitting status information, then only bits bO and bl are used. When transmitting status information to the host personal computer 20, the PAL UA36 912b transmits the H-DU signal from the flip- flop 902 and the PE-DA signal- from the flip-flop * 904 respectively as bits bO and bl of the PE-host register 98. A value of zero in bO bit of the PE-host register 98 indicates that a data word from the PE to be fetched by the host is presently stored in the latches 982a and 982b. A value of zero in the bl bit of the PE-host register 98 indicates that the PE 40 has fetched the previous data word stored by the host personal computer in the latches 962a and 962b. The PAL UA36 912b transmits complementary information to the PE CPU 82 via the DO and Dl signal lines of the PE data section 646 included in the PE.bus 64.
To effect transfers of data back and forth between the first and second multi-port VRAMs 44 and 46 and to effect other types of inter-processor communication, the CPU 22 of the personal computer 20 and the PE CPU 82, respectively, execute complementary routines set forth below in computer programs UTIL.C and PE01UTIL.017.
Within the personal computer 20, a computer program, FUNCTION.C set forth below, invokes the routines in the computer program UTIL.C to provide all the communication and supervisory functions required to perform particular mathematical computations requested by program calls to FUNCTION.C. For example, if the program calling FUNCTION.C wanted to solve a set of linear equations for which the data were already available, that program would make two subroutine calls to FUNCTION.C. The first of these subroutine calls would invoke a mathematical function described in the book "LINPAK Users' Guide," copyrighted 1979 by the Society for Industrial and Applied Mathematics, to cause the PE to factor the matrix of coefficients for the linear equations. The second subroutine call would then invoke another mathematical function described in that book to cause the PE to solve the triangular matrix resulting from the factorization.
To permit the PE 40 to perform computations as directed by the program FUNCTION.C executed by the CPU 22 in the personal computer 22, the PE CPU 82 executes a supervisory computer program, PE01IOS.011 also set forth below, to supervises the overall operation of the PE 40. In supervising the overall operation of the PE 40, the computer program PE01IOS.011 invokes routines in the computer program PE01UTIL.017 to look for requests from the personal computer 20 and to respond to such requests to the extent they involve communication between the PE 40 and the host personal computer 20. If a request involves performing a mathematical computation on data that is already present in the second multi-port VRAM 46 as the result of inter-processor communication effected by routines in the computer program UTIL.C in the personal computer 20 and by routines in the computer program PE01UTIL.017 in the PE CPU 82, then the computer program PE01IOS.011 invokes another computer program PE01MATH. The computer program PE01MATH is an assembly language program that implements the mathematical algorithms described in the "LINPAK Users' Guide." Accordingly, the "LINPAK Users' Guide" is incorporated by reference as though fully set forth here.
To provide the PE CPU 82 with data for a mathematical computatiCi. in the PE 40, a computer program executed by the host personal computer 20 first loads the data into the first multi-port VRAM 44. After having loaded the data into the VRAM 44, the computer program executed by the host personal computer 20 supplies signals to the PE 40 which cause it to transfer the data over the inter-memory bus 48 from the VRAM 44 to the second multi-port VRAM 46. Once the data is present in the VRAM 46, the computer program executed by the host personal computer 20 then directs the PE CPU 82 to perform the desired mathematical computation. If there is sufficient available memory in each of the multi-port VRAMs 44 and 46 to store the results of an ongoing computation and the data for a succeeding one, while the PE 40 is performing the mathematical computation the personal computer 20 may be preparing the data for a succeeding computation and storing it in the first multi-port VRAM 44 free from contention with memory exchanges occurring between the PE CPU 82 and the second multi-port VRAM 46. When the PE CPU 82 finishes the mathematical computation, it transmits signals to the host computer 20 indicating that fact. Upon receiving notification that the PE CPU 82 has completed the requested mathematical computation, the computer program executed by the host personal computer 20 then supplies additional signals to the PE 40 that cause the results of the computation to be transferred back over the inter-memory bus 48 from the VRAM 46 to the VRAM 44. The details of the signals required to effect the inter-processor communications outlined above and the techniques used to perform those communications are completely set forth below in the following computer programs.
UTIL.C
The following computer program called UTIL.C, contains routines executed by the host personal computer 20 to effect different types of interprocessor communications between the personal computer 20 and the PE 40.
/* Util.015 */
#include "util.h" #include <ctype.h> #include <stdio.h> #include <dos.h> #include <time.h> #include <conio.h> #include <stdlib.h> finclude <string.h> #include "style.h" void intel_to motorola
(unsTgned long Source, unsigned long Bytes, unsigned int Unit); void X_Mover
(unsigned long Source,unsigned long Target,unsigned long Bytes); void SwitchWords
(unsigned long Source,unsigned long Bytes,unsigned int Unit); uns uns uns uns uns int int int int int int int int cha uns uns
Figure imgf000045_0001
char hex_digit[] = "0123456789ABCDEF";
#define BLACK_BACK 7 #define DOUBLE_LINE 2 #define CLEAR 1 #define NO CLEAR 0 int SC_Init ( ) i n t H_Mode,PE_Mode,IOMode,Answer,Status,StartRow,Token,Signal,PE= 0x300; int HES,VES,HEB,VEB,HSB,VSB,HT,VT; int rsw,bsw,rbp,bbp,wpr,rpb,rfp, fp; /* init PE */ PCAddress=PHYS(matrix) ; Signal=Init(PE) ; IOMode=TRUE; ExtAddress=0x500000L; /* interpret Signal from PE */ if(Signal EQ FALSE)
- {
PauseHere(20,5,"PE can not be initialized"); PE_Mode=TX; return(IOMode) ; }
Display(PE); /* Display PE ID message */ PE2HXfr(OFF); H2PEXfr(OFF); PE_Mode=RX;
/* Initialize Host bRAM parameters */ Status=InitHost(PE,IOMode) ; if(Status EQ FALSE) H_Mode=TX; /* reset default mode */
PauseHere(20,5,"Init of Host to TX mode has failed! "); return(IOMode) ;
H_Mode=TX; return(IOMode) ;
int InitHost(PE,IOMode) int PE,IOMode; { int Byte,Poll,StartRow,Status,Signal,Data; int HES,VES,HEB,VEB,HSB,VSB,HT,VT;
XSync(HOST,ON); Refreshes(HOST,7);
Waits(HOST,0);
Words(HOST,4) ; /* E.G., allowing for 2 bits of Tap, set 0100 binary */
Byte=get_byte(OxODOCO,100) ; Byte&=0xBF; /* turn bl4 off */ put_byte(Byte,OxODOCO,100);
/* note: this is default for chip power up init */
Byte=get_byte(OxODOCO,88) ; /* get current value */ ByteI=0x80; /* turn bit 7 on */ put_byte(Byte,OxODOCO,88) ; Byte=get_byte(0x0D0C0,88) ;- /* get lower byte of Host
CRI */ Byte&=0xF0; put_byte(Byte,0x0D0C0,88);
TXRowL(HOST,256);
/* Set Host bRAM Controller to starting Row of transfer */
Status=BufStart(HOST,0); /* Host TX buffer starting row is 0 */
/* Set Host bRAM Controller to transfer 128 Rows-per-Buffer */ BufLength(HOST,129); /* Length=128+1 */ /* Set PE to RX mode */ if(IOMode EQ TRUE)
Display(PE); /* display request for token */ H2PE(PE, 'e' ); /* send Token to PE for setting PE to RX mode */
Data=PE2H(PE); /* receive echo from PE */ if(Data NE 'e') /* PE is not doing the right function */ return(FALSE) ;
/* send starting row number to PE */
H2PE(PE,127);
Data=PE2H(PE); if(Data NE 127) return(FALSE);
/* send Length in rows to PE */
H2PE(PE,129);
Data=PE2H(PE); if(Data NE 129) return(FALSE) ;
/* Check for PE ACK to make sure the PE is in RX mode before continuing because we don't want both to drive S-Bus! */ Signal=CheckPE(PE) ; if(Signal NE ACK)
PauseHere(20,5,"Change of PE to RX mode was unsucessful *'); return(FALSE) ; }
} return(TRUE) ;
unsigned long HostAddress(void *Operand) unsigned long address; address = (long)FP_SEG(Operand) ; /* get the segment for Operand */ address «= 4; /* shift segment one nibble, down */ address += FP_OFF(Operand) ; /* get offset and add to shifted seg */ return address; /* to get 24bit Host addr of Operand */ } int H2PE_B2H(PE,Data) int PE,Data; { char HexString[20] ; char *p; int i, Length, Signal;
/* convert Data from binary number into a string of hex characters */ p = itoa(Data, HexString, 16);
/* send the string to PE */ Length = strlen(HexString); for(i=0;i<Length;i++) H2PE(PE, (int)HexString[i] ) ;
/* send cr to end string */ H2PE(PE,0x0D); /* if ACK received return true, else false */
Signal = CheckPE(PE); /* get signal from host */ if(Signal EQ ACK) return TRUE; return FALSE;
int H2PE_LB2H(PE,Data) int PE; unsigned long Data; char HexString[20]; char *p; int i, Length, Signal, Status;
/* convert Data from binary number into a string of hex characters */ p = ltoa(Data, HexString, 16);
/* send the string to PE */ Length = strlen(HexString) ; for (i = 0; i < Length; i++)
Signal = (int)HexString[i]; H2PE(PE,Signal);
/* send cr to end string */ H2PE(PE,0x0D);
/* if ACK received return true, else false */ Signal = CheckPE(PE); /* get signal from host */ if (Signal EQ ACK) return TRUE; return FALSE; } int H2PE_F2H(int PE, float Data) char HexString[20]; char *p; int i, Length, Signal;
/* convert Data from binary number into a string of hex characters */
/* send 8 chars, no cr */
HexStringfO] = hex_digit[ (*(unsigned long *)&Data) » 28) & OxOOOOOOOf];
HexString[l] = hex_digit[ (*(unsigned long *)&Data) » 24) & OxOOOOOOOf];
HexString[2] = hex_digit[ (*(unsigned long *)&Data) » 20) & OxOOOOOOOf];
HexString[3] = hex_digit[ (*(unsigned long *)&Data) » 16) & OxOOOOOOOf]; HexString[4] = hex_digit[ (*(unsigned long *)&Data) » 12) & OxOOOOOOOf];
HexString[5] = hex_digit[ (*(unsigned long *)&Data) » 8 ) & OxOOOOOOOf];
HexString[6] = hex_digit[ (*(unsigned long *)&Data) » 4 ) & OxOOOOOOOf];
HexString[7] = hex_digit[ (*(unsigned long *)&Data) ) & OxOOOOOOOf];
HexString!8] = 0;
/* send the string to PE */ /* Length = strlen(HexString) ; */ /* for (i = 0; i < Length; i++) { */ for (i = 0; i < 8; i++)
S rignal = (int)HexStringfi] ; H2PE(PE,Signal);
/* if ACK received return true, else false */ Signal=CheckPE(PE); /* get signal from host */ if (Signal EQ ACK) return TRUE; return FALSE;
} void ClearH() { int i;
/* clear 16,384 (4000 hex) Words in Host Working Area
'/ for(i=0;i<16384;i++)
{ matrix[i]=0;
} /* store in selected Host quarter buffer */ XMove(PCAddress,ExtAddress, 0x8000) XMove(PCAddress,ExtAddress+0x8000L, 0x8000) XMove(PCAddress,ExtAddress+OxlOOOOL,0x8000) XMove(PCAddress,ExtAddress+0xl8000L,0x8000) /* PauseHere(20,5," Host Buffer has been cleared ");*/ return; } int FillH(Value,StartRow,EndRow) unsigned int Value; unsigned int StartRow,EndRow; unsigned int End, ords,Bytes,Rows,Length,k,1,i,j; unsigned long StartByte=0L; te t_window(CLEAR," Generate a Host output data set ",""); wgoto(2,2); Rows=EndRow-StartRow+l; if(Rows GT 256) return(FALSE) ; /* more than one job is required */ if(Rows LE 64) /* upto 1 block required {
/* generate 32,768 Words of data in Host output buffer
V k=0; for(i=0;i<Rows;i++) /* for each row */ { for(j=0;j<256;j++) matrix[k]=Value; k++; }
} StartByte=StartRow«9;
XMove(PCAddress ,ExtAddress+ ( ( (unsigned long) (StartRow) )«9) ,Rows*512) ; } else /* one or more full blocks are required */
{ k=0; Loop: for(i=0;i<64;i++) /* for each row of a block */ for(i=0;j<256;j++) matrix[k]=Value; k++; } } XMove(PCAddress,ExtAddress+ ( ( (unsigned long ) ( StartRow) ) «9 ) , 0x8000 ) ; k=0; /* reset index */
Rows-=64; /* how many rows left to do? */ StartRow+=64; /* start 64 rows farther */ if (Rows GE 64) goto Loop; /* do another full block */ if (Rows EQ 0) goto Fini; else /* we have a partial block left to do */ for(i=StartRow;i<=EndRow;i++) /* do remaining rows
( for(j=0;j<256;j++) { matrix[k]=Value; k++;
} } XMove(PCAddress,ExtAddress+( ( (unsigned long) (StartRow) ) )«9,Rows*512) ;
} Fini: PauseHere(20,5," Host Buffer has been loaded with data
"); return(TRUE) ;
DumpH(StartRow,EndRow) unsigned int StartRow,EndRow; unsigned int Rows,k,l,i,j,x; te t_window(CLEAR," Printing Host output buffer Row",""); wgoto(2,2);
Rows=EndRow-StartRow+l; if(Rows GT 256) return(FALSE); /* more than one job is required */ k=0/*StartRow*256*/; l=StartRow; if(Rows LE 64) /* upto 1 block required */
XMo v e ( Ex tAdd r es s + ( ( ( u ns i g ned long) (StartRow) )«9) ,PCAddress,Rows*512) ; for(i=0;i<Rows;i++) /* for each row */ { x=l; printf("\nHost Buffer Dump - Row %d, ecimal,",1); printf(" %02X,hex follows\n",x); for(j=0;j<256;j++) { printf("%04X ",matrix[k]); k++;
}
1++; }
} else /* one or more full blocks are required */ l=StartRow; Loop:
XMo v e ( Ex tAdd r e s s + ( ( ( u n s i g n ed long) (StartRow) )«9),PCAddress, 0x8000); k=0; for(i=0;i<64;i++) /* for each row of a block */ { x=l; printf("\nHost Buffer Dump - Row %d, ecimal,",1) ; printf(" %02X,hex foll-ows\n",x) ; for(j=0;j<256;j++) printf("%04X ",matrix[k] ) ; k++;
} ι++;
} Rows-=64; /* how many rows left to do? */ StartRow+=64; /* start 64 rows farther */ if(Rows GE 64) goto Loop; /* do another full block */ if(Rows EQ 0) goto DumpFini; else /* we have a partial block left to do */ XMove ( ExtAddr es s+ ( ( ( uns i gned long) (StartRow) ) )«9,PCAddress, Rows* 512) ; for(i=StartRow;i<=EndRow;i++) /* do remaining rows { x=l; printf( "\nHost Buffer Dump - Row
%d,decimal,",1); printf(" %02X,hex follows\n",x) ; for(j=0;j<256;j++) printf("%04X ",matrix[k] ) ; k++; 1++;
} }
} } DumpFini:
PauseHere(20,5," Host Buffer data has been displayed "); return(TRUE);
int Init(PE) int PE; { int Signal,Data;
Reset(PE); /* this resets PE. Warning puts PE into default TX mode */ Signal=CheckPE(PE) ; return(Signal) ;
int ClearPE(PE) int PE; { int Signal,Data,MSB,LSB; char Token='a'; /* Token for clearing all buffer addresses */ /* Assume PE is waiting for a Token */ text_window(CLEAR," Display Host Buffer",""); wgoto(2,2) ; if(CheckPE(PE) NE ENQ) return(FALSE);
H2PE(PE,Token) /* send selected Token */
Data=PE2H(PE); if(Data NE Token) return(FALSE) ;
Display(PE); /* ACK */ /* PauseHere(20,5," PE Buffer has been cleared by internal code ");*/ return(TRUE);
} int FillPE(PE,Value,StartRow,EndRow) int PE,StartRow,EndRow; int Signal,Data,MSB,LSB; char Token='b'; /* Token for writing dummy data */ /* Assume PE is waiting for a Token */ text_window(CLEAR," Display Host Buffer",""); wgoto(2,2); if(CheckPE(PE) NE ENQ) return(FALSE);
H2PE(PE,Token); /* send selected Token */
Data=PE2H(PE); if(Data NE Token) return(FALSE); /* send starting row number to PE */
/* NOTE: I!!!!!!!!!!!!!!!!!!! no parameter version yet in peθlutil.008 */ /* H2PE(PE,StartRow);
Data=PE2H(PE); if(Data NE StartRow) return(FALSE); printf("\n Start: %02X \n",Data); wgoto(10,2); */
/* send ending row number to PE */ /* H2PE(PE,EndRow);
Data=PE2H(PE); if(Data NE EndRow) return(FALSE); */
/* Data=PE2H(PE);*/ /* get number of row tobe printed
V /* printf("\n Number of Row to Print: %02X \n",Data);*/ Display(PE); /* ACK */
PauseHere(20,5," PE Buffer has been filled through I/O port ") return(TRUE); } int DumpPE(PE,StartRow,EndRow) int PE,StartRow,EndRow; int i,j,Signal,Data,MSB,LSB; char Token='c'; /* Token for dumping data */ /* Assume PE is waiting for a Token */ text windo (CLEAR," Display Host Buffer",""); wgoto(2,2); if(CheckPE(PE) NE ENQ) return(FALSE) ; H2PE(PE,Token) ; /* send selected Token */ Data=PE2H(PE); if(Data NE Token) return(FALSE) ;
/* send starting row number to PE */ H2PE(PE,StartRow) ; Data=PE2H(PE); if(Data NE StartRow) return(FALSE) ; printf("\n Start Row: %02X \n",Data); wgoto(10,2);
/* send ending row number to PE */ H2PE(PE,EndRow) ;
Data=PE2H(PE); printf("\n End Row: %02X \n",Data) ; wgoto(12,2) ; if(Data NE EndRow) return(FALSE) ;
Data=PE2H(PE) ; /* get number of rows to be printed */ printf("\n Number of Rows to Print: %02X \n",Data); for(i=StartRow;i<=EndRow;i++) { printf("\nPE Buffer Dump - Row %d,decimal; hex follows:",i) ; printf(" %02X\n",i); for(j=0;j<256;j++) /* j is the column number */ {
MSB=PE2H(PE); LSB=PE2H(PE); printf("%02X%02X ",MSB,LSB); } printf("\n"); Display(PE); /* ACK */
PauseHere(20,5," PE Buffer data has been displayed through I/O port "); return(TRUE);
int Host2RX(PE,HStart,HLength,PEStartrPELength) int PE,HStart,HLength,PEStart,PELength; { int Status, Signal, Data, Poll; unsigned long Address;
/* Turn Off Host bRAM Controller AutoTransfer function */ /* note: this is default for chip power up init but it may be left on by previous processing */
/* Set Host bRAM Controller to receive 256 Words-per-Row */ RXRowL(HOST,256);
/* Set Host MC to Receive with PseudoSAM2RAM (Host Pseudo write cycle) */ Status=MC_Ctl(HOST,RX); if(Status EQ FALSE)
{
PauseHere(20,5,"Change of Host to RX mode was unsucessful "); return(FALSE);
/* Set Host bRAM Controller data direction to PE-to-Host (SAM-to-bRAM) */
Status=DataDir(HOST,RX) ;
/* Set Host bRAM Controller to start at row StartRow */ BufStart(HOST,HStart) ; BufLength(HOS ,HLength);
/* Tell PE to go to the TX mode */ if(CheckPE(PE) NE ENQ) return(FALSE); H2PE(PE, 'f• ); /* send Token for setting PE to TX mode */
Data=PE2H(PE); /* receive echo */ if(Data NE 'f') return(FALSE);
/* send starting row number to PE */ H2PE(PE,PEStart); Data=PE2H(PE); if(Data NE PEStart) return(FALSE);
/* send length in rows to PE */ H2PE(PE,PELength); Data=PE2H(PE); if(Data NE PELength) return(FALSE) ;
/* Check Status to see if PE is in TX mode before continuing */
Signal=CheckPE(PE); if(Signal NE ACK) {
PauseHere(20,5,"Change of PE to TX mode was unsucessful "); return(FALSE) ; return(TRUE);
int Host2TX(PE,HStart,HLength,PEStart,PELength) int PE,HStart,HLength,PEStart,PELength; int Signal, Status, Data, Poll; unsigned long Address;
/* Turn Off H-MC AutoTransfer function */
/* note: this is default for chip power up init but it may be left on by previous processing */
/* Set Host bRAM Controller to transfer 256 Words-per-Row */ RXRowL(HOST,256); /* new trial */ /* Set Host bRAM Controller data direction to Host-to-PE (bRAM-to-SAM) */
Status=DataDir(HOST,TX) ;
/* Set Host bRAM Controller to starting Row of transfer */
Status=BufStart(HOST,HStart) ;
/* Set Host bRAM Controller to transfer Length Rows-per-Buffer */
BufLength(HOST,HLength);
/* Set PE to RX mode */ if(CheckPE(PE) NE ENQ) return(FALSE) ; H2PE(PE, 'e' ); /* send Token to PE for setting PE to RX mode */ Data=PE2H(PE) ; /* receive echo from PE */ if(Data NE 'e') /* PE is not doing the right function */ return(FALSE);
/* send starting row number to PE */ H2PE(PE,PEStart); Data=PE2H(PE); if(Data NE PEStart) return(FALSE) ;
/* send Length in rows to PE */ H2PE(PE,PELength); Data=PE2H(PE); if(Data NE PELength) return(FALSE) ;
/* Check for PE ACK to make sure the PE is in RX mode before continuing because we don't want both to drive S-Bus! */
Signal=CheckPE(PE); if(Signal NE ACK)
PauseHere(20,5,"Change of PE to RX mode was unsucessful "); return(FALSE) ; return(TRUE) ;
int MC_Ctl(Processor,State) int Processor,State;
{ int Status; if(State EQ TX) /* Switch Host MC to Transmit mode */ put_word(0xAAAA,0x0D080,0); /* do a dummy RAM2SAM cycle */ return(TRUE) ; } if(State EQ RX) /* Switch Host MC to Receive mode */ - 55 -
{
/* do a pseudo SAM2RAM cycle */ put_word(0xAAAA,0x0D060,0); return(TRUE); } return(FALSE) ;
int PE2HXfr(State) int State; int Bytel,Byte2,PE=0x300;
Bytel=get_byte(HOST_REGS,CRl_LSB); Byte2=get_byte(H0ST_REGS,CR2_MSB); if(State EQ ON)
{ if(CheckPE(PE) NE ENQ) return(FALSE) ; /* PE is somewhere else */ /* Start writing to PE SAM from PE buffer */
H2PE(PE, 'h' ); /* send Token to PE for starting auto update */ /* Start writing to Host SAM from PE SAM */ put_byte(Byte2|0x20,HOST_REGS,CR2_MSB) ; /* Turn on SCLK gate
*/ /* Start writing to Host buffer from Host SAM */ put_byte(Bytel&0xDF,HOST_REGS,CRl_LSB); /* Host
AutoUpdate On */ if(PE2H(PE) NE 'h') return(FALSE); /* PE is deaf V if(CheckPE(PE) NE ACK) return(FALSE); /* PE is screwed up */
} if(State EQ OFF) if(CheckPE(PE) NE ENQ) return(FALSE); /* PE is somewhere else */ /* Stop writing to Host buffer from Host SAM */ put_byte(Bytel|0x20,HOST_REGS,CRl_LSB); /* Host
AutoUpdate Off */
/* Stop writing to Host SAM from PE SAM */ put_byte(Byte2&0xDF,HOST_REGS,CR2_MSB); /* turn off SCLK gate */ /* Stop writing to PE SAM from PE buffer */
H2PE(PE, 'g' ); /* send Token to PE to turn off autoupdate */ if(PE2H(PE) NE 'g') return(FALSE); /* PE is deaf
*/ if(CheckPE(PE) NE ACK) return(FALSE) ; /* PE is screwed up */ } return(TRUE) ;
> int H2PEXfr(State) int State;
{ int Bytel,Byte2,PE=0x300;
Bytel=get_byte(HOST_REGS,CR1_LSB) ; Byte2=get_byte(HOST_REGS,CR2_MSB) ; if(State EQ ON) if(CheckPE(PE) NE ENQ) return(FALSE); /* PE is somewhere else */
/* Start writing to Host SAM from Host buffer */ ' put_byte(Bytel&0xDF,HOST_REGS,CRl_LSB); /* Host
AutoUpdate On */ /* Start writing to PE SAM from Host SAM */ put_byte(Byte2|0x20,HOST_REGS,CR2_MSB) ; /* turn on
SCLK gate /* Start writing to PE buffer from PE SAM V*/ H2PE(PE, 'h* ); /* send Token to PE to start auto update */ if(PE2H(PE) NE 'h') return(FALSE); /* PE is deaf V if(CheckPE(PE) NE ACK) return(FALSE) ; /* PE is screwed up
} v if(State EQ OFF) if(CheckPE(PE) NE ENQ) return(FALSE) ; /* PE is somewhere else */ /* Stop writing to PE buffer from PE SAM */ H2PE(PE, 'g' ); /* send Token to PE to stop auto update */
/* Stop writing to PE SAM from Host SAM */ put_byte(Byte2&0xDF,HOST_REGS,CR2_MSB); /* turn off SCLK gate */ /* Stop writing to Host SAM from Host buffer */ put_byte(Bytel|0x20,HOST_REGS,CRl_LSB); /* Host
AutoUpdate Off */ if(PE2H(PE) NE 'g') return(FALSE) ; /* PE is deaf */ if(CheckPE(PE) NE ACK) return(FALSE) ; /* PE is screwed up
} return(TRUE);
} int BufLength(Processor,Size) int Processor,Size;
{ int Byte,VSB,VES,VEB,VT; if(Processor EQ HOST)
/*
Set Host bRAM Controller to transfer "Size"
Rows-per-Buffer Calculate new(VSB) from new( rows_per_buffer ) and old(VEB) Units are lines which equal rows since we set 1 row per line.
VSB = Size + buf fer_back_porch + buf fer_sync_width -
1
= 128+2+5-1 = 134 */ VSB=Size+6; /* (256+5+2)-l=262 VT=(256+2+5+2)-l=264 */ put_byte(VSB&0xFF,HOST_REGS,VSB_LSB); /* send it to register */ Byte=VSB » 8; /* shift MSB to LSB location */ put_byte(Byte&0xFF,HOST_REGS,VSB_MSB); /* send it to register */
/* calculate new(VES) from new(bsw) */ / *
VES = buffer_sync_width - 1 VES = 5 - 1 = 4
* /
VES=4; put_byte(VES & 0x00FF,HOST_REGS,VES_LSB) ; /* send LSB to register
V Byte=VES » 8; /* shift MSB to LSB location */ put_byte(Byte&0x00FF,HOST_REGS,VES_MSB); /* send MSB to register
V
/* calculate new(VEB) from new(bbp) */
/* VEB = buffer_sync_width + buffer_back_porch - 1 VEB = 5 + 2 - 1
V
VEB=6; put_byte(VEB & 0x00FF,HOST_REGS,VEB_LSB) ; /* send LSB to register
V Byte=VEB » 8; /* shift MSB to LSB location */ put_byte(Byte&0x00FF,HOST_REGS,VEB_MSB) ; /* send MSB to register */
/* calculate new(VT) from new(bfp) */
/*
VT = VSB + buf fer_f ront_porch - 1 /* calculate new(VT) from new(bfp) VT = VSB + buffer_f ront_porch - 1 = 134 + 2 - 1 = 135
'/
VT=VSB+2 ; put_byte ( VT & 0x00FF,HOST_REGS ,VT_LSB ) ; /* send LSB to register
V put_byte ( VT & 0x00FF,HOST_REGS ,VI_LSB) ; /* send it to register
*/ Byte=VT » 8 ; /* shift MSB to LSB location */ put_byte ( Byte & 0x00FF,HOST_REGS ,VT_MSB) ; /* send MSB to register
*/ put_byte ( Byte & 0x00FF,HOST_REGS ,VI_MSB) ; /* send it to register
*/ return(TRUE) ; if(Processor GT HOST) /* use value of "Processor" to address PE */ return(TRUE); return(FALSE) ;
int question(string) char string[20];
{ int si; wputs(string) ; wputs(" (y or n)? "); while(TRUE) sl=wgetf(entry,"",3); /* loop until you get 'y..' or
'n.. ' only */ if(strnicmp(entry,"y",l) EQ 0) return(YES); if(strnicmp(entry,"n",l) EQ 0) return(NO);
} void Quit( ) { int PE=0x300;
Reset(PE); /* puts PE in RX mode */ PE2HXfr(OFF); H2PEXfr(OFF); exit(0);
int EnterInt(old_data,edit_flag,fields) int old_data, edit_flag, fields; { int si, col, skip=5, new_data; sl=0; col=wcol(); /* remember where old data starts */ if( (edit_flag EQ TRUE) OR (fields GT 0)) { printf("%3d",old_data); wgo(0,skip) ; sl=wgetf(entry,"",20) ; wgo(0, (col-wcol( )) ); /* go back to start of old data */ if(si EQ 0) return(old_data); else new_data=atoi(entry) ; /* convert it to integer */ printf("%3d ",new_data); /* show it and erase entry */ } else
{ sl=wgetf(entry,"",20) ; wgo(0, (col-wcol( ) ) ); /* go back to start of old data
V new_data=atoi(entry); /* convert it to integer */ printf("%3d ",new_data); /* show it and erase entry */ } return(new_data) ; } text_window(cmd,stringl,string2) /* show main working screen window */ int cmd; char stringl[20], string2[20]; if(cmd EQ CLEAR) wclean(BLACK_BACK); /* erase if required
*/ wframe(DOUBLE_LINE,BLACK_BACK); /* put frame back */ wgoto(0,1); wputs(stringl) ; wgoto(1,1) ; wputs(string2) ; wgoto(3,2); return;
} init menus( ) /* top row, left col, # rows, # cols, col width */
/* mn_disclaimer=mopen( 5,20,12,1,38,7,7,1); mn_define= mopen( 8,10,10,1,30,
F G N D _ W H I E I B G N D _ R E D | R E V E R S E , FGND_WHITE | BGND_BLUE , sash ) ; mn_control= mopen( 1,60,12,1,16,
FGND_WHITEIBGND_BLUE |REVERSE, FGND_WHITE|BGND_BLUE, sash);
V return;
} init windows( ) τ/*top-row, bottom-row, left-column, right-column, buffer=TRUE/FALSE*/ w_test= wopen(0,24,0,80,FALSE) ; /* main working window */ test_window(0,0,1) ; /* set up main window */ w_text=wopen(4,22,4,58,TRUE) ; /* dialog window */ wselect(w_test) ; /* reselect main window */ return; } test_window(problem_status,load_status,cmd) /* show main working screen window */ int problem status,load status,cmd;
{ wpush(w test); /* select main window */ if(cmd EQ CLEAR) wclean(BLACK_BACK); /* erase if required */ wframe(DOUBLE_LINE,BLACK_BACK) ; /* put frame back */ wgoto(0,0) ; wputs(" Parallel Processor Testbench"); wgoto(1,0) ; wputs(" Celtek, Inc. Version 0.009 "); wgoto(2,0) ; wpop(0); /* restore previous window */ return; } halt_here( ) char *key; *key=0; wputs("\n "); wputsa(" Hit RETURN to continue ",112); scanf("%c",&key) ; return; }
PauseHere(line,column,string) char *string; int line,column; { wgoto(line,column) ; wputsa(string,112) ; halt_here( ) ; return; } void Reset(PE) int PE;
{ unsigned long wait; outp(PE+0xC,0); /* for alpha */ outp(PE+0x8,0); /* for beta */
Delay(wait = 20); /* wait for PE to settle */ return; } int CheckPE(PE) int PE;
{ int Signal,Data; Signal=0; wprintf("\n"); do
{
Data=PE2H(PE) ; /* receive signal */ if(Data EQ ENQ) Signal=ENQ; /* we are out of sync */ if(Data EQ ACK) Signal=ACK; /* this is what we want */ if(Data EQ NAK)
Signal=NAK; /* bad news */ wprintf("\n PE reports Exception: "); Display(PE);
PauseHere(18,5,""); return(Signal) ;
} while(Data NE EOS); return(Signal);
int Display(PE) int PE;
{ int Signal,Data; Signal=0; do {
Data=PE2H(PE); if(Data GE ' • ) printf("%c",Data); if(Data EQ OxOD) printf("\n") ; while(Data NE EOS); return Signal;
void Delay(amount) unsigned long amount; double x=1.0; unsigned long i,j; for(i=0;iomount;i++) { for(j=0;j<amount;j++) x=x*x; return;
} int H2PEhex(PE) int PE;
{ int x,i,length; char entry[8]; length=wgetf(entry,"",8); for(i=0;i<length;i++) x=entry[i] ; if(x GT 0x60) x&=0x5F; if(isxdigit(x) NE FALSE)
H2PE(PE,x); } } H2PE(PE,0x0D); return(TRUE) ;
int PE2Hhex(PE) int PE;
{ int i,ch; for(i=0;i<8;i++) ch=PE2H(PE); if(ch EQ OxOD) break; wprintf("%c",ch); return(ch); } void Error(error_text) char error text[];
{ printf("\nCeltek Inc., PACE Utilities run_time error....\n"); printf("%s\n",error_text); printf("...now exiting to system...\n"); exit(l); } int DataDir(Processor,State) int Processor,State;
{ /* Set Host bRAM Controller data direction to bRAM-to-SAM */ int Byte; if(Processor EQ HOST) /* Host is processor 0x0 */
Byte=get_byte(HOST_REGS ,CR1_LSB) ; if(State EQ TX) Byte&=0xBF; /* set bit 6 to a 0
(bRAM2SAM) */ if(State EQ RX) Byte|=0x40; /* set bit 6 to a 1
(SAM2bRAM) */ put_byte(Byte,HOST_REGS,CR1_LSB); return(TRUE);
} if(Processor GT HOST)
/* use value of "Processor" to address PE */ return(TRUE) ; return(FALSE); /* an init function */ int XSync(Processor,State) int Processor,State; { int Byte; if(Processor EQ HOST) /* Host is processor 0x0 */
Byte=get_byte(HOST_REGS,CR1_MSB) ; if(State EQ OFF) Byte&=0xEF; /* bit 8 in CRI to zero*/ if(State EQ ON) Byte|=0x10; /* bit 8 in CRI to high */ put_byte(Byte,HOST_REGS,CRl_MSB); return(TRUE); if(Processor GT HOST)
/* use value of "Processor" to address PE */ return(TRUE); return(FALSE);
}
/* an init function */ int Words(Processor,Value) int Processor,Value; put_byte(Value&0x000F,HOST_REGS,DU_LSB); /* get
U p d a t e Regi ster
V return (TRUE) ; } int BufIntPoll() { int Byte=0; Byte=get byte(HOST REGS,SR LSB); /* get interrupt byte
V if(Byte&=0xl EQ TRUE) return(TRUE) ; /* at vertical blank */ else return(FALSE) ; /* not at vertical blank
* /
} int Refreshes(Processor,Number) int Processor, umber;
{ int Byte;
/* Set Processor bRAM Controller for "State" Refreshes-per-cycle */ if(Processor EQ HOST)
Number&=0x07; /* restrict value of Refreshes per Cycle to 0-7 */ Number«=4; /* shift value of State to correct location */
Byte=get byte(HOST REGS,CRI MSB); /* get current value
~ */ Byte&=0x8F; /* clear old value */
Bytej=Number; /* set bits 12, 13, and 14 of Byte to value of State */ put_byte(Byte,HOST_REGS,CR1_MSB) ; return(TRUE); if(Processor GT HOST)
{
/* use value of "Processor" to address PE */ return(TRUE) ;
} return(FALSE) ;
} int Waits(Processor, umber) int Processor,Number;
{ int Byte;
/* Set Host bRAM Controller for "Number" Waits */ if(Processor EQ HOST)
Number&=0x07; /* restrict value of Waits to 0-7 */ Byte=get_byte(HOST REGS,CR2 MSB); /* get current value
*/ Byte&=0xF8; /* clear old value */
Byte|=Number; /* set bits 12, 13, and 14 of Byte to value of State */ put_byte(Byte,HOST_REGS,CR2_MSB) ; return(TRUE) ; } else
{
/* use value of "Processor" to address PE */ return(TRUE); } return(FALSE) ; } int RXRowL(Processor,Size) int Processor,Size;
{ int Byte,HSB,HES,HEB,HT; if(Processor EQ HOST)
{ /* calc new(HSB) from new(words_per_row) and old(HEB)
V
/* units are VIDCLK cycles or 200 nSEC each (SCLK=20MHz. ,VIDCLK=5MHz.) In every VIDCLK cycle a row of 256 words is copied to the SAM.
In every unblanked (active) period 256 SCLKs must occur, or 64
VIDCLKs. Therefore the number of VIDCLKs in HSB must be:
HSB = words_per_row/4 + row_back_porch + row_sync_width - 1 Size=256; Size/4=64; HSB = 64 + 5 + 5 - 1 HSB = Size/4+10-1;
V HSB=73;
/* store new(HSB) */
Byte=HSB & OxOOFF; /* separate out LSB */ put_byte(Byte,OxODOCO,16) ; /* send it to register */ Byte=HSB » 8; /* shift MSB to LSB location */ Byte &= OxOOFF; /* clean it */ put_byte(Byte,OxODOCO,20) ; /* send it to register */
/* calculate new(HES) from new(rsw) */
/* HES = row_sync_width - 1 HES = 5 - 1 = 4
V
HES=4; put_byte(HES&0x00FF,0x0D0C0f0) ; /* send LSB to register */
Byte=HES » 8; /* shift MSB to LSB location */ put_byte(Byte&0x00FF,OxODOCO,4) ; /* send MSB to register */ /* calculate new( B) from new(rbp) */
/*
HEB = row_sync_width + row_back_porch - 1 HEB = 5 + 5 - 1 = 9
V HEB=9; put_byte(HEB&0x00FF,0x0D0C0,8); /* send LSB to register */ Byte=HEB » 8; /* shift MSB to LSB location */ put_byte(Byte&0x00FF,OxODOCO,12); /* send MSB to register */
/ * calculate new(HT) from new(rfp)
HT = Size/4 + row_front_porch + row-back-porch + sync width - 1
HT = Size/4 + 5 + 5 + 5 - 1 = 78;
*/
HT=78; put_byte(HT & OxOOFF,OxODOCO,24) ; /* send LSB to register */
Byte=HT » 8; /* shift MSB to LSB location */ put_byte(Byte&OxOOFF,OxODOCO,28) ; /* send MSB to register */ return(TRUE) ; } return(FALSE) ;
int TXRowL(Processor,Size) int Processor,Size;
{ int Byte,HSB,HES,HEB,HT; if(Processor EQ HOST)
{ /* calc ne (HSB) from new(words_per_row) and old(HEB)
*/ /* units are VIDCLK cycles or 200 nSEC each (SCLK=20MHz. ,VIDCLK=5MHz.)
In every VIDCLK cycle a row of 256 words is copied to the SAM. In every unblanked (active) period 256 SCLKs must occur, or 64
VIDCLKs. Therefore the number of VIDCLKs in HSB must be:
HSB = words_per_row/4 + row_back_porch + row_sync_width - 1
Si-ze=256; Size/4=64; HSB = 64 + 5 + 5 - 1 HSB = Size/4+10-1;
V HSB=70;
/* store new(HSB) */
Byte=HSB & OxOOFF; /* separate out LSB */ put_byte(Byte,OxODOCO,16) ; /* send it to register */
Byte=HSB » 8; /* shift MSB to LSB location */ Byte &= OxOOFF; /* clean it */ put_byte(Byte,OxODOCO,20) ; /* send it to register */
/* calculate ne (HES) from new(rsw) */
/* HES = row_sync_width - 1 HES = 5 - 1 = 4
/
HES=4; put_byte(HES&0x00FF,0x0D0C0,0); /* send LSB to register */
Byte=HES » 8; /* shift MSB to LSB location */ put_byte(Byte&OxOOFF,OxODOCO,4); /* send MSB to register */ /* calculate new(HEB) from new(rbp) */
/*
HEB = row_sync_width + row_back_porch - 1 HEB = 5 + 5 - 1 = 9
*/ HEB=6; put_byte(HEB&0x00FF,0x0D0C0,8); /* send LSB to register */ Byte=HEB » 8; /* shift MSB to LSB location */ put_byte(Byte&0x00FF,OxODOCO,12); /* send MSB to register */
/ * calculate new(HT) from new(rfp)
HT = Size/4 + row_front_porch + row-back-porch + sync width - 1
HT = Size/4 + 5 + 5 + 5 - 1 = 78; V HT=78; put_byte(HT & OxOOFF,OxODOCO,24) ; /* send LSB to register */ Byte=HT » 8; /* shift MSB to LSB location */ put_byte(Byte&OxOOFF,OxODOCO,28); /* send MSB to register */ return(TRUE); return(FALSE) ; } int BufStart(Processor,StartRow) int Processor,StartRow; { int Byte; if(Processor EQ HOST)
StartRow«=2; /* shift Address up two bits for BO and Bl */ Byte=OxFF&StartRow; put_byte(Byte,HOST_REGS,DS_LSB);
Byte=StartRow»8; /* shift MSB to lower position */
Byte&=0xFF; put_byte(Byte,HOST_REGS,DS_MSB); return(TRUE); if(Processor GT HOST)
/* use value of "Processor" to address PE */ return(TRUE); return(FALSE);
int PE2H_H2L(int PE, long *val) int i; unsigned long temp; unsigned int tempi; temp = 0; for (i = 0; i < 8; i++) { temp «= 4; tempi = PE2H(PE); if ( !isxdigit(tempi)) { printf("PE2H_H2L returning 0"); return FALSE;
} if (tempi <= '9' ) temp += (tempi - '0' ); else if (tempi <= 'F') temp += (tempi - ('A' - 0x0a)); else temp += (tempi - ('a1 - 0x0a));
*val = temp; return TRUE; int PE2H H2F(int PE, long *val")
{ int i; unsigned long temp; unsigned int tempi; temp=0; for (i=0;i<8;i++)
{ temp«=4; templ=PE2H(PE); if (not isxdigit(tempi) ) printf("PE2H_H2F returning 0"); return FALSE;
" ) if (templ<='9') temp+=(tempi-10' ) ; else if (tempi <= 'F') temp+=(tempi-( 'A'-0x0a) ) ; else temp+=(tempi-( 'a'-0x0a) ) ; }
*(long *)val=temp; return TRUE; } unsigned long PHYS(int *s) unsigned long result; result=(long)FP_SEG(s) ; result=result«4; result+=FP_OFF(s); return result; } void X_Move(unsigned long Source, unsigned long Target, unsigned long Bytes, unsigned int Unit) unsigned long MaxBytes=0xFFFE; /* maximum 64k bytes per
X_Mover operation */ unsigned long source,target,bytes; if(Unit NE 1) if ( (Source & OxFFFOOOOO) EQ 0) intel_to_motorola( Source, Bytes, Unit) ; bytes =Bytes; source=Source; target=Target; while(bytes GT MaxBytes)
X_Mover(source,target,MaxBytes) ; bytes -=MaxBytes; source+=MaxBytes; target+=MaxBytes; X_Mover(source,target,bytes); if(Unit NE 1) if ( (Source & OxFFFOOOOO) EQ 0) intel_to_motorola(Source,Bytes,Unit) ; else intel_to_motorola(Target,Bytes,Unit) ; return; } void X_Mover
(unsigned long Source, unsigned long Target, unsigned long Bytes) { unsigned char *g,gdt[48]; union REGS r; struct SREGS s; /* Someday, put this into init routines and globlize gdt[] */ gdt[0] =gdt[l] =gdt[2] =gdt[3] =gdt[4] =gdt[5] =gdt[6] =gdt[7] =0; gdt[8] =gdt[9] =gdt[10] =gdt[ll] =gdt[12] =gdt[13] =gdt[14] =gdt[15] =0; gdt[22] =gdt[23] =gdt[30] =gdt[31] =gdt[32] =gdt[33] =gdt[34] =gdt[35] =0; gdt[36] =gdt[37] =gdt[38] =gdt[39] =gdt[40] =gdt[41] =gdt[42] =gdt[43] =0; gdt[44]=gdt[45]=gdt[46]=gdt[47]=0; gdt[21]=gdt[29]=(unsigned char)0x93;
/* Source Descriptor */ gdt[16]=(unsigned char)Bytes; gdtf17]=(unsigned char)(Bytes » 8); gdt[18]=(unsigned char) (Source); gdt[19]=(unsigned char)(Source » 8); gdtf20]=(unsigned char)(Source » 16);
/* Target Descriptor */ gdt[24]=(unsigned char) (Bytes); gdt[25]=(unsigned char) (Bytes»8); gdt[26]=(unsigned char) (Target); gdt[27]=(unsigned char) (Target»8); gdt[28]=(unsigned char) (Target»16); g = gdt; r.h.ah=0x87; r.x.cx=Bytes»l; s.es=FP_SEG(g); r.x.si=FP_OFF(g); int86x(0xl5,&r,&r,&s) ; if (r.h.ah NE 0) PEError(15);
}
/* For now, this is used by older sc_util routines */ XMove(unsigned long source, unsigned long target, unsigned Bytes) unsigned char gdt[48]; unsigned char *g; union REGS r; struct SREGS s; g = gdt; gdt[0] = gdt[l] = gdt[2] = gdt[3] = gdt[4] = gdt[5] = gdt[6] = gdt[7] = 0; gdt[8] = gdt[9] = gdt[10] = gdt[ll] = gdt[12] = gdt[13] = gdt[14] = gdt[15] =0;
/* Source Descriptor */ gdt[16] = (unsigned char)Bytes; gdt[17] = (unsigned char) (Bytes » 8); gdt[18] = (unsigned char.source; gdt[19] = (unsigned char) (source » 8); gdt[20] = (unsigned char) (source » 16); gdt[21] = (unsigned char)0x93; gdt[22] = gdt[23] = 0;
/* Target Descriptor */ gdt[24] = (unsigned char)Byte__; gdt[25] = (unsigned char) (Bytes » 8); gdt[26] = (unsigned char)target; αdt-f27Ϊ = msionec! πharWi-arαph » 8A
gdt[32] = gdt[33] = gdt[34] = gdt[35] = gdt[36] = gdt[37] = gdt[38]
= gdt[39] = 0; gdt[40] = gdt[41] = gdt[42] = gdt[43] =.gdt[44] = gdt[45] = gdt[46] = gdt[47] = 0; r.h.ah = 0x87; r.x.cx = Bytes » 1; s.es = FP_SEG(g); r.x.si = FP_OFF(g); int86x(0xl5, &r, &r, &s); if (r.h.ah != 0) PEError(15) ;
void intel_to_motorola
(unsigned long Source, unsigned long Bytes, unsigned int Unit) { unsigned int *ptr; unsigned int temp; unsigned int i; unsigned long MaxBytes=0xFFFC; while(Bytes GT MaxBytes) {
SwitchWords(Source,MaxBytes,Unit); Bytes -=MaxBytes; Source+=MaxBytes; SwitchWords(Source,Bytes,Unit);
void SwitchWords
(unsigned long Source, unsigned long Bytes, unsigned int Unit) unsigned int *ptr; unsigned int temp; unsigned int i;
FP_SEG(ptr) = (int) (Source » 4);
FP_OFF(ptr) = (int) (Source & OxOOOOOOOf); if (Unit == 2) { for (i=0;i<(Bytes»2);++i) temp=*ptr; *ptr=*(ptr+l); *(ptr+l)=temp; ptr+=2;
} else /* unit == 4 */ { for(i=0;i<(Bytes»4);++i) temp=*ptr;
*ptr=*(ptr+3); *(ptr+3)=temp; temp=*(ptr+l);
*(ptr+l)=*(ptr+2);
*(ptr+2)=temp; ptr+=4; J
}
unsigned long init_xmem(void)
ExtAddress = 0x500000L; return ExtAddress; } int PE2H(int PE) /* get data from PE */ int Data;
PE_DAWait(PE) ; /* Host waits for PE to send it */
Data = inp(PE + 4) ; /* Assume PE uses H_DU
V return Data; /* to meter out data } void H2PE(PE,Data) int PE,Data; /* assuming Host has data (H_DA=TRUE) { /* send it to PE */
PE_DUWait(PE); /* don't over run H2PE register "*/ outp(PE+4,Data) ;
void PE_DUWait(PE) int PE; /* PE should wait until Host data */
{ /* has been used */ int Status;
PE_DULoop:
Status=inp(PE) ; Status&=0x01; /* isolate status bit 0
*/ if(Status NE 0) goto PE_DULoop; /* H2PE latch is clear */ } void PE_DAWait(PE) int PE; /* Host waits until PE has */
{ /* data available */ int Status;
PE_DALoop: Status=inp(PE) ;
Status&=0x02; /* isolate status bit 1 */ if(Status NE 0) goto PE_DALoop; /* PE has data to send */ } void put_word(val,seg,offset) int val,seg,offset; { int *ptr;
FP_SEG(ptr)=seg;
FP_OFF(ptr)=offset;
*ptr=val; } void put byte(val,seg,offset) int val,seg,offset; unsigned char *ptr; FP_SEG(ptr) = seg;
FP_OFF(ptr) = offset; *ptr = (unsigned char)val; } int get_word(seg,offset) int seg,offset;
{ int *ptr; FP_SEG(ptr) = seg;
FP_OFF(ptr) = offset; return *ptr; } int get_byte(seg,offset) int seg,offset;
{ unsigned char *ptr; FP_SEG(ptr) = seg;
FP_OFF(ptr) = offset; return (int)*ptr;
PE01UTIL.017
The following computer program called PE01UTIL.017 contains assembly language routines executed by the PE CPU 82 to effect various different types of interprocessor communications between the PE 40 and the host personal computer
20.
**************************************************************
* peθlutil.017
CR = $0D ;Enter (Return)
EOS = $00 ;End Of String
ENQ = $05 ;prompt for input from Host
ACK = $06 acknowledges a Host Token execution NAK = $15 ;can't execute Token buffer = $100000 globl Dup,Mult,Functl globl H2PEhex,PE2Hhex,InitPE
* These subroutines are in Util globl PE2RX,PE2TX,ACKer,NAKer,ENQer,ClearbRAM,WritebRAM globl ReadbRAM globl SyncOn,SyncOff,XfrOff,XfrOn,DirR2S,DirS2R,PEXfrOn globl PEXfrOff globl RAM2SAM,SAM2RAM,Refs,Waits,BufIntOn,Words,RASMode globl TXRowL,RXRowL,BufLength,BufStart,BufIntPoll globl H2PEs,H2PEd,PE2Hs,PE2Hd
* in ios
* These assignments are in peOlpre globl HES_LSB,HES_MSB,HEB_LSB,HEB_MSB,HSBJSB,HSB_MSB globl HT_LSB,HT_MSB globl VES_LSB,VES_MSB,VEB_LSB,VEB_MSB,VSB_LSB,VSB_MSB globl VT_LSB,VT_MSB globl DU_LSB,DU_MSB,DS_LSB,DS_MSB,VI_LSB,VI_MSB globl CR1_LSB,CR1_MSB,CR2_LSB,CR2_MSB globl SR_LSB,SR_MSB,XYO_LSB,XY0_MSB,XYA_LSB,XYA_MSB globl DA_LSB,DA_MSB globl . VC_LSB,VC_MSB globl ctlreg,xyreg,ram2sam,sam2ram,dram,vram * These are in pio/sio globl H2PE,PE2H,ShowString
.even
VERSION dc.b ' peθlutil.017 ' DATE dc.b ' 07/21/90 '
.even ******************************************
* Set sync to "external" ****************************************** SyncOff: move.l #CRl_MSB,aO ;point to MSB crl move.w (a0),d0 ;get msb of crl or.w #$01,dO ;set bit 8 move.w dO, (aO) rts
******************************************
* Set Sync to "internal", VSYNC* & HSYNC* are genrated in * TMS34061
******************************************
SyncOn: move.l #CRl_MSB,aO ;point to MSB crl move.w (a0),d0 ;get msb of crl and.w #$FE,d0 ;clear bit 8 move.w d0,(a0) rts
**************************************** * Turn off PE-AutoTransfer function
****************************************
XfrOff: move.l #CRl_LSB,a0 ;point to LSB crl move.w (a0),d0 ;get lsb of crl or.w #$0020,dO ;set bit 5, SAM update off move.w d0,(a0) move.l #CR2_MSB,aO move.w (a0),d0 and.w #$00DF,d0 ;set bit 13 low move.w d0,(a0) bsr ACKer ; tell host everything is ok rts
**************************************** * Turn on PE-AutoTransfer function
****************************************
XfrOn: move.l #CRl_LSB,a0 ;point to LSB crl move.w (a0),d0 ;get lsb of crl and.w #$OODF,d0 ;clear bit 5, SAM update on move.w d0,(a0) move.l #CR2_MSB,aO move.w (a0),d0 or.w #$0020,dO ;set bit 13 high move.w d0,(a0) bsr ACKer ; tell host everything is ok rts
*********************************************
* Set PE AutoTransfer data direction to TX (bRAM2SAM) *********************************************
DirR2S: move.l #CRl_LSB,a0 ;point to LSB crl move.w (a0),d0 ;get lsb of crl and.w #$00BF,d0 ;clear bit 6, direction: RAM2SAM move.w dO, (aO) rts *********************************************
* Set PE AutoTransfer data direction to RX (SAM2bRAM) *********************************************
DirS2R: move.l #CRl_LSB,aO ;point to LSB crl move.w (a0),d0 ;get lsb of crl or.w #$0040,dO ;set bit 6, direction: SAM2RAM move.w d0,(a0) rts *********************************************
* Set PE-bRAMs to transmit mode ********************************************* RAM2SAM:
* Switch Buffers to send mode move.l #$230000,aO ; address of RAM2SAM operation move.w d0,(a0) ; dummy RAM2SAM rts
*********************************************
* Set PE-bRAMs to receive mode *********************************************
SAM2RAM: * Switch Buffer controls to Receive Mode move.l #$248000,aO ; address for PseudoSAM2RAM
* operation move.w d0,(a0) ; dummy (pseudo) SAM2RAM rts
******************************************
* Set Number of bRAM Refreshes ******************************************
Refs: move.l #CRl_MSB,a0 ;point to MSB crl move.w (a0),d0 ;get msb of crl and.w #$008F,dO ;clear previous value or.w #$0010,dO ;set to 1 move.w d0,(a0) rts
******************************************
* Set Number of bRAM Wait States to 1 ****************************************** Waits: . move.l #CR2_MSB,aO ;point to MSB cr2 move.w (aO) ,d0 and.w #$00F8,d0 ; clear bit 8, bit 9 and bit 10 * to 0 or.w #$0001,d0 ; set bit 8 to one move.w d0,(a0) rts ******************************************
* Set Display Update RAS mode ****************************************** * Set Host bRAM Controller for bank 0, only/ on auto-transfers
RASMode: move.l #CRl_LSB,aO ;point to MSB cr2 move.w (a0),d0 or.w #$0080,d0 ;set bit 7 on move.w d0,(a0) rts ******************************************
* Set PE-MC Buffer Interrupt On ******************************************
BuflntOn: move.l #CRl_MSB,aO move.w (a0),d0 or.w #$0004, O ;set bit 10 high move.w d0,(a0) rts ******************************************
* Set PE-MC to transfer words ******************************************
Words: move.l #DU_LSB,a0 move.w (a0),d0 or.w #$0004, O ; 0100 binary => 00 tap, 1 row
* per cycle move.w d0,(a0) * rts
******************************************
* Set Transmit Row Length to number of words in dO ******************************************
TXRowL: move.l #HSB_LSB,a0 ; point to lsb of HSB move.w #70, (aO) ; put it into LSB of Vert. Start
* Blank register move.l #HSB_MSB,a0 ; point to MSB of HSB register move.w #0,(a0) ; put byte there mo e.1 #HT_LSB,a0 move.w #78,(aO) ;#71,(a0) move.l #HT_MSB,a0 move.w #0,(a0) ; put it into MSB of register move.l #HES_LSB,a0 move.w #4,(a0) move.l #HES_MSB,a0 move.w #0,(a0) move.l #HEB_LSB,a0 move.w #6,(a0) move.l #HEB MSB,a0 move.w #0,(a0) rts ******************************************
* Set Receive Row Length to number of words in dO ******************************************
RXRowL: move.l #HSB_LSB,aO ; point to lsb of HSB move.w #73, (aO) ; put it into LSB of Vert.
Start * Blank register move.1 #HSB_MSB,aO ; point to MSB of HSB register move.w #0,(a0) ; put byte there move.1 #HT_LSB,aO move. #78, (aO) ;#71,(a0) move.1 #HT_MSB,aO move.w #0,(a0) put it into MSB of register move.l #HES_LSB,aO move.w #4,(a0) move.1 #HES_MSB,aO move.w #0,(a0) move.1 #HEB_LSB,aO move.w #9,(a0) move.1 #HEB_MSB,aO move.w #0,(a0) rts
******************************************
* Set Buffer Length to number of visible rows in d2
* NOTE: the VI register is set with same value ******************************************
BufLength: movem.l d0-d2/a0,-(a7) move.w d2,dl get length add.w #6,dl compute VSB * 262=256+5+2-1 move.l #VSB_LSB,a0 point to lsb of VSB move.w dl,(a0) move.l #VSB MSB,a0 point to MSB of Vert. Start Blank register lsr.l #8,dl move.w dl, (aO) put byte there move.w d2,dl get length again add.w #8,dl compute VT * 264=256+5+2+2-1 move.l #VT_LSB,a0 move.w dl,(a0) move.l #VT_MSB,aO lsr.l #8,dl move.w dl,(a0) put it into MSB of register move.l #VI_LSB,aO point to LSB Vertical Interrupt reg move.w d2,(a0) move.l #VI_MSB,aO ; point to MSB of Vert. Interrupt register lsr.l #8,d2 move.w d2, (aO) ; put byte into it also move.l #VES_LSB,aO ; Sync is 5 row cycles long
.move.w #4,(a0) move.l #VES_MSB,aO ; Front and back porch are 2 row * cycles long move.w #0,(a0) move.l #VEB_LSB,aO move.w #6,(a0) move.1 #VEB_MSB,a0 move.w #0,(a0) movem.l (a7)+,d0-d2/a0 rts
******************************************
* Set Start Row of Buffer Transfer ******************************************
Shift left 2 bit to allow for B0 and Bl = 0
Get the LSB of row number point to LSB of PE-MC register
Put it in DS_LSB get MSB of row number point to MSB of PE-MC register
Put it in DS MSB
Figure imgf000081_0001
******************************************
* Buffer Interrupt Poll ******************************************
BuflntPoll: move.l #SR_LSB,a0 ; point to LSB of PE-MC Status register move.w (a0),d0 ; get byte there and.w #$0001,dO ; strip out Buffer Interrupt, bit 0 bne bip if (bit NE 0) branch to bip clr.w dO else set dO FALSE rts and return bip: move.w #l,d0 set d0=TRUE rts and return
PE2HB1; rts ******************************************
H2PEs: * Get a 32 bit single float from Host I/O port in Hex format ****************************************** movem.l d0-d2,-(a7) ; push registers move.w #7,d2 ; 8 hex numbers => 32 bits
;get a hex character into dO ;clear parity and junk ;skip any nulls
;else, convert to upper case, if letter
; convert value in dO from hex to binary ; if error flag was set, goto error handler if larger than base was an error
Figure imgf000082_0001
shift previous 8 bit numbers up one byte add.l d0,dl ; add in new 8 bit number in lower byte bvs.s serror ; check for overflow error dbra d2,nxts sexit: move.l dl,-(a5) push float number into computational stack jsr ACKer tell host we got it movem.l (a7)+,d0-d2 pop registers rts serror move.l dl,-(a5) push into computational stack jsr NAKer tell Host we messed up movem.l (a7)+,d0-d2 pop registers rts
******************************************
H2PEd: ****************************************** jsr H2PEs ; push first 32 bits
•jsr H2PEs ; push second 32 bits rts ****************************************** PE2Hs: *Sends a hex string of 8 characters for a single float
* number ***************************** *************
; push registers
; pop registers
get the word from computational stack do top word first by converting and sending 4 hex digits now do bottom word by converting and sending
Figure imgf000083_0001
hex digits move.w dl,d2 save in temp ror.w #8,dl get upper byte to lower * location bsr.s PEx2 do upper byte move.w d2,dl get and do lower byte by converting and sending 2 hex digits do upper nibble by converting 1 nibble do lower nibble by converting and sending 1 hex character strip upper nibble convert to ASCII check for ASCII A thru F no, just send it yes, add bias
send to Host
Figure imgf000083_0002
******************************************
PE2Hd: ****************************************** jsr PE2Hs jsr PE2Hs rts
**************************************************************
H2PEhex: * read hex number from input port, return in dO ************************************************************** movem.l d0-dl,-(a7) push registers
;get a character into dO ;clear parity and junk
Figure imgf000083_0003
;skip any nulls if end of string quit else, convert to upper case, if letter
; convert value in dO from hex to binary if error flag was set, goto error handler ; if larger than base ; was an error
check for overflow error
Figure imgf000084_0001
nexit: push into computational stack ; tell host we got it ; pop registers
Figure imgf000084_0002
nerror move.l dl,d0 move.l d0,-(a5) push into computational stack jsr NAKer ; tell Host we messed up movem.l (a7)+,d0-dl ; pop registers rts
* Convert value in dO to hex hex2bin: sub.b #'0',d0 remove ASCII bias blt.s h2berror if less than 0, error cmp.b #9,dO if(dO LE 9) ble.s h2bok quit, we are done cmp.b #$11,dO if(do LT 'A' ) blt.s h2berror then error cmp.b #$16,dO if(dO GT 'F' ) bgt.s h2berror then error sub.b #7,dO else remove 'A' - 'F' bias h2bok: btst.l #7,dO ;set Z flag for OK h2berror: rts ;Z clear, error
**************************************************************
PE2Hhex: * PE sends 32 bit binary number as 8 hex characters to * Host
************************************************************** movem.l d0-d3,-(a7) ; push registers bsr.s PE2H8x
* move.w #EOS,d0 ; send EOS * jsr PE2H ; send to Host movem.l (a7)+,d0-d3 ; pop registers rts get the word from computational stack do top word first by converting and sending hex digits now do bottom word by converting and sending hex digits save in temp get upper byte to lower location do upper byte get and do lower byte by converting and sending hex digits do upper nibble by converting 1 nibble do lower nibble by converting and sending hex character strip upper nibble convert to ASCII check for ASCII A thru F no, just send it yes, add bias send to Host
Figure imgf000085_0001
*************************************************************
* WARNING: All functions following are returned after an ACK *******************************************
****************************************
* Function g: Turn off PE-AutoTransfer function ****************************************
PEXfrOff:
; push registers
;point to LSB crl
;get lsb of crl
;set bit 5, SAM update off
;set bit 13 low
; pop registers
; tell host everything is ok
Figure imgf000085_0002
****************************************
* Function h: Turn on PE-AutoTransfer function ****************************************
PEXfrOn: movem.l d0/a0,-(a7) ; push registers point to LSB crl
;get lsb of crl
;clear bit 5, SAM update on
set bit 13 high
; pop registers ; tell host everything is ok
Figure imgf000086_0001
************************************************************** PE2TX: * Function f: Host going to RX mode and calls this
* - function ************************************************************** movem.l d0-d3,-(a7) ; push registers
* Calculate number of rows to send bsr H2PE ; get starting row bsr PE2H ; echo
* bsr H2PEhex
* move.l (a5)+,d0 ; pop parameter and.l #$FF,d0 move.l d0,d2 bsr H2PE ; get Length in rows bsr PE2H ; echo
* bsr H2PEhex
* move.l (a5)+,d0 ; pop parameter and.l, #$FF,d0 move.w d0,d3
* Host should be the source of sync control. Therefore we
* assure that the * PE is set to "external sync" mode, bsr SyncOff
* Turn Off PE bRAM Controller AutoTransfer function
* bsr XfrOff ; done now by host function call bsr TXRowL
* Set PE-MC data direction to bRAM-to-SAM bsr DirR2S
* Set PE-MC to start transfer at StartRow move.w d2,d0 bsr BufStart * Set Buffer length to Length rows move.w d3,d2 bsr BufLength move.w #0,d0 ;Poll=FALSE; *TXAutol: * bsr BuflntPoll ;Poll=BufIntPoll( )
* beq TXAutol ;while(Poll EQ FALSE);
* bsr XfrOn ; done thru function call in host * code
* Second buffer interrupt should turn transfer off, here
;Poll=FALSE;
;Poll=BufIntPoll( )
;while(Poll EQ FALSE); tell host everything is ok ; pop registers
Figure imgf000087_0001
************************************************************
PE2RX: * Function e: Host to TX mode calls this function ************************************************************ movem.l d0-d3,-(a7) ; push registers * Calculate number of rows to send
; get StartRow ; echo
get Length in rows echo
Figure imgf000087_0002
PE is set to "slave sync" mode, bsr SyncOff
* Turn Off PE-MC Auto-Update function, in case it was left on * bsr XfrOff ; done in host code by function call bsr TXRowL ; new trial * Set PE-MC to SAM2RAM with PE Pseudo write cycle (receive mode) bsr SAM2RAM
* Se PE-MC data direction to Host-to-PE (SAM-to-bRAM) bsr DirS2R
* Set PE-MC to starting Row of transfer move.w d2,d0 bsr BufStart ; input buffer starting row
* Set Buffer Length move.w d3,d2 bsr BufLength * Start to Poll BufInt. If BufInt goes TRUE, turn On PE
* AutoTransfer function move.w #0,d0 ; Poll=FALSE; RXAutol:
* bsr BuflntPoll ; Poll=BufIntPoll( ) * beq RXAutol ; while(Poll EQ FALSE);
* bsr XfrOn ; done in function call from host
* Second interrupt here should turn transfer off : Poll=FALSE;
; Poll=BufIntPoll( ) : while(Poll EQ FALSE); : turn off autotransfer tell host every thing is ok ; pop registers
Figure imgf000088_0001
*******************************************
* Function a: Write zeros's into bRAM *******************************************
ClearbRAM:
* get Function Parameters here move.l #vram,a6 ; bRAM bank 0 address move.l #$FFFF,d2 ; loop count (clear entire memory) ClearLoop: clr.w (a6)+ move word into bRAM and bump pointer sub.w #l,d2 bne ClearLoop bsr ACKer rts
*******************************************
* Function b: Load data into bRAM *******************************************
WritebRAM: get number of rows to receive
; get starting chunk ; echo
get ending chunk ; echo
Figure imgf000088_0002
Compute bRAM address of rows sub.w d2,d3 compute number of chunks to load less 1 move.w d3,d0 add.w #l,d0
* bsr PE2H ; echo number of chunks to read
- 1 lsl.l #8,d2 put start chunk in MSB (row address) lsl.l #l,d2 to allow for byte addresses move.l #vram,a6 get bRAM bank 0 starting address and.l #$0001FF00,d2 ; make sure starting row address * is correct add.l d2,a6 ; compute bRAM starting address
* write for each row (number of rows - 1 is in d3) RowWLoop: * write each column in this chunk (row) move.w #$00FF,d4 dbra=Column loop count - 1 (256 16bit words)
; get MSB from host
; shift to upper 1/2 MSB of dO ; copy into d2 ; get LSB from host
Figure imgf000089_0001
; copy into lower 1/2 of d2 move.w d2,(a6)+ ; put word in d2 into bRAM, * bump pointer dbra d4,ColWLoop ; return for next column dbra d3,RowWLoop return for next row bsr ACKer rts
******************************************** * Function c: Read a block of bRAM data ********************************************
ReadbRAM:
* Calculate number of rows to send get starting row echo starting row
get ending row echo
Figure imgf000089_0002
* Compute bRAM address of rows sub.w d2,d3 compute number of rows to read * less 1 move.w d3,d0 add.w #l,d0 bsr PE2H echo number of rows to read
- 1 put start row in MSB (row address) to allow for byte addresses get bRAM bank 0 starting address ; make sure starting row is correct
Figure imgf000089_0003
; compute bRAM starting address
* read for each row (number of rows - 1 is in d3) RowRLoop:
* read each column in this row move.w #$00FF,d4 dbra=Column loop count - 1 * (256 words) ColRLoo : get word from bRAM to d2 copy into dO shift MSB send MSB to host get word again send LSB to host return for next column return for next row
Figure imgf000090_0001
**************************************************************
InitPE: ************************************************************** bsr SyncOff ; was SyncOn before 03/14/90 set number of refreshes to 7 bsr Refs * set number of wait states to 1 * move.w #l,d0 bsr Waits set CRI bit 8 on bsr RASMode set PE-MC for 256 word rows move.l #256,dO bsr RXRowL set PE-MC Buffer Interrupt On bsr BuflntOn
* Set PE-MC to transfer 1 row per cycle bsr Words
* Set PE to RX mode initially with a pseudo SAM2RAM cycle bsr SAM2RAM
* clear bRAM move.1 #vram,a6 ; bRAM bank 0 address move.1 #$FFFF,d2 ; loop count (clear entire * memory)
BuffClear: clr.w (a6)+ move word into bRAM and bump * pointer sub.w #l,d2 bne BuffClear rts ShowBuffer: move.l #vram,a6 ; bRAM bank 0 address move.w #$0FFF,d3 ; loop count - 1 (16 rows of 256 words ) get word from PE-RAM to d2 copy into dO shift MSB to lower byte send MSB to host get word again send LSB to host
send host an enq signal
send host an acknowledge signal
send host a not acknowledged signal ; e.g., not implemented yet
Figure imgf000091_0001
ENQmsg: dc.b ENQ,EOS ;prompt for input from Host ACKmsg: dc.b ACK,EOS acknowledges a Host Token execution NAKmsg: dc.b NAK,EOS ;can't execute Token end
FUNCTION. C
The following computer program called FUNCTION.C, that the CPU 22 of the host personal computer 20 executes, illustrates the use of the various functions provided by the routines in the program UTIL.C for exchanging data between the host personal computer 20 and the PE 40.
/*
FUNCTIONAL OPERATION PROCESSOR */
/* Formats */
#define BYTES 0x00 /* 8 bits int or char - not used here yet */ #define INTS 0x01 /* 16 bit int - (temp) use
Format code 0x03 */
#define LONGS 0x02 /* 32 bit long */ #define SINGLES 0x03 /* 32 bit single float */ #define DOUBLES 0x04 /* 64 bit double float */
/* PE System Ops */ #define NOP 0x00 /* not yet available */ #define LINPACK 0x64 /* PE Linpack Ops Current Usage */
#define AXPY1 0x01 /* (rolled) use SINGLES format only
*/
#define DOT 0x02 /* use SINGLES format only */
#define SCAL 0x03 /* use SINGLES format only */ #define ISAMAX 0x04 /* use SINGLES format only */
#define AXPY2 OxOB /* (unrolled) use SINGLES format only */
#define GESL OxOC /* use SINGLES format only */ #define GEFA OxOD /* use SINGLES format only */
/* PE test Ops */ #define SC TEST OxOA /* use INTS format only */ /* for now, use Linpack System Ops to get to this */
#include <math.h> #include <conio.h> #include <ctype.h> #include <stdio.h> #include <string.h> #include <stdlib.h> #include "util.h" #include "style.h" extern int IOMode; void UpdatePtrs( ); long pe bytes required; /* used by init_write_pe( ) , */ /* wri.te_pe long(), term write pe()
V
/* etc */ int pace_sgefa(float **A, int m, int n, int *ipvt, BufPnt_t *pnt) int Signal,Status,answer; int PE=0x300; unsigned long N; unsigned long Address_A,Address_i; long info; static long pivots[200]; int key,i,Unit=2;
ClearH(); /* clear host buffer */
ClearPE(PE); /* clear old data - maybe not reqd
V N=(unsigned long)(n);
/* convert pivot vector to longs */ for (i=0;i<n;++i) pivots[i]=ipvt[i]; /* Convert PC-AT SEG/OFF addresses to linear 24 bit addresses */ Address_A=HostAddress((void *) (*A)); Address_i=HostAddress((void *)pivots); /* Move matrix A from SMEM to XMEM */
X_Move(Address_A,pnt->Hbuf_A,pnt->Offset_A,Unit);
/* Show what is in host buffer before transfer? */ answer=question("\nSGEFA: Show contents of Host Buffer before Xfr"); if(answer EQ YES) DumpH(0,35);
/* Transfer Host buffer to PE buffer */ Status = Host2TX(PE,0,255,0,255); if (Status EQ FALSE) PEError(5); H2PEXfr(ON); Delay(6L); H2PEXfr(OFF); UpdatePtrs(pnt);
/* Show PE buffer A after transfer? */ answer=question("\nSGEFA: Show contents of PE buffer before computation"); if(answer EQ YES) DumpPE(PE,0,35);
/* Wait for PE ENQ (PE request to start operation) */ Signal=CheckPE(PE); if(Signal NE ENQ) PEError(6); /* something is wrong with
PE */
/* Send PE Linpack math setup request */ Signal=LINPACK; H2PE(PE,Signal);
Status=PE2H(PE) ; * /* get signal echo back
V if(Status NE Signal) PEError(7); /* something is wrong with PE */
/* The following data is sent to PE by the I/O port */
/* Send "GEFA" Token */ if(H2PE_B2H(PE, GEFA) EQ FALSE) PEError(8);
/* Send Data Format code: */ if(H2PE_B2H(PE,SINGLES) EQ FALSE) PEError(8); /* Send matrix size, N, twice */ if(H2PE_B2H(PE,n) EQ FALSE) PEError(8); if(H2PE_B2H(PE,n) EQ FALSE) PEError(8);
/* Send Address of matrix A */ if(H2PE_LB2H(PE,pnt->PEbuf_A) EQ FALSE) PEError(ll);
/* Send Address for pointers into A */ if(H2PE_LB2H(PE,pnt->PEbuf_p) EQ FALSE) PEError(ll); /* Send Address for pivot vector */ if(H2PE_LB2H(PE,pnt->PEbuf_i) EQ FALSE) PEError(ll);
/* PE computation starts automatic after last parameter is entered) */
/* get "info" from PE */
Status=PE2H_H2L(PE,&info) ; if(Status EQ FALSE) PEError(12); /* Wait for PE ACK indicating computation is done */ Signal = CheckPE(PE); if (Signal != ACK)
PEError(12); /* something went wrong with
PE */ answer=question( "\nSGEFA: Show contents of PE buffer after computation") ; if(answer EQ YES) DumpPE(PE,0,36) ; /* Transfer PE buffer A to Host buffer A */
Status=Host2RX(PE,0,255,0,255); if(Status == FALSE) PEError(13);
PE2HXfr(ON);
Delay(6L); PE2HXfr(OFF) ;
UpdatePtrs(pnt) ; answer=question("\nSGEfA: Show contents of Host buffer after transfer of results"); if(answer EQ YES) DumpH(0,35);
/* get data back into Host SMem from Host XMem */ X_Move (pnt->Hbuf_A,Address_A,pnt->Offset_A,Unit ) ; X_Move (pnt->Hbuf_i ,Address_i ,pnt->Offset_i , Unit ) ; for (i=0;i<n;++i) ipvt[i]=(int)pivots[i]; return (int)info; } void pace_sgesl
(float **A,int m,int n,int *ipvt,float *b,int Job,BufPnt_t *pnt)
{ int Signal,Status,answer; int PE=0x300; /* 10 port address of PE number
0 */ unsigned long Address_A,Address_i,Address_b,N; int key; static long pivots[200]; int i, Unit=2; N=(unsigned long)(n);
/* Convert PC-AT SEG/OFF addresses to linear 24 bit addresses */ Address_A=HostAddress( (void *)(*A)); Address_i=HostAddress((void *)pivots); Address_b=HostAddress( (void *)b);
/* convert pivot vector to longs */ for (i=0;i<^n;++i) pi ots[i]=ipvt[i];
/* move pivot vector b */
X_Move(Address_b, pnt->Hbuf_b,pnt->Offset_b,Unit) ;
/* Show what is in host buffer before transfer? */ answer=question("\nSGESL: Show contents of Host Buffer before Xfr"); if(answer EQ YES) DumpH(0,35);
/* Transfer Host buffer A to PE buffer A */ Status=Host2TX(PE,0,255,0,255); if(Status EQ FALSE) PEError(5);
H2PEXfr(ON);
Delay(lOL);
H2PEXfr(OFF); UpdatePtrs(pnt);
/* Show PE buffer A after transfer? */ answer=question("\nSGESL: Show contents of PE buffer before computation"); if(answer EQ YES) DumpPE(PE,0,35);
/* Wait for PE ENQ (PE request to start operation) */ Signal=CheckPE(PE) ; if(Signal NE ENQ) PEError(6); /* something is wrong with PE */
/* Send PE Linpack math setup request */ Signal=LINPACK; H2PE(PE,Signal) ;
Status=PE2H(PE) ; /* get signal echo back */ if(Status NE Signal) PEError(7); /* something is wrong with PE */
/* The following data is sent to PE by the I/O port */
/* Send "GESL" Token */ if(H2PE_B2H(PE,GESL) EQ FALSE) PEError(8);
/* Send Data Format code */ if(H2PE_B2H(PE,SINGLES) EQ FALSE) PEError(8); /* Send matrix size, N, twice */ if(H2PE_B2H(PE,n) EQ FALSE) PEError(8); if(H2PE_B2H(PE,n) EQ FALSE) PEError(8);
/* Send Address of matrix A */ if(H2PE_LB2H(PE,pnt->PEbuf_A) EQ FALSE) PEError(ll);
/* Send Address for pointers into A */ if(H2PE_LB2H(PE,pnt->PEbuf_p) EQ FALSE) PEError(ll); /* Send Address for pivot vector */ if(H2PE_LB2H(PE,pnt->PEbuf_i) EQ FALSE) PEError(ll);
/* Send Address for b vector */ if(H2PE_LB2H(PE,pnt->PEbuf_b) EQ FALSE) PEError(ll);
/* Send Job index */ if(H2PE B2H(PE,Job) EQ FALSE) PEError(11) ; ;
/* PE computation starts automatic after last parameter is entered) */
/* Wait for PE ACK indicating computation is done */ Signal=CheckPE(PE) ; if(Signal NE ACK) PEError(12); /* something went wrong with PE */ answer=question("\nSGESL: Show contents of PE buffer after computation") ; if(answer EQ YES) DumpPE(PE,0,35) ;
/* Transfer PE buffer to Host buffer */
Status=Host2RX(PE,0,255,0,255) ; if(Status EQ FALSE) PEError(13);
PE2HXfr(ON); Delay(lOL);
PE2HXfr(OFF);
UpdatePtrs(pnt) ; answer=question("\nSGESL: Show contents of Host buffer after transfer of results"); if(answer EQ YES) DumpH(0,35); X_Move(pnt->Hbuf_b,Address_b,pnt->Offset_b,Unit);
/* end of sgesl */
void UpdatePtrs(pnt) BufPnt t *pnt;
{ unsigned long XOffset=0x202; pnt->PEbuf_A+=XOffset; pnt->PEbuf_p+=XOffset; pnt->PEbuf_i+=XOffset; pnt->PEbuf_b+=XOffset; pnt->Hbuf_A +=XOffset; pnt->Hbuf_p +=XOffset pnt->Hbuf_i +=XOffset; pnt->Hbuf b +=XOffset; } BufPnt t *BufAlloc(int n)
{
BufPnt_t *pnt; unsigned long HBuf, PEBuf, Offset_A, Offset_p, Offset_i,
Offset_b; unsigned long N,Chunks_A, Chunks_p, Chunks_i, Chunks_b;
N=(unsigned long)(n);
/* The following 32 bit addresses point to the start of each buffer */ HBuf = 0x00500000; PEBuf= 0x00300000;
/* Calculate byte offset for matrix A and vectors i and p */ pnt->Offset_A=4*N*N; pnt->Offset_p=4*N; pnt->Offset_i=4*N; pnt->Offset_b=4*N;
/* Setup PE addresses for matrix A, vector p and vector i in buffer */
Chunks_A=(pnt->Offset_A/512)+1;
Chunks_p=(pnt->Offset_p/512)+1; Chunks_i=(pnt->Offset_i/512)+l;
Chunks_b=(pnt->Offset_b/512)+1;
Figure imgf000097_0001
pnt->Hbuf_A=HBuf; pnt->Hbuf_p=pnt->Hbuf_A+Chunks_A*512 pnt->Hbuf_i=pnt->Hbuf_p+Chunks_p*512 pnt->Hbuf_b=pnt->Hbuf_i+Chunks_b*512 return(pnt); } float port_smatgen(int n, float *b) float norma; int i, j; unsigned int init; float a; long start_row; long num_rows; long end_row; int key; int PE; PE = 0x300; start_row = 1; num_rows = ((long)n * (long)n * (long)sizeof(float) + 511) / 512; end_row = start_row + num_rows - 1; if ( !init_write_pe(PE, (int)start_row, (int)end_row) ) return 0; init = 1325; norma = (float)0.0; if (b) for (i = 0; i < n; i++) b[i] = (float)0.0; for (j = 0; j < n; j++) { /* column */ for (i = 0; i < n; i++) { /* row */ init = 3125 * init; a = {(float)init - 32768.0) / 16384.0; norma = MAX(a, norma); if (b) b[i] += a; if ( !write_pe_long(PE, *(unsigned long *)&a)) return 0;
} } if ( !term_write_pe(PE) ) return 0; if (b) { start_row = end_row + 1; num_rows = ((long)n * (long)sizeof(float) + 511) / 512; end_row = start_row + num_rows - 1; if ( !init_write_pe(PE, (int)start_row, (int)end_row) ) return 0; for (i = 0; i < n; ++i) if ( !write_pe_long(PE, *(unsigned long *)&b[i])) return 0; if ( !term_write_pe(PE) ) return 0;
} return norma;
int port sgefa(int n)
{ int Signal, Status; int PE; /* 10 port address of PE number
0 */ unsigned long PEStrt_a; /* 24 bit PE bRAM (buffer) strt adrs */ unsigned long PEStrt_b; /* 24 bit PE bRAM (buffer) strt adrs */ unsigned long PEStrt_p; /* 24 bit PE bRAM (buffer) strt adrs */ unsigned long PEStrt i; /* 24 bit PE bRAM (buffer) strt adrs */ unsigned long HBufA, HBufB, PEBufA, PEBufB; long info; int key; long row;
PE = 0x300;
/* The following 32 bit addresses point to the start of each buffer */ HBufA = 0x500000; /* PE installed */ PEBufA = 0x00300000;
/* Setup PE addresses in PE Buffer */ row = 1; PEStrt_a = PEBufA + row * 512; row += (((long)n * (long)n * (long)sizeof(float) + 511) / 512);
PEStrt_b = PEBufA + row * 512; row += (((long)n * (long)sizeof(float) + 511) / 512); PEStrt_p = PEBufA + row * 512; row += (((long)n * (long)sizeof(void *) + 511) / 512);
PEStrt_i = PEBufA + row * 512; row += (((long)n * (long)sizeof(long) + 511) / 512); /* Show PE buffer A after transfer? */
DEBUG_PROMPT("port_sgefa: Show PE Buffer before computation (Y/N) : ", key); if (key) DumpPE(PE, 0, (int)row);
/* Wait for PE ENQ (PE request to start operation) */ Signal = CheckPE(PE); if (Signal != ENQ) PEError(6); /* something is wrong with PE
*/
/* Send PE Linpack math setup request */ Signal = LINPACK; if (H2PE(PE, Signal) == -1)
PEError(7); /* something is wrong with PE
V Status = PE2H(PE); /* get signal echo back */ if (Status != Signal) PEError(7); /* something is wrong with PE */
/* The following data is sent to PE by the I/O port */ /* Send "GEFA" Token
NOTE: this is the token for Rolled version of Saxpy */ if (H2PE_B2H(PE, GEFA) == FALSE)
PEError(8);
/* Send Data Format code: */ if (H2PE_B2H(PE, SINGLES) == FALSE)
PEError(8) ; /* Send matrix size, N, twice */ if(H2PE_B2H(PE,n) EQ FALSE) PEError(8); if(H2PE_B2H(PE,n) EQ FALSE) PEError(8);
/* Send Address of matrix a */ if (H2PE_LB2H(PE, PEStrt_a) == FALSE) PEError(11);
/* Send Address for pointers into a */ if (H2PE_LB2H(PE, PEStrt_p) == FALSE) PEError(11); /* Send Address for pivot vector */ if (H2PE_LB2H(PE, PEStrt_i) == FALSE) PEError(ll);
/* PE computation starts automatic after last parameter is entered) */ /* wait for PE to complete operation */ while (PE DAWait(PE) == 0);
/* get "info" from PE */ if ( !PE2H_H2L(PE, &info)) PEError(16);
/* Wait for PE ACK indicating computation is done */
Signal = CheckPE(PE); if (Signal != ACK) PEError(12); /* something went wrong with PE */ return (int)info;
}
?ort_sgesl_term(int n, float *b) int PE=0x300; /* 10 port address of PE number
0 */ port_svecget(n, b);
int port_svecget(int n, float *b) long start_row; long num_rows; long end_row; int PE; int i;
PE = 0x300; start"_row = 1 + ((long)n * (long)n * (long)sizeof(float) + 511) / 512; num rows = {(long)n * (long)sizeof(float) + 511) / 512; end_row = start_row + num_rows - 1; if ( !init_read_pe(PE, (int)start_row, (int)end_row) ) return 0; for (i = 0; i < n; ++i) 5 if ( !read_pe_long(PE, (unsigned long *)&b[i])) return 0; if ( !term_read_pe(PE) ) return 0; return 1; 10 } void port_sgefa_init(int n, float *b) int PE=0x300; /* 10 port address of PE number
15 0 */
ClearPE(PE); /* clear old data - maybe not reqd */
ClearH(); /* clear host buffer */
20 /* - not really necessary */ port_smatgen(n, b); /* generate matrix and vector on PE
*/
25 void port_sgesl(int n, int job) int Signal, Status; unsigned long PEStrt_a; /* 24 bit PE bRAM (buffer) strt
30 adrs */ unsigned long PEStrt_p; /* 24 bit PE bRAM (buffer) strt adrs */ unsigned long PEStrt_i; /* 24 bit PE bRAM (buffer) strt adrs */
35 unsigned long PEStrt_b; /* 24 bit PE bRAM (buffer) strt adrs */ unsigned long HStart_b; /* 24 bit Host XMEM (buff) strt adrs */ unsigned long HBufA, HBufB, PEBufA, PEBufB;
40 int key; long row; int dummy; int PE=0x300;
45 /* The following 32 bit addresses point to the start of each buffer */
HBufA = 0x500000 /* PE installed */ PEBufA = 0x00300000 PEBufB = 0x00310202
50
/* Setup PE addresses in PE Buffer */ row = 1;
PEStrt_a = PEBufA + row * 512; row += (((long)n * (long)n * (long)sizeof(float) + 511) / 55 512);
PEStrt_b = PEBufA + row * 512; row += (((long)n * (long)sizeof(float) + 511) / 512); PEStrt_p = PEBufA + row * 512;* row += (((long)n * (long)sizeof(void *) + 511) / 512); PEStrt_i = PEBufA + row * 512; row += (((long)n * (long)sizeof(long) + 511) / 512);
/* Wait for PE ENQ (PE request to start operation) */ Signal = CheckPE(PE); if (Signal != ENQ)
PEError(6); /* something is wrong with PE */
/* Send PE Linpack math setup request */
Signal = LINPACK; if (H2PE(PE, Signal) == -1)
PEError(7); /* something is wrong with PE */ Status = PE2H(PE); /* get signal echo back */ if (Status != Signal)
PEError(7); /* something is wrong with PE
*/ /* The following data is sent to PE by the I/O port */ /* Send "GESL" Token
NOTE: this is the token for Rolled version of Saxpy */ if (H2PE_B2H(PE, GESL) == FALSE) PEError(8) ;
/* Send Data Format code: */ if (H2PE_B2H(PE, SINGLES) == FALSE) PEError(8) ; /* Send matrix size, N, twice */ if (H2PE_B2H(PE, n) == FALSE)
PEError(8); if (H2PE_B2H(PE, n) == FALSE) PEError(8) ;
/* Send Address of matrix a */ if (H2PE_LB2H(PE, PEStrt_a) == FALSE) PEError(11) ; /* Send Address for pointers into a */ if (H2PE_LB2H(PE, PEStrt_p) == FALSE) PEError(11);
/* Send Address for pivot vector */ if (H2PE_LB2H(PE, PEStrt_i) == FALSE) PEError(11) ;
/* Send Address for b vector */ if (H2PE_LB2H(PE, PEStrt_b) == FALSE) PEError(11);
/* Send job id code */ if (H2PE_B2H(PE, job) == FALSE) PEError(8) ;
/* PE computation starts automatic after last parameter is entered) */ - 101 -
/* Wait for PE ACK indicating computation is done */ Signal = CheckPE(PE); if (Signal != ACK) PEError(12); /* something went wrong with
PE */
} int init_write_pe(int PE, int StartRow, int EndRow) char Token; /* Token for writing dummy data
V int Data;
Status=CheckPE(PE) ; if(Status 1= ENQ) PEErrorf*); Status=H2PE(PE, Token); /* send selected Token */
/* send starting row number to PE */ Status=H2PE(PE, StartRow); /* send ending row number to PE */ Status=H2PE(PE, EndRow); pe_bytes_required=( (long)EndRow-(long)StartRow+1)*512; return TRUE; } int write_pe_long(int PE, unsigned long val) int Status; if (pe_bytes_required < 4) PEError(8); Status=H2PE(PE, (unsigned int) (val » 24)); Status=H2PE(PE, (unsigned int) (val » 16)); Status=H2PE(PE, (unsigned int) (val » 8)); Status=H2PE(PE, (unsigned int)(val)); pe_bytes_required -= 4; return TRUE; } int term_write_pe(int PE) int Status; for (; pe_bytes_required > 0; —pe_bytes_required) {
Status=H2PE(PE, 0); else Status=TRUE;
Display(PE); /* ACK */ return Status; int init_read_pe(int PE, int StartRow, int EndRow) char Token; /* Token for writing dummy data */ int Data; Token = 'c' ; Status=CheckPE(PE) if(Status 1= ENQ) error(8);
Status=H2PE(PE, Token); /* send selected Token */ Data = PE2H(PE); if (Data != Token) error(8);
/* send starting row number to PE */
Status=H2PE(PE, StartRow);
Data = PE2H(PE); if (Data != StartRow) Error(8);
/* send ending row number to PE */
Status=H2PE(PE, EndRow);
Data = PE2H(PE); if (Data != EndRow) error(8);
/* get number of rows to be sent */
Data = PE2H(PE); if (Data != (EndRow - StartRow + 1)) error(8); pe_bytes_required = ( (long)EndRow - (long)StartRow + 1) * 512; return TRUE; } int read_pe_long(int PE, unsigned long *pval) unsigned long temp; if (pe bytes required < 4) Error(8) temp = PE2H(PE); *pval = temp « 24; temp = PE2H(PE); *pval += (temp « 16); temp = PE2H(PE);
*pval += (temp « 8); temp = PE2H(PE); *p al += temp; pe_bytes_required -= 4; return TRUE; } int term_read_pe(int PE) { for (; pe_bytes_required > 0; —pe_bytes_required) PE2H(PE); - 103 -
Display(PE) ; /* ACK */ return TRUE;
PE01IOS.011
The following computer program called PE01IOS.011 contains assembly language routines executed by the PE CPU 82 in supervising the overall operation of the PE 40.
**************************************************************
* Name: PE01IOS.011 *
************************************************************** * Globals
************************************************************** globl iobase,stack,Command globl initio,H2PE,PE2H,NewLine,ShowString ; in peOlpio globl ram,CS,RS globl Cold,Status,Token globl HES_LSB, HES_MSB, HEB_LSB, HEB_MSB, HSB_LSB, HSB_MSB globl HT_LSB, HT_MSB globl VES_LSB, VES_MSB, VEB_LSB, VEB_MSB, VSB_LSB, VSB_MSB globl VT_LSB, VT_MSB globl DU_LSB,- DU_MSB, DS_LSB, DS_MSB, VI_LSB, VI_MSB globl CR1_LSB, CR1_MSB, CR2_LSB, CR2_MSB globl SR_LSB, SR_MSB, XYO_LSB, XY0_MSB, XYA_LSB, XYA_MSB globl DA_LSB, DA_MSB globl VC_LSB, VC_MSB globl ctlreg, xyreg, ram2sam, sam2ram, dram, vram
* Globl subroutines in UTIL globl SyncOn, SyncOff, XfrOff, XfrOn, DirR2S, DirS2R, PEXfrOn globl PEXfrOff globl RAM2SAM, SAM2RAM, Refs, Waits, BuflntOn, Words, RASMode globl TXRowL, RXRowL, BufLength, BufStart, BuflntPoll globl InitPE, ACKer, NAKer, ENQer
* Globl Functions, in UTIL globl ClearbRAM, WritebRAM, ReadbRAM, PE2TX, PE2RX
* Globl Functions, in MATH globl Functl ************************************************************** * Equates
**************************************************************
TRUE = 0
FALSE = 1 cr = $0D If = $0A eos = $00
Ctl_C = $03 eot = $00 crlf = $0D0A ENQ = $05 ;prompt for input from Host
ACK = $06 acknowledges a Host Token execution
NAK = $15 ;can't execute Token
EOS = $00 ;end of string .even VERSION dc.b PE023 ' DATE dc.b 06/12/90 .even * Status word contains these items
Mode 0 Bit 0 is Mode
State = 1 Bit 1 is State Result = 2 Bit 2 is result True=l, False=0 Hex 3 1 if Hex 0 if Decimal
* Register Usage: * aO is used for scratch, e.g., message pointers mainly * al is used at i/o base register * a2 is SRAM pointer (not used) * a3 is a pointer to the Function List * a4 is the code pointer * a5 * a6 is the bRAM pointer * a7 is stack pointer * dO carries data byte to and from pio module * dl carries status byte for pio module * d2 is used by ShowString * d3 is the token in list * d4 is the token commanded
* On RESET 68k comes here:
Cold:
init computational stack
Figure imgf000107_0001
init parallel i/o hardware clr.b intstate clear s/w state flags
Start: bsr ACKer ; display ACK to tell Host we are alive! move.l #signon,a0 bsr ShowString ; display ID, to tell who we are
; set registers etc. for RX
clear Status word e.g., Set Mode bit to 0 (execution
Set State bit to 0 Set Result to 0 (False) Set numeric base to Hex show request for Token Get token into dO
Figure imgf000107_0002
Echo it back move.b d0,d4 store token in safe register bsr.s Search ; Search for token in dictionary btst.b #Result,Status See what happened bne.s Execute if found. Execute token Error: * mode based patchup stuff here move.l #err,a0 else its an error bsr ShowString ; say so bra Command then abort and try again
Clear result point to top of list of commands get candidate compare to Token if the same quit search
Figure imgf000108_0001
else, bump over Tag to next
Token cmpa.l #ListEnd,a3 if not end of Token list bne.s SLoop continue to search bclr.b #Result,Status else, not found, set result
False rts and return Found: bset.b #Result,Status Set result true (found) rts and return
Execute: adda.l #l,a3 ; point to where address of function lies movea.1 (a3),a4 ; get address there
Dsr (a4) then use it to go and execute the code bra.s Command ; get next command token srch; dc.b 'Searching for Token' ,cr,If,eos ex: dc.b 1Executing Token' ,cr,If,eos err: dc.b 'Token not in List' ,cr,lf,eos
.even
List: dc.b 'a' del ClearbRAM Clear bRAM dc.b 'b' del WritebRAM Write dummy data into bRAM dc.b 'c' del ReadbRAM Read a block of bRAM data dc.b 'd' del Functl Do math dc.b del PE2RX Switch PE to receive mode deb del PE2TX ; Switch PE to transmit mode dc.b •g- del PEXfrOff ; Switch off PE auto update dc.b 'h' del PEXfrOn ; Switch on PE auto update
ListEnd: deb 0 .even signon: deb ' PE-IOS version 023, 06/12/90 use with: PACE ',cr,lf dc.b ' Copyright (c) 1989, 1990 CELTEK,Ine', cr,lf,eos
.even .end
Industrial Applicability
While the first multi-port VRAM 44 is primarily intended to be used in transmitting data between the host personal computer 20 and the PE CPU 82, when the PE 40 is not being used to perform computations, the first multi-port VRAM 44 is available to the personal computer 20 to be used in the same manner as any extended memory installed in an IBM PC AT.
While the Motorola MC68020 and MC68882 are presently preferred respectively for the PE CPU 82 and the PE FPU 84, other types of microprocessors and floating point units might be used in a PE 40 in accordance with the present invention. Accordingly, it is within the concept of this invention to use other microprocessors such as the Motorola MC68030, MC68040, MC88100, MC88200 and 96002 DSP, the Intel i80960, the SGS- Thomson INMOS T800, the Intergraph Clipper, or the Advanced Micro Devices 29K. Because of each processor's unique characteristics, selection of one of these alternative types of microprocessors for use in a PE 40 in accordance with the present invention could compel certain minor design changes. For example, if a Motorola MC68040 were chosen for the PE CPU 74, then the PE 40 could omit all FPUs 68 because Motorola's MC68040 includes a FPU.
While the IBM PC AT is the presently preferred host personal computer 20 for the PE 40, a PE 40 in accordance with the present invention may be constructed for use with many other different types of presently existing digital computers including IBM PC clones using either the ISA or EISA bus, the IBM P/S2, Sun digital computers and Digital Equipment Corporation ("DEC") computers. While the presently preferred embodiment of the program memory 94b is an EPROM memory, a PE 40 in accordance with the present invention may used other types of memories for the program memory 94b including EEPROM integrated circuits such as "FLASH" EEPROMs.
Although the present invention has been described in terms of the presently preferred embodiment, it is to be understood that such disclosure is purely illustrative and is not to be interpreted as limiting. Consequently, without departing from the spirit and scope of the invention, various alterations, modifications, and/or alternative applications of the invention will, no doubt, be suggested to those skilled in the art after having read the preceding disclosure. Accordingly, it is intended that the following claims be interpreted as encompassing all alterations, modifications, or alternative applications as fall within the true spirit and scope of the invention.

Claims

The ClaimsWhat Is Claimed Is:
1. A processing element ("PE") for inclusion in a host computer to provide a multi-processor computing system, said host computer including a central processing unit ("host CPU"), a host memory into which data may be stored and from which data may be retrieved, and a host bus coupling said CPU of said host computer to said host memory for exchanging data between said host CPU and said host memory, said processing element comprising: a. a first PE memory having a plurality of memory ports, a host port of said first PE memory being adapted for exchanging data with said host bus; b. a second PE memory also having a plurality of memory ports; e an inter-memory bus coupling a shared port of said second PE memory to a shared port of said first PE memory, said inter-memory bus being adapted for exchanging data between said first PE memory and said second PE memory; d. a PE bus adapted for coupling a PE port of said second PE memory to a PE central processing unit ("PE CPU") and for exchanging data between said PE
CPU and said second PE memory; and e. memory control means for controlling exchanges of data between said host bus and said first PE memory, between said first PE memory and said second PE memory, and between said PE bus and said second PE memory, said PE control means controlling such exchanges of data in response to signals received from said host computer and from said PE bus, said first PE memory exchanging data with said host bus free from contention with memory exchanges occurring between said second PE memory and said PE bus and said second PE memory exchanging data with said PE bus free from contention with memory - Ill - exchanges occurring between said first PE memory and said host bus.
2. The PE of claim 1 further comprising register means for exchanging control signals between said host computer and said PE bus.
3. The PE of claim 1 further comprising register means for exchanging status signals between said host computer and said PE bus.
4. The PE of claim 1 further comprising register means for exchanging control and status signals between said host computer and said PE bus.
5. The PE of claim 1 wherein said first PE memory and said second PE memory are video ram integrated circuits.
6. The PE of claim 1 wherein said first PE memory operates in response to signals from said second PE memory for exchanging data between said first PE memory and said second PE memory over said inter-memory bus.
7. The PE of claim 1 wherein said second PE memory operates in response to signals from said first PE memory for exchanging data between said first PE memory and said second PE memory over said inter-memory bus.
8. The PE of claim 1 further comprising a PE CPU coupled to said PE bus for exchanging data with said second PE memory.
9. The PE of claim 8 further comprising a PE floating point unit ("PE FPU") which processes data present in said second PE memory in response to signals which said PE FPU receives from said PE CPU.
10. The PE of claim 9 further comprising register means for exchanging control and status signals between said host computer and said PE bus.
11. The PE of claim 10 further comprising a first additional memory for storing intermediate results produced by said PE CPU and a second additional memory for storing programs executed by said PE CPU.
12. The PE of claim 8 further comprising a plurality of PE floating point units ("PE FPUs") which processes data present in said second PE memory in response to signals which said PE FPUs receive from said PE CPU.
13. The PE of claim 8 further comprising another memory for storing intermediate results produced by said PE CPU.
14. The PE of claim 8 further comprising another memory for storing programs executed by said PE CPU.
15. The PE of claim 8 further comprising register means for exchanging control signals between said host computer and said PE bus.
16. The PE of claim 8 further comprising register means for exchanging status signals between said host computer and said PE bus.
17. The PE of claim 8 further comprising register means for exchanging control and status signals between said host computer and said PE bus.
18. A multi-processor computing system comprising: a. a host computer including: i. a central processing unit ("host CPU"); ii. a host memory into which data may be stored and from which data may be retrieved; and iii. a host bus coupling said CPU of said host computer to said host memory for exchanging data between said host CPU and said host memory; 5 b. a processing element ("PE") comprising: i. a first PE memory having a plurality of memory ports, a host port of said first PE memory being adapted for exchanging data with said host bus;
10 ii. a second PE memory also having a plurality of memory ports; iii. an inter-memory bus coupling a shared port of said second PE memory to a shared port of said first PE memory, said inter-memory bus being
15 adapted for exchanging data between said first
PE memory and said second PE memory; iv. a PE central processing unit ("PE CPU"); v. a PE bus for coupling a PE port of said second PE memory to said PE CPU and for exchanging
20 data between said PE CPU and said second PE memory; and vi. memory control means for controlling exchanges of data between said host bus and said first PE memory, between said first PE memory and
25 said second PE memory, and between said PE bus and said second PE memory, said PE control means controlling such exchanges of data in response to signals received from said host computer and from said PE bus, said first PE
30 memory exchanging data with said host bus free from contention with memory exchanges occurring between said second PE memory and said PE bus and said second PE memory exchanging data with said PE bus free from
35 contention with memory exchanges occurring between said first PE memory and said host bus.
19. The multi-processor computing system of claim 18 further comprising register means for exchanging control signals between said host computer and said PE bus.
20. The multi-processor computing system of claim 18 further comprising register means for exchanging status signals between said host computer and said PE bus.
21. The multi-processor computing system of claim 18 further comprising register means for exchanging control and status signals between said host computer and said PE bus.
22. The multi-processor computing system of claim 18 wherein said first PE memory and said second PE memory are video ram integrated circuits.
23. The multi-processor computing system of claim 18 wherein said first PE memory operates in response to signals from said second PE memory for exchanging data between said first PE memory and said second PE memory over said inter- memory bus.
24. The multi-processor computing system of claim 18 wherein said second PE memory operates in response to signals from said first PE memory for exchanging data between said first PE memory and said second PE memory over said inter- memory bus.
25. The multi-processor computing system of claim 18 further comprising a PE floating point unit ("PE FPU") which processes data present in said second PE memory in response to signals which said PE FPU receives from said PE CPU.
26. The multi-processor computing system of claim 25 further comprising register means for exchanging control and status signals between said host computer and said PE bus.
27. The multi-processor computing system of claim 26 further comprising a first additional memory for storing intermediate results produced by said PE CPU and a second additional memory for storing programs executed by said PE CPU.
28. The multi-processor computing system of claim 18 further comprising a plurality of PE floating point units ("PE FPUs") which processes data present in said second PE memory in response to signals which said PE FPUs receive from said PE CPU.
29. The multi-processor computing system of claim 18 further comprising another memory for storing intermediate results produced by said PE CPU.
30. The multi-processor computing system of claim 18 further comprising another memory for storing programs executed by said PE CPU.
PCT/US1990/004376 1990-08-06 1990-08-06 Processing element for a multi-processor digital computing system WO1992002885A1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1033722A2 (en) * 1999-02-12 2000-09-06 Hiroshima University Shared memory
US6563163B1 (en) 1999-05-18 2003-05-13 Hiroshima University Nonvolatile memory using deep level capture of carrier at corner structure of oxide film
WO2007149317A2 (en) * 2006-06-16 2007-12-27 Bono Vincent P Systems and methods for providing a personal computer with non-volatile system memory

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4570217A (en) * 1982-03-29 1986-02-11 Allen Bruce S Man machine interface

Patent Citations (1)

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Publication number Priority date Publication date Assignee Title
US4570217A (en) * 1982-03-29 1986-02-11 Allen Bruce S Man machine interface

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1033722A2 (en) * 1999-02-12 2000-09-06 Hiroshima University Shared memory
EP1033722A3 (en) * 1999-02-12 2001-05-23 Hiroshima University Shared memory
US6874068B1 (en) 1999-02-12 2005-03-29 Hiroshima University Shared memory
US6563163B1 (en) 1999-05-18 2003-05-13 Hiroshima University Nonvolatile memory using deep level capture of carrier at corner structure of oxide film
WO2007149317A2 (en) * 2006-06-16 2007-12-27 Bono Vincent P Systems and methods for providing a personal computer with non-volatile system memory
WO2007149317A3 (en) * 2006-06-16 2008-09-12 Vincent P Bono Systems and methods for providing a personal computer with non-volatile system memory
US7886099B2 (en) * 2006-06-16 2011-02-08 Superspeed Llc Systems and methods for providing a personal computer with non-volatile system memory

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