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WO1990005993A1 - Transistor a canal p submicronique de hautes performances, a implant de germanium - Google Patents

Transistor a canal p submicronique de hautes performances, a implant de germanium Download PDF

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Publication number
WO1990005993A1
WO1990005993A1 PCT/US1988/004155 US8804155W WO9005993A1 WO 1990005993 A1 WO1990005993 A1 WO 1990005993A1 US 8804155 W US8804155 W US 8804155W WO 9005993 A1 WO9005993 A1 WO 9005993A1
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WO
WIPO (PCT)
Prior art keywords
oxide
forming
implant
wafer
implanting
Prior art date
Application number
PCT/US1988/004155
Other languages
English (en)
Inventor
Ruojia R. Lee
Original Assignee
Micron Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology, Inc. filed Critical Micron Technology, Inc.
Priority to PCT/US1988/004155 priority Critical patent/WO1990005993A1/fr
Publication of WO1990005993A1 publication Critical patent/WO1990005993A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants

Definitions

  • This invention is related to semiconductor devices. Specifically it is related to high-performance sub-micron channel length P-channel MOS (metal-oxide-semiconductor) transistor (PMOS for short) for the Very Large Scale Integrated (VLSI) or the Ultra Large Scale Integrated (ULSI) circuits. It employs the use of Germanium implant into the channel regions of transistors to both pre-amorphize the channel surface to alleviate the channelling of subsequent enhancement implant required by threshold voltage Vt adjustment and to retard the diffusion of the boron dopants (from enhancement implant) in the region to form a very shallow enhancement implant profile.
  • PMOS metal-oxide-semiconductor
  • VLSI Very Large Scale Integrated
  • ULSI Ultra Large Scale Integrated
  • the invention uses various materials which are electrically either conductive, insulating or semiconducting, although the completed semiconductor circuit device itself is usually referred to as a "semiconductor".
  • One of the materials used is silicon, which is used as either single crystal silicon or as polycrystalline silicon material, referred to as polysilicon or "poly" in this disclosure.
  • P-CH sub-micron P-channel
  • the prior art relating to Germanium in VLSI devices has been in the area of (1 ) field isolation improvement and (2) transistor source/drain regions to achieve shallow source and drain junctions.
  • the former deals with device isolation and an improvement in electrical encroachment; yet it does not improve transistor performance; the later deals with device performance by means of achieving shallower source drain junction depths so that the reduction in charge-sharing effect would improve transistor short channel characteristics. It however does not solve or reduce P-channel transistor short channel effects caused by the very nature of buried channel behavior.
  • the present invention deals directly with PMOS buried channel characteristics by making the buried channel enhancement implant profile more shallow.
  • the shallow implant profile results in the P-CH device will have less or no buried channel characteristics. This avoids undesirable short channel effects, and therefore permits further reduction in the transistor channel length.
  • the shallow profile causes surface channel characteristics to be dominant.
  • Surface channel devices will have better short channel characteristics, i.e., higher punch through voltage
  • Implantation of germanium into the channel to permit the enhancement implant profile to be made shallower will reduce or event solve P-channel buried channel-induced short channel effects and enable further decrease in device length to deep sub-micron range.
  • the drawing Figures each show cross-sections of a portion of a semiconductor circuit device which utilizes the present invention.
  • Figure 1 shows growth of an initial gate oxide, patterning of active areas and channel stop implant
  • Figure 2 shows a LOCOS step
  • Figure 3 shows nitride strip and initial oxide strip
  • Figure 4 shows growth of sacrificial oxide and germanium implant
  • Figure 5 shows V ⁇ enhancement implant and sacrificial oxide strip
  • Figure 6 shows final gate oxide growth, gate polysilicon deposition and phosphorus deposition
  • Figure 7 shows " transistor gate definition and lightly doped source/drain BF_ implant
  • Figure 8 shows spacer formation and heavy source/drain BF- implant
  • Figure 9 shows source/drain activation.
  • Figure 1 shows a cross-section of a semiconductor circuit during its fabrication.
  • a silicon wafer 13 is prepared by forming a thin film of oxide 15 and then depositing nitride 17 over the thin oxide 15. The nitride is masked and etched in order to define active area (31, Fig. 3). The unmasked portions of the wafer 13 are then implanted with boron in order to increase parasitic field transistor threshold voltage V .
  • a thick layer of silicon oxide 21 is grown onto the wafer 13 to form field ox, as shown in Figure 2.
  • the growth of silicon oxide occurs in areas which are not covered by the nitride mask 17, but tends to encroach on the active area, marked AA.
  • the encroachment is present around the edges of the nitride 17, as indicated by dashed lines 23, where the oxide 21 begins to "buck up" or lift the nitride 17.
  • the nitride 17 is then stripped and the wafer 13 is oxide etched in order to remove a top portion 41 of the field ox 21 , as shown in Figure 3. This reduces the encroachment of the silicon oxide 21 into the active area 31 by reducing the thickness of the field oxide 21 in the regions of encroachment.
  • This stripping of the top layer referred to as dilute buffered hydrofluoric acid wet oxide etch, is timed to remove a pre-determined- fraction of the field oxide.
  • the reduced thickness of the field oxide 21 adjacent to the active area 31 establishes an active parasitic MOS transistor device in the completed wafer. This parasitic MOS transistor device could result in shunting between adjacent active areas 31.
  • a germanium implant is applied to the wafer by ion implantation, as shown in Figure 4.
  • Any of various sources of germanium may be used, such as GeF. gas.
  • a preferred method for implanting the germanium is by ion implantation.
  • the germanium does not pass through the thick fieldox 21, but does penetrate the wafer 13 where the oxide 41 has been stripped (shown in Fig. 3).
  • the germanium is allowed to penetrate to a level indicated by the dashed line by controlling implant energy, as well as other factors including temperature. This forms a germanium layer 45 to the depth of the dashed line.
  • the germanium layer 45 is used to reduce P- channel transistor buried channel effects by reducing counter-doping junction depth. A reduction in counter doping junction depths will, in turn, reduce short channel effects in the completed transistor. This also pre-amorphizes the channel surface in order to alleviate channeling of subsequent enhancement implant with boron.
  • Figure 4 also shows the addition of a sacrificial layer 47 of oxide which is grown on to the wafer 13 after the germanium implant. Subsequent to the growth of the sacrificial layer, a boron implant is applied. The boron is able to penetrate the thin sacrificial layer 47 in order to permit control of V of the transistors.
  • the boron dopants diffuse into the wafer 13, but this diffusion remains very shallow as a result of the earlier implant of the germanium. This results in the germanium layer 45 being doped with the boron, and the infusion of the boron being largely confined to the germanium layer 45.
  • the sacrificial oxide 47 is stripped and a final gate oxide 49 is grown to improve gate oxide quality.
  • BF_ may be used instead of boron in the boron implant steps in order to provide the boron implant.
  • a layer of polysilicon 55 is applied to the substrate 13 and, as a result of the final gate oxide 53, remains isolated from the boron doped germanium implant layer 45.
  • This layer of polysilicon 55 forms the gates to transistors formed with the boron doped germanium layer 45, so that the boron doped germanium layer 45 forms source and drain regions.
  • phosphorus deposition is applied to establish the polysilicon layer 55 as N+ type polysilicon.
  • the wafer is masked in order to define the transistor gate.
  • the definition of the transistor gates is accomplished by etching the N+ polysilicon in order to form gate portions 61 of the transistors.
  • a lightly doped source and drain implant is applied by using BF_- as an implant aterial. This results in a lightly doped source drain profile 63 as shown in Figure 8.
  • a spacer oxide 65 is grown from the transistor gate 61 , followed by a heavy source/drain BF- implant.
  • the heavy source/drain BF profession implant results in the profile 73 of P+ areas shown in Figure 9.
  • the germanium implant earlier also reduces the diffusion of both P+ and P- and makes it possible to have shallower P+ and P- junctions.
  • heavy germanium impurity in the N- channel devices can increase impact ionization rate and therefore make it easier to program in EPROMs by avalanching hot electrons.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention concerne l'implantation de germanium (45) dans un MOS à canal P noyé permettant d'améliorer un profil d'implant (45) à rendre moins profond. Le profil peu profiond réduit ou éventuellement élimine les effets de canaux courts induits par des canaux noyés dans des canaux P, et permet de diminuer davantage la longueur du dispositif à une plage submicronique profonde. Entre autres avantages on distingue de meilleures caractéristiques de canaux courts, c'est-à-dire une tension de pénétration BVDSS supérieure, moins de sensibilité VT à la tension de drain (définie comme vecteur tourbillon), ainsi que de meilleures caractéristiques de fuite de seuil inférieur.
PCT/US1988/004155 1988-11-21 1988-11-21 Transistor a canal p submicronique de hautes performances, a implant de germanium WO1990005993A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US1988/004155 WO1990005993A1 (fr) 1988-11-21 1988-11-21 Transistor a canal p submicronique de hautes performances, a implant de germanium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1988/004155 WO1990005993A1 (fr) 1988-11-21 1988-11-21 Transistor a canal p submicronique de hautes performances, a implant de germanium

Publications (1)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0536869A2 (fr) * 1991-06-05 1993-04-14 National Semiconductor Corporation Méthode de fabrication de couches enterrées de type P pour des dispositifs PNP
US5266510A (en) * 1990-08-09 1993-11-30 Micron Technology, Inc. High performance sub-micron p-channel transistor with germanium implant
WO1999057759A1 (fr) * 1998-05-05 1999-11-11 Aeroflex Utmc Microelectronic Systems Inc. Procede de fabrication d'un dispositif semiconducteur rendu resistant aux radiations, comportant des zones actives et des zones isolantes
US6432791B1 (en) * 1999-04-14 2002-08-13 Texas Instruments Incorporated Integrated circuit capacitor and method

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4352236A (en) * 1981-07-24 1982-10-05 Intel Corporation Double field oxidation process
US4366613A (en) * 1980-12-17 1983-01-04 Ibm Corporation Method of fabricating an MOS dynamic RAM with lightly doped drain
US4413401A (en) * 1979-07-23 1983-11-08 National Semiconductor Corporation Method for making a semiconductor capacitor
US4536947A (en) * 1983-07-14 1985-08-27 Intel Corporation CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors
US4617066A (en) * 1984-11-26 1986-10-14 Hughes Aircraft Company Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing
US4728619A (en) * 1987-06-19 1988-03-01 Motorola, Inc. Field implant process for CMOS using germanium
US4764477A (en) * 1987-04-06 1988-08-16 Motorola, Inc. CMOS process flow with small gate geometry LDO N-channel transistors
US4791610A (en) * 1985-05-24 1988-12-13 Fujitsu Limited Semiconductor memory device formed of a SOI-type transistor and a capacitor

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4413401A (en) * 1979-07-23 1983-11-08 National Semiconductor Corporation Method for making a semiconductor capacitor
US4366613A (en) * 1980-12-17 1983-01-04 Ibm Corporation Method of fabricating an MOS dynamic RAM with lightly doped drain
US4352236A (en) * 1981-07-24 1982-10-05 Intel Corporation Double field oxidation process
US4536947A (en) * 1983-07-14 1985-08-27 Intel Corporation CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors
US4617066A (en) * 1984-11-26 1986-10-14 Hughes Aircraft Company Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing
US4791610A (en) * 1985-05-24 1988-12-13 Fujitsu Limited Semiconductor memory device formed of a SOI-type transistor and a capacitor
US4764477A (en) * 1987-04-06 1988-08-16 Motorola, Inc. CMOS process flow with small gate geometry LDO N-channel transistors
US4728619A (en) * 1987-06-19 1988-03-01 Motorola, Inc. Field implant process for CMOS using germanium

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5266510A (en) * 1990-08-09 1993-11-30 Micron Technology, Inc. High performance sub-micron p-channel transistor with germanium implant
USRE37158E1 (en) * 1990-08-09 2001-05-01 Micron Technology, Inc. High performance sub-micron P-channel transistor with germanium implant
EP0536869A2 (fr) * 1991-06-05 1993-04-14 National Semiconductor Corporation Méthode de fabrication de couches enterrées de type P pour des dispositifs PNP
EP0536869A3 (en) * 1991-06-05 1993-06-23 National Semiconductor Corporation Method of fabricating p-buried layers for pnp devices
WO1999057759A1 (fr) * 1998-05-05 1999-11-11 Aeroflex Utmc Microelectronic Systems Inc. Procede de fabrication d'un dispositif semiconducteur rendu resistant aux radiations, comportant des zones actives et des zones isolantes
US6511893B1 (en) 1998-05-05 2003-01-28 Aeroflex Utmc Microelectronics, Inc. Radiation hardened semiconductor device
US6855618B2 (en) 1998-05-05 2005-02-15 Aeroflex Colorado Springs, Inc. Radiation hardened semiconductor device
US6432791B1 (en) * 1999-04-14 2002-08-13 Texas Instruments Incorporated Integrated circuit capacitor and method

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