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WO1990005993A1 - High performance sub-micron p-channel transistor with germanium implant - Google Patents

High performance sub-micron p-channel transistor with germanium implant Download PDF

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Publication number
WO1990005993A1
WO1990005993A1 PCT/US1988/004155 US8804155W WO9005993A1 WO 1990005993 A1 WO1990005993 A1 WO 1990005993A1 US 8804155 W US8804155 W US 8804155W WO 9005993 A1 WO9005993 A1 WO 9005993A1
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Prior art keywords
oxide
forming
implant
wafer
implanting
Prior art date
Application number
PCT/US1988/004155
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French (fr)
Inventor
Ruojia R. Lee
Original Assignee
Micron Technology, Inc.
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Priority to PCT/US1988/004155 priority Critical patent/WO1990005993A1/en
Publication of WO1990005993A1 publication Critical patent/WO1990005993A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants

Definitions

  • This invention is related to semiconductor devices. Specifically it is related to high-performance sub-micron channel length P-channel MOS (metal-oxide-semiconductor) transistor (PMOS for short) for the Very Large Scale Integrated (VLSI) or the Ultra Large Scale Integrated (ULSI) circuits. It employs the use of Germanium implant into the channel regions of transistors to both pre-amorphize the channel surface to alleviate the channelling of subsequent enhancement implant required by threshold voltage Vt adjustment and to retard the diffusion of the boron dopants (from enhancement implant) in the region to form a very shallow enhancement implant profile.
  • PMOS metal-oxide-semiconductor
  • VLSI Very Large Scale Integrated
  • ULSI Ultra Large Scale Integrated
  • the invention uses various materials which are electrically either conductive, insulating or semiconducting, although the completed semiconductor circuit device itself is usually referred to as a "semiconductor".
  • One of the materials used is silicon, which is used as either single crystal silicon or as polycrystalline silicon material, referred to as polysilicon or "poly" in this disclosure.
  • P-CH sub-micron P-channel
  • the prior art relating to Germanium in VLSI devices has been in the area of (1 ) field isolation improvement and (2) transistor source/drain regions to achieve shallow source and drain junctions.
  • the former deals with device isolation and an improvement in electrical encroachment; yet it does not improve transistor performance; the later deals with device performance by means of achieving shallower source drain junction depths so that the reduction in charge-sharing effect would improve transistor short channel characteristics. It however does not solve or reduce P-channel transistor short channel effects caused by the very nature of buried channel behavior.
  • the present invention deals directly with PMOS buried channel characteristics by making the buried channel enhancement implant profile more shallow.
  • the shallow implant profile results in the P-CH device will have less or no buried channel characteristics. This avoids undesirable short channel effects, and therefore permits further reduction in the transistor channel length.
  • the shallow profile causes surface channel characteristics to be dominant.
  • Surface channel devices will have better short channel characteristics, i.e., higher punch through voltage
  • Implantation of germanium into the channel to permit the enhancement implant profile to be made shallower will reduce or event solve P-channel buried channel-induced short channel effects and enable further decrease in device length to deep sub-micron range.
  • the drawing Figures each show cross-sections of a portion of a semiconductor circuit device which utilizes the present invention.
  • Figure 1 shows growth of an initial gate oxide, patterning of active areas and channel stop implant
  • Figure 2 shows a LOCOS step
  • Figure 3 shows nitride strip and initial oxide strip
  • Figure 4 shows growth of sacrificial oxide and germanium implant
  • Figure 5 shows V ⁇ enhancement implant and sacrificial oxide strip
  • Figure 6 shows final gate oxide growth, gate polysilicon deposition and phosphorus deposition
  • Figure 7 shows " transistor gate definition and lightly doped source/drain BF_ implant
  • Figure 8 shows spacer formation and heavy source/drain BF- implant
  • Figure 9 shows source/drain activation.
  • Figure 1 shows a cross-section of a semiconductor circuit during its fabrication.
  • a silicon wafer 13 is prepared by forming a thin film of oxide 15 and then depositing nitride 17 over the thin oxide 15. The nitride is masked and etched in order to define active area (31, Fig. 3). The unmasked portions of the wafer 13 are then implanted with boron in order to increase parasitic field transistor threshold voltage V .
  • a thick layer of silicon oxide 21 is grown onto the wafer 13 to form field ox, as shown in Figure 2.
  • the growth of silicon oxide occurs in areas which are not covered by the nitride mask 17, but tends to encroach on the active area, marked AA.
  • the encroachment is present around the edges of the nitride 17, as indicated by dashed lines 23, where the oxide 21 begins to "buck up" or lift the nitride 17.
  • the nitride 17 is then stripped and the wafer 13 is oxide etched in order to remove a top portion 41 of the field ox 21 , as shown in Figure 3. This reduces the encroachment of the silicon oxide 21 into the active area 31 by reducing the thickness of the field oxide 21 in the regions of encroachment.
  • This stripping of the top layer referred to as dilute buffered hydrofluoric acid wet oxide etch, is timed to remove a pre-determined- fraction of the field oxide.
  • the reduced thickness of the field oxide 21 adjacent to the active area 31 establishes an active parasitic MOS transistor device in the completed wafer. This parasitic MOS transistor device could result in shunting between adjacent active areas 31.
  • a germanium implant is applied to the wafer by ion implantation, as shown in Figure 4.
  • Any of various sources of germanium may be used, such as GeF. gas.
  • a preferred method for implanting the germanium is by ion implantation.
  • the germanium does not pass through the thick fieldox 21, but does penetrate the wafer 13 where the oxide 41 has been stripped (shown in Fig. 3).
  • the germanium is allowed to penetrate to a level indicated by the dashed line by controlling implant energy, as well as other factors including temperature. This forms a germanium layer 45 to the depth of the dashed line.
  • the germanium layer 45 is used to reduce P- channel transistor buried channel effects by reducing counter-doping junction depth. A reduction in counter doping junction depths will, in turn, reduce short channel effects in the completed transistor. This also pre-amorphizes the channel surface in order to alleviate channeling of subsequent enhancement implant with boron.
  • Figure 4 also shows the addition of a sacrificial layer 47 of oxide which is grown on to the wafer 13 after the germanium implant. Subsequent to the growth of the sacrificial layer, a boron implant is applied. The boron is able to penetrate the thin sacrificial layer 47 in order to permit control of V of the transistors.
  • the boron dopants diffuse into the wafer 13, but this diffusion remains very shallow as a result of the earlier implant of the germanium. This results in the germanium layer 45 being doped with the boron, and the infusion of the boron being largely confined to the germanium layer 45.
  • the sacrificial oxide 47 is stripped and a final gate oxide 49 is grown to improve gate oxide quality.
  • BF_ may be used instead of boron in the boron implant steps in order to provide the boron implant.
  • a layer of polysilicon 55 is applied to the substrate 13 and, as a result of the final gate oxide 53, remains isolated from the boron doped germanium implant layer 45.
  • This layer of polysilicon 55 forms the gates to transistors formed with the boron doped germanium layer 45, so that the boron doped germanium layer 45 forms source and drain regions.
  • phosphorus deposition is applied to establish the polysilicon layer 55 as N+ type polysilicon.
  • the wafer is masked in order to define the transistor gate.
  • the definition of the transistor gates is accomplished by etching the N+ polysilicon in order to form gate portions 61 of the transistors.
  • a lightly doped source and drain implant is applied by using BF_- as an implant aterial. This results in a lightly doped source drain profile 63 as shown in Figure 8.
  • a spacer oxide 65 is grown from the transistor gate 61 , followed by a heavy source/drain BF- implant.
  • the heavy source/drain BF profession implant results in the profile 73 of P+ areas shown in Figure 9.
  • the germanium implant earlier also reduces the diffusion of both P+ and P- and makes it possible to have shallower P+ and P- junctions.
  • heavy germanium impurity in the N- channel devices can increase impact ionization rate and therefore make it easier to program in EPROMs by avalanching hot electrons.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Implantation of germanium (45) into a PMOS buried channel to permit the enhancement implant profile (to 45) to be made more shallow. The shallow profile will reduce or eventually solve P-channel buried channel-induced short channel effects and enable further decrease in device length to deep sub-micron range. Benefits include better short channel characteristics, i.e., higher punch through voltage BVDSS, less VT sensitivity to the drain voltage (defined as curl) and better subthreshold leakage characteristics.

Description

HIGH PERFORMANCE SUB-MICRON P-CHANNEL TRANSISTOR WITH GERMANIUM IMPLANT
Field of the Invention
This invention is related to semiconductor devices. Specifically it is related to high-performance sub-micron channel length P-channel MOS (metal-oxide-semiconductor) transistor (PMOS for short) for the Very Large Scale Integrated (VLSI) or the Ultra Large Scale Integrated (ULSI) circuits. It employs the use of Germanium implant into the channel regions of transistors to both pre-amorphize the channel surface to alleviate the channelling of subsequent enhancement implant required by threshold voltage Vt adjustment and to retard the diffusion of the boron dopants (from enhancement implant) in the region to form a very shallow enhancement implant profile.
Background of the Invention
The invention uses various materials which are electrically either conductive, insulating or semiconducting, although the completed semiconductor circuit device itself is usually referred to as a "semiconductor". One of the materials used is silicon, which is used as either single crystal silicon or as polycrystalline silicon material, referred to as polysilicon or "poly" in this disclosure.
Shallow channel junction will reduce significantly the undesirable short channel effects of transistors. This is significant in the
Figure imgf000004_0001
-2-
fabrication of sub-micron P-channel (P-CH) transistors in which n+ doped poly gate is used and buried channel is formed. - It is desired to further reduce or even solve P-channel buried channel-induced short channel effects and enable further decrease in device length to the sub-micron range.
The prior art relating to Germanium in VLSI devices has been in the area of (1 ) field isolation improvement and (2) transistor source/drain regions to achieve shallow source and drain junctions. The former deals with device isolation and an improvement in electrical encroachment; yet it does not improve transistor performance; the later deals with device performance by means of achieving shallower source drain junction depths so that the reduction in charge-sharing effect would improve transistor short channel characteristics. It however does not solve or reduce P-channel transistor short channel effects caused by the very nature of buried channel behavior.
Summary of the Invention
The present invention deals directly with PMOS buried channel characteristics by making the buried channel enhancement implant profile more shallow. The shallow implant profile results in the P-CH device will have less or no buried channel characteristics. This avoids undesirable short channel effects, and therefore permits further reduction in the transistor channel length.
The shallow profile causes surface channel characteristics to be dominant. Surface channel devices will have better short channel characteristics, i.e., higher punch through voltage
BVDSS, less V sensitivity to the drain voltage
(defined as curl) and better subthreshold leakage characteristics.
Implantation of germanium into the channel to permit the enhancement implant profile to be made shallower will reduce or event solve P-channel buried channel-induced short channel effects and enable further decrease in device length to deep sub-micron range.
Brief Description of the Drawings
The drawing Figures each show cross-sections of a portion of a semiconductor circuit device which utilizes the present invention.
Figure 1 shows growth of an initial gate oxide, patterning of active areas and channel stop implant;
Figure 2 shows a LOCOS step;
Figure 3 shows nitride strip and initial oxide strip;
Figure 4 shows growth of sacrificial oxide and germanium implant;
Figure 5 shows Vτ enhancement implant and sacrificial oxide strip;
Figure 6 shows final gate oxide growth, gate polysilicon deposition and phosphorus deposition; -4-
Figure 7 shows "transistor gate definition and lightly doped source/drain BF_ implant;
Figure 8 shows spacer formation and heavy source/drain BF- implant; and
Figure 9 shows source/drain activation.
Detailed Description of the Preferred Embodiment
Figure 1 shows a cross-section of a semiconductor circuit during its fabrication. A silicon wafer 13 is prepared by forming a thin film of oxide 15 and then depositing nitride 17 over the thin oxide 15. The nitride is masked and etched in order to define active area (31, Fig. 3). The unmasked portions of the wafer 13 are then implanted with boron in order to increase parasitic field transistor threshold voltage V .
After the field implant, a thick layer of silicon oxide 21 is grown onto the wafer 13 to form field ox, as shown in Figure 2. The growth of silicon oxide occurs in areas which are not covered by the nitride mask 17, but tends to encroach on the active area, marked AA. The encroachment is present around the edges of the nitride 17, as indicated by dashed lines 23, where the oxide 21 begins to "buck up" or lift the nitride 17.
The nitride 17 is then stripped and the wafer 13 is oxide etched in order to remove a top portion 41 of the field ox 21 , as shown in Figure 3. This reduces the encroachment of the silicon oxide 21 into the active area 31 by reducing the thickness of the field oxide 21 in the regions of encroachment. This stripping of the top layer, referred to as dilute buffered hydrofluoric acid wet oxide etch, is timed to remove a pre-determined- fraction of the field oxide.
The reduced thickness of the field oxide 21 adjacent to the active area 31 establishes an active parasitic MOS transistor device in the completed wafer. This parasitic MOS transistor device could result in shunting between adjacent active areas 31.
-At this point, a germanium implant is applied to the wafer by ion implantation, as shown in Figure 4. Any of various sources of germanium may be used, such as GeF. gas. A preferred method for implanting the germanium is by ion implantation.
The germanium does not pass through the thick fieldox 21, but does penetrate the wafer 13 where the oxide 41 has been stripped (shown in Fig. 3). The germanium is allowed to penetrate to a level indicated by the dashed line by controlling implant energy, as well as other factors including temperature. This forms a germanium layer 45 to the depth of the dashed line.
The germanium layer 45 is used to reduce P- channel transistor buried channel effects by reducing counter-doping junction depth. A reduction in counter doping junction depths will, in turn, reduce short channel effects in the completed transistor. This also pre-amorphizes the channel surface in order to alleviate channeling of subsequent enhancement implant with boron. Figure 4 also shows the addition of a sacrificial layer 47 of oxide which is grown on to the wafer 13 after the germanium implant. Subsequent to the growth of the sacrificial layer, a boron implant is applied. The boron is able to penetrate the thin sacrificial layer 47 in order to permit control of V of the transistors. The boron dopants diffuse into the wafer 13, but this diffusion remains very shallow as a result of the earlier implant of the germanium. This results in the germanium layer 45 being doped with the boron, and the infusion of the boron being largely confined to the germanium layer 45. After the boron implant, the sacrificial oxide 47 is stripped and a final gate oxide 49 is grown to improve gate oxide quality.
BF_ may be used instead of boron in the boron implant steps in order to provide the boron implant.
A layer of polysilicon 55 is applied to the substrate 13 and, as a result of the final gate oxide 53, remains isolated from the boron doped germanium implant layer 45. This layer of polysilicon 55 forms the gates to transistors formed with the boron doped germanium layer 45, so that the boron doped germanium layer 45 forms source and drain regions. At that point, phosphorus deposition is applied to establish the polysilicon layer 55 as N+ type polysilicon.
The wafer is masked in order to define the transistor gate. As shown in Figure 7, the definition of the transistor gates is accomplished by etching the N+ polysilicon in order to form gate portions 61 of the transistors. After the transistor gate definition, a lightly doped source and drain implant is applied by using BF_- as an implant aterial. This results in a lightly doped source drain profile 63 as shown in Figure 8.
Also as shown in Figure 8, a spacer oxide 65 is grown from the transistor gate 61 , followed by a heavy source/drain BF- implant. The heavy source/drain BF„ implant results in the profile 73 of P+ areas shown in Figure 9. The germanium implant earlier also reduces the diffusion of both P+ and P- and makes it possible to have shallower P+ and P- junctions.
The basic fabrication process flow of the inventive P-channel MOS transistor is as follows:
(1 ) grow initial gate oxide
(2) pattern active area, channel stop implant, LOCOS, nitride strip
(3) initial oxide strip
(4) sacrificial oxide grow
(5) germanium implant
(6) V-, enhancement implant
(7) sacrificial oxide strip
(8) final gate oxide grow, gate polysilicon deposition and phosphorus deposition
(9) transistor gate definition
(10) lightly doped source/drain BF implant -8-
(11 ) spacer formation and heavy source/drain BF_ implant
(12) source/drain activation
While the invention is described in terms of 5 DRAMs, this is merely the preferred embodiment for which the inventive techniques were developed. Pertinent examples are EPROMs, video random access memories (VRAMs), other multiport RAMs, and other semicφnductor devices.
10 For example, heavy germanium impurity in the N- channel devices can increase impact ionization rate and therefore make it easier to program in EPROMs by avalanching hot electrons.
Clearly, other steps may be taken within the
15 scope of the invention in order to accomplish either same or different circuit results. Accordingly, the invention should be read only as limited by the claims.

Claims

Claims
1. Method of forming semiconductor circuit devices which include, as a part of each device, a plurality of cells active circuit elements to control signals, the method comprising:
a) preparing a silicon wafer and establishing the wafer as a substrate;
b) forming nitride on the wafer to define field oxide and active areas;
c) forming a pattern of nitride layer over selected portions of the active areas;
d) implanting the oxide adjacent the nitride with an implant dopant which functions as a channel stop for isolating parasitic field transistors;
e) growing oxide on the substrate around the nitride, using local control of oxidation techniques;
f) removing the nitride;
g) removing a portion of the oxide such that a substantial percentage of the oxide in areas formerly under the nitride is removed;
■ h) implanting germanium into the substrate through the areas from which a substantial percentage of the oxide has been removed;
i ) growing further oxide over the germanium- implanted wafer; -1 0-
j ) stripping said oxide;
k) regrowing the said oxide;
1) implanting boron through said further oxide;
m) depositing a first conductive layer over the further oxide and etching the conductive layer to leave conductive material from the conductive layer in a gate pattern;
n) implanting a lightly doped source drain implant around the gate pattern;
o) forming oxide spacers adjacent to the conductive material in the gate pattern;
p) implanting source and drain impurities to form source and drain regions of P+ regions adjacent to gate areas, separated by P- regions immediately adjacent to the gate areas.
2. Method of forming semiconductor circuit memory devices which include, as a part of each device, a plurality of memory cells and active circuit elements to control signals, the cells and active circuit elements forming a repeating pattern on the device, the method comprising:
a) preparing a wafer and establishing the wafer as a substrate;
b) forming oxide on the wafer to define field oxide and active areas; c) implanting germanium into the active areas;
d) implant the wafer with a transition voltage impurity which effect a change in a transition voltage of the device;
e) forming gate electrodes;
f) implanting an N-type bottom plate capacitor implant at an implant dose sufficient to significantly compensate the transition voltage implant so as to insure a desired bottom plate junction formation.
3. Method of forming semiconductor devices as described in claim 1 or 2, further characterized by:
a) prior to said implanting of source and drain impurities, implanting source and drain areas into the substrate around the conductive material in the gate pattern; and
b) growing a spacer oxide from the conductive material in the gate pattern.
4. Method of forming semiconductor devices as described in claim 2, further characterized by:
a) etching said defined regions of field isolation oxide to be reduced in thickness to remove a pre-determined fraction of field oxide present; and
b) implanting the wafer with a boron implant wherein the boron is implanted with energy levels which are optimized for penetration through the field -1 2-
oxide remaining after said etching of said defined regions of field isolation oxide to be reduced in thickness.
5. Method of forming semiconductor memory devices as described in claim 1 or 2, further characterized by:
isotropically etching - the field oxide by application of a wet oxide etch to remove said pre-determined fraction of the field oxide, by using dilute buffered hydrofluoric acid wet oxide etch as said oxide etch.
6. Method of forming semiconductor memory devices as described in claim 1 or 2, further characterized by:
said predetermined fraction of oxide removed being greater than 50% of the field ox thickness.
7. Method of forming semiconductor memory devices as described in claim 6, further characterized by:
said predetermined fraction of oxide removed being determined by considerations of leakage from closely spaced N+ to N+ junctions.
8. Method of forming semiconductor memory devices as described in claim 1 , further characterized by:
a) said predetermined fraction of oxide removed being greater than 50% of the field ox thickness; b) said predetermined fraction of oxide removed being determined by considerations of leakage from closely spaced N+ to N+ junctions; and
c) said implanting the wafer with boron at an implantation dose being performed subsequent to transistor formation and prior to cell poly formation.
9. Method of forming semiconductor memory devices as described in claim 1 or 2, further characterized by:
forming each of said semiconductor memory devices with a V / 2 field plate.
10. Method of forming semiconductor memory devices as described in claim 1 or 2, further characterized by:
forming each of said semiconductor memory devices with a grounded field plate.
11. Method of forming semiconductor memory devices as described in claim 1 or 2 , further characterized by:
forming each of said semiconductor memory devices with a grounded field plate.
PCT/US1988/004155 1988-11-21 1988-11-21 High performance sub-micron p-channel transistor with germanium implant WO1990005993A1 (en)

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PCT/US1988/004155 WO1990005993A1 (en) 1988-11-21 1988-11-21 High performance sub-micron p-channel transistor with germanium implant

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0536869A2 (en) * 1991-06-05 1993-04-14 National Semiconductor Corporation Method of fabricating P-buried layers for PNP devices
US5266510A (en) * 1990-08-09 1993-11-30 Micron Technology, Inc. High performance sub-micron p-channel transistor with germanium implant
WO1999057759A1 (en) * 1998-05-05 1999-11-11 Aeroflex Utmc Microelectronic Systems Inc. Method of manufacturing a radiation hardened semiconductor device having active regions and isolation regions
US6432791B1 (en) * 1999-04-14 2002-08-13 Texas Instruments Incorporated Integrated circuit capacitor and method

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4352236A (en) * 1981-07-24 1982-10-05 Intel Corporation Double field oxidation process
US4366613A (en) * 1980-12-17 1983-01-04 Ibm Corporation Method of fabricating an MOS dynamic RAM with lightly doped drain
US4413401A (en) * 1979-07-23 1983-11-08 National Semiconductor Corporation Method for making a semiconductor capacitor
US4536947A (en) * 1983-07-14 1985-08-27 Intel Corporation CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors
US4617066A (en) * 1984-11-26 1986-10-14 Hughes Aircraft Company Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing
US4728619A (en) * 1987-06-19 1988-03-01 Motorola, Inc. Field implant process for CMOS using germanium
US4764477A (en) * 1987-04-06 1988-08-16 Motorola, Inc. CMOS process flow with small gate geometry LDO N-channel transistors
US4791610A (en) * 1985-05-24 1988-12-13 Fujitsu Limited Semiconductor memory device formed of a SOI-type transistor and a capacitor

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4413401A (en) * 1979-07-23 1983-11-08 National Semiconductor Corporation Method for making a semiconductor capacitor
US4366613A (en) * 1980-12-17 1983-01-04 Ibm Corporation Method of fabricating an MOS dynamic RAM with lightly doped drain
US4352236A (en) * 1981-07-24 1982-10-05 Intel Corporation Double field oxidation process
US4536947A (en) * 1983-07-14 1985-08-27 Intel Corporation CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors
US4617066A (en) * 1984-11-26 1986-10-14 Hughes Aircraft Company Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing
US4791610A (en) * 1985-05-24 1988-12-13 Fujitsu Limited Semiconductor memory device formed of a SOI-type transistor and a capacitor
US4764477A (en) * 1987-04-06 1988-08-16 Motorola, Inc. CMOS process flow with small gate geometry LDO N-channel transistors
US4728619A (en) * 1987-06-19 1988-03-01 Motorola, Inc. Field implant process for CMOS using germanium

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5266510A (en) * 1990-08-09 1993-11-30 Micron Technology, Inc. High performance sub-micron p-channel transistor with germanium implant
USRE37158E1 (en) * 1990-08-09 2001-05-01 Micron Technology, Inc. High performance sub-micron P-channel transistor with germanium implant
EP0536869A2 (en) * 1991-06-05 1993-04-14 National Semiconductor Corporation Method of fabricating P-buried layers for PNP devices
EP0536869A3 (en) * 1991-06-05 1993-06-23 National Semiconductor Corporation Method of fabricating p-buried layers for pnp devices
WO1999057759A1 (en) * 1998-05-05 1999-11-11 Aeroflex Utmc Microelectronic Systems Inc. Method of manufacturing a radiation hardened semiconductor device having active regions and isolation regions
US6511893B1 (en) 1998-05-05 2003-01-28 Aeroflex Utmc Microelectronics, Inc. Radiation hardened semiconductor device
US6855618B2 (en) 1998-05-05 2005-02-15 Aeroflex Colorado Springs, Inc. Radiation hardened semiconductor device
US6432791B1 (en) * 1999-04-14 2002-08-13 Texas Instruments Incorporated Integrated circuit capacitor and method

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