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SHA256-core Public
Verilog implementation of the SHA-256 cryptographic hash function
Verilog UpdatedOct 4, 2025 -
gatelevel-journal Public
A personal collection of hardware experiments, from pipelining and math units to low-level design techniques in Verilog.
Verilog UpdatedSep 19, 2025 -
memory-controllers Public
A set of simple, synthesizable memory controller cores in Verilog/VHDL for FPGA development.
Verilog UpdatedAug 24, 2025 -
RISCV-32I-core Public
An RTL implementation of the 32-bit RISC-V base integer ISA (RV32I).
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processor_design_practice Public
This repository contains Verilog RTL implementations of simple processing units. These examples serve as part of my ongoing journey to learn and practice digital design using Verilog HDL. The proje…
Verilog UpdatedJul 17, 2025 -
Final-year-project Public
FPGA based offload engine for network intrusion detection.
VHDL UpdatedApr 24, 2025 -
8_bit_CPU Public
8-bit CPU using basic logic gates, flipflops and EPROM chip simulated on proteus
2 UpdatedApr 26, 2024
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