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1. 8_bit_CPU 8_bit_CPU Public

   8-bit CPU using basic logic gates, flipflops and EPROM chip simulated on proteus

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2. RISCV-32I-core RISCV-32I-core Public

   An RTL implementation of the 32-bit RISC-V base integer ISA (RV32I).

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3. Final-year-project Final-year-project Public

   FPGA based offload engine for network intrusion detection.

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4. processor_design_practice processor_design_practice Public

   This repository contains Verilog RTL implementations of simple processing units. These examples serve as part of my ongoing journey to learn and practice digital design using Verilog HDL. The proje…

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5. Load_forecasting Load_forecasting Public

   Jupyter Notebook

6. gatelevel-journal gatelevel-journal Public

   A personal collection of hardware experiments, from pipelining and math units to low-level design techniques in Verilog.

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