这是indexloc提供的服务,不要输入任何密码
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@SimonSapin
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This PR contains various changes and additions. I would have preferred to find a meaningful split of them into multiple PRs that I could send independently, but I expect this would have caused merge conflicts so here is everything a single linear branch on top of #1. Please see individual commit messages.

At a high-level, I’m trying to use QEMU’s ramfb device from RISC-V guest code, which for involves memory-mapped fw_cfg instead of port I/O, writing to a fw_cfg file instead of just reading, and DMA access (required for writing) instead of just the data register. RISC-V support is added to the test harness and CI in order to have coverage for the memory-mapped mode. Also as drive-by changes: supporting stable Rust, adding a file iterator.

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For the sake of smaller PRs: #3 is the next batch

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Updated to use rust-embedded/riscv-rt#95 instead of hard-coding the QEMU device tree address.

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Friendly ping :)

#3 is the next part of this

@lion328
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lion328 commented Jul 16, 2022

Friendly ping :)

#3 is the next part of this

Sorry for a late reply, I've been quite busy lately. #3 is merged now.

src/lib.rs Outdated
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Is this also works on x86/x86_64?

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qemu-system-i386 and qemu-system-x86_64 don’t expose a memory-mapped fw-cfg device, so there is no valid address that could be passed to this constructor. But if you somehow had an x86/x86_64 with such a device, this should work.

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Sorry I forgot about this! 😅

Again if you prefer single-purpose PRs, #4 is the next batch of commits from this one.

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lion328 commented Apr 4, 2023

Thanks. I will go ahead and merge this larger one.

@lion328 lion328 merged commit d84bcb5 into lion328:master Apr 4, 2023
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2 participants