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WO2025092297A1 - 一种显示面板及其驱动方法 - Google Patents

一种显示面板及其驱动方法 Download PDF

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Publication number
WO2025092297A1
WO2025092297A1 PCT/CN2024/120454 CN2024120454W WO2025092297A1 WO 2025092297 A1 WO2025092297 A1 WO 2025092297A1 CN 2024120454 W CN2024120454 W CN 2024120454W WO 2025092297 A1 WO2025092297 A1 WO 2025092297A1
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WO
WIPO (PCT)
Prior art keywords
display unit
electrically connected
display
layer
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/120454
Other languages
English (en)
French (fr)
Other versions
WO2025092297A9 (zh
Inventor
石领
陈义鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2025092297A1 publication Critical patent/WO2025092297A1/zh
Publication of WO2025092297A9 publication Critical patent/WO2025092297A9/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present disclosure relates to the technical field of pixel data line layout, and in particular to a display panel and a driving method thereof.
  • the red sub-pixels and the blue sub-pixels share a data line.
  • the voltage on the data line needs to be refreshed once in each odd and even row, and it cyclically jumps between L255 and L0, thereby generating additional power consumption.
  • the purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a display panel and a driving method thereof to reduce the power consumption of the display panel.
  • a display panel comprising a plurality of display unit sets sequentially arranged along a row direction; the display unit sets comprise a plurality of first display units located in different display unit columns and a plurality of second display units located in different display unit columns;
  • the display panel is also provided with a first data line and a second data line corresponding to the display unit set; each first display unit of the display unit set is electrically connected to the first data line, and each second display unit of the display unit set is electrically connected to the corresponding second data line.
  • the display unit set includes a first display unit column arranged adjacent to the first data wiring and a second display unit column arranged adjacent to the second data wiring.
  • the first display unit column comprises first display units and second display units which are alternately arranged in sequence along the column direction;
  • the second display unit column comprises second display units and first display units which are alternately arranged in sequence along the column direction.
  • the first display units and the second display units are alternately arranged.
  • each row of sub-pixels includes a first display unit, a second display unit and two third display units.
  • the display panel is further provided with a third data routing line and a fourth data routing line corresponding to the display unit set;
  • Each third display unit in the third display unit column is electrically connected to a third data line
  • each third display unit in the fourth display unit column is electrically connected to a fourth data line.
  • the third data wiring is disposed adjacent to the first data wiring and is located between each pixel driving circuit of the first display unit column and each pixel driving circuit of the third display unit column;
  • the fourth data wiring is disposed adjacent to the second data wiring and is located between each pixel driving circuit of the second display unit column and each pixel driving circuit of the fourth display unit column.
  • the display panel is provided with a first adapter wire and a second adapter wire;
  • the second display unit located in the first display unit column is electrically connected to the second data wiring through the second adapter wire;
  • the first display unit located in the second display unit column is connected to the The first data line is electrically connected.
  • the display panel includes a base substrate, a driving circuit layer and a pixel layer which are stacked in sequence;
  • the driving circuit layer includes a transistor layer, a first source-drain metal layer, a transfer metal layer and a second source-drain metal layer which are stacked in sequence; each transistor of the pixel driving circuit of the display unit is arranged in the transistor layer; the sub-pixel of the display unit is arranged in the pixel electrode layer;
  • the data voltage input terminal of the pixel driving circuit of the first display unit adjacent to the first data wiring is electrically connected to the first transfer metal structure corresponding to the first display unit through a via hole; the first transfer metal structure is electrically connected to the first data wiring through a via hole;
  • the data voltage input terminal of the pixel driving circuit of the first display unit adjacent to the second data wiring is electrically connected to the first end of the first adapter wire through a via hole, and the second end of the first adapter wire is electrically connected to the first data wiring through a via hole;
  • the data voltage input terminal of the pixel driving circuit of the second display unit adjacent to the first data wiring is electrically connected to the first end of the second adapter wire through a via hole, and the second end of the second adapter wire is electrically connected to the second data wiring through a via hole.
  • the shape of the first end of the second patch cord is the same as the shape of the first patch metal structure; the second end of the second patch cord is adjacent to and insulated from the first end of the first patch cord;
  • the shape of the first end of the first transition wire is the same as that of the first transition metal structure; the second end of the first transition wire is adjacent to and insulated from the first end of the second transition wire.
  • the second source-drain metal layer further includes a driving voltage wiring
  • a first avoidance gap is formed on a side of the driving voltage wiring close to the first data wiring; the orthographic projection of the second end of the first adapter wire on the plane where the display panel is located is located within the orthographic projection of the first avoidance gap on the plane where the display panel is located;
  • a second avoidance gap is formed on one side of the driving voltage wiring close to the second data wiring; the orthographic projection of the second end of the second adapter wire on the plane where the display panel is located is located within the orthographic projection of the second avoidance gap on the plane where the display panel is located.
  • the first data wiring has a first side branch portion that penetrates into the first avoidance gap, and the first side branch portion is electrically connected to the second end of the first adapter wire through a via;
  • the second data wiring has a second side branch portion extending deep into the second avoidance gap, and the second side branch portion is electrically connected to the second end of the second adapter wire through a via.
  • a method for driving a display panel comprising: driving each display unit row by row;
  • the driving voltage required by the first display unit of the display unit set is loaded onto the first data line corresponding to the display unit set, and the driving voltage required by the second display unit of the display unit set is loaded onto the second data line corresponding to the display unit set.
  • FIG. 1 is a schematic diagram of the structure of a display panel in the related art.
  • FIG. 2 is a schematic diagram of the structure of a display panel in one embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a cross-sectional structure of a display panel in one embodiment of the present disclosure.
  • FIG. 4 is an equivalent circuit diagram of a pixel driving circuit in one embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a stacked structure of a polysilicon semiconductor layer, a first gate layer, a second gate layer, a metal oxide semiconductor layer, a third gate layer, and a first source-drain metal layer in a circuit layout region according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a partial structure of a metal light-shielding layer in one embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a partial structure of a polysilicon semiconductor layer in one embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a partial structure of a first gate layer in one embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a partial structure of a second gate layer in one embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a partial structure of a metal oxide semiconductor layer in one embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a partial structure of a third gate layer in one embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a partial structure of a first source-drain metal layer in one embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a stacked structure of a second gate layer, a metal oxide semiconductor layer, a third gate layer and a first source-drain metal layer in one embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of a partial structure of a transfer metal layer in one embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of the stacked structure of the second source-drain metal layer in one embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram of a stacked structure of a transfer metal layer and a second source-drain metal layer in one embodiment of the present disclosure.
  • FIG. 17 is a schematic diagram of a stacked structure of a transfer metal layer, a second source-drain metal layer, and a pixel layer in one embodiment of the present disclosure.
  • a transistor refers to an element including at least three terminals: a gate, a drain, and a source.
  • the transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source.
  • the channel region refers to the region where the current mainly flows.
  • structure A and structure B when describing the overlapping arrangement of structure A and structure B, it means that structure A and structure B are arranged in different film layers, and there is an overlapping part between the orthographic projection of structure A on the substrate and the orthographic projection of structure B on the substrate.
  • the overlapping portion of structure C and structure D refers to a specific portion C1 in structure C; the orthographic projection of the specific portion C1 on the substrate is the overlapping portion of the orthographic projection of structure C on the substrate and the orthographic projection of structure D on the substrate.
  • the structure layer E is located on the side of the structure layer F away from the base substrate, which can be understood as the structure layer E is formed on the side of the structure layer F away from the base substrate.
  • the structure layer F is a patterned structure
  • part of the structure layer E may also be located at the same physical height of the structure layer E or lower than the physical height of the structure layer E, wherein the base substrate is a height reference.
  • FIG1 is a schematic diagram of a display panel structure in the related art.
  • the display panel has display unit columns and data lines DL corresponding to the display unit columns.
  • Each pixel driving circuit PDC of the display unit column is electrically connected to the data line DL corresponding to the display unit column.
  • Some of the display unit columns have display units of different colors.
  • Unit DU these display units DU of different colors are driven by the same data line DL.
  • at least one display unit column includes red display units and blue display units arranged alternately; the voltage on the data line needs to be refreshed once in each odd row and even row, and it jumps cyclically from grayscale Lmax to grayscale L0, resulting in additional power consumption.
  • grayscale Lmax is the maximum value of the grayscale of the display panel, for example, 255 grayscales.
  • the display panel PNL includes a display area AA and a peripheral area BB located at least on one side of the display area AA.
  • the display panel PNL is provided with array-distributed display units DU (e.g., the first display unit DU1, the second display unit DU2, and the third display unit DU3 in FIG. 2 ), and the display unit DU includes sub-pixels PIX (e.g., the first sub-pixel PIX1, the second sub-pixel PIX2, and the third sub-pixel PIX3 in FIG. 2 ) and a pixel driving circuit PDC for driving the sub-pixels PIX.
  • array-distributed display units DU e.g., the first display unit DU1, the second display unit DU2, and the third display unit DU3 in FIG. 2
  • the display unit DU includes sub-pixels PIX (e.g., the first sub-pixel PIX1, the second sub-pixel PIX2, and the third sub-pixel PIX3 in FIG.
  • the display panel PNL does not provide a display unit DU in the peripheral area BB, or the provided display unit DU is not used to display a picture.
  • the display panel PNL is provided with a plurality of scan lines (not shown in FIG. 2 ) extending along the row direction DH in the display area AA, and each scan line is provided in a one-to-one correspondence with each display unit row HDU.
  • the pixel driving circuit PDC of each display unit DU of the display unit row is electrically connected to the corresponding scan line.
  • the display panel PNL is also provided with a plurality of data traces DL extending along the column direction DV in the display area AA. Each data line DL is set in one-to-one correspondence with each display unit column VDU.
  • the pixel driving circuit PDC of each display unit DU is connected to a scan line and a data line DL.
  • the driving voltage loaded on the data line DL can be written into the pixel driving circuit PDC, so that the pixel driving circuit PDC can control the brightness of the sub-pixel PIX according to the written driving voltage.
  • the display panel PNL includes a plurality of display unit sets DUS (only one is illustrated in FIG2 ) arranged in sequence along a row direction DH; referring to FIG2 , the display unit set DUS includes a plurality of first display units DU1 located in different display unit columns VDU and a plurality of second display units DU2 located in different display unit columns VDU.
  • the display panel PNL is also provided with a first data line DL1 and a second data line DL2 corresponding to the display unit set DUS.
  • Each first display unit DU1 of the display unit set DUS is electrically connected to the first data line DL1, and the display unit set DUS is electrically connected to the first display unit DU1.
  • Each second display unit DU2 of DUS is electrically connected to the corresponding second data line DL2.
  • the first data line DL1 can be used to load the data voltage for controlling each first display unit DU1
  • the second data line DL2 can be used to load the data voltage for controlling each second display unit DU2, thereby avoiding the extra power consumption generated by the same data line controlling both the first display unit DU1 and the second display unit DU2, and reducing the power consumption of the display panel.
  • the voltage signal on the first data line DL1 is written into the pixel driving circuit PDC of each first display unit DU1 in sequence according to the preset control timing
  • the voltage signal on the second data line DL2 is written into the pixel driving circuit PDC of each second display unit DU2 in sequence according to the preset control timing
  • the corresponding sub-pixel PIX is controlled by the pixel driving circuit PDC.
  • the display unit set DUS includes a first display unit column VDU1, a third display unit column VDU3A, a second display unit column VDU2, and a fourth display unit column VDU3B arranged in sequence along the row direction DH.
  • the first display unit column VDU1 is arranged adjacent to the first data line DL1
  • the second display unit column VDU2 is arranged adjacent to the second data line DL2.
  • the first display unit column VDU1 includes a first display unit DU1 and a second display unit DU2 arranged alternately in sequence along DV
  • the second display unit column VDU2 includes a second display unit DU2 and a first display unit DU1 arranged alternately in sequence along DV.
  • the second display unit DU2 in the first display unit column VDU1 is electrically connected to the second data line DL2, and the first display unit DU1 in the second display unit column VDU2 is electrically connected to the first data line DL1.
  • the first data line DL1 controls the first display unit DU1
  • the second data line DL2 controls the second display unit DU2 in a display unit set DUS.
  • the display panel PNL is further provided with a third data line DL3A and a fourth data line DL3B corresponding to the display unit set DUS.
  • the third display unit column VDU3A is adjacent to the third data line DL3A
  • the fourth display unit column VDU3B is adjacent to the fourth data line DL3B.
  • the four display unit columns VDU3B each include a plurality of third display units DU3 sequentially arranged along DV.
  • Each third display unit DU3 of the third display unit column VDU3A is electrically connected to the third data line DL3A
  • each third display unit DU3 of the fourth display unit column VDU3B is electrically connected to the fourth data line DL3B.
  • the same display unit row includes a first display unit DU1, a second display unit DU2, and two third display units DU3.
  • the first display unit DU1 and the second display unit DU2 are alternately arranged.
  • the sub-pixels of the first display unit row in the display unit set DUS are the first display unit DU1, the third display unit DU3, the second display unit DU2, and the third display unit DU3 in sequence; then the sub-pixels of the adjacent second display unit row are the second display unit DU2, the third display unit DU3, the first display unit DU1, and the third display unit DU3 in sequence.
  • the third data routing DL3A and the first data routing DL1 are arranged adjacent to each other, and the third data routing DL3A and the first data routing DL1 are both located between each pixel driving circuit PDC of the first display unit column VDU1 and each pixel driving circuit PDC of the third display unit column VDU3A; the fourth data routing DL3B and the second data routing DL2 are arranged adjacent to each other, and the fourth data routing DL3B and the second data routing DL2 are both located between each pixel driving circuit PDC of the second display unit column VDU2 and each pixel driving circuit PDC of the fourth display unit column VDU3B.
  • the display panel PNL is provided with a first adapter wire TRL1 and a second adapter wire TRL2; the second display unit DU2 located in the first display unit column VDU1 is electrically connected to the second data line DL2 via the second adapter wire TRL2; the first display unit DU1 located in the second display unit column VDU2 is electrically connected to the first data line DL1 via the first adapter wire TRL1.
  • the same data line DL only needs to control the display unit DU of one color, without affecting the existing pixel arrangement. Based on the pixel arrangement, the power consumption of the display panel is reduced.
  • the first display unit DU1 includes a pixel driving circuit PDC and a first sub-pixel PIX1 driven by the pixel driving circuit PDC;
  • the second display unit DU2 includes a pixel driving circuit PDC and a second sub-pixel PIX2 driven by the pixel driving circuit PDC;
  • the third display unit DU3 includes a pixel driving circuit PDC and a third sub-pixel PIX3 driven by the pixel driving circuit PDC.
  • the colors of the first sub-pixel PIX1, the second sub-pixel PIX2 and the third sub-pixel PIX3 are different; further, the sizes of the first sub-pixel PIX1, the second sub-pixel PIX2 and the third sub-pixel PIX3 are different.
  • the sizes of the first sub-pixel PIX1 , the second sub-pixel PIX2 , and the third sub-pixel PIX3 decrease in sequence.
  • the first sub-pixel PIX1 is a blue sub-pixel
  • the second sub-pixel PIX2 is a red sub-pixel
  • the third sub-pixel PIX3 is a green sub-pixel.
  • Fig. 3 illustrates a cross-sectional view of a display panel in an embodiment of the present disclosure.
  • the display panel includes a base substrate BP, a driving circuit layer FA and a pixel layer FB which are stacked in sequence.
  • the substrate substrate BP may be a substrate substrate BP of an inorganic material, or may be a substrate substrate BP of an organic material.
  • the material of the substrate substrate BP may be a glass material such as soda-lime glass, quartz glass, sapphire glass, or may be a metal material such as stainless steel, aluminum, nickel, etc.
  • the material of the substrate substrate BP may be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) or a combination thereof.
  • the substrate substrate BP may also be a flexible substrate substrate BP, for example, the material of the substrate substrate BP may be polyimide (PI).
  • PI polyimide
  • the substrate BP can also be a composite of multiple layers of materials.
  • the substrate BP may include a bottom film layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer which are stacked in sequence.
  • the material of the base substrate BP is polyimide, so that the display panel is a flexible display panel.
  • the display panel can be first formed on a support substrate SBP, and the support substrate SBP can be peeled off after the preparation is completed. In this way, during the process, the support substrate SBP can provide support for the display panel.
  • the driving circuit layer FA is provided with a pixel driving circuit PDC for driving sub-pixels.
  • the driving circuit layer FA includes a transistor layer, and each transistor of the pixel driving circuit PDC of the display unit DU is arranged in the transistor layer.
  • any pixel driving circuit PDC may include a transistor and a storage capacitor.
  • the driving circuit layer may be provided with a polycrystalline silicon semiconductor layer SEMI1 and a metal oxide semiconductor layer SEMI2, so that the transistors in the driving circuit layer may include metal oxide transistors and polycrystalline silicon transistors (such as low-temperature polycrystalline silicon transistors) at the same time. Further, these transistors may be thin film transistors.
  • polycrystalline silicon transistors may also be amorphous silicon transistors; accordingly, the polycrystalline silicon semiconductor layer SEMI1 of the driving circuit layer may be replaced by an amorphous silicon semiconductor layer.
  • the polysilicon transistor may be a top-gate thin film transistor, a bottom-gate thin film transistor or a dual-gate thin film transistor, whichever is more effective in controlling the transistor.
  • the metal oxide transistor is a dual-gate thin film transistor, that is, the channel region of the transistor is sandwiched between the top gate (the gate on the side away from the substrate) and the bottom gate (the gate on the side close to the substrate); in this way, the bottom gate can block light from the substrate side, preventing light from irradiating the channel region of the transistor and causing abnormal operation of the transistor.
  • the gate of the polysilicon transistor can be arranged in the same layer as a gate of the metal oxide transistor, for example, the gate of the polysilicon transistor and the bottom gate of the metal oxide transistor are arranged in the same gate layer. In other embodiments, the gate of the polysilicon transistor and the top gate and the bottom gate of the metal oxide transistor can be arranged in different gate layers respectively.
  • the driving circuit layer includes a polysilicon semiconductor layer SEMI1, a first gate insulating layer GI1, a first gate layer GT1, a second buffer layer Buff2, a second gate layer GT2, a second gate insulating layer GI2, a metal oxide semiconductor layer SEMI2, a third gate insulating layer GI3, and a third gate layer GT3, which are sequentially stacked on one side of the substrate BP.
  • the polysilicon semiconductor layer SEMI1 is provided with an active area of a polysilicon transistor
  • the first gate layer GT1 is provided with a gate of a polysilicon transistor.
  • the metal oxide semiconductor layer SEMI2 is provided with an active area of a metal oxide transistor; the second gate layer GT2 is provided with a bottom gate of a metal oxide transistor; and the third gate layer GT3 is provided with a top gate of a metal oxide transistor.
  • the active area of a transistor includes a channel area of the transistor and a source and a drain located on both sides of the channel area; wherein the channel area maintains semiconductor characteristics, and the source and the drain are conductorized.
  • the display panel further has control wirings for applying control signals to the gates of the transistors. These control wirings may extend substantially along the row direction and be electrically connected to the gates of the driven transistors.
  • the driving circuit layer further comprises a metal layer, which is located on the side of each gate layer and semiconductor layer away from the substrate BP.
  • the metal layer is provided with a data line DL for loading a data voltage Data and a driving voltage line VDDL for loading a driving voltage VDD; the data line DL is used to load the data voltage Data to the pixel driving circuit PDC, so that the pixel driving circuit PDC controls the brightness of the sub-pixel according to the voltage value of the data voltage Data.
  • the metal layer is three layers, including a first source-drain metal layer SD1, a transfer metal layer DRL and a second source-drain metal layer SD2 arranged in a stacked manner.
  • An interlayer dielectric layer ILD is provided on the surface of the first source-drain metal layer SD1 close to the substrate BP, a first planarization layer PLN1 is provided between the first source-drain metal layer SD1 and the transfer metal layer DRL, a second planarization layer PLN2 is provided between the transfer metal layer DRL and the second source-drain metal layer SD2, and a third planarization layer PLN3 is provided on the side of the second source-drain metal layer SD2 away from the substrate BP.
  • the driving circuit layer FA may further include a first buffer layer Buff1 disposed between the substrate BP and the semiconductor layer, and the semiconductor layer and the gate layer are all located on a side of the first buffer layer Buff1 away from the substrate BP.
  • the material of the first buffer layer Buff1 may be an inorganic insulating material such as silicon oxide or silicon nitride.
  • the first buffer layer Buff1 may be a single inorganic material layer or a plurality of stacked inorganic material layers.
  • the driving circuit layer FA may also include a metal shading layer LS located between the first buffer layer Buff1 and the substrate BP, and the metal shading layer LS may shield at least part of the channel region of the transistor.
  • the metal shading layer LS may be electrically connected to the metal layer through a via, so that the metal shading layer LS may transmit signals, shield signals or perform other functions as needed.
  • the metal shading layer LS may be loaded with a common electrode voltage so that the metal shading layer LS can achieve the function of signal shielding.
  • a portion of the metal shading layer LS is patterned into a conductive wire so that the conductive wire located in the metal shading layer LS can be used to transmit signals, such as transmitting touch signals.
  • an inorganic barrier layer Barr may be provided between the metal light shielding layer LS and the first buffer layer Buff1 to prevent the material in the base substrate BP from penetrating into the driving circuit layer.
  • the pixel layer FB is provided with light-emitting elements distributed in an array, and each light-emitting element emits light under the control of a pixel driving circuit. These light-emitting elements can be used as sub-pixels of the embodiments of the present disclosure.
  • the light-emitting element can be an organic light-emitting diode (OLED), a micro light-emitting diode (Micro LED), a quantum dot-organic light-emitting diode (QD-OLED), a quantum dot light-emitting diode (QLED) or other types of light-emitting elements.
  • OLED organic light-emitting diode
  • Micro LED micro light-emitting diode
  • QD-OLED quantum dot-organic light-emitting diode
  • QLED quantum dot light-emitting diode
  • the pixel layer FB can be arranged on the side of the driving circuit layer FA away from the base substrate BP, which may include a pixel electrode layer ANL, a pixel definition layer PDL, a support column layer PS, an organic light-emitting functional layer EL and a common electrode layer COML stacked in sequence.
  • the pixel electrode layer ANL has a plurality of pixel electrodes in the display area of the display panel;
  • the pixel definition layer PDL has a plurality of through pixel openings arranged one-to-one corresponding to the plurality of pixel electrodes in the display area, and any pixel opening exposes at least a portion of the corresponding pixel electrode.
  • the support column layer PS includes a plurality of support columns in the display area, and the support columns are located on the surface of the pixel definition layer PDL away from the base substrate BP so as to support the fine metal mask (Fine Metal Mask, FMM) during the evaporation process.
  • the organic light-emitting functional layer EL at least covers the pixel electrode exposed by the pixel definition layer PDL.
  • the organic light-emitting functional layer EL may include an organic electroluminescent material layer, and may include a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer and an electron injection layer. One or more of.
  • the various film layers of the organic light-emitting functional layer EL can be prepared by an evaporation process, and a fine metal mask or an open mask (Open Mask) can be used to define the pattern of each film layer during evaporation.
  • the common electrode layer COML can cover the organic light-emitting functional layer EL in the display area. In this way, the pixel electrode, the common electrode layer COML and the organic light-emitting functional layer EL located between the pixel electrode and the common electrode layer COML form an organic electroluminescent diode, and any organic electroluminescent diode can be used as a sub-pixel of the display panel.
  • the sub-pixel PIX may include sub-pixels PIX of multiple different colors, for example, a red sub-pixel R for emitting red light, a blue sub-pixel B for emitting blue light, and a green sub-pixel G for emitting green light.
  • the pixel layer FB may further include a light extraction layer located on a side of the common electrode layer COML away from the substrate BP to enhance the light extraction efficiency of the organic light emitting diode.
  • the display panel may further include a thin film encapsulation layer TFE.
  • the thin film encapsulation layer TFE is disposed on the surface of the pixel layer FB away from the base substrate BP, and may include an inorganic encapsulation layer and an organic encapsulation layer alternately stacked.
  • the inorganic encapsulation layer can effectively block external moisture and oxygen, and prevent water and oxygen from invading the organic light-emitting functional layer EL and causing material degradation.
  • the edge of the inorganic encapsulation layer may be located in the peripheral area.
  • the organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce the stress between the inorganic encapsulation layers.
  • the edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer.
  • the thin film encapsulation layer TFE includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the side of the pixel layer FB away from the base substrate BP.
  • the pixel driving circuit PDC includes a storage capacitor Cst and a plurality of transistors, wherein a portion of the transistors may be polysilicon transistors and another portion may be metal oxide transistors.
  • FIG4 provides a pixel driving circuit PDC as an example.
  • the exemplary pixel driving circuit PDC includes a storage capacitor Cst, a threshold compensation transistor T2, a driving transistor T3, a capacitor reset transistor T1, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, and a pixel electrode reset transistor T7.
  • the threshold compensation transistor T2 is a metal oxide transistor, which is used to respond to the threshold compensation signal GN1.
  • the threshold voltage of the driving transistor T3 is compensated.
  • the driving transistor T3 is a polysilicon transistor, which can generate a driving current under the control of the first node N1.
  • the pixel driving circuit PDC can also include other transistors or storage capacitors Cst, or can have fewer transistors; the electrical connection relationship between the transistors and the loaded signals and the timing of the loaded signals can also be different from the pixel driving circuit PDC illustrated in Figure 3.
  • the first electrode plate of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode plate of the storage capacitor Cst is used to load the driving voltage VDD. In this way, the voltage loaded on the second electrode plate of the storage capacitor Cst is stable.
  • the second electrode plate of the storage capacitor Cst can be loaded with other power supply voltages, such as the same common voltage as the common electrode layer.
  • the voltage of the second electrode plate of the storage capacitor may not be constant, for example, the drain of the capacitor reset transistor and the drain of the data write transistor are electrically connected to the second electrode plate of the storage capacitor; the capacitor reset transistor is used to reset the voltage of the second electrode plate of the storage capacitor, and the data write transistor is used to load the data voltage to the second electrode plate of the storage capacitor; through coupling, the voltage of the first node can be adjusted as the voltage of the second electrode plate of the storage capacitor is adjusted.
  • the pixel driving circuit PDC further includes a first light-emitting control transistor T5 and a second light-emitting control transistor T6, the source of the first light-emitting control transistor T5 being used to load a driving voltage VDD, for example, being electrically connected to a data routing line DL for loading the driving voltage VDD.
  • the drain of the first light-emitting control transistor T5 is electrically connected to a third node N3.
  • the source of the second light-emitting control transistor T6 is electrically connected to a second node N2, and the drain of the second light-emitting control transistor T6 is electrically connected to a fourth node N4, and the fourth node N4 is also electrically connected to a pixel electrode of a sub-pixel.
  • the gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6 are used to load a light-emitting control signal EM, for example, being electrically connected to a light-emitting control routing line EML for loading a light-emitting control signal EM.
  • the driving current generated by the driving transistor T3 can flow to the sub-pixel, thereby driving the sub-pixel to emit light.
  • the first light-emitting control transistor T5 and the second light-emitting control transistor T6 can be polysilicon transistors.
  • the pixel driving circuit PDC may include only one of the first light emission control transistor T5 and the second light emission control transistor T6 .
  • the pixel driving circuit PDC further includes a capacitor reset transistor T1 and a data write transistor T4.
  • the source of the capacitor reset transistor T1 is used to load the first initialization voltage Vinit1, and the drain of the capacitor reset transistor T1 is electrically connected to the first node N1; the capacitor reset transistor T1 is used to load the first initialization voltage Vinit1 to the first node N1 in response to the capacitor reset signal GN2, so as to reset the first node N1.
  • the capacitor reset transistor T1 is a metal oxide semiconductor transistor; in other examples of the present disclosure, the capacitor reset transistor T1 may also be a polysilicon transistor.
  • the data write transistor T4 is a polysilicon transistor.
  • the source of the data write transistor T4 is used to load the data voltage Data, for example, electrically connected to the data line DL for loading the data voltage Data; the drain of the data write transistor T4 is electrically connected to the third node N3; the data write transistor T4 is used to load the data voltage Data to the third node N3 in response to the data scan signal GP.
  • the pixel driving circuit PDC further includes a pixel electrode reset transistor T7, which is a polysilicon transistor; the source of the pixel electrode reset transistor T7 is used to load the second initialization voltage Vinit2, for example, electrically connected to the second initialization voltage wiring Vinit2L used to load the second initialization voltage Vinit2.
  • the drain of the pixel electrode reset transistor T7 is electrically connected to the fourth node N4, and the pixel electrode reset transistor T7 is used to load the second initialization voltage Vinit2 to the fourth node N4 in response to the pixel electrode reset signal RP, thereby resetting the pixel electrode of the sub-pixel.
  • the pixel driving circuit PDC may not include the pixel electrode reset transistor T7, or the pixel electrode reset transistor T7 may be a metal oxide thin film transistor.
  • the first initialization voltage Vinit1 loaded by the source of the capacitor reset transistor T1 and the second initialization voltage Vinit2 loaded by the source of the pixel electrode reset transistor T7 may be different voltage signals, for example, voltage signals from different wirings (the voltages may be the same).
  • the first initialization voltage Vinit1 loaded by the source of the capacitor reset transistor T1 and the second initialization voltage Vinit2 loaded by the source of the pixel electrode reset transistor T7 may also be the same signal, for example, a signal from the same wiring.
  • the pixel driving circuit PDC shown in FIG. 4 can be sequentially The operation is performed according to the following timing.
  • the gate of the capacitor reset transistor T1 is loaded with the capacitor reset signal GN2 and turned on, so that the first node N1 is reset to the first initialization voltage Vinit1.
  • the driving transistor T3 is turned on.
  • the threshold compensation transistor T2, the first light emission control transistor T5, the second light emission control transistor T6, the data writing transistor T4, and the pixel electrode reset transistor T7 remain turned off.
  • the gate of the data writing transistor T4 is loaded with the data scanning signal GP so that the data writing transistor T4 is turned on, so that the data voltage Data is written to the third node N3;
  • the gate of the threshold compensation transistor T2 is loaded with the threshold compensation signal GN1 so that the threshold compensation transistor T2 is turned on.
  • the capacitor reset transistor T1, the first light emitting control transistor T5, and the second light emitting control transistor T6 remain turned off. In this way, the third node N3 can charge the first node N1 so that the voltage of the first node N1 is pulled up until the first node N1 is pulled up to turn off the driving transistor T3.
  • the data voltage Data and the threshold voltage of the driving transistor T3 are written into the first node N1, and the voltage of the first node N1 is VData+Vth 3 , Vth 3 is the threshold voltage of the driving transistor T3, and VData is the voltage value of the data voltage Data. In this way, in the data writing stage, data writing and threshold compensation of the driving transistor T3 are realized at the same time.
  • the gate of the pixel electrode reset transistor T7 is loaded with the pixel electrode reset signal RP, so that the pixel electrode reset transistor T7 is turned on, and then the second initialization voltage Vinit2 is loaded to the fourth node N4.
  • the pixel electrode reset signal RP of the pixel driving circuit PDC of the previous row and the data scanning signal GP of the pixel driving circuit PDC of the next row are the same signal, so that when the pixel driving circuit PDC of the previous row is in the pixel electrode reset stage, the pixel driving circuit PDC of the next row is in the data writing stage.
  • the pixel electrode reset signal RP and the data scanning signal GP of the pixel driving circuit PDC of the same row can be the same signal, and the pixel electrode reset stage and the data writing stage of the pixel driving circuit PDC of this row are the same stage, that is, the data writing transistor T4 and the pixel electrode reset transistor T7 are synchronously turned on or off.
  • the gate of the first light emitting control transistor T5 and the gate of the second light emitting control transistor T6 are loaded with the light emitting control signal EM, so that the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on.
  • the driving voltage VDD is loaded to the third node N3, and the second node N2 is electrically connected to the sub-pixel; the driving transistor T3 outputs the driving current under the control of the first node N1, thereby driving the sub-pixel to emit light.
  • the pixel driving circuit PDC of 7T1C (7 transistors and 1 storage capacitor) in the above example of the present disclosure is only one of the exemplary pixel driving circuits PDC of the display panel of the present disclosure, rather than a specific limitation of the pixel driving circuit PDC used in the display panel of the present disclosure.
  • the pixel driving circuit PDC may include more or fewer transistors, for example, 8 transistors, 9 transistors, etc., and one or more of the transistors illustrated in the above 7T1C may also be set as a plurality of sub-transistors connected in series in sequence.
  • the pixel driving circuit PDC may include more storage capacitors Cst, for example, two or three storage capacitors.
  • the pixel driving circuit PDC can reduce the leakage of the first node N1 by setting the threshold compensation transistor T2 as a metal oxide transistor, thereby improving the voltage holding capability of the pixel driving circuit PDC, reducing the flicker risk of the display panel under low-frequency driving and reducing the power consumption of the display panel.
  • the specific layout of the pixel driving circuit PDC of the above-mentioned 7T1C example in the display panel is introduced and explained in conjunction with the accompanying drawings. It can be understood that the 7T1C exampled in the embodiments of the present disclosure can also be presented in other layout modes, and the display panel of the present disclosure can also adopt other pixel driving circuits PDC. When other pixel driving circuit PDC structures are adopted, the layout mode of the pixel driving circuit PDC in the display panel of the present disclosure can be adjusted accordingly.
  • the driving circuit layer FA includes a metal light shielding layer LS, an inorganic barrier layer Barr, a first buffer layer Buff1, a polysilicon semiconductor layer SEMI1, a first gate insulating layer GI1, a first gate layer GT1, a second buffer layer Buff2, a second gate layer GT2, a second gate insulating layer GI2, a metal oxide semiconductor layer SEMI2, a third gate insulating layer GI3, a third gate layer GT3, an interlayer dielectric layer ILD, a first source-drain metal layer SD1, a first planarization layer PLN1, a transfer metal layer DRL, a second planarization layer PLN2, a second source-drain metal layer SD2, and a third planarization layer PLN3, which are sequentially stacked on one side of the substrate BP.
  • the metal light shielding layer LS may not be provided.
  • the main area where the pixel driving circuit PDC is set can be defined as the circuit layout area PDCA corresponding to the pixel driving circuit PDC.
  • the circuit layout area PDCA can be rectangular.
  • the pixel electrode reset transistor T7 of the pixel driving circuit PDC of the previous row can be arranged in the circuit layout area PDCA corresponding to the pixel driving circuit PDC of the next row.
  • the capacitor reset transistor T1 to the second light emitting control transistor T6 and the storage capacitor Cst of the pixel driving circuit PDC are arranged in the circuit layout area PDCA corresponding to the pixel driving circuit PDC, and the pixel electrode reset transistor T7 of the pixel driving circuit PDC is arranged in the circuit layout area PDCA of the next row.
  • the layout of two adjacent pixel driving circuits PDC can be arranged in a mirror image.
  • the layout of two adjacent pixel driving circuits PDC can also be the same instead of a mirror image.
  • FIG6 shows a schematic diagram of the partial structure of the metal shading layer LS of the display panel of the example disclosed in the present invention.
  • the metal shading layer LS in the circuit layout area PDCA, has a metal shading portion LSP and a connecting line LSL; adjacent metal shading portions LSP in the same row and adjacent metal shading portions in the same column are connected by connecting lines LSL.
  • the metal shading layer LS is in a grid shape, which can shield external signals and prevent signals outside the display panel from affecting the normal display of the display panel.
  • the metal shading portion LSP needs to have a larger size to shield the light irradiating the channel region of the driving transistor T3 to ensure the stability of the characteristics of the driving transistor T3.
  • FIG7 shows a schematic diagram of the partial structure of the polysilicon semiconductor layer SEMI1 of the display panel of the example of the present disclosure.
  • FIG8 shows a schematic diagram of the partial structure of the first gate layer GT1 of the display panel of the example of the present disclosure.
  • the polysilicon semiconductor layer SEMI1 has a polysilicon pattern corresponding to each pixel driving circuit PDC, and the polysilicon pattern forms a channel region T3Act of the driving transistor T3 with semiconductor characteristics, a channel region T4Act of the data writing transistor T4, a channel region T5Act of the first light emission control transistor T5, a channel region T6Act of the second light emission control transistor T6, and a channel region T7Act of the pixel electrode reset transistor T7, and forms a first polysilicon strip PL1, a second polysilicon strip PL2, a third polysilicon strip PL3, a fourth polysilicon strip PL4, a fifth polysilicon strip PL5, and a sixth polysilicon strip PL6 that are conductorized.
  • the first polysilicon strip PL1, the second polysilicon strip PL2, the third polysilicon strip PL3, the fourth polysilicon strip PL4, the fifth polysilicon strip PL5, and the sixth polysilicon strip PL6 may be conductorized after the first gate layer GT1 is patterned.
  • the first polysilicon strip PL1 is electrically connected to one end of the channel region T4Act of the data writing transistor T4 and serves as the source of the data writing transistor T4.
  • the second polysilicon strip PL2 is electrically connected to the other end of the channel region T4Act of the data writing transistor T4, one end of the channel region T3Act of the driving transistor T3, and one end of the channel region T5Act of the first light emitting control transistor T5 and serves as the source of the first light emitting control transistor T5.
  • the third polysilicon strip PL3 is electrically connected to the other end of the channel region T5Act of the first light-emitting control transistor T5 and serves as the source of the first light-emitting control transistor T5.
  • the fourth polysilicon strip PL4 is electrically connected to the other end of the channel region T3Act of the drive transistor T3 and one end of the channel region T6Act of the second light-emitting control transistor T6 and serves as a part of the second node N2, and serves as the drain of the drive transistor T3 and the source of the second light-emitting control transistor T6.
  • the fifth polysilicon strip PL5 is electrically connected to the other end of the channel region T6Act of the second light-emitting control transistor T6 and one end of the channel region T7Act of the pixel electrode reset transistor T7 and serves as a part of the fourth node N4, and serves as the drain of the second light-emitting control transistor T6 and the drain of the pixel electrode reset transistor T7.
  • the sixth polysilicon strip PL6 is electrically connected to the other end of the channel region T7Act of the pixel electrode reset transistor T7 and serves as the source of the pixel electrode reset transistor T7.
  • the channel region T7Act of the pixel electrode reset transistor T7, the sixth polysilicon strip PL6, and a portion of the fifth polysilicon strip PL5 of the polysilicon pattern corresponding to the pixel driving circuit PDC can be arranged in the circuit layout area PDCA corresponding to the next row of pixel driving circuits PDC; correspondingly, the channel region T7Act of the pixel electrode reset transistor T7, the sixth polysilicon strip PL6, and a portion of the fifth polysilicon strip PL5 of the previous row of pixel driving circuits PDC are arranged in the circuit layout area PDCA corresponding to the pixel driving circuit PDC.
  • the channel region T3Act of the driving transistor T3 is bent so that the channel region T3Act of the driving transistor T3 has a greater length, for example, a length of 15 to 25 microns. Further, the area where the channel region T3Act of the driving transistor T3 is distributed can be completely located within the metal shading portion LSP in the positive projection of the metal shading layer LS. In this way, the metal shading portion LSP can shield the channel region T3Act of the driving transistor T3. Referring to FIG. 5 and FIG.
  • the first gate layer GT1 is provided with a first electrode plate CP1 of a storage capacitor Cst, and the first electrode plate CP1 of the storage capacitor Cst completely covers the channel region T3Act of the driving transistor T3; that is, the positive projection of the channel region T3Act of the driving transistor T3 on the first gate layer GT1 is located within the range of the first electrode plate CP1 of the storage capacitor Cst. In this way, the first electrode plate CP1 of the storage capacitor Cst can serve as the gate of the driving transistor T3.
  • the channel region T4Act of the data writing transistor T4 of the next row pixel driving circuit PDC is arranged adjacent to the channel region T7Act of the pixel electrode reset transistor T7 of the previous row pixel driving circuit PDC.
  • the data scanning line GPL carries the data scanning signal GP and extends substantially in the row direction.
  • the data scanning line GPL overlaps with the channel area T4Act of the data writing transistor T4.
  • the overlapped portion of the data scanning line GPL and the channel area T4Act of the data writing transistor T4 can be reused as the gate T4G of the data writing transistor T4.
  • the data scanning line GPL also overlaps with the channel area T7Act of the pixel electrode reset transistor T7.
  • the overlapped portion of the data scanning line GPL and the channel area T7Act of the pixel electrode reset transistor T7 can be reused as the gate of the pixel electrode reset transistor T7.
  • the data scanning signal GP loaded on the data scanning line GPL can be used as the pixel electrode reset signal RP at the same time, so that the data scanning line GPL can be reused as the pixel electrode reset line RPL.
  • the channel region T5Act of the first light emission control transistor T5 and the channel region T6Act of the second light emission control transistor T6 are arranged in the same row or substantially in the same row.
  • the first gate layer GT1 is provided with a light emission control trace EML for loading the light emission control signal EM and extending substantially in the row direction.
  • the light emission control trace EML overlaps with the channel region T5Act of the first light emission control transistor T5 and the channel region T6Act of the second light emission control transistor T6; the portion where the light emission control trace EML overlaps with the channel region T5Act of the first light emission control transistor T5 is reused as the gate of the first light emission control transistor T5, and the portion where the light emission control trace EML overlaps with the channel region T6Act of the second light emission control transistor T6 is reused as the gate of the second light emission control transistor T6.
  • Figure 9 shows a partial structural diagram of the second gate layer GT2 of the display panel of the present disclosure.
  • Figure 10 shows a partial structural diagram of the metal oxide semiconductor layer SEMI2 of the display panel of the present disclosure.
  • Figure 11 shows a partial structural diagram of the third gate layer GT3 of the display panel of the present disclosure.
  • the metal oxide semiconductor layer SEMI2 has a metal oxide pattern corresponding to each pixel driving circuit PDC, and the metal oxide pattern of the pixel driving circuit PDC is completely located in the circuit layout area PDCA corresponding to the pixel driving circuit PDC.
  • the metal oxide pattern of the pixel driving circuit PDC and the orthographic projection of the polysilicon pattern on the substrate BP do not overlap.
  • the metal oxide pattern of the pixel driving circuit PDC includes a channel region T1Act of the capacitor reset transistor T1 and a channel region T2Act of the threshold compensation transistor T2 that maintain semiconductor characteristics, and a first metal oxide portion OL1, a second metal oxide portion OL2, and a third metal oxide portion OL3 that are conductorized.
  • the first metal oxide portion OL1, the second metal oxide portion OL2, and the third metal oxide portion OL3 can be conductorized after the third gate layer GT3 is patterned.
  • the second metal oxide portion OL2 is electrically connected to one end of the channel region T1Act of the capacitor reset transistor T1 and one end of the channel region T2Act of the threshold compensation transistor T2 to serve as a part of the first node N1, and also serves as the drain of the capacitor reset transistor T1 and the drain of the threshold compensation transistor T2.
  • the first metal oxide portion OL1 is electrically connected to the other end of the channel region T1Act of the capacitor reset transistor T1 to serve as the source of the capacitor reset transistor T1; the third metal oxide portion OL3 is electrically connected to the other end of the channel region T2Act of the threshold compensation transistor T2 to serve as the source of the threshold compensation transistor T2.
  • the third gate layer GT3 is provided with a capacitor reset top routing GN2UL and a threshold compensation top routing GN1UL extending substantially in the row direction.
  • the capacitor reset top routing GN2UL is used to load the capacitor reset signal GN2, and has a channel definition portion GN2ULP of the capacitor reset top routing GN2UL overlapping with the channel region T1Act of the capacitor reset transistor T1, and the portion where the channel definition portion GN2ULP of the capacitor reset top routing GN2UL overlaps with the channel region T1Act of the capacitor reset transistor T1 is reused as the top gate T1GU of the capacitor reset transistor T1, and is used to define the boundary of the channel region T1Act of the capacitor reset transistor T1 in its length direction.
  • the threshold compensation top routing GN1UL is used to load the threshold compensation signal GN1, and has a channel defining portion GN1ULP of the threshold compensation top routing GN1UL that overlaps with the channel region T2Act of the threshold compensation transistor T2.
  • the portion of the channel defining portion GN1ULP of the threshold compensation top routing GN1UL that overlaps with the channel region T2Act of the threshold compensation transistor T2 is reused as the top gate T2GU of the threshold compensation transistor T2, and is used to define the boundary of the channel region T2Act of the threshold compensation transistor T2 in the length direction.
  • the second gate layer GT2 is provided with a capacitor reset bottom wiring GN2DL extending substantially in the row direction, a threshold compensation bottom wiring GN1DL, and a second electrode plate CP2 provided with storage capacitors Cst corresponding to each pixel driving circuit PDC.
  • the expanded portion GN2DLP of the capacitor reset bottom wiring GN2DL can not only load the capacitor reset signal GN2 to the channel region T1Act of the capacitor reset transistor T1 to eliminate the floating body effect of the capacitor reset transistor T1, but also shield the substrate base.
  • the channel area T1Act of the capacitor reset transistor T1 is kept stable by the light on one side of the plate BP.
  • the threshold compensation bottom routing GN1DL is used to load the threshold compensation signal GN1, and has an enlarged portion GN1DLP of the threshold compensation bottom routing GN1DL overlapping with the channel area T2Act of the threshold compensation transistor T2.
  • the positive projection of the channel definition portion GN1ULP of the threshold compensation top routing GN1UL on the second gate layer GT2 is completely located in the enlarged portion GN1DLP of the threshold compensation bottom routing GN1DL, which makes the positive projection of the channel area T2Act of the threshold compensation transistor T2 on the second gate layer GT2 completely located in the enlarged portion GN1DLP of the threshold compensation bottom routing GN1DL.
  • the enlarged portion GN1DLP of the threshold compensation bottom routing GN1DL can not only load the threshold compensation signal GN1 to the channel area T2Act of the threshold compensation transistor T2 to eliminate the floating body effect of the threshold compensation transistor T2, but also shield the light on one side of the substrate BP to keep the channel area T2Act of the threshold compensation transistor T2 stable.
  • the second electrode plate CP2 of the storage capacitor Cst is overlapped with the first electrode plate CP1 of the storage capacitor Cst to form the storage capacitor Cst.
  • the second electrode plate CP2 of the storage capacitor Cst has a notch CP2G, and the notch CP2G exposes a partial area of the first electrode plate CP1 of the storage capacitor Cst, so that the first electrode plate CP1 of the storage capacitor Cst can be connected to the first source-drain metal layer SD1 through a via located in the notch CP2G.
  • the second gate layer GT2 may also be provided with a first initialization voltage trace Vinit1L for loading the first initialization voltage Vinit1, and the first initialization voltage trace Vinit1L extends substantially in the row direction. Further, the capacitor reset bottom trace GN2DL is located between the threshold compensation bottom trace GN1DL and the first initialization voltage trace Vinit1L.
  • Figure 12 shows a schematic diagram of the partial structure of the first source-drain metal layer SD1 of the display panel of the present disclosure.
  • Figure 13 shows a schematic diagram of the partial structure of the second gate layer GT2, the metal oxide semiconductor layer SEMI2, the third gate layer GT3, and the first source-drain metal layer SD1 of the display panel of the present disclosure.
  • Figure 14 shows a schematic diagram of the partial structure of the transfer metal layer DRL of the display panel of the present disclosure.
  • the first source-drain metal layer SD1 is provided with the first conductive structure ML1 to the sixth conductive structure ML6, and is provided with a second initialization voltage trace Vinit2L extending substantially along the row direction and used to load the second initialization voltage Vinit2.
  • the second initialization voltage trace Vinit2L can be bent in the circuit layout area PDCA to avoid other conductive structures.
  • Figure 14 shows a schematic diagram of the structure of the transfer metal layer DRL of the circuit layout area corresponding to eight local sub-pixels of the display panel of the example disclosed in the present invention
  • Figure 15 shows a schematic diagram of the structure of the second source-drain metal layer SD2 of the circuit layout area corresponding to eight local sub-pixels of the display panel of the example disclosed in the present invention
  • Figure 16 shows a schematic diagram of the structural coordination of the transfer metal layer DRL and the second source-drain metal layer SD2 of the circuit layout area corresponding to eight local sub-pixels of the display panel of the example disclosed in the present invention.
  • the second source-drain metal layer SD2 includes a data line DL and a driving voltage line VDDL, and a pixel transfer structure PA;
  • the data line DL includes the first data line DL1, the second data line DL2, the third data line DL3A and the fourth data line DL3B.
  • the transfer metal layer DRL is provided with a second transfer metal structure TRP2 and a third transfer metal structure TRP3.
  • the second transfer metal structure TRP2 is electrically connected to the pixel transfer structure PA through a via hole, and is electrically connected to the output end of the pixel driving circuit through a via hole, for example, it is electrically connected to the sixth conductive structure ML6 located in the first source-drain metal layer through a via hole.
  • the pixel transfer structure PA is electrically connected to the pixel electrode of the sub-pixel through a via hole. In this way, the driving current of the pixel driving circuit can be loaded to the sub-pixel through the sixth conductive structure ML6, the second transfer metal structure TRP2, and the pixel transfer structure PA.
  • the third transfer metal structure TRP3 is electrically connected to the driving voltage line VDDL through a via, and provides a driving voltage to the pixel driving circuit through the via, for example, it is electrically connected to the second conductive structure ML2 located in the first source-drain metal layer SD1 through a via. In this way, the driving voltage of the driving voltage line VDDL is loaded to the pixel driving circuit through the third transfer metal structure TRP3 and the second conductive structure ML2.
  • a first transfer metal structure TRP1 is further provided in the transfer metal layer DRL in the circuit layout area of the display unit.
  • the first transfer metal structure TRP1 is electrically connected to the data line through a via, and a data voltage is loaded to the pixel driving circuit through the via, for example, it is electrically connected to the first conductive structure ML1 of the pixel driving circuit through the via.
  • the transfer metal layer DRL is also provided with a first transfer wire TRL1 and a second transfer wire TRL2.
  • the second display unit DU2 located in the first display unit column VDU1 is electrically connected to the second data line DL2 through the second transfer wire TRL2.
  • the first conductive structure ML1 of the second display unit DU2 located in the first display unit column VDU1 is electrically connected to the first end TRL21 of the second transfer wire TRL2 through a via hole
  • the second end TRL2 of the second transfer wire TRL2 is electrically connected to the first end TRL21 of the second transfer wire TRL2 through a via hole.
  • TRL22 is electrically connected to the second data line DL2 through a via.
  • the first display unit DU1 located in the second display unit column VDU2 is electrically connected to the first data line DL1 through the first adapter line TRL1.
  • the first conductive structure ML1 of the first display unit DU1 located in the second display unit column VDU2 is electrically connected to the first end TRL11 of the first adapter line TRL1 through a via
  • the second end TRL12 of the first adapter line TRL1 is electrically connected to the first data line DL1 through a via.
  • the transfer metal layer DRL includes the first transfer metal structure TRP1, the second transfer metal structure TRP2 and the third transfer metal structure TRP3.
  • the transfer metal layer DRL includes the first end TRL21 of the second transfer line, the second end TRL12 of the first transfer line, the second transfer metal structure TRP2 and the third transfer metal structure TRP3.
  • the transfer metal layer DRL includes the second end TRL22 of the second transfer line, the first end TRL11 of the first transfer line, the second transfer metal structure TRP2 and the third transfer metal structure TRP3; wherein the second end TRL12 of the first transfer line is electrically connected to the first end TRL11 of the first transfer line through TRL1; the second end TRL22 of the second transfer line is electrically connected to the first end TRL21 of the second transfer line through TRL2.
  • the shape of the first end TRL21 of the second adapter wire is the same as the shape of the first adapter metal structure TRP1; the second end TRL22 of the second adapter wire is adjacent to and insulated from the first end TRL11 of the first adapter wire; the shape of the first end TRL11 of the first adapter wire is the same as the shape of the second adapter metal structure TRP2; the second end TRL12 of the first adapter wire is adjacent to and insulated from the first end TRL21 of the second adapter wire.
  • the first display unit DU1 adjacent to the first data line DL1, the second display unit DU2 adjacent to the second data line DL2, and the data circuit of the driving circuit layer FA in the third display unit DU3 are The electrical conduction connection relationship between the voltage and the driving voltage is described in detail as follows. Take the third display unit DU3 in the third display unit column VDU3A as an example.
  • the first conductive structure ML1 overlaps with the first polysilicon strip PL1 and is electrically connected through a via hole.
  • the first conductive structure ML1 also overlaps with the first transfer metal structure TRP1 and is electrically connected through a via hole.
  • the first transfer metal structure TRP1 overlaps with the third data line DL3A and is electrically connected through a via hole. In this way, the data voltage Data loaded on the data line DL can be loaded to the first polysilicon strip PL1 as the source of the data writing transistor T4 through the first transfer metal structure TRP1 and the first conductive structure ML1.
  • the second conductive structure ML2 overlaps with the third polysilicon strip PL3 and is electrically connected through a via hole, overlaps with the second electrode plate CP2 of the storage capacitor Cst and is electrically connected through a via hole, and also overlaps with the third transfer metal structure TRP3 and is electrically connected through a via hole, and the third transfer metal structure TRP3 overlaps with the driving voltage line VDDL and is electrically connected through a via hole.
  • the driving voltage VDD loaded on the driving voltage line VDDL can be loaded to the second electrode plate CP2 of the storage capacitor Cst and the third polysilicon strip PL3 as the source of the first light-emitting control transistor T5 through the third transfer metal structure TRP3 and the second conductive structure ML2.
  • two adjacent second conductive structures ML2 are connected to each other, so that two adjacent driving voltage traces VDDL are electrically connected through the second conductive structure ML2.
  • the driving voltage VDD of the display panel in the display area AA is distributed in a grid, which can improve the signal uniformity of the driving voltage VDD, thereby avoiding the driving voltage VDD from causing the display panel to display unevenly due to voltage drop or current unevenness.
  • the third conductive structure ML3 overlaps with the second metal oxide portion OL2 and is electrically connected through a via, and also overlaps with the first electrode plate CP1 of the storage capacitor Cst and is electrically connected through a via.
  • the via between the third conductive structure ML3 and the first electrode plate CP1 of the storage capacitor Cst can pass through the gap CP2G.
  • the second metal oxide portion OL2 which is a drain of the threshold compensation transistor T2, a drain of the capacitor reset transistor T1 and a part of the first node N1, is electrically connected to the second electrode plate CP2 of the storage capacitor Cst through the third conductive structure ML3.
  • the fourth conductive structure ML4 overlaps with the first initialization voltage trace Vinit1L and is electrically connected through a via hole, and overlaps with the first metal oxide portion OL1 and is electrically connected through a via hole.
  • the electrical structure ML4 is electrically connected to the first initialization voltage wiring Vinit1L.
  • the first initialization voltage Vinit1 loaded on the first initialization voltage wiring Vinit1L can be loaded to the source of the capacitor reset transistor T1.
  • the fifth conductive structure ML5 overlaps and is electrically connected to the third metal oxide portion OL3, and also overlaps and is electrically connected to the fourth polysilicon strip PL4.
  • the third metal oxide portion OL3, which is the source of the threshold compensation transistor T2 is electrically connected to the fourth polysilicon strip PL4, which is a drain of the driving transistor T3, a source of the second light emission control transistor T6, and a part of the second node N2, through the fifth conductive structure ML5.
  • the sixth conductive structure ML6 overlaps with the fifth polysilicon strip PL5 and is electrically connected through a via hole, and also overlaps with the second transfer metal structure TRP2 and is electrically connected through a via hole, and the second transfer metal structure TRP2 overlaps with the pixel transfer structure PA and is electrically connected through a via hole.
  • the fifth polysilicon strip PL5 which is the drain of the second light-emitting control transistor T6, the drain of the pixel electrode reset transistor T7, and a part of the fourth node N4, is electrically connected to the pixel transfer structure PA through the sixth conductive structure ML6 and the third transfer metal structure TRP3, and the pixel transfer structure PA is used to be electrically connected to the pixel electrode of the sub-pixel, as shown in FIGS. 15 and 16 .
  • the driving voltage line VDDL has a first avoidance gap on one side close to the first data line DL1; the orthographic projection of the second end TRL12 of the first adapter line TRL1 on the plane where the display panel PNL is located is located within the orthographic projection of the first avoidance gap on the plane where the display panel PNL is located.
  • the driving voltage line VDDL has a second avoidance gap on one side close to the second data line DL2; the orthographic projection of the second end TRL22 of the second adapter line on the plane where the display panel PNL is located is located within the orthographic projection of the second avoidance gap on the plane where the display panel PNL is located.
  • the first data line DL1 has a first side branch LBP1 extending deep into the first avoidance gap, and the first side branch LBP1 is electrically connected to the second end TRL12 of the first adapter line TRL1 through a via.
  • the second data line DL2 has a second side branch LBP2 extending deep into the second avoidance gap, and the second side branch LBP2 is electrically connected to the second end TRL22 of the second adapter line through a via.
  • the first conductive structure ML1 corresponding to the first display unit DU1 adjacent to the second data line DL2 is connected to the first transfer line through a via hole.
  • the first end TRL11 of TRL1 is electrically connected, the second end TRL12 of the first adapter line TRL1 is electrically connected to the first side branch portion LBP1 through a via, and the first side branch portion LBP1 is electrically connected to the first data line DL1.
  • the data voltage loaded on the first data line DL1 can be loaded to the first polysilicon strip PL1 of the source of the data write transistor T4 corresponding to the first display unit DU1 adjacent to the second data line DL2 through the first side branch portion LBP1, the second end TRL12 of the first transfer line TRL1, the first transfer line TRL1, the first end TRL11 of the first transfer line TRL1, and the first conductive structure ML1.
  • the first conductive structure ML1 corresponding to the second display unit DU2 adjacent to the first data line DL1 is electrically connected to the first end TRL21 of the second transfer line TRL2 through a via
  • the second end TRL22 of the second transfer line is electrically connected to the second side branch portion LBP2 through a via
  • the second side branch portion LBP2 is electrically connected to the second data line DL2.
  • the data voltage loaded on the second data line DL2 can be loaded to the first polysilicon strip PL1 of the source of the data writing transistor T4 corresponding to the second display unit DU2 adjacent to the first data line DL1 through the second side branch portion LBP2, the second end TRL22 of the second transfer line, the second transfer line TRL2, the first end TRL21 of the second transfer line TRL2, and the first conductive structure ML1.
  • the cross-bridge connection between the second display unit DU2 adjacent to the first data line DL1 and the second data line DL2 and the cross-bridge connection between the first display unit DU1 adjacent to the second data line DL2 and the first data line DL1 are realized.
  • the disclosed embodiment also provides a method for driving a display panel PNL, the method comprising: driving each DU row by row; when driving any HDU, loading the driving voltage required by the first display unit DU1 of the display unit set DUS onto the first data line DL1 corresponding to the display unit set DUS, and loading the driving voltage required by the second display unit DU2 of the display unit set DUS onto the second data line DL2 corresponding to the display unit set DUS.
  • the first data line DL1 and the second data line DL2 are prevented from alternately controlling the first display unit DU1 and the second display unit DU2 to generate additional energy consumption.

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Abstract

一种显示面板（PNL）及其驱动方法。显示面板（PNL）包括沿行方向（DH）依次排列的多个显示单元集（DUS）；显示单元集（DUS）包括位于不同显示单元列（VDU）的多个第一显示单元（DU1）和位于不同显示单元列（VDU）的多个第二显示单元（DU2）；显示面板（PNL）还设置有与显示单元集（DUS）对应的第一数据走线（DL1）和第二数据走线（DL2）；显示单元集（DUS）的各个第一显示单元（DU1）均与第一数据走线（DL1）电连接，显示单元集（DUS）的各个第二显示单元（DU2）均与对应的第二数据走线（DL2）电连接。显示面板（PNL）能够降低功耗。

Description

一种显示面板及其驱动方法
交叉引用
本公开要求于2023年10月31日提交的申请号为202311434410.2、名称为“一种显示面板及其驱动方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及像素数据线布局技术领域，具体而言，涉及一种显示面板及其驱动方法。
背景技术
Pentile像素排布方式中，红色子像素和蓝色子像素共用一条数据线，数据线上的电压在奇数行和偶数行每行都要进行一次电压刷新，并且是从L255～L0之间循环跳变，从而产生额外的功耗。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种显示面板及其驱动方法，降低显示面板的功耗。
根据本公开的一个方面，提供一种显示面板，包括沿行方向依次排列的多个显示单元集；所述显示单元集包括位于不同显示单元列的多个第一显示单元和位于不同显示单元列的多个第二显示单元；
所述显示面板还设置有与所述显示单元集对应的第一数据走线和第二数据走线；所述显示单元集的各个第一显示单元均与第一数据走线电连接，所述显示单元集的各个第二显示单元均与对应的第二数据走线电连接。
根据本公开的一种实施方式，所述显示单元集包括与所述第一数据走线相邻设置的第一显示单元列和与所述第二数据走线相邻设置的第二显 示单元列；所述第一显示单元列包括沿列方向依次交替设置的第一显示单元和第二显示单元；所述第二显示单元列包括沿列方向依次交替设置的第二显示单元和第一显示单元。
根据本公开的一种实施方式，在同一所述显示单元行中，所述第一显示单元和所述第二显示单元交替设置。
根据本公开的一种实施方式，所述显示单元集包括沿行方向依次排列的第一显示单元列、第三显示单元列、第二显示单元列和第四显示单元列；所述第三显示单元列和所述第四显示单元列均包括沿列方向依次排列的多个第三显示单元。
根据本公开的一种实施方式，同一所述显示单元行中，每行子像素包括一个第一显示单元、一个第二显示单元和两个第三显示单元。
根据本公开的一种实施方式，所述显示面板还设置有与所述显示单元集对应的第三数据走线和第四数据走线；
所述第三显示单元列的各个第三显示单元均与第三数据走线电连接，所述第四显示单元列的各个第三显示单元均与第四数据走线电连接。
根据本公开的一种实施方式，所述第三数据走线和所述第一数据走线相邻设置，且位于所述第一显示单元列的各个像素驱动电路和第三显示单元列的各个像素驱动电路之间；
所述第四数据走线和所述第二数据走线相邻设置，且位于所述第二显示单元列的各个像素驱动电路和第四显示单元列的各个像素驱动电路之间。
根据本公开的一种实施方式，所述显示面板设置有第一转接线和第二转接线；
位于所述第一显示单元列的第二显示单元通过所述第二转接线与所述第二数据走线电连接；
位于所述第二显示单元列的第一显示单元通过所述第一转接线与所 述第一数据走线电连接。
根据本公开的一种实施方式，所述显示面板包括依次层叠设置的衬底基板、驱动电路层和像素层；所述驱动电路层包括依次层叠设置的晶体管层、第一源漏金属层、转接金属层和第二源漏金属层；显示单元的像素驱动电路的各个晶体管设置于所述晶体管层；所述显示单元的子像素设置于像素电极层；
所述第二源漏金属层设置有所述第一数据走线和所述第二数据走线；
所述转接金属层设置有第一转接金属结构、第一转接线和第二转接线；其中，
与所述第一数据走线相邻的所述第一显示单元的像素驱动电路的数据电压输入端，通过过孔与第一显示单元对应的所述第一转接金属结构电连接；所述第一转接金属结构通过过孔与所述第一数据走线电连接；
与所述第二数据走线相邻的所述第二显示单元的像素驱动电路的数据电压输入端通过过孔与第二显示单元对应的所述第一转接金属结构电连接，所述第一转接金属结构通过过孔与所述第二数据走线电连接；
与所述第二数据走线相邻的所述第一显示单元的像素驱动电路的数据电压输入端通过过孔与所述第一转接线的第一端电连接，所述第一转接线的第二端通过过孔与所述第一数据走线电连接；
与所述第一数据走线相邻的所述第二显示单元的像素驱动电路的数据电压输入端通过过孔与所述第二转接线的第一端电连接，所述第二转接线的第二端通过过孔与所述第二数据走线电连接。
根据本公开的一种实施方式，所述第二转接线的第一端的形状与所述第一转接金属结构的形状相同；所述第二转接线的第二端与所述第一转接线的第一端相邻且绝缘；
所述第一转接线的第一端的形状与所述第一转接金属结构的形状相同；所述第一转接线的第二端与所述第二转接线的第一端相邻且绝缘。
根据本公开的一种实施方式，所述第二源漏金属层还包括驱动电压走线；
所述驱动电压走线靠近所述第一数据走线的一侧具有第一避让缺口；所述第一转接线的第二端在所述显示面板所在平面上的正投影，位于所述第一避让缺口在所述显示面板所在平面上的正投影内；
所述驱动电压走线靠近所述第二数据走线的一侧具有第二避让缺口；所述第二转接线的第二端在所述显示面板所在平面上的正投影，位于所述第二避让缺口在所述显示面板所在平面上的正投影内。
根据本公开的一种实施方式，所述第一数据走线具有深入所述第一避让缺口的第一侧枝部，所述第一侧枝部与所述第一转接线的第二端通过过孔电连接；
所述第二数据走线具有深入所述第二避让缺口的第二侧枝部，所述第二侧枝部与所述第二转接线的第二端通过过孔电连接。
根据本公开的另一个方面，提供一种显示面板的驱动方法，包括：逐行驱动各个显示单元；
在驱动任意一个显示单元行时，将所述显示单元集的第一显示单元所需的驱动电压加载至所述显示单元集对应的第一数据走线上，将所述显示单元集的第二显示单元所需的驱动电压加载至所述显示单元集对应的第二数据走线上。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中显示面板的结构示意图。
图2为本公开一种实施方式中，显示面板的结构示意图。
图3为本公开一种实施方式中，显示面板的剖面结构示意图。
图4为本公开一种实施方式中，像素驱动电路的等效电路图。
图5为本公开一种实施方式的电路布图区中，多晶硅半导体层、第一栅极层、第二栅极层、金属氧化物半导体层、第三栅极层、第一源漏金属层的层叠结构示意图。
图6为本公开一种实施方式中，金属遮光层的局部结构示意图。
图7为本公开一种实施方式中，多晶硅半导体层的局部结构示意图。
图8为本公开一种实施方式中，第一栅极层的局部结构示意图。
图9为本公开一种实施方式中，第二栅极层的局部结构示意图。
图10为本公开一种实施方式中，金属氧化物半导体层的局部结构示意图。
图11为本公开一种实施方式中，第三栅极层的局部结构示意图。
图12为本公开一种实施方式中，第一源漏金属层的局部结构示意图。
图13为本公开一种实施方式中，第二栅极层、金属氧化物半导体层、第三栅极层和第一源漏金属层的层叠结构示意图。
图14为本公开一种实施方式中，转接金属层的局部结构示意图。
图15为本公开一种实施方式中，第二源漏金属层的层叠结构示意图。
图16为本公开一种实施方式中，转接金属层、第二源漏金属层的层叠结构示意图。
图17为本公开一种实施方式中，转接金属层、第二源漏金属层、像素层的层叠结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反， 提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
在本公开中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区，并且电流可以流过漏极、沟道区以及源极。沟道区是指电流主要流过的区域。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”是可以互相调换的、相对的概念。
在本公开中，当描述结构A和结构B交叠设置时，指的是结构A和结构B设置于不同的膜层，且结构A在衬底基板上的正投影与结构B在衬底基板上的正投影存在重合的部分。
在本公开中，结构C与结构D的交叠部分，指的是结构C中的特定部分C1；该特定部分C1在衬底基板上的正投影，即为结构C在衬底基板上的正投影和结构D在衬底基板上的正投影的重合部分。
在本公开中，结构层E位于结构层F远离衬底基板的一侧，可以理解为，结构层E在结构层F远离衬底基板的一侧形成。当结构层F为图案化结构时，结构层E的部分结构也可以位于结构层E的同一物理高度或低于结构层E的物理高度，其中，衬底基板为高度基准。
图1为相关技术中的一种显示面板的结构示意图。参见图1，在相关技术中，显示面板具有显示单元列和与显示单元列一一对应的数据走线DL。其中，显示单元列的各个像素驱动电路PDC均电连接于该显示单元列对应的数据走线DL。其中一些显示单元列，具有不同颜色的显示 单元DU，这些不同颜色的显示单元DU受到同一个数据走线DL的驱动。举例而言，至少一个显示单元列包括交替设置的红色显示单元和蓝色显示单元；数据走线上的电压在奇数行和偶数行每行都要进行一次电压刷新，并且是从灰度Lmax～灰度L0之间循环跳变，从而导致额外功耗的产生。其中，灰度Lmax为显示面板的灰阶的最大值，例如为255灰阶。
本公开提供一种显示面板PNL，参见图2，显示面板PNL包括显示区AA和位于显示区AA至少一侧的外围区BB。在显示区AA中，显示面板PNL设置有阵列分布的显示单元DU(例如图2中的第一显示单元DU1、第二显示单元DU2、第三显示单元DU3)，所述显示单元DU包括子像素PIX(例如图2中的第一子像素PIX1、第二子像素PIX2、第三子像素PIX3)和驱动所述子像素PIX的像素驱动电路PDC。所述显示面板PNL在外围区BB不设置显示单元DU，或者所设置的显示单元DU不用于显示画面。所述显示面板PNL在所述显示区AA设置有沿行方向DH延伸的多个扫描线(图2中未示出)，各个扫描线与各个显示单元行HDU一一对应设置。所述显示单元行的各个显示单元DU的像素驱动电路PDC，均与对应的扫描线电连接。所述显示面板PNL在显示区AA还设置有沿列方向DV延伸的多个数据走线DL。各个数据走线DL与各个显示单元列VDU一一对应设置。每个显示单元DU的像素驱动电路PDC与一个扫描线和一个数据走线DL连接。当扫描走线上加载扫描信号时，可以使得数据走线DL上加载的驱动电压写入像素驱动电路PDC中，进而使得像素驱动电路PDC可以根据所写入的驱动电压来控制子像素PIX的亮度。
该显示面板PNL包括沿行方向DH依次排列的多个显示单元集DUS(图2中仅示例了一个)；参见图2，所述显示单元集DUS包括位于不同显示单元列VDU的多个第一显示单元DU1和位于不同显示单元列VDU的多个第二显示单元DU2。所述显示面板PNL还设置有与所述显示单元集DUS对应的第一数据走线DL1和第二数据走线DL2。显示单元集DUS的各个第一显示单元DU1均与第一数据走线DL1电连接，显示单元集 DUS的各个第二显示单元DU2均与对应的第二数据走线DL2电连接。如此，第一数据走线DL1可用于加载控制各个第一显示单元DU1的数据电压，第二数据走线DL2可用于加载控制各个第二显示单元DU2的数据电压，避免了同一数据走线同时控制第一显示单元DU1和第二显示单元DU2所产生的额外功耗，降低了显示面板的功耗。
可以理解的是，第一数据走线DL1上的电压信号按照预设控制时序依次写入各个第一显示单元DU1的像素驱动电路PDC中，第二数据走线DL2上的电压信号按照预设控制时序依次写入各个第二显示单元DU2的像素驱动电路PDC中，通过像素驱动电路PDC实现对对应子像素PIX的控制。
在本公开的一种实施方式中，如图2所示，所述显示单元集DUS包括沿行方向DH依次排列的第一显示单元列VDU1、第三显示单元列VDU3A、第二显示单元列VDU2和第四显示单元列VDU3B。第一显示单元列VDU1与第一数据走线DL1相邻设置，第二显示单元列VDU2与第二数据走线DL2相邻设置。在一种示例中，第一显示单元列VDU1包括沿DV依次交替设置的第一显示单元DU1和第二显示单元DU2；所述第二显示单元列VDU2包括沿DV依次交替设置的第二显示单元DU2和第一显示单元DU1。第一显示单元列VDU1中第二显示单元DU2与第二数据走线DL2电连接，第二显示单元列VDU2中的第一显示单元DU1与第一数据走线DL1电连接。如此，在保持现有像素排布方式不变的前提下，实现在一个显示单元集DUS中，第一数据走线DL1对第一显示单元DU1的控制，第二数据走线DL2对第二显示单元DU2的控制。
在本公开的一种实施方式中，显示面板PNL还设置有与显示单元集DUS对应的第三数据走线DL3A和第四数据走线DL3B。其中，第三显示单元列VDU3A与第三数据走线DL3A相邻设置，第四显示单元列VDU3B与第四数据走线DL3B相邻设置，所述第三显示单元列VDU3A和所述第 四显示单元列VDU3B均包括沿DV依次排列的多个第三显示单元DU3。第三显示单元列VDU3A的各个第三显示单元DU3均与第三数据走线DL3A电连接，第四显示单元列VDU3B的各个第三显示单元DU3均与第四数据走线DL3B电连接。
在本公开的一种实施方式中，显示单元集DUS中，同一所述显示单元行包括一个第一显示单元DU1、一个第二显示单元DU2和两个第三显示单元DU3。同一所述显示单元行中，所述第一显示单元DU1和所述第二显示单元DU2交替设置。举例而言，如图2所示，显示单元集DUS中第一显示单元行的子像素依次为第一显示单元DU1、第三显示单元DU3、第二显示单元DU2、第三显示单元DU3；则相邻的第二显示单元行的子像素依次为第二显示单元DU2、第三显示单元DU3、第一显示单元DU1、第三显示单元DU3。
在本公开的一种实施方式中，第三数据走线DL3A和所述第一数据走线DL1相邻设置，且所述第三数据走线DL3A和第一数据走线DL1均位于所述第一显示单元列VDU1的各个像素驱动电路PDC和第三显示单元列VDU3A的各个像素驱动电路PDC之间；第四数据走线DL3B和所述第二数据走线DL2相邻设置，且所述第四数据走线DL3B和第二数据走线DL2均位于所述第二显示单元列VDU2的各个像素驱动电路PDC和第四显示单元列VDU3B的各个像素驱动电路PDC之间。
在本公开的一种实施方式中，参见图2，显示面板PNL设置有第一转接线TRL1和第二转接线TRL2；位于所述第一显示单元列VDU1的第二显示单元DU2通过所述第二转接线TRL2与所述第二数据走线DL2电连接；位于所述第二显示单元列VDU2的第一显示单元DU1通过所述第一转接线TRL1与所述第一数据走线DL1电连接。如此，通过第一转接线TRL1和第二转接线TRL2的桥接，使得在原有像素排布的基础上，实现同一数据走线DL只需要控制一种颜色的显示单元DU，在不影响现有像 素排布的基础上，减低显示面板的功耗。
在本公开的一种实施方式中，第一显示单元DU1包括像素驱动电路PDC和所述像素驱动电路PDC驱动的第一子像素PIX1；第二显示单元DU2包括像素驱动电路PDC和所述像素驱动电路PDC驱动的第二子像素PIX2；第三显示单元DU3包括像素驱动电路PDC和所述像素驱动电路PDC驱动的第三子像素PIX3。其中，第一子像素PIX1、第二子像素PIX2和第三子像素PIX3的颜色不同；进一步的，第一子像素PIX1、第二子像素PIX2和第三子像素PIX3的尺寸不同。
在一种示例中，第一子像素PIX1、第二子像素PIX2和第三子像素PIX3的尺寸依次减小。
在一种示例中，第一子像素PIX1为蓝色子像素；第二子像素PIX2为红色子像素；第三子像素PIX3为绿色子像素。
图3示例了本公开实施方式中一种显示面板的剖视结构示意图。显示面板包括依次层叠设置的衬底基板BP、驱动电路层FA和像素层FB。
衬底基板BP可以为无机材料的衬底基板BP，也可以为有机材料的衬底基板BP。举例而言，在本公开的一种实施方式中，衬底基板BP的材料可以为钠钙玻璃(soda-lime glass)、石英玻璃、蓝宝石玻璃等玻璃材料，或者可以为不锈钢、铝、镍等金属材料。在本公开的另一种实施方式中，衬底基板BP的材料可以为聚甲基丙烯酸甲酯(Polymethyl methacrylate，PMMA)、聚乙烯醇(Polyvinyl alcohol，PVA)、聚乙烯基苯酚(Polyvinyl phenol，PVP)、聚醚砜(Polyether sulfone，PES)、聚酰亚胺、聚酰胺、聚缩醛、聚碳酸酯(Poly carbonate，PC)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，PET)、聚萘二甲酸乙二酯(Polyethylene naphthalate，PEN)或其组合。在本公开的另一种实施方式中，衬底基板BP也可以为柔性衬底基板BP，例如衬底基板BP的材料可以为聚酰亚胺(polyimide，PI)。衬底基板BP还可以为多层材料的复合，举例而言，在本公开的一种实施方式 中，衬底基板BP可以包括依次层叠设置的底膜层(Bottom Film)、压敏胶层、第一聚酰亚胺层和第二聚酰亚胺层。
作为一种示例，在图3中，衬底基板BP的材料为聚酰亚胺，以使得显示面板为柔性显示面板。参见图3，显示面板可以先形成于一支撑基板SBP上，在制备完成后可以剥离支撑基板SBP。这样，在制程过程中，支撑基板SBP可以为显示面板提供支撑。
驱动电路层FA设置有用于驱动子像素的像素驱动电路PDC。驱动电路层FA包括晶体管层，显示单元DU的像素驱动电路PDC的各个晶体管设置于所述晶体管层。在驱动电路层FA中，任意一个像素驱动电路PDC可以包括有晶体管和存储电容。在图3的示例中，该驱动电路层可以设置有多晶硅半导体层SEMI1和金属氧化物半导体层SEMI2，以使得该驱动电路层中的晶体管可以同时包括金属氧化物晶体管和多晶硅晶体管(例如低温多晶硅晶体管)。进一步的，这些晶体管可以为薄膜晶体管。当然的，在本公开的其他实施方式是中，多晶硅晶体管也可以为非晶硅晶体管；相应的，驱动电路层的多晶硅半导体层SEMI1可以被替换为非晶硅半导体层。
在本公开的一种实施方式中，多晶硅晶体管可以为顶栅型薄膜晶体管、底栅型薄膜晶体管或者双栅型薄膜晶体管，以能够有效控制晶体管为准。金属氧化物晶体管为双栅型薄膜晶体管，即晶体管的沟道区夹设于顶栅极(远离衬底基板一侧的栅极)和底栅极(靠近衬底基板一侧的栅极)之间；这样，底栅极可以遮挡来自衬底基板一侧的光线，避免光线照射至晶体管的沟道区而导致晶体管工作异常。
在本公开的一些实施方式中，多晶硅晶体管的栅极可以与金属氧化物晶体管的一个栅极同层设置，例如多晶硅晶体管的栅极与金属氧化物晶体管的底栅极设置于同一栅极层。在另外一些实施方式中，多晶硅晶体管的栅极与金属氧化物晶体管的顶栅极和底栅极可以分别设置在不同的栅极层。
作为一种示例，参见图3，驱动电路层包括依次层叠设置于衬底基板BP一侧的多晶硅半导体层SEMI1、第一栅极绝缘层GI1、第一栅极层GT1、第二缓冲层Buff2、第二栅极层GT2、第二栅极绝缘层GI2、金属氧化物半导体层SEMI2、第三栅极绝缘层GI3、第三栅极层GT3。其中，多晶硅半导体层SEMI1设置有多晶硅晶体管的有源区，第一栅极层GT1设置有多晶硅晶体管的栅极。金属氧化物半导体层SEMI2设置有金属氧化物晶体管的有源区；第二栅极层GT2设置有金属氧化物晶体管的底栅极；第三栅极层GT3设置有金属氧化物晶体管的顶栅极。在本公开中，晶体管的有源区包括晶体管的沟道区和位于沟道区两侧的源极和漏极；其中，沟道区保持半导体特性，源极和漏极被导体化。
在一种示例中，显示面板还具有用于向晶体管的栅极加载控制信号的控制走线。这些控制走线可以基本沿行方向延伸且与所驱动的晶体管的栅极电连接。
在本公开的实施方式中，驱动电路层还包括金属层，金属层位于各个栅极层和半导体层远离衬底基板BP的一侧。金属层设置有用于加载数据电压Data的数据走线DL和用于加载驱动电压VDD的驱动电压走线VDDL；数据走线DL用于向像素驱动电路PDC加载数据电压Data，以使得像素驱动电路PDC根据数据电压Data的电压值控制子像素的亮度。在图3的示例中，金属层为三层，包括层叠设置的第一源漏金属层SD1、转接金属层DRL和第二源漏金属层SD2。在第一源漏金属层SD1靠近衬底基板BP的表面设置有层间电介质层ILD，在第一源漏金属层SD1与转接金属层DRL之间设置有第一平坦化层PLN1，在转接金属层DRL与第二源漏金属层SD2之间设置有第二平坦化层PLN2，在第二源漏金属层SD2远离衬底基板BP的一侧设置有第三平坦化层PLN3。
可选地，驱动电路层FA还可以包括设于衬底基板BP与半导体层之间的第一缓冲层Buff1，且半导体层和栅极层等均位于第一缓冲层Buff1远离衬底基板BP的一侧。第一缓冲层Buff1的材料可以为氧化硅、氮化硅等无机绝缘材料。第一缓冲层Buff1可以为一层无机材料层，也可以为多层层叠的无机材料层。
可选地，驱动电路层FA还可以包括位于第一缓冲层Buff1与衬底基板BP之间的金属遮光层LS，金属遮光层LS可以屏蔽至少部分晶体管的沟道区。进一步地，在一些实施方式中，金属遮光层LS可以与金属层通过过孔电连接，这样，金属遮光层LS可以根据需要而发挥传输信号、屏蔽信号或者其他功能。举例而言，金属遮光层LS可以被加载公共电极电压以使得该金属遮光层LS能够达成信号屏蔽的作用。再例如，金属遮光层LS的局部被图案化为导线，以使得位于金属遮光层LS的导线可以用于传输信号，例如传输触控信号等。
可选的，在金属遮光层LS与第一缓冲层Buff1之间，还可以设置有无机阻挡层Barr，以阻挡衬底基板BP中的材料向驱动电路层渗透。
像素层FB设置有阵列分布的发光元件，且各个发光元件在像素驱动电路的控制下发光。这些发光元件可以作为本公开实施方式的子像素。在本公开中，发光元件可以为有机电致发光二极管(OLED)、微发光二极管(Micro LED)、量子点-有机电致发光二极管(QD-OLED)、量子点发光二极管(QLED)或者其他类型的发光元件。示例性地，如下，以发光元件为有机电致发光二极管为例，对像素层的一种可行结构进行示例性的介绍。
在该示例中，像素层FB可以设置于驱动电路层FA远离衬底基板BP的一侧，其可以包括依次层叠设置的像素电极层ANL、像素定义层PDL、支撑柱层PS、有机发光功能层EL和公共电极层COML。其中，像素电极层ANL在显示面板的显示区具有多个像素电极；像素定义层PDL在显示区具有与多个像素电极一一对应设置的多个贯通的像素开口，任意一个像素开口暴露对应的像素电极的至少部分区域。支撑柱层PS在显示区包括多个支撑柱，且支撑柱位于像素定义层PDL远离衬底基板BP的表面，以便在蒸镀制程中支撑精细金属掩模版(Fine Metal Mask，FMM)。有机发光功能层EL至少覆盖被像素定义层PDL所暴露的像素电极。其中，有机发光功能层EL可以包括有机电致发光材料层，以及可以包括有空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中 的一种或者多种。可以通过蒸镀工艺制备有机发光功能层EL的各个膜层，且在蒸镀时可以采用精细金属掩模版或者开放式掩膜板(Open Mask)定义各个膜层的图案。公共电极层COML在显示区可以覆盖有机发光功能层EL。如此，像素电极、公共电极层COML和位于像素电极和公共电极层COML之间的有机发光功能层EL形成有机发电致光二极管，任意一个有机电致发光二极管可以作为显示面板的一个子像素。在该实施方式中，参见图17，子像素PIX可以包括多种不同颜色的子像素PIX，例如包括用于发出红光的红色子像素R、用于发出蓝光的蓝色子像素B和用于发出绿光的绿色子像素G。
在一些实施方式中，像素层FB还可以包括位于公共电极层COML远离衬底基板BP一侧的光取出层，以增强有机发光二极管的出光效率。
可选地，显示面板还可以包括薄膜封装层TFE。薄膜封装层TFE设于像素层FB远离衬底基板BP的表面，可以包括交替层叠设置的无机封装层和有机封装层。其中，无机封装层可以有效的阻隔外界的水分和氧气，避免水氧入侵有机发光功能层EL而导致材料降解。可选地，无机封装层的边缘可以位于外围区。有机封装层位于相邻的两层无机封装层之间，以便实现平坦化和减弱无机封装层之间的应力。其中，有机封装层的边缘，可以位于显示区的边缘和无机封装层的边缘之间。示例性地，薄膜封装层TFE包括依次层叠于像素层FB远离衬底基板BP一侧的第一无机封装层、有机封装层和第二无机封装层。
在本公开的一种实施方式中，像素驱动电路PDC包括存储电容Cst和多个晶体管，其中，晶体管中的一部分可以为多晶硅晶体管，另外一部分可以为金属氧化物晶体管。
图4提供了一种像素驱动电路PDC作为示例。参见图4，该示例性的像素驱动电路PDC包括存储电容Cst、阈值补偿晶体管T2、驱动晶体管T3、电容复位晶体管T1、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和像素电极复位晶体管T7等晶体管。其中，所述阈值补偿晶体管T2为金属氧化物晶体管，用于响应阈值补偿信号GN1而 对所述驱动晶体管T3的阈值电压进行补偿。驱动晶体管T3为多晶硅晶体管，可以在第一节点N1的控制下产生驱动电流。可以理解的是，在本公开的其他示例中，像素驱动电路PDC还可以包括其他的晶体管或者存储电容Cst，或者可以具有更少的晶体管；各个晶体管之间的电连接关系以及所加载的信号、所加载的信号的时序也可以与图3中示例的像素驱动电路PDC不同。
如下，以图4示例的像素驱动电路PDC为例，对本公开实施方式的显示面板的结构、原理和效果做进一步地介绍和说明。
在图4示例的像素驱动电路PDC中，存储电容Cst的第一电极板与第一节点N1电连接，且存储电容Cst的第二电极板用于加载驱动电压VDD。这样，存储电容Cst的第二电极板上所加载的电压稳定。在本公开的另外一些实施方式中，存储电容Cst的第二电极板可以加载其他电源电压，例如与公共电极层加载相同的公共电压。当然的，在本公开的其他实施方式中，存储电容的第二电极板的电压还可以不恒定，例如电容复位晶体管的漏极和数据写入晶体管的漏极与存储电容的第二电极板电连接；电容复位晶体管用于对存储电容的第二电极板的电压进行复位，数据写入晶体管用于将数据电压加载至存储电容的第二电极板；通过耦合作用，第一节点的电压可以随着存储电容的第二电极板的电压的调整而调整。
在图4示例的像素驱动电路PDC中，像素驱动电路PDC还包括第一发光控制晶体管T5和第二发光控制晶体管T6，第一发光控制晶体管T5的源极用于加载驱动电压VDD，例如与用于加载驱动电压VDD的数据走线DL电连接。第一发光控制晶体管T5的漏极与第三节点N3电连接。第二发光控制晶体管T6的源极与第二节点N2电连接，第二发光控制晶体管T6的漏极与第四节点N4电连接，第四节点N4还与子像素的像素电极电连接。第一发光控制晶体管T5的栅极和第二发光控制晶体管T6的栅极用于加载发光控制信号EM，例如与用于加载发光控制信号EM的发光控制走线EML电连接。当第一发光控制晶体管T5和第二发光控制晶体管T6响应发光控制信号EM而导通时，驱动晶体管T3所产生的驱动电流可以流向子像素，进而驱动子像素发光。进一步地，第一发光控制晶体管T5和第二发光控制晶体管T6可以为多晶硅晶体管。当然的，在本公开的 其他实施方式中，像素驱动电路PDC可以仅包括第一发光控制晶体管T5和第二发光控制晶体管T6中的一个。
在图4示例的像素驱动电路PDC中，像素驱动电路PDC还包括电容复位晶体管T1和数据写入晶体管T4。其中，电容复位晶体管T1的源极用于加载第一初始化电压Vinit1，电容复位晶体管T1的漏极与第一节点N1电连接；电容复位晶体管T1用于响应电容复位信号GN2而将第一初始化电压Vinit1加载至第一节点N1，实现对第一节点N1的复位。在该示例中，电容复位晶体管T1为金属氧化物半导体晶体管；在本公开的其他示例中，电容复位晶体管T1也可以为多晶硅晶体管。数据写入晶体管T4为多晶硅晶体管。其中，数据写入晶体管T4的源极用于加载数据电压Data，例如与用于加载数据电压Data的数据走线DL电连接；数据写入晶体管T4的漏极与第三节点N3电连接；数据写入晶体管T4用于响应数据扫描信号GP而将数据电压Data加载至第三节点N3。
在图4示例的像素驱动电路PDC中，像素驱动电路PDC还包括像素电极复位晶体管T7，像素电极复位晶体管T7为多晶硅晶体管；像素电极复位晶体管T7的源极用于加载第二初始化电压Vinit2，例如与用于加载第二初始化电压Vinit2的第二初始化电压走线Vinit2L电连接。像素电极复位晶体管T7的漏极与第四节点N4电连接，像素电极复位晶体管T7用于响应像素电极复位信号RP而将第二初始化电压Vinit2加载至第四节点N4，进而对子像素的像素电极进行复位。当然的，在本公开的其他实施方式中，像素驱动电路PDC可以不包括像素电极复位晶体管T7，或者像素电极复位晶体管T7可以为金属氧化物薄膜晶体管。
在图4示例的像素驱动电路PDC中，电容复位晶体管T1的源极所加载的第一初始化电压Vinit1和像素电极复位晶体管T7的源极所加载的第二初始化电压Vinit2可以为不同的电压信号，例如可以为来自不同走线上的电压信号(电压的大小可以相同)。在本公开的其他示例中，电容复位晶体管T1的源极所加载的第一初始化电压Vinit1和像素电极复位晶体管T7的源极所加载的第二初始化电压Vinit2也可以为同一信号，例如为来自同一走线上的信号。
在本公开的显示面板中，图4所示的像素驱动电路PDC可以依次按 照如下时序进行工作。在电容复位阶段，电容复位晶体管T1的栅极加载电容复位信号GN2而导通，使得第一节点N1被复位为第一初始化电压Vinit1。此时，在第一节点N1的控制下，驱动晶体管T3导通。阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6、数据写入晶体管T4、像素电极复位晶体管T7保持截止。
在数据写入阶段，数据写入晶体管T4的栅极加载数据扫描信号GP而使得数据写入晶体管T4导通，使得数据电压Data被写入至第三节点N3节点；阈值补偿晶体管T2的栅极加载阈值补偿信号GN1而使得阈值补偿晶体管T2导通。电容复位晶体管T1、第一发光控制晶体管T5、第二发光控制晶体管T6保持截止。这样，第三节点N3可以向第一节点N1充电而使得第一节点N1的电压被拉升，直至第一节点N1被拉升至使得驱动晶体管T3截止。如此，数据电压Data和驱动晶体管T3的阈值电压被写入第一节点N1，第一节点N1的电压为VData+Vth3，Vth3为驱动晶体管T3的阈值电压，VData为数据电压Data的电压值。如此，在数据写入阶段，同时实现了数据写入和驱动晶体管T3的阈值补偿。
在像素电极复位阶段，像素电极复位晶体管T7的栅极加载像素电极复位信号RP而使得像素电极复位晶体管T7导通，进而使得第二初始化电压Vinit2加载至第四节点N4。在一些实施方式中，上一行像素驱动电路PDC的像素电极复位信号RP和下一行像素驱动电路PDC的数据扫描信号GP为同一信号，这使得上一行像素驱动电路PDC处于像素电极复位阶段时下一行像素驱动电路PDC处于数据写入阶段。当然的，在本公开的其他示例中，同一行像素驱动电路PDC的像素电极复位信号RP和数据扫描信号GP可以为同一信号，该行像素驱动电路PDC的像素电极复位阶段和数据写入阶段为同一阶段，即数据写入晶体管T4和像素电极复位晶体管T7同步导通或者截止。
在发光阶段，第一发光控制晶体管T5的栅极和第二发光控制晶体管T6的栅极加载发光控制信号EM，使得第一发光控制晶体管T5和第二发光控制晶体管T6导通。这样，驱动电压VDD加载至第三节点N3节点，第二节点N2节点与子像素电连接；驱动晶体管T3在第一节点N1的控制下输出驱动电流，进而驱动子像素发光。
可以理解的是，本公开上述示例的7T1C(7个晶体管和1个存储电容)的像素驱动电路PDC仅仅为本公开的显示面板的其中一种示例性像素驱动电路PDC，而非对本公开的显示面板中所用到的像素驱动电路PDC的具体限定。在本公开的其他实施方式中，像素驱动电路PDC中可以包括更多或者更少晶体管，例如包括8个晶体管、9个晶体管等，上述7T1C中所示例的晶体管中的一个或者多个也可以被设置为依次串联的多个子晶体管。在本公开的其他实施方式中，像素驱动电路PDC中可以包括更多的存储电容Cst，例如包括两个或者3个存储电容。
本公开的显示面板中，像素驱动电路PDC通过将阈值补偿晶体管T2设置为金属氧化物晶体管，可以减小第一节点N1的漏电，进而提高像素驱动电路PDC的保压能力，降低显示面板在低频驱动下的闪烁风险并降低显示面板的功耗。
如下，结合附图对上述示例的7T1C的像素驱动电路PDC在显示面板中的具体布图进行介绍和说明。可以理解的是，本公开实施方式中示例的7T1C也可以呈现为其他的布图方式，且本公开的显示面板也可以采用其他的像素驱动电路PDC。当采用其他的像素驱动电路PDC结构时，本公开的显示面板中的像素驱动电路PDC的布图方式可以进行相应的调整。
参见图3，在该示例的显示面板中，驱动电路层FA包括依次层叠设置于衬底基板BP一侧的金属遮光层LS、无机阻挡层Barr、第一缓冲层Buff1、多晶硅半导体层SEMI1、第一栅极绝缘层GI1、第一栅极层GT1、第二缓冲层Buff2、第二栅极层GT2、第二栅极绝缘层GI2、金属氧化物半导体层SEMI2、第三栅极绝缘层GI3、第三栅极层GT3、层间电介质层ILD、第一源漏金属层SD1、第一平坦化层PLN1、转接金属层DRL、第二平坦化层PLN2、第二源漏金属层SD2、第三平坦化层PLN3。可以理解的是，在本公开的显示面板的另外一些实施方式中，可以不设置金属遮光层LS。
在显示区AA，可以将设置像素驱动电路PDC的主要区域定义为该像素驱动电路PDC对应的电路布图区PDCA。这样，像素驱动电路PDC的主要或者多数晶体管和存储电容Cst设置于对应的电路布图区PDCA中。参见图5，电路布图区PDCA可以为矩形。在相邻两行像素驱动电路PDC 中，上一行像素驱动电路PDC的像素电极复位晶体管T7可以布设于下一行像素驱动电路PDC对应的电路布图区PDCA中。换言之，像素驱动电路PDC的电容复位晶体管T1～第二发光控制晶体管T6和存储电容Cst布设于该像素驱动电路PDC对应的电路布图区PDCA中，像素驱动电路PDC的像素电极复位晶体管T7布设于下一行的电路布图区PDCA中。在本公开的示例中，相邻两个像素驱动电路PDC的布图可以呈镜像设置。当然的，在本公开的其他实施方式中，相邻两个像素驱动电路PDC的布图也可以相同而非镜像设置。
图6示出了本公开示例的显示面板的金属遮光层LS的局部结构示意图。参见图6，在电路布图区PDCA中，金属遮光层LS具有金属遮光部LSP和连接走线LSL；同行相邻和同列相邻的金属遮光部LSP之间均通过连接走线LSL连接。这样，金属遮光层LS呈网格状，可以起到屏蔽外部信号的作用，避免显示面板以外的信号影响显示面板的正常显示。金属遮光部LSP需要具有较大的尺寸，以遮蔽照射向驱动晶体管T3的沟道区的光线，保证驱动晶体管T3的特性稳定。
图7示出了本公开示例的显示面板的多晶硅半导体层SEMI1的局部结构示意图。图8示出了本公开示例的显示面板的第一栅极层GT1的局部结构示意图。参见图7，多晶硅半导体层SEMI1具有与各个像素驱动电路PDC一一对应的多晶硅图案，该多晶硅图案形成具有半导体特性的驱动晶体管T3的沟道区T3Act、数据写入晶体管T4的沟道区T4Act、第一发光控制晶体管T5的沟道区T5Act、第二发光控制晶体管T6的沟道区T6Act和像素电极复位晶体管T7的沟道区T7Act，以及形成有被导体化的第一多晶硅条PL1、第二多晶硅条PL2、第三多晶硅条PL3、第四多晶硅条PL4、第五多晶硅条PL5、第六多晶硅条PL6。其中，第一多晶硅条PL1、第二多晶硅条PL2、第三多晶硅条PL3、第四多晶硅条PL4、第五多晶硅条PL5、第六多晶硅条PL6可以是在第一栅极层GT1图案化以后被导体化的。参见图7，第一多晶硅条PL1与数据写入晶体管T4的沟道区T4Act的一端电连接而作为数据写入晶体管T4的源极。第二多晶硅条PL2与数据写入晶体管T4的沟道区T4Act的另一端、驱动晶体管T3的沟道区T3Act的一端、第一发光控制晶体管T5的沟道区T5Act的一端电连接而作为第 三节点N3节点的一部分，并同时作为数据写入晶体管T4的漏极、驱动晶体管T3的源极和第一发光控制晶体管T5的漏极。第三多晶硅条PL3与第一发光控制晶体管T5的沟道区T5Act的另一端电连接而作为第一发光控制晶体管T5的源极。第四多晶硅条PL4与驱动晶体管T3的沟道区T3Act的另一端、第二发光控制晶体管T6的沟道区T6Act的一端电连接而作为第二节点N2的一部分，并同时作为驱动晶体管T3的漏极、第二发光控制晶体管T6的源极。第五多晶硅条PL5与第二发光控制晶体管T6的沟道区T6Act的另一端、像素电极复位晶体管T7的沟道区T7Act的一端电连接而作为第四节点N4的一部分，并同时作为第二发光控制晶体管T6的漏极和像素电极复位晶体管T7的漏极。第六多晶硅条PL6与像素电极复位晶体管T7的沟道区T7Act的另一端电连接而作为像素电极复位晶体管T7的源极。参见图7，该像素驱动电路PDC对应的多晶硅图案的像素电极复位晶体管T7的沟道区T7Act、第六多晶硅条PL6和第五多晶硅条PL5的一部分，可以布设于下一行像素驱动电路PDC对应的电路布图区PDCA中；相应的，该像素驱动电路PDC对应的电路布图区PDCA中布设有上一行像素驱动电路PDC的像素电极复位晶体管T7的沟道区T7Act、第六多晶硅条PL6和部分第五多晶硅条PL5。
参见图7，驱动晶体管T3的沟道区T3Act弯折设置，以使得驱动晶体管T3的沟道区T3Act具有更大的长度，例如具有15～25微米的长度。进一步的，驱动晶体管T3的沟道区T3Act分布的区域在金属遮光层LS的正投影，可以完全位于金属遮光部LSP内。这样，金属遮光部LSP可以为驱动晶体管T3的沟道区T3Act遮光。参见图5和图8，第一栅极层GT1设置有存储电容Cst的第一电极板CP1，存储电容Cst的第一电极板CP1完全覆盖驱动晶体管T3的沟道区T3Act；即驱动晶体管T3的沟道区T3Act在第一栅极层GT1的正投影，位于存储电容Cst的第一电极板CP1的范围内。如此，存储电容Cst的第一电极板CP1可以作为驱动晶体管T3的栅极。
参见图7，下一行像素驱动电路PDC的数据写入晶体管T4的沟道区T4Act与上一行像素驱动电路PDC的像素电极复位晶体管T7的沟道区T7Act相邻设置。这样，参见图5和图8，第一栅极层GT1设置有用于加 载数据扫描信号GP且基本沿行方向延伸的数据扫描走线GPL，数据扫描走线GPL与数据写入晶体管T4的沟道区T4Act交叠设置；数据扫描走线GPL与数据写入晶体管T4的沟道区T4Act交叠的部分可以复用为数据写入晶体管T4的栅极T4G。数据扫描走线GPL还与像素电极复位晶体管T7的沟道区T7Act交叠设置，这样数据扫描走线GPL与像素电极复位晶体管T7的沟道区T7Act交叠的部分可以复用为像素电极复位晶体管T7的栅极；数据扫描走线GPL上加载的数据扫描信号GP可以同时作为像素电极复位信号RP，使得数据扫描走线GPL可以复用为像素电极复位走线RPL。
参见图5、图7和图8，第一发光控制晶体管T5的沟道区T5Act和第二发光控制晶体管T6的沟道区T6Act同行或者基本同行设置。第一栅极层GT1设置有用于加载发光控制信号EM且基本沿行方向延伸的发光控制走线EML。发光控制走线EML与第一发光控制晶体管T5的沟道区T5Act、第二发光控制晶体管T6的沟道区T6Act交叠设置；发光控制走线EML与第一发光控制晶体管T5的沟道区T5Act交叠的部分复用为第一发光控制晶体管T5的栅极，发光控制走线EML与第二发光控制晶体管T6的沟道区T6Act交叠的部分复用为第二发光控制晶体管T6的栅极。
图9示出了本公开示例的显示面板的第二栅极层GT2的局部结构示意图。图10示出了本公开示例的显示面板的金属氧化物半导体层SEMI2的局部结构示意图。图11示出了本公开示例的显示面板的第三栅极层GT3的局部结构示意图。
参见图10，金属氧化物半导体层SEMI2具有与各个像素驱动电路PDC一一对应的金属氧化物图案，像素驱动电路PDC的金属氧化物图案完全位于该像素驱动电路PDC对应的电路布图区PDCA中。其中，像素驱动电路PDC的金属氧化物图案和多晶硅图案在衬底基板BP上的正投影不交叠。像素驱动电路PDC的金属氧化物图案包括保持半导体特性的电容复位晶体管T1的沟道区T1Act和阈值补偿晶体管T2的沟道区T2Act，和被导体化的第一金属氧化物部OL1、第二金属氧化物部OL2和第三金属氧化物部OL3。其中，第一金属氧化物部OL1、第二金属氧化物部OL2和第三金属氧化物部OL3可以在第三栅极层GT3图案化以后被导体化。 第二金属氧化物部OL2与电容复位晶体管T1的沟道区T1Act的一端、阈值补偿晶体管T2的沟道区T2Act的一端电连接而作为第一节点N1的一部分，且同时作为电容复位晶体管T1的漏极和阈值补偿晶体管T2的漏极。第一金属氧化物部OL1与电容复位晶体管T1的沟道区T1Act的另一端电连接而作为电容复位晶体管T1的源极；第三金属氧化物部OL3与阈值补偿晶体管T2的沟道区T2Act的另一端电连接而作为阈值补偿晶体管T2的源极。
参见图5和图11，第三栅极层GT3设置有基本沿行方向延伸的电容复位顶走线GN2UL和阈值补偿顶走线GN1UL。电容复位顶走线GN2UL用于加载电容复位信号GN2，且具有与电容复位晶体管T1的沟道区T1Act交叠的电容复位顶走线GN2UL的沟道定义部GN2ULP，电容复位顶走线GN2UL的沟道定义部GN2ULP与电容复位晶体管T1的沟道区T1Act交叠的部分复用为电容复位晶体管T1的顶栅极T1GU，且用于定义电容复位晶体管T1的沟道区T1Act在其长度方向的边界。阈值补偿顶走线GN1UL用于加载阈值补偿信号GN1，且具有与阈值补偿晶体管T2的沟道区T2Act交叠的阈值补偿顶走线GN1UL的沟道定义部GN1ULP，阈值补偿顶走线GN1UL的沟道定义部GN1ULP与阈值补偿晶体管T2的沟道区T2Act交叠的部分复用为阈值补偿晶体管T2的顶栅极T2GU，且用于定义阈值补偿晶体管T2的沟道区T2Act在长度方向的边界。
参见图5和图9，第二栅极层GT2设置有基本沿行方向延伸的电容复位底走线GN2DL、阈值补偿底走线GN1DL，以及设置有与各个像素驱动电路PDC一一对应的存储电容Cst的第二电极板CP2。其中，电容复位底走线GN2DL用于加载电容复位信号GN2，且具有与电容复位晶体管T1的沟道区T1Act交叠的电容复位底走线GN2DL的膨大部GN2DLP，电容复位顶走线GN2UL的沟道定义部GN2ULP在第二栅极层GT2上的正投影完全位于电容复位底走线GN2DL的膨大部GN2DLP内，这使得电容复位晶体管T1的沟道区T1Act在第二栅极层GT2的正投影完全位于电容复位底走线GN2DL的膨大部GN2DLP内。这样，电容复位底走线GN2DL的膨大部GN2DLP既可以向电容复位晶体管T1的沟道区T1Act加载电容复位信号GN2以消除电容复位晶体管T1的浮体效应，又可以屏蔽衬底基 板BP一侧的光线而使得电容复位晶体管T1的沟道区T1Act保持性能稳定。阈值补偿底走线GN1DL用于加载阈值补偿信号GN1，且具有与阈值补偿晶体管T2的沟道区T2Act交叠的阈值补偿底走线GN1DL的膨大部GN1DLP，阈值补偿顶走线GN1UL的沟道定义部GN1ULP在第二栅极层GT2上的正投影完全位于阈值补偿底走线GN1DL的膨大部GN1DLP内，这使得阈值补偿晶体管T2的沟道区T2Act在第二栅极层GT2的正投影完全位于阈值补偿底走线GN1DL的膨大部GN1DLP内。这样，阈值补偿底走线GN1DL的膨大部GN1DLP既可以向阈值补偿晶体管T2的沟道区T2Act加载阈值补偿信号GN1以消除阈值补偿晶体管T2的浮体效应，又可以屏蔽衬底基板BP一侧的光线而使得阈值补偿晶体管T2的沟道区T2Act保持性能稳定。
参见图5和图8、图9，存储电容Cst的第二电极板CP2与存储电容Cst的第一电极板CP1交叠设置以形成存储电容Cst。存储电容Cst的第二电极板CP2具有缺口CP2G，缺口CP2G暴露存储电容Cst的第一电极板CP1的部分区域，以使得存储电容Cst的第一电极板CP1可以通过位于缺口CP2G的过孔连接至第一源漏金属层SD1。参见图9，第二栅极层GT2还可以设置有用于加载第一初始化电压Vinit1的第一初始化电压走线Vinit1L，第一初始化电压走线Vinit1L基本沿行方向延伸。进一步的，电容复位底走线GN2DL位于阈值补偿底走线GN1DL和第一初始化电压走线Vinit1L之间。
图12示出了本公开示例的显示面板的第一源漏金属层SD1的局部结构示意图。图13示出了本公开示例的显示面板的第二栅极层GT2、金属氧化物半导体层SEMI2、第三栅极层GT3、第一源漏金属层SD1的局部结构示意图。图14示出了本公开示例的显示面板的转接金属层DRL的局部结构示意图。
参见图5、图12和图13，在电路布图区PDCA，第一源漏金属层SD1设置有第一导电结构ML1～第六导电结构ML6，以及设置有基本沿行方向延伸且用于加载第二初始化电压Vinit2的第二初始化电压走线Vinit2L。第二初始化电压走线Vinit2L在电路布图区PDCA中可以弯折设置以避让其他导电结构。
图14示出本公开示例的显示面板的局部八个子像素分别对应的电路布图区的转接金属层DRL的结构示意图；图15示出本公开示例的显示面板的局部八个子像素分别对应的电路布图区的第二源漏金属层SD2的结构示意图；图16示出本公开示例的显示面板的局部八个子像素分别对应的电路布图区的转接金属层DRL和第二源漏金属层SD2的结构配合示意图。
如图14～图16所示，第二源漏金属层SD2包括数据走线DL和驱动电压走线VDDL，以及像素转接结构PA；所述数据走线DL包括所述第一数据走线DL1、所述第二数据走线DL2、第三数据走线DL3A和第四数据走线DL3B。在各个显示单元DU的电路布局图，转接金属层DRL均设置有第二转接金属结构TRP2和第三转接金属结构TRP3。其中，第二转接金属结构TRP2通过过孔与像素转接结构PA电连接，且通过过孔与像素驱动电路的输出端电连接，例如通过过孔与位于第一源漏金属层的第六导电结构ML6电连接。像素转接结构PA通过过孔与子像素的像素电极电连接。这样，像素驱动电路的驱动电流可以通过第六导电结构ML6、第二转接金属结构TRP2、像素转接结构PA加载至子像素。第三转接金属结构TRP3通过过孔与驱动电压走线VDDL电连接，且通过过孔向像素驱动电路提供驱动电压，例如通过过孔与位于第一源漏金属层SD1的第二导电结构ML2电连接。如此，驱动电压走线VDDL的驱动电压通过第三转接金属结构TRP3、第二导电结构ML2加载至像素驱动电路。
对于直接与相邻的数据走线相连的显示单元，该显示单元的电路布图区在转接金属层DRL还设置有第一转接金属结构TRP1，该第一转接金属结构TRP1通过过孔与数据走线电连接，且通过过孔向像素驱动电路加载数据电压，例如通过过孔与像素驱动电路的第一导电结构ML1电连接。
该转接金属层DRL还设置有第一转接线TRL1和第二转接线TRL2。其中，位于所述第一显示单元列VDU1的第二显示单元DU2通过所述第二转接线TRL2与所述第二数据走线DL2电连接。例如，位于所述第一显示单元列VDU1的第二显示单元DU2的第一导电结构ML1通过过孔与第二转接线TRL2的第一端TRL21电连接，第二转接线TRL2的第二端 TRL22通过过孔与第二数据走线DL2电连接。位于所述第二显示单元列VDU2的第一显示单元DU1通过所述第一转接线TRL1与所述第一数据走线DL1电连接。例如，位于所述第二显示单元列VDU2的第一显示单元DU1的第一导电结构ML1通过过孔与第一转接线TRL1的第一端TRL11电连接，第一转接线TRL1的第二端TRL12通过过孔与第一数据走线DL1电连接。
举例而言，如图14所示，第一显示单元列VDU1的第一显示单元DU1的电路布图区PDCA、第二显示单元列VDU2的第二显示单元DU2的电路布图区PDCA、第三显示单元列VDU3A和第四显示单元列VDU3B的第三显示单元DU3的电路布图区PDCA中，转接金属层DRL均包括第一转接金属结构TRP1、第二转接金属结构TRP2和第三转接金属结构TRP3。第一显示单元列VDU1的第二显示单元DU2的像素驱动电路PDC对应的电路布图区PDCA中，转接金属层DRL包括第二转接线的第一端TRL21、第一转接线的第二端TRL12、第二转接金属结构TRP2和第三转接金属结构TRP3。第二显示单元列VDU2的第一显示单元DU1的像素驱动电路PDC对应的电路布图区PDCA中，转接金属层DRL包括第二转接线的第二端TRL22、第一转接线的第一端TRL11、第二转接金属结构TRP2和第三转接金属结构TRP3；其中，第一转接线的第二端TRL12通过TRL1与第一转接线的第一端TRL11电连接；第二转接线的第二端TRL22通过TRL2与第二转接线的第一端TRL21电连接。
在一种示例中，所述第二转接线的第一端TRL21的形状与所述第一转接金属结构TRP1的形状相同；所述第二转接线的第二端TRL22与所述第一转接线的第一端TRL11相邻且绝缘；所述第一转接线的第一端TRL11的形状与所述第二转接金属结构TRP2的形状相同；所述第一转接线的第二端TRL12与所述第二转接线的第一端TRL21相邻且绝缘。
如图7、图12、图13、图14和图15所示，与所述第一数据走线DL1相邻的所述第一显示单元DU1，与所述第二数据走线DL2相邻的所述第二显示单元DU2及所述第三显示单元DU3中的驱动电路层FA的数据电 压和驱动电压的电传导连接关系详细说明如下。以第三显示单元列VDU3A中的所述第三显示单元DU3为例。
第一导电结构ML1与第一多晶硅条PL1交叠设置且通过过孔电连接，第一导电结构ML1还与第一转接金属结构TRP1交叠设置且通过过孔电连接，第一转接金属结构TRP1与第三数据走线DL3A交叠设置且通过过孔电连接。这样，数据走线DL上加载的数据电压Data可以通过第一转接金属结构TRP1、第一导电结构ML1加载至作为数据写入晶体管T4的源极的第一多晶硅条PL1。
第二导电结构ML2与第三多晶硅条PL3交叠设置且通过过孔电连接，与存储电容Cst的第二电极板CP2交叠设置且通过过孔电连接，还与第三转接金属结构TRP3交叠设置且通过过孔电连接，第三转接金属结构TRP3与驱动电压走线VDDL交叠设置且通过过孔电连接。这样，驱动电压走线VDDL上加载的驱动电压VDD可以通过第三转接金属结构TRP3、第二导电结构ML2加载至存储电容Cst的第二电极板CP2和作为第一发光控制晶体管T5的源极的第三多晶硅条PL3。
在本公开的一种实施方式中，参见图12，相邻设置的两个第二导电结构ML2之间连接，以使得相邻两个所述驱动电压走线VDDL之间通过所述第二导电结构ML2电连接。这样，显示面板在显示区AA的驱动电压VDD分布网格化，可以提高驱动电压VDD的信号均一性，进而避免驱动电压VDD因压降或者电流不均一而导致显示面板显示不均一。
参见图5、图10和图12，第三导电结构ML3与第二金属氧化物部OL2交叠设置且通过过孔电连接，还与存储电容Cst的第一电极板CP1交叠设置且通过过孔电连接。其中，第三导电结构ML3与存储电容Cst的第一电极板CP1之间的过孔可以穿过缺口CP2G。这样，作为阈值补偿晶体管T2的漏极、电容复位晶体管T1的漏极和第一节点N1一部分的第二金属氧化物部OL2，通过第三导电结构ML3与存储电容Cst的第二电极板CP2电连接。
第四导电结构ML4与第一初始化电压走线Vinit1L交叠设置且通过过孔电连接，且与第一金属氧化物部OL1交叠设置且通过过孔电连接。这样，作为电容复位晶体管T1的源极的第一金属氧化物部OL1通过第四导 电结构ML4与第一初始化电压走线Vinit1L电连接，第一初始化电压走线Vinit1L上加载的第一初始化电压Vinit1可以加载至电容复位晶体管T1的源极。
第五导电结构ML5与第三金属氧化物部OL3交叠设置且电连接，还与第四多晶硅条PL4交叠设置且电连接。这样，作为阈值补偿晶体管T2的源极的第三金属氧化物部OL3与作为驱动晶体管T3的漏极、第二发光控制晶体管T6的源极、第二节点N2一部分的第四多晶硅条PL4通过第五导电结构ML5电连接。
第六导电结构ML6与第五多晶硅条PL5交叠且通过过孔电连接，还与第二转接金属结构TRP2交叠且通过过孔电连接，第二转接金属结构TRP2与像素转接结构PA交叠且通过过孔电连接。这样，作为第二发光控制晶体管T6的漏极、像素电极复位晶体管T7的漏极、第四节点N4一部分的第五多晶硅条PL5通过第六导电结构ML6、第三转接金属结构TRP3与像素转接结构PA电连接，像素转接结构PA用于与子像素的像素电极电连接，如图15和图16所示。
在本公开的一种实施方式中，参见图14～图16，所述驱动电压走线VDDL靠近所述第一数据走线DL1的一侧具有第一避让缺口；所述第一转接线TRL1的第二端TRL12在所述显示面板PNL所在平面上的正投影，位于所述第一避让缺口在所述显示面板PNL所在平面上的正投影内。所述驱动电压走线VDDL靠近所述第二数据走线DL2的一侧具有第二避让缺口；所述第二转接线的第二端TRL22在所述显示面板PNL所在平面上的正投影，位于所述第二避让缺口在所述显示面板PNL所在平面上的正投影内。所述第一数据走线DL1具有深入所述第一避让缺口的第一侧枝部LBP1，所述第一侧枝部LBP1与所述第一转接线TRL1的第二端TRL12通过过孔电连接。所述第二数据走线DL2具有深入所述第二避让缺口的第二侧枝部LBP2，所述第二侧枝部LBP2与所述第二转接线的第二端TRL22通过过孔电连接。如此，与所述第二数据走线DL2相邻的所述第一显示单元DU1对应的第一导电结构ML1通过过孔与所述第一转接线 TRL1的第一端TRL11电连接，所述第一转接线TRL1的第二端TRL12通过过孔与所述第一侧枝部LBP1电连接，所述第一侧枝部LBP1与第一数据走线DL1电连接。
这样，第一数据走线DL1上加载的数据电压可以通过第一侧枝部LBP1、第一转接线TRL1的第二端TRL12、第一转接线TRL1、第一转接线TRL1的第一端TRL11、第一导电结构ML1加载至与所述第二数据走线DL2相邻的第一显示单元DU1对应的数据写入晶体管T4的源极的第一多晶硅条PL1。同样的，与所述第一数据走线DL1相邻的所述第二显示单元DU2对应的第一导电结构ML1通过过孔与所述第二转接线TRL2的第一端TRL21电连接，所述第二转接线的第二端TRL22通过过孔与所述第二侧枝部LBP2电连接，所述第二侧枝部LBP2与第二数据走线DL2电连接。这样，第二数据走线DL2上加载的数据电压可以通过第二侧枝部LBP2、第二转接线的第二端TRL22、第二转接线TRL2、第二转接线TRL2的第一端TRL21、第一导电结构ML1加载至与所述第一数据走线DL1相邻的第二显示单元DU2对应的数据写入晶体管T4的源极的第一多晶硅条PL1。如此，实现了与所述第一数据走线DL1相邻的所述第二显示单元DU2与第二数据走线DL2的跨桥连接，及与所述第二数据走线DL2相邻的所述第一显示单元DU1与第一数据走线DL1的跨桥连接。
本公开实施例还提供一种显示面板PNL的驱动方法，该方法包括，逐行驱动各个DU；在驱动任意一个HDU时，将所述显示单元集DUS的第一显示单元DU1所需的驱动电压加载至所述显示单元集DUS对应的第一数据走线DL1上，将所述显示单元集DUS的第二显示单元DU2所需的驱动电压加载至所述显示单元集DUS对应的第二数据走线DL2上。以实现通过第一数据走线DL1上加载的数据电压均可以写入显示单元集DUS的第一显示单元DU1的像素驱动电路PDC中，通过第二数据走线DL2上加载的数据电压均可以写入显示单元集DUS的第二显示单元DU2的像 素驱动电路PDC中，避免了第一数据走线DL1和第二数据走线DL2对第一显示单元DU1、第二显示单元DU2交替控制产生额外的能耗。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (13)

  1. 一种显示面板，其中，包括沿行方向依次排列的多个显示单元集；所述显示单元集包括位于不同显示单元列的多个第一显示单元和位于不同显示单元列的多个第二显示单元；
    所述显示面板还设置有与所述显示单元集对应的第一数据走线和第二数据走线；所述显示单元集的各个第一显示单元均与第一数据走线电连接，所述显示单元集的各个第二显示单元均与对应的第二数据走线电连接。
  2. 根据权利要求1所述的显示面板，其中，所述显示单元集包括与所述第一数据走线相邻设置的第一显示单元列和与所述第二数据走线相邻设置的第二显示单元列；所述第一显示单元列包括沿列方向依次交替设置的第一显示单元和第二显示单元；所述第二显示单元列包括沿列方向依次交替设置的第二显示单元和第一显示单元。
  3. 根据权利要求1所述的显示面板，其中，在同一所述显示单元行中，所述第一显示单元和所述第二显示单元交替设置。
  4. 根据权利要求1-3任意一项所述的显示面板，其中，所述显示单元集包括沿行方向依次排列的第一显示单元列、第三显示单元列、第二显示单元列和第四显示单元列；所述第三显示单元列和所述第四显示单元列均包括沿列方向依次排列的多个第三显示单元。
  5. 根据权利要求4所述的显示面板，其中，同一所述显示单元行中，每行子像素包括一个第一显示单元、一个第二显示单元和两个第三显示单元。
  6. 根据权利要求4所述的显示面板，其中，所述显示面板还设置有与所述显示单元集对应的第三数据走线和第四数据走线；
    所述第三显示单元列的各个第三显示单元均与第三数据走线电连接，所述第四显示单元列的各个第三显示单元均与第四数据走线电连接。
  7. 根据权利要求6所述的显示面板，其中，所述第三数据走线和所 述第一数据走线相邻设置，且位于所述第一显示单元列的各个像素驱动电路和第三显示单元列的各个像素驱动电路之间；
    所述第四数据走线和所述第二数据走线相邻设置，且位于所述第二显示单元列的各个像素驱动电路和第四显示单元列的各个像素驱动电路之间。
  8. 根据权利要求7所述的显示面板，其中，所述显示面板设置有第一转接线和第二转接线；
    位于所述第一显示单元列的第二显示单元通过所述第二转接线与所述第二数据走线电连接；
    位于所述第二显示单元列的第一显示单元通过所述第一转接线与所述第一数据走线电连接。
  9. 根据权利要求1所述的显示面板，其中，所述显示面板包括依次层叠设置的衬底基板、驱动电路层和像素层；所述驱动电路层包括依次层叠设置的晶体管层、第一源漏金属层、转接金属层和第二源漏金属层；显示单元的像素驱动电路的各个晶体管设置于所述晶体管层；所述显示单元的子像素设置于像素电极层；
    所述第二源漏金属层设置有所述第一数据走线和所述第二数据走线；
    所述转接金属层设置有第一转接金属结构、第一转接线和第二转接线；其中，
    与所述第一数据走线相邻的所述第一显示单元的像素驱动电路的数据电压输入端，通过过孔与第一显示单元对应的所述第一转接金属结构电连接；所述第一转接金属结构通过过孔与所述第一数据走线电连接；
    与所述第二数据走线相邻的所述第二显示单元的像素驱动电路的数据电压输入端通过过孔与第二显示单元对应的所述第一转接金属结构电连接，所述第一转接金属结构通过过孔与所述第二数据走线电连接；
    与所述第二数据走线相邻的所述第一显示单元的像素驱动电路的数 据电压输入端通过过孔与所述第一转接线的第一端电连接，所述第一转接线的第二端通过过孔与所述第一数据走线电连接；
    与所述第一数据走线相邻的所述第二显示单元的像素驱动电路的数据电压输入端通过过孔与所述第二转接线的第一端电连接，所述第二转接线的第二端通过过孔与所述第二数据走线电连接。
  10. 根据权利要求9所述的显示面板，其中，所述第二转接线的第一端的形状与所述第一转接金属结构的形状相同；所述第二转接线的第二端与所述第一转接线的第一端相邻且绝缘；
    所述第一转接线的第一端的形状与所述第一转接金属结构的形状相同；所述第一转接线的第二端与所述第二转接线的第一端相邻且绝缘。
  11. 根据权利要求9所述的显示面板，其中，所述第二源漏金属层还包括驱动电压走线；
    所述驱动电压走线靠近所述第一数据走线的一侧具有第一避让缺口；所述第一转接线的第二端在所述显示面板所在平面上的正投影，位于所述第一避让缺口在所述显示面板所在平面上的正投影内；
    所述驱动电压走线靠近所述第二数据走线的一侧具有第二避让缺口；所述第二转接线的第二端在所述显示面板所在平面上的正投影，位于所述第二避让缺口在所述显示面板所在平面上的正投影内。
  12. 根据权利要求11所述的显示面板，其中，所述第一数据走线具有深入所述第一避让缺口的第一侧枝部，所述第一侧枝部与所述第一转接线的第二端通过过孔电连接；
    所述第二数据走线具有深入所述第二避让缺口的第二侧枝部，所述第二侧枝部与所述第二转接线的第二端通过过孔电连接。
  13. 一种权利要求1～12任意一项所述的显示面板的驱动方法，其中，包括：逐行驱动各个显示单元；
    在驱动任意一个显示单元行时，将所述显示单元集的第一显示单元所 需的驱动电压加载至所述显示单元集对应的第一数据走线上，将所述显示单元集的第二显示单元所需的驱动电压加载至所述显示单元集对应的第二数据走线上。
PCT/CN2024/120454 2023-10-31 2024-09-23 一种显示面板及其驱动方法 Pending WO2025092297A1 (zh)

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