WO2024131330A1

WO2024131330A1 - Storage chip, storage chip control method and storage system

Info

Publication number: WO2024131330A1
Application number: PCT/CN2023/129101
Authority: WO
Inventors: 陈一峰; 王成旭; 童浩; 谭海波
Original assignee: 华为技术有限公司
Priority date: 2022-12-22
Filing date: 2023-11-01
Publication date: 2024-06-27
Also published as: CN118248194A

Abstract

Embodiments of the present disclosure relate to the technical field of storage, and in particular, to a storage chip, a storage chip control method, and a storage system. The storage chip comprises a plurality of storage units, each storage unit comprises an ovonic threshold switch (OTS) and a storage medium, the OTS has a threshold switching voltage, and a read-write voltage is applied to the storage unit according to the threshold switching voltage so as to read and write the storage medium. The control method comprises: when a preset condition is detected, applying a reset voltage to a first storage unit in the plurality of storage units; and when the first storage unit in the plurality of storage units is a storage unit in a low-resistance state, turning on an OTS of the first storage unit by means of the reset voltage, so that the threshold switching voltage of the OTS of the first storage unit decreases. According to the present disclosure, the error probability of reading the storage units can be reduced.

Description

Storage chip, storage chip control method and storage system

This application claims priority to Chinese patent applications with application number 202211658162.5 filed on December 22, 2022, with invention name “A phase change memory chip” and with application number 202310366759.0 filed on March 31, 2023, with invention name “Memory chip, memory chip control method and memory system”, the entire contents of which are incorporated by reference into this application.

Technical Field

The present disclosure relates to the field of storage technology, and in particular to a storage chip, a storage chip control method and a storage system.

Background technique

The single selector one resistor (One Selector One Resistor, 1S1R) storage unit in the phase change memory chip consists of a phase change memory (Phase Change Memory, PCM) and a bidirectional threshold switch (Ovonic Threshold Switch, OTS).

When the 1S1R memory cell stores "0", the 1S1R memory cell has a higher threshold voltage, and when the 1S1R memory cell stores "1", the 1S1R memory cell has a lower threshold voltage. Therefore, the data stored in the 1S1R memory cell can be determined by detecting the threshold voltage of the 1S1R memory cell.

The threshold voltage of the 1S1R memory cell is related to the threshold voltage of the PCM and the threshold conversion voltage of the OTS. Changes in the threshold voltage of the PCM or the threshold conversion voltage of the OTS will affect the threshold voltage of the 1S1R memory cell.

The threshold conversion voltage of OTS has a significant drift phenomenon. For example, after each read and write operation on the 1S1R storage cell, the threshold conversion voltage of OTS will have a significant drop and cannot be recovered for a long time. For example, it usually takes several hours or even days to recover. In this way, the threshold conversion voltage drift phenomenon of OTS will affect the threshold voltage of the 1S1R storage cell, increasing the error probability of reading the 1S1R storage cell.

Summary of the invention

The embodiments of the present disclosure provide a memory chip, a memory chip control method, and a memory system, which can reduce the error probability of reading a memory unit. The corresponding technical solutions are as follows:

In a first aspect, a control method for a memory chip is provided, which is applied to the memory chip, wherein the memory chip includes a plurality of memory cells, each memory cell includes a bidirectional threshold switch OTS and a storage medium, the OTS has a threshold transition voltage, and a read/write voltage is applied to the memory cell according to the threshold transition voltage to perform a read/write operation on the storage medium. The control method includes:

When a preset condition is detected, a reset voltage is applied to a first memory cell among the plurality of memory cells. When the first memory cell among the plurality of memory cells is a memory cell in a low resistance state, the reset voltage turns on the OTS of the first memory cell to reduce the threshold transition voltage of the OTS of the first memory cell.

In the control method provided in the present disclosure, by applying a reset voltage to the first storage cell, the OTS of the storage cell in the low-resistance state can be turned on, so that the threshold transition voltage of the OTS in the storage cell in the low-resistance state can be maintained at a relatively low level. This can avoid the problem that the read voltage cannot distinguish between the storage cells in the low-resistance state and the high-resistance state due to the drift of the OTS threshold transition voltage, and can reduce the error probability in reading the storage cell.

In one achievable manner, the reset voltage is greater than the read voltage of the memory chip.

In the control method provided by the present disclosure, since the read voltage of the memory chip is greater than the threshold voltage corresponding to the memory cell in the low resistance state, applying a reset voltage to the memory cell can at least turn on the OTS in the memory cell in the low resistance state, so that the threshold transition voltage of the OTS in the memory cell in the low resistance state is maintained at a relatively low level, which can reduce the error probability of reading the memory cell.

In an achievable manner, detecting the preset condition includes detecting a preset time, where the preset time is the time after a specified time interval has arrived.

In the control method provided in the present disclosure, a reset voltage can be applied to the first storage unit at a specified time interval, so that the threshold transition voltage of OTS in the first storage unit can be maintained at a low level, thereby reducing the error probability of reading the storage unit.

In one achievable manner, the preset condition is detecting a reset request. The reset request may carry the first storage unit The address information can realize flexible application of a reset voltage to the first storage unit.

In one achievable manner, the first storage unit is all storage units included in the storage chip.

In one achievable manner, the first storage unit is a portion of storage units included in the storage chip.

In one achievable manner, the first storage unit is a storage unit in the storage chip for which the number of read operations and write operations performed within a specified time is less than a number threshold.

In the control method provided by the present disclosure, when the first storage unit is part of the storage units included in the storage chip, the first storage unit may be a storage unit in the storage chip whose number of read and write operations within a specified time is less than the number threshold, that is, the first storage unit is a storage unit that performs read and write operations infrequently. In this way, applying a reset voltage to the storage unit that performs read and write operations infrequently can maintain the threshold transition voltage of the OTS of the part of the storage units at a lower level, and can prevent the threshold transition voltage of the OTS of the part of the storage units from drifting to a relatively high threshold transition voltage due to long-term non-operation.

In one achievable manner, the first storage unit is a storage unit in the storage chip that has not been subjected to a read operation or a write operation within a specified time period.

In the control method provided in the present disclosure, after performing read operations and write operations on each storage cell, the storage cell can be timed. When the storage cell has not been subjected to read operations and write operations within a specified time period, a reset voltage can be applied to the storage cell, which can prevent the threshold transition voltage of the OTS of the part of the storage cells from drifting to a relatively high threshold transition voltage due to long-term non-operation.

In one achievable manner, applying a reset voltage to a first memory cell among a plurality of memory cells includes: applying a first voltage to a word line coupled to the first memory cell, applying a second voltage to a bit line coupled to the first memory cell, and a voltage difference formed on the first memory cell by the first voltage and the second voltage being equal to the reset voltage.

In an implementable manner, the specified time interval is shorter than the time duration for the threshold voltage of the memory cell in the low resistance state to drift to the read voltage of the memory chip.

In the control method provided by the present disclosure, when the reset voltage is applied to the first storage unit at a specified time interval, the specified time interval will not be longer than the time length for the threshold voltage of the storage unit in the low-resistance state to drift to the read voltage of the storage chip. This can avoid the problem that the threshold voltage of the storage unit is affected by the threshold transition voltage drift of the OTS, and the reset voltage cannot turn on the OTS.

In one achievable method, before detecting the preset condition, it also includes: obtaining the current target temperature of the storage chip; determining the target duration corresponding to the target temperature in the corresponding relationship between temperature and duration, wherein the temperature is negatively correlated with the duration in the corresponding relationship between temperature and duration; and determining the target duration as a specified time interval.

In the control method provided by the present disclosure, the upward drift speed of the OTS threshold transition voltage is related to the temperature. The higher the temperature, the faster the upward drift speed of the OTS threshold transition voltage. Therefore, the above-specified time interval can be flexibly adjusted according to the current target temperature. When the temperature is low, the time interval can be extended to reduce the power consumption of the memory chip. When the temperature is high, the time interval can be shortened to avoid the OTS threshold transition voltage drifting to a higher threshold transition voltage, and the reset voltage cannot turn on the OTS.

In one achievable method, before applying a reset voltage to a first storage cell among a plurality of storage cells, it also includes: obtaining a fatigue count corresponding to the storage chip; in a correspondence between the count and the voltage, determining a target voltage corresponding to the fatigue count, wherein in the correspondence between the count and the voltage, the count is negatively correlated with the voltage; and determining the target voltage as the reset voltage.

In the control method provided in the present disclosure, the fatigue times refer to the times of reading and writing operations on the memory chip. As the times of reading and writing operations on the memory cell in the locked memory chip increase, the storage medium in the memory cell decays, resulting in a decrease in the threshold voltage of the memory cell. Therefore, when applying a reset voltage to the first memory cell, the reset voltage can be dynamically adjusted according to the fatigue times of the memory chip, which can reduce the power consumption of the memory chip when applying the reset voltage.

In one achievable manner, applying a reset voltage to a first storage unit among a plurality of storage units includes: applying the reset voltage to each first storage unit in batches according to a preset order, wherein the number of first storage units in each batch to which the reset voltage is applied is positively correlated with the temperature of the storage chip.

In the control method provided by the present disclosure, the upward drift speed of the OTS threshold transition voltage is related to the temperature. The higher the temperature, the faster the upward drift speed of the OTS threshold transition voltage. In this way, when the temperature is high, the number of first storage units to which the reset voltage is applied can be increased, so that the duration of the reset voltage applied to each first storage unit as a whole can be shortened, and the OTS threshold transition voltage can be prevented from drifting to a higher threshold transition voltage.

In a second aspect, a memory chip is provided, which includes a peripheral circuit and a plurality of memory cells, wherein the peripheral circuit is connected to each memory cell through a word line and a bit line in the memory chip, and each memory cell includes a bidirectional threshold switch OTS and a storage medium, wherein the OTS has a threshold A transition voltage, applying a read/write voltage to the storage unit according to the threshold transition voltage to perform a read/write operation on the storage medium;

The peripheral circuit is used to: when a preset condition is detected, apply a reset voltage to a first storage cell among the multiple storage cells, and when the first storage cell among the multiple storage cells is a storage cell in a low-resistance state, the reset voltage turns on the OTS of the first storage cell to reduce the threshold transition voltage of the OTS of the first storage cell.

In one achievable manner, the preset condition is detecting a reset request.

In one achievable manner, the peripheral circuit is used to: apply a first voltage to a word line coupled to the first storage cell, apply a second voltage to a bit line coupled to the first storage cell, and a voltage difference formed by the first voltage and the second voltage on the first storage cell is equal to a reset voltage.

In one achievable manner, the peripheral circuit is also used to: obtain the current target temperature of the storage chip; determine the target duration corresponding to the target temperature in the corresponding relationship between temperature and duration, wherein the temperature is negatively correlated with the duration in the corresponding relationship between temperature and duration; and determine the target duration as a specified time interval.

In one feasible manner, the peripheral circuit is also used to: obtain the fatigue times corresponding to the storage chip; determine the target voltage corresponding to the fatigue times in the corresponding relationship between the times and the voltage, wherein the times and the voltage are negatively correlated in the corresponding relationship between the times and the voltage; and determine the target voltage as the reset voltage.

In one achievable manner, the peripheral circuit is further used to: apply a reset voltage to each first storage unit in batches according to a preset sequence, wherein the number of first storage units in each batch to which the reset voltage is applied is positively correlated with the temperature of the storage chip.

In a third aspect, a storage system is provided, comprising: one or more storage chips as described in the second aspect; and a storage controller connected to the storage chip and used to control the storage chip.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a memory chip provided by an embodiment of the present disclosure;

FIG2 is a threshold voltage distribution diagram of a 1S1R memory cell under different conditions provided by an embodiment of the present disclosure;

FIG3 is a schematic diagram of a control method for a memory chip provided by an embodiment of the present disclosure;

FIG4 is a schematic diagram of a control method for a memory chip provided by an embodiment of the present disclosure;

FIG5 is a schematic diagram of a control method for a memory chip provided by an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a storage system provided by an embodiment of the present disclosure.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

FIG1 is a schematic diagram of the structure of a memory chip provided by an embodiment of the present disclosure. As shown in FIG1 , the memory chip 100 includes at least one memory array 110 and a peripheral circuit 120. Among them, the memory array 110 includes a plurality of memory cells distributed in an array. Among the plurality of memory cells, the R memory cells in the same row are connected to the same word line (Word Line, WL), and the memory cells in the same column are connected to the same bit line (bit line, BL). Each memory cell may be composed of a storage medium and an Ovonic Threshold Switch (OTS). The peripheral circuit 120 may be connected to the bit line and the word line (not shown in FIG1 ), select the memory cell through the bit line and the word line, and perform operations such as reading and writing on the memory cell. Among them, the memory chip 100 in the embodiment of the present disclosure may be a three-dimensional memory chip, that is, the memory chip includes a plurality of memory arrays 110. The above-mentioned storage medium may be a phase change memory (Phase Change Memory, PCM). When the storage medium is PCM When the memory cell is configured as a phase change memory chip, the memory cell can be referred to as a single selector single resistor (1S1R) memory cell, and the memory chip can be referred to as a phase change memory chip.

To facilitate understanding of the control method of the memory chip provided in the embodiment of the present disclosure, some terms involved in the embodiment of the present disclosure are explained below:

Phase change memory: A new type of non-volatile semiconductor memory based on sulfur compounds, which can use the electrical properties of the crystalline and amorphous phase change materials that make up the phase change memory to achieve the storage of "0" and "1". When the phase change material is in the crystalline state, the phase change material is in a high resistance state, that is, it has a higher resistance value, which is defined as the RESET (0) state; when the phase change material is in the amorphous state, the phase change material is in a low resistance state, that is, it has a lower resistance value, which is defined as the SET (1) state.

Bidirectional threshold switch: A new type of bidirectional gating device based on sulfur compounds. When an electric pulse of any positive and negative direction and lower than the threshold voltage corresponding to the bidirectional threshold switch is applied to the bidirectional threshold switch, the response current on the bidirectional threshold switch is small, showing a high-resistance non-conduction state. When an electric pulse of any positive and negative direction and higher than the threshold voltage corresponding to the bidirectional threshold switch is applied to the bidirectional threshold switch, the response current on the bidirectional threshold switch is large, showing a low-resistance conduction state.

1S1R memory cell: A memory cell composed of an OTS and a PCM. In one achievable manner, when the PCM in the 1S1R memory cell is in the RESET (0) state, "0" is stored in the 1S1R memory cell, and at this time, the 1S1R memory cell has a higher threshold voltage Vthr. When the PCM in the 1S1R memory cell is in the SET (1) state, "1" is stored in the 1S1R memory cell, and at this time, the 1S1R memory cell has a lower threshold voltage Vths. Wherein, Vthr is equal to the threshold transition voltage of the OTS plus the threshold voltage corresponding to the PCM in the RESET (0) state, and Vths is equal to the threshold transition voltage of the OTS plus the threshold voltage corresponding to the PCM in the SET (1) state.

Based on the above characteristics, it can be known that when "0" is stored in the 1S1R memory cell, the 1S1R device cell responds to a smaller current under a specific read voltage Vread (greater than Vths and less than Vthr); when "1" is stored in the 1S1R memory cell, the 1S1R device cell responds to a larger current under a specific read voltage Vread. In this way, the data stored in the 1S1R memory cell can be read by applying the read voltage Vread.

Write operation (RESET): It is realized by applying a high-amplitude and narrow-width electric pulse to the 1S1R storage cell. The amplitude of the electric pulse is higher than the threshold transition voltage of the OTS. Under the action of the electric pulse, the temperature of the PCM in the 1S1R storage cell is rapidly raised to above the melting temperature and then suddenly cooled. Since the microscopic atoms do not have sufficient time to crystallize, they remain in a high-resistance amorphous state, that is, the storage of "0" is realized.

Erase operation (SET): It is realized by applying an electric pulse with a lower amplitude than the write operation but a relatively longer duration to the 1S1R storage cell. The amplitude of the electric pulse is higher than the threshold transition voltage of OTS. Under the action of the electric pulse, the temperature of the PCM in the 1S1R storage cell is raised to above the crystallization temperature and below the melting temperature. The PCM can be transformed into a low-resistance state through the thermal crystallization process, that is, the storage of "1" is realized.

Read operation (READ): data stored in the 1S1R memory cell can be read by applying a fixed read voltage Vread across the 1S1R memory cell and according to the response current of the 1S1R memory cell.

Word line: The signal line required to select a row of 1S1R memory cells in the memory array. It works together with the bit line to complete the selection of a 1S1R memory cell.

Bit line: A signal line required to select a column in a storage array. It works together with the word line to select a 1S1R storage cell. By applying corresponding electrical pulses to the word line and the bit line, the above-mentioned write operation, erase operation or read operation can be performed on the selected 1S1R storage cell.

Threshold transition voltage drift of OTS: The characteristic that the threshold transition voltage of OTS is affected by the time interval from the last turn-on to the current turn-on and the ambient temperature is called the threshold transition voltage drift of OTS.

OTS has a greater current conduction capability each time when it is higher than the corresponding threshold voltage. This is caused by the transition of the originally low-energy balanced non-conductive electrons to a high-energy non-equilibrium conductive state under high voltage. When the threshold voltage is removed, the high-energy non-equilibrium carriers in OTS excited by the threshold transition voltage will not all return to the equilibrium state in an instant, but will gradually return to the low-energy balanced non-conductive state according to a certain probability. Therefore, after each operation on the 1S1R storage unit, the threshold transition voltage of the OTS in the 1S1R storage unit will suddenly decrease, and then gradually increase over time. Among them, the higher the ambient temperature of the OTS, the faster its threshold voltage drifts. In addition, when the OTS is placed for a long time, its threshold transition voltage will also drift to a higher state.

FIG2 is a threshold voltage distribution diagram of a 1S1R memory cell under different conditions provided by an embodiment of the present disclosure. As shown in FIG2:

Case 1 is an ideal state, when each 1S1R memory cell in the memory chip stores "1" and "0", the corresponding threshold voltage distribution. That is, there is an obvious window between the threshold voltage distribution of the 1S1R memory cell storing "1" and the threshold voltage of the 1S1R memory cell storing "0". In case 1, by reading the voltage Vread, it is possible to accurately distinguish whether "0" or "1" is stored in the 1S1R memory cell.

In case 2, when there are a large number of 1S1R memory cells that have just been written to in the memory chip, the 1S1R The OTS in the storage cell will be turned on by the write operation, so the corresponding threshold voltage will drop significantly, causing the threshold voltage of the 1S1R storage cell that has just been written to a write operation to drop significantly. The threshold voltage of the 1S1R storage cell that has just been written with "0" may drop below the read voltage Vread. In this case, the 1S1R storage cell that has just been written with "0" will be read as "1" through the read voltage Vread, resulting in a read error.

In case 3, when there are a large number of 1S1R memory cells that have not been operated for a long time in the memory chip, due to the drift of the threshold transition voltage of OTS, the OTS in these 1S1R memory cells will drift to a higher threshold voltage, causing the threshold voltage corresponding to these 1S1R memory cells to increase. In this way, the threshold voltage of these 1S1R memory cells that have been written with "1" for a long time may rise above the read voltage Vread. In this case, the 1S1R memory cells that have been written with "1" will be read as "0" through the read voltage Vread, resulting in a read error.

It can be seen from the above cases 2 and 3 that the threshold transition voltage drift of the OTS seriously affects the accuracy of the memory chip reading.

The disclosed embodiment provides a control method for a phase change memory chip, in which a reset voltage can be applied to a first memory cell among a plurality of memory cells when a preset condition is detected. When the first memory cell is a memory cell in a low resistance state, the reset voltage is used to turn on the OTS in the first memory cell, so that the threshold transition voltage of the OTS of the first memory cell is reduced.

By applying a reset voltage to the first memory cell, at least the memory cell in the low resistance state can be turned on, that is, at least the OTS in the memory cell in the low resistance state can be turned on, so that the threshold transition voltage of the OTS is reduced. In this way, the memory cell in the low resistance state can be maintained at a relatively low threshold voltage, and the influence of the threshold transition voltage drift phenomenon of the OTS on the memory cell in the low resistance state can be avoided, so that there is a larger voltage between the threshold voltage of the memory cell in the low resistance state and the threshold voltage of the high resistance state. In other words, the memory cell in the low resistance state and the memory cell in the high resistance state can be accurately distinguished by the read voltage.

In the embodiment of the present disclosure, the reset voltage is applied to the first storage cell by turning on the OTS of the first storage cell instantaneously. For example, the reset voltage applied to the first storage cell may be equal to the read voltage. In this way, applying the reset voltage to the first storage cell can keep the storage cell at a relatively low threshold voltage without affecting the storage state written to the storage cell.

The present disclosure provides a control method for a memory chip, wherein the memory unit included in the memory chip may be a memory unit composed of an OTS and any storage medium. The following takes a 1S1R memory unit as an example to describe in detail a control method for a phase change memory chip provided by the present disclosure:

When different storage states are written into the 1S1R storage cell, the threshold voltage and resistance state corresponding to the 1S1R storage cell are different. For example, the storage states that can be written into the 1S1R storage cell include "0" and "1", the 1S1R storage cell storing "0" has a high resistance state, the 1S1R storage cell storing "1" has a low resistance state, and the threshold voltage corresponding to the 1S1R storage cell storing "0" is greater than the threshold voltage corresponding to the 1S1R storage cell storing "1".

In the embodiment of the present disclosure, when a preset condition is detected, a reset voltage is applied to the first memory cell in the memory chip, so that at least the 1S1R memory cell in the low-resistance state (hereinafter referred to as the low-resistance 1S1R memory cell) in the memory chip will be turned on, and the OTS in the turned-on low-resistance 1S1R memory cell will always be maintained at a lower threshold transition voltage. Since the OTS written into the low-resistance 1S1R memory cell will always be maintained at a lower threshold transition voltage, even if the OTS in the 1S1R memory cell in the high-resistance state (hereinafter referred to as the high-resistance 1S1R memory cell) also drifts to a lower threshold transition voltage, the threshold voltages corresponding to the low-resistance 1S1R memory cell and the high-resistance 1S1R memory cell still have a large difference. Among them, the difference is the difference corresponding to the threshold voltage of the PCM written into the low-resistance 1S1R memory cell and the threshold voltage of the PCM written into the high-resistance 1S1R memory cell. In this way, when reading the 1S1R memory cell in the memory chip, the voltage between the threshold voltage corresponding to the low-resistance 1S1R memory cell and the threshold voltage corresponding to the high-resistance 1S1R memory cell can be determined as the read voltage, and the storage state written in the 1S1R memory cell can be accurately read through the read voltage.

As shown in FIG3 , since the reset voltage is applied to the 1S1R storage unit in the storage chip at a specified time interval, it can be seen that due to the threshold transition voltage drift phenomenon of OTS, the threshold voltage corresponding to at least the low-resistance 1S1R storage unit in the storage chip can be maintained in a relatively low range. In this way, there is an obvious window between the threshold voltage of the low-resistance 1S1R storage unit and the threshold voltage of the high-resistance 1S1R storage unit, so that the low-resistance 1S1R storage unit and the high-resistance 1S1R storage unit can be accurately read through the read voltage within the window. It can be seen that the control method of the storage chip provided by the present disclosure can reasonably utilize the threshold transition voltage drift phenomenon of OTS to solve the problem of decreased storage chip reading accuracy caused by the threshold transition voltage drift phenomenon of OTS.

In an achievable manner, the reset voltage can be greater than the read voltage of the phase change memory chip and not less than the threshold voltage of the low-resistance 1S1R memory cell. Thus, by applying a reset voltage greater than the read voltage to the 1S1R memory cell, at least the OTS in the low-resistance 1S1R memory cell can be turned on. The reset voltage can also be greater than the threshold voltage of the high-resistance 1S1R memory cell. Thus, by applying a reset voltage greater than the read voltage to the 1S1R memory cell, the OTS in all the 1S1R memory cells to which the reset voltage is applied can be turned on, and all The threshold transition voltage of the OTS of the 1S1R memory cell is maintained at a relatively low level, thereby improving the accuracy of reading the 1S1R memory cell.

In an achievable manner, the above-mentioned detection of the preset condition may be the detection of a preset time, which is the time after the specified time interval arrives. That is, in the embodiment of the present disclosure, a reset voltage may be applied to the first storage unit at a specified time interval.

In implementation, a reset timing circuit may be provided in the phase change memory chip, and whenever the timing duration of the reset timing circuit reaches a specified time interval, a reset voltage may be triggered to be applied to the first memory cell in the phase change memory chip. The specified time interval may be less than the time duration for the threshold voltage of the low resistance 1S1R memory cell to drift to the read voltage of the memory chip. In this way, it is possible to avoid the threshold voltage of the 1S1R memory cell drifting beyond the read voltage of the memory chip during the time interval, so that the reset voltage cannot turn on the OTS of the 1S1R memory cell.

The read voltage currently used by the memory chip is a voltage between the threshold voltage of the low-resistance 1S1R memory cell and the threshold voltage of the high-resistance 1S1R memory cell after applying a reset voltage to the 1S1R memory cell in the memory chip at a specified time interval. If the threshold voltage in the low-resistance 1S1R memory cell drifts to the set read voltage and exceeds the read voltage, the reset voltage cannot turn on the low-resistance 1S1R memory cell, that is, the OTS in the low-resistance 1S1R memory cell cannot be turned on by the reset voltage, and the threshold transition voltage of the corresponding OTS drift cannot be reduced to the minimum. This in turn causes the low-resistance 1S1R memory cell to be misread. Therefore, in the embodiment of the present disclosure, the specified time interval is set to be less than the duration of the threshold voltage of the low-resistance 1S1R memory cell drifting to the read voltage of the memory chip, which can improve the accuracy of reading the 1S1R memory cell through the read voltage.

In addition, the specified time interval may be a fixed time interval, that is, the reset voltage may be applied to the 1S1R storage unit in the storage chip in a cycle with a duration of the specified time interval. Alternatively, the specified time interval may be not fixed, that is, the time interval for applying the reset voltage to the 1S1R storage unit in the storage chip each time is not fixed.

It should be noted that, depending on the type of the 1S1R storage unit, the number of storage states written into the 1S1R storage unit is not limited to 2, but may be more. For example, the storage states written into the 1S1R storage unit may include "00", "01", "11", and "10".

In an achievable manner, the above-mentioned preset condition may also be detection of a reset request. The reset request may be triggered by a user, or may be triggered by the above-mentioned specified time interval. For example, the phase-change memory chip is connected to a storage controller, and the storage controller may send a reset request to the phase-change memory chip at specified time intervals. After receiving the reset request, the phase-change memory chip may apply a reset voltage to the first storage unit. In addition, the reset request may also carry address information of the first storage unit.

The first storage unit may be all 1S1R storage units included in the phase-change memory chip, or may be some 1S1R storage units included in the phase-change memory chip. When the first storage unit is some 1S1R storage units included in the phase-change memory chip, it may include at least the following two situations:

Case 1: the first storage unit is a 1S1R storage unit in the storage chip, the number of read operations and write operations of which is less than a threshold number according to statistics within a specified time.

In implementation, the storage controller connected to the phase-change memory chip can count the number of read and write operations of each 1S1R memory cell in the phase-change memory chip within a specified time. For 1S1R memory cells whose corresponding number of operations is less than the number threshold, they can be considered as 1S1R memory cells with infrequent operations. For 1S1R memory cells with infrequent operations, their OTS may drift to a higher level due to not being turned on for a long time. Therefore, a reset voltage can be applied to these 1S1R memory cells with infrequent operations, which can improve the accuracy of reading 1S1R memory cells in the phase-change memory chip.

Case 2: The first storage unit is a 1S1R storage unit in the storage chip that has not been subjected to a read operation or a write operation within a specified time period.

In implementation, after performing read and write operations on each storage unit, the storage controller can time the storage unit. When the storage unit has not been read and written within a specified time, a reset voltage can be applied to the storage unit to prevent the threshold transition voltage of the OTS of the storage unit from drifting to a relatively high threshold transition voltage. This can improve the accuracy of reading 1S1R storage units in phase change memory chips. The specified time can be set to be less than the time it takes for the threshold voltage of the low-resistance 1S1R storage unit to drift to the read voltage of the storage chip.

In the embodiment of the present disclosure, the process of applying a reset voltage to a first memory cell among the plurality of memory cells may include: applying a first voltage to a word line coupled to the first memory cell, applying a second voltage to a bit line coupled to the first memory cell, and a voltage difference formed on the first memory cell by the first voltage and the second voltage is equal to the reset voltage. In one example, the first voltage may be directly applied to the word line coupled to the first memory cell and the second voltage may be applied to the bit line coupled to the first memory cell through a read/write circuit that performs read/write operations on the 1S1R memory cell, so as to complete the application of the reset voltage to the first memory cell.

In one achievable manner, applying the reset voltage to the 1S1R memory cell in the memory chip may be performed by applying the reset voltage to each 1S1R memory cell in batches according to a set application sequence. introduce:

Method 1: Applying a reset voltage to each 1S1R memory cell in the memory chip in row units in sequence, that is, each 1S1R memory cell to which the reset voltage is applied is connected to the same word line.

In implementation, whenever a corresponding time interval is reached, a reset voltage may be sequentially applied to the 1S1R memory cells in the corresponding row in units of rows until the reset voltage is applied to all first memory cells in the memory chip. For example, in the order of word lines, a reset voltage is sequentially applied to each 1S1R memory cell connected to the word line until the reset voltage is applied to each 1S1R memory cell in the memory chip.

When a reset voltage is applied to each 1S1R memory cell connected to a word line, some of the 1S1R memory cells connected to the word line will be turned on, and the current on the bit line connected to the partially turned-on 1S1R memory cells will converge on the same word line. The converged current may exceed the maximum current that the word line can withstand. Therefore, in order to avoid this problem, the technician can pre-set the first number of 1S1R memory cells to which the reset voltage is applied to the same word line each time. The first number can be set according to the maximum current that the word line can withstand. For example, the maximum current that the word line can withstand is 1A, and the current of the 1S1R memory cell turned on is 0.1A, then the first number can be up to 10.

As shown in FIG. 4 , in the case of setting the first number, a selected voltage (first voltage) may be applied to the target word line, a non-selected voltage may be applied to other word lines other than the target word line, and a second voltage may be applied to the first number of word lines at the same time. The voltage difference formed at both ends of the 1S1R memory cell by the second voltage applied to the bit line and the selected voltage applied to the word line may be equal to the reset voltage. The target word line may be one or more. When there are more than one target word lines, the reset voltage may be applied to 1S1R memory cells in multiple rows and columns at the same time. When the number of target word lines and the first number are both 1, the reset voltage may be applied to only one 1S1R memory cell.

In implementation, the read/write circuit in the memory chip is directly used to apply the selected voltage to the target word line and the second voltage to the first number of bit lines. Alternatively, before applying the reset voltage, the capacitors connected to the first number of bit lines can be charged to the second voltage. When the second voltage needs to be applied to the first number of bit lines, the second voltage is applied to the bit lines by controlling the word lines connected to the bit lines to discharge. The capacitor connected to the bit lines can be a parasitic capacitor of the bit lines or a capacitor connected to either end of the bit lines.

By applying the second voltage to the bit line through the capacitor, the second voltage will only be applied to the bit line at the moment when the capacitor is turned on, and then the voltage applied by the capacitor to the bit line will gradually decrease. In this way, the reset voltage acts on both ends of the 1S1R memory cell for a shorter time, which can reduce the impact of the reset voltage on the 1S1R memory cell.

In addition, in order to further reduce the impact of the reset voltage on the 1S1R memory cell, the overall efficiency of applying the reset voltage to each 1S1R memory cell of the memory chip is improved. After applying the second voltage to the first number of bit lines through the capacitor for a first specified time, the first number of bit lines are grounded, and the first specified time is less than the discharge time of the capacitor. In this way, by grounding the bit line, the time for applying the voltage to both ends of the 1S1R memory cell can be reduced, and the impact of the applied voltage on the 1S1R memory cell can be reduced. And by grounding the bit line, the voltage in the capacitor can be released faster, and then the reset voltage can be applied to other 1S1R memory cells in the memory chip, which can shorten the time interval between two reset voltage applications, and improve the overall efficiency of applying the reset voltage to each 1S1R memory cell of the memory chip.

Method 2: Applying a reset voltage to each 1S1R memory cell in the memory chip in order in columns, that is, each 1S1R memory cell to which the reset voltage is applied is connected to the same bit line.

In implementation, whenever a corresponding time interval is reached, a reset voltage may be applied to the 1S1R memory cells in the corresponding column in units of columns, until the reset voltage is applied to all first memory cells in the memory chip. For example, a reset voltage may be applied to each 1S1R memory cell connected to the bit line in sequence, until the reset voltage is applied to all 1S1R memory cells in the memory chip.

When a reset voltage is applied to each 1S1R memory cell connected to the bit line, some of the 1S1R memory cells connected to the bit line will be turned on, and the current on the word line connected to the partially turned-on 1S1R memory cells will converge on the same bit line. The converged current may exceed the maximum current that the bit line can withstand. Therefore, in order to avoid this problem, the technician can pre-set the second number of 1S1R memory cells that apply the reset voltage to the same bit line each time. The second number can be set according to the maximum current that the bit line can withstand. For example, the maximum current that the bit line can withstand is 1A, and the current of the 1S1R memory cell turned on is 0.1A, then the second number can be up to 10.

As shown in FIG. 5 , in the case of setting the second number, a selected voltage (second voltage) may be applied to the target bit line, a non-selected voltage may be applied to other bit lines other than the target bit line, and the first voltage may be applied to the second number of word lines at the same time. The voltage difference formed at both ends of the 1S1R memory cell by the first voltage applied to the word line and the selected voltage applied to the bit line may be equal to the reset voltage. The target bit line may be one or more. When there are more than one target bit lines, the reset voltage may be applied to 1S1R memory cells in multiple rows and columns at the same time. When the number of target bit lines and the second number are both 1, the reset voltage may be applied to only one 1S1R memory cell.

In implementation, the read/write circuit in the memory chip is directly used to apply the selected voltage to the target bit line and the first voltage to the second number of word lines. Alternatively, before applying the reset voltage, the capacitors connected to the second number of word lines can be charged to the first voltage. When the first voltage needs to be applied to the second number of word lines, the first voltage is applied to the word lines by controlling the word lines to be connected to discharge. The capacitor connected to the word line may be a parasitic capacitor of the word line, or may be a capacitor connected to either end of the word line.

By applying the first voltage to the word line through the capacitor, the first voltage will only be applied to the word line at the moment when the capacitor is turned on, and then the voltage applied by the capacitor to the word line will gradually decrease. In this way, the reset voltage acts on both ends of the 1S1R memory cell for a shorter time, which can reduce the impact of the reset voltage on the 1S1R memory cell.

In addition, in order to further reduce the impact of the reset voltage on the 1S1R memory cell, the overall efficiency of applying the reset voltage to each 1S1R memory cell of the memory chip is improved. After applying the first voltage to the second number of word lines through the capacitor for a second specified time, the second number of word lines is grounded, and the second specified time is less than the discharge time of the capacitor. In this way, by grounding the word line, the time for applying the voltage to both ends of the 1S1R memory cell can be reduced, and the impact of the applied voltage on the 1S1R memory cell can be reduced. And by grounding the word line, the voltage in the capacitor can be released faster, and then the reset voltage can be applied to other 1S1R memory cells in the memory chip, which can shorten the time interval between the two applications of the reset voltage, and improve the overall efficiency of applying the reset voltage to each 1S1R memory cell of the memory chip.

In one achievable manner, before applying the reset voltage to the 1S1R storage unit in the storage chip at a specified time interval, the length of the time interval may also be determined according to the current temperature of the storage chip.

As the temperature increases, the threshold transition voltage of the OTS drifts faster. Therefore, in order to avoid being affected by temperature, the corresponding threshold voltage of the 1S1R storage unit drifts above the read voltage within a specified time interval after the reset voltage is applied. The technician can pre-set the corresponding relationship between temperature and duration, in which the temperature and duration are negatively correlated. In implementation, the current target temperature of the storage chip can be detected according to the detection cycle or before each application of the reset voltage, and then the target duration corresponding to the target temperature can be determined in the corresponding relationship, and then the currently used specified time interval is updated to the target duration. The higher the current target temperature of the storage chip, the shorter the duration of the specified time interval determined according to the corresponding relationship. By shortening the specified time interval in this way, the influence of the temperature increase can be avoided, and the threshold voltage of the 1S1R storage unit drifts above the read voltage within the specified time interval.

In one achievable manner, when the time after the last application of the reset voltage to the 1S1R memory cell in the memory chip reaches a specified time interval, the reset voltage is applied to each 1S1R memory cell in the memory chip in batches, wherein the number of 1S1R memory cells to which the reset voltage is applied in each batch is positively correlated with the temperature of the memory chip. The above-mentioned specified time interval may be the time taken to apply the reset voltage to each 1S1R memory cell in the memory chip in batches. When the temperature rises, the number of 1S1R memory cells to which the reset voltage is applied in each batch may be increased, thereby reducing the number of times the reset voltage is applied to each 1S1R memory cell in the memory chip, thereby reducing the time interval for applying the reset voltage to the 1S1R memory cell. In this way, the specified time interval can be shortened, and the threshold voltage of the 1S1R memory cell can be prevented from drifting above the read voltage within the specified time interval due to the temperature increase.

In an achievable manner, the magnitude of the above-mentioned reset voltage may be related to the fatigue times corresponding to the memory chip. The fatigue times refer to the number of times the memory chip is read, written, and other operations. As the number of times the memory chip is read, written, and other operations increases, the material properties of the memory cell in the 1S1R memory cell will weaken, and the threshold voltage of the 1S1R memory cell will decrease accordingly. Therefore, in order to avoid the reset voltage from affecting the memory cell after the material properties weaken, the technician may pre-set the corresponding relationship between the fatigue times and the voltage. Before applying the reset voltage to the 1S1R memory cell in the memory chip, the target voltage corresponding to the fatigue times of the current memory chip may be determined in the corresponding relationship, and the target voltage may be determined as the reset voltage. In this corresponding relationship, the times are negatively correlated with the voltage. That is, when the fatigue times corresponding to each memory chip are higher, the reset voltage applied to the first memory cell is smaller. In this way, by adjusting the voltage of the reset voltage according to the fatigue times, the power consumption of the phase change memory chip applying the reset voltage to the first memory cell can be reduced.

FIG6 is a schematic diagram of the structure of a storage system provided by an embodiment of the present disclosure. Referring to FIG6 , a storage chip and a storage controller are included in the storage system. The peripheral circuit of the phase change memory may include an IO circuit module, an instruction decoder, a control circuit, a reset timing circuit, a reset address management circuit, a reset circuit, a read-write circuit, a row decoder, and a column decoder. Among them, the reset timing circuit, the reset address management circuit, and the reset circuit may be logic circuits newly added to the storage chip provided by the embodiment of the present disclosure relative to the traditional storage chip. The storage controller may also be connected to a processor of a device provided with the storage system (not shown in FIG6 ).

The reset timing circuit is used to implement the timing function. When the timing duration reaches the set duration, it can trigger the sending of a reset instruction (reset request) to the reset address management circuit.

The reset address management circuit is used to calculate the address information of the 1S1R storage unit that needs to perform a reset operation (that is, an operation of applying a reset voltage) after receiving a reset instruction, and send the address information to the reset circuit.

The reset circuit is used to charge and discharge the bit line connected to the corresponding 1S1R storage unit according to the address information after receiving the address information, so as to apply a reset voltage to the corresponding 1S1R storage unit.

In one achievable manner, the reset instruction may include a forced reset instruction and an automatic reset instruction. The forced reset instruction is a command issued by the storage controller. The automatic reset command is a reset command triggered by the memory chip.

The process of triggering a forced reset instruction on the storage controller can be as follows:

S1. The storage controller starts the automatic timing circuit.

S2. The automatic timing circuit adds a forced reset instruction to the controller instruction queue at a certain reset time interval.

The ratio of the reset time interval to the above-mentioned specified time interval is equal to the ratio of the number of 1S1R storage units to which the reset voltage can be applied by one reset instruction to the total number of 1S1R storage units.

S3. After receiving the forced reset instruction, the controller instruction queue executes the currently executed instruction first, and then sends the forced reset instruction to the storage chip.

S4. After the memory chip receives the forced reset instruction, the memory chip calculates the target address of the next reset instruction through the internal reset address management circuit, and the reset circuit performs the reset action.

The process of triggering an automatic reset instruction for a memory chip can be as follows:

S1. The storage controller sends an automatic reset instruction.

S2. After receiving the automatic reset instruction, the storage chip automatically calculates the time of the next reset instruction through the internal timing circuit, and sends an internal reset request signal after the time arrives. The time is the above reset time interval.

S3. When the internal reset signal of the memory chip arrives, the memory chip automatically calculates the target address of the next reset instruction through the internal reset address management circuit.

S4. The memory chip automatically performs the reset action of the address.

S5. After the memory chip completes the reset, it continues to wait until the internal timing circuit sends an internal reset request signal again. During the automatic reset process, the memory chip does not accept any read or write instructions, but can accept the exit automatic reset instruction. After receiving the exit automatic reset instruction, the memory chip enters the idle state.

An embodiment of the present disclosure provides a memory chip, which may be the memory chip shown in FIG. 1 , including a peripheral circuit and a plurality of memory cells, wherein the peripheral circuit is connected to each memory cell via a word line and a bit line in the memory chip, wherein each memory cell includes a bidirectional threshold switch OTS and a storage medium, wherein the OTS has a threshold transition voltage, and a read/write voltage is applied to the memory cell according to the threshold transition voltage to perform read/write operations on the storage medium.

To implement the control method for the memory chip in the above embodiment, the peripheral circuit is used to: when a preset condition is detected, apply a reset voltage to a first memory cell among the multiple memory cells; when the first memory cell among the multiple memory cells is a memory cell in a low-resistance state, the reset voltage turns on the OTS of the first memory cell, so that the threshold transition voltage of the OTS of the first memory cell is reduced.

In one achievable manner, the preset condition is detecting a reset request.

In an achievable manner, the peripheral circuit is further used to: obtain the fatigue times corresponding to the memory chip; determine the target voltage corresponding to the fatigue times in the corresponding relationship between the times and the voltage, wherein the times and the voltage are negatively correlated in the corresponding relationship between the times and the voltage; determine the target voltage Set as reset voltage.

In one achievable manner, the peripheral circuit is further used to: apply a reset voltage to each 1S1R first storage unit in batches according to a preset sequence, wherein the number of first storage units in each batch to which the reset voltage is applied is positively correlated with the temperature of the storage chip.

It should be noted that the embodiment of the present disclosure provides a memory chip and the control method of the memory chip provided in the above embodiment, which has the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here. The memory chip provided by the present disclosure can turn on the OTS of the memory cell in the low-resistance state by applying a reset voltage to the first memory cell, so that the threshold transition voltage of the OTS in the memory cell in the low-resistance state can be maintained at a lower level, thereby avoiding the problem that the read voltage cannot distinguish between the memory cells in the low-resistance state and the high-resistance state due to the drift of the OTS threshold transition voltage, and can reduce the error probability of reading the memory cell.

The embodiment of the present disclosure provides a storage system, which can be a storage system as shown in FIG6. The storage system includes a storage chip in the above embodiment and a storage controller for controlling the storage chip. The storage controller can control the storage chip to implement the control method for the storage chip provided in the above embodiment. The storage controller can also be set in the same storage device as the storage chip. Or the storage controller can be set on the same device as the storage chip, for example, it can be a processor on the device. The storage system provided by the present disclosure can turn on the OTS of the storage cell in the low-resistance state by applying a reset voltage to the first storage cell in the storage chip, so that the threshold transition voltage of the OTS in the storage cell in the low-resistance state can be maintained at a lower level, so that the problem of the read voltage being unable to distinguish between the storage cells in the low-resistance state and the high-resistance state due to the drift of the OTS threshold transition voltage can be avoided, and the error probability of reading the storage cell can be reduced.

In the present disclosure, the words such as "first" and "second" are used to distinguish the same or similar items with basically the same effects and functions. It should be understood that there is no logical or sequential dependency between "first" and "second", and the quantity and execution order are not limited. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of various examples, the first voltage can be referred to as the second voltage, and similarly, the second voltage can be referred to as the first voltage. The first voltage and the second voltage can both be collectively referred to as voltages, and in some cases, can be voltages of separate and different values.

The term "at least one" in the present disclosure means one or more, and the term "plurality" in the present disclosure means two or more.

The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present disclosure, and these modifications or replacements should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

A control method for a memory chip, characterized in that it is applied to a memory chip, wherein the memory chip comprises a plurality of memory cells, each memory cell comprises a bidirectional threshold switch (OTS) and a storage medium, the OTS has a threshold transition voltage, and a read/write voltage is applied to the memory cell according to the threshold transition voltage to perform a read/write operation on the storage medium;

The method comprises:

When a preset condition is detected, a reset voltage is applied to a first memory cell among the multiple memory cells. When the first memory cell among the multiple memory cells is a memory cell in a low resistance state, the reset voltage turns on the OTS of the first memory cell to reduce the threshold transition voltage of the OTS of the first memory cell.
The method according to claim 1, characterized in that the reset voltage is greater than the read voltage of the memory chip.
The method according to claim 1 or 2 is characterized in that the detection of the preset condition includes detecting a preset time, and the preset time is the time after the specified time interval arrives.
The method according to claim 1 or 2, characterized in that the preset condition is detection of a reset request.
The method according to any one of claims 1 to 4 is characterized in that the first storage unit is all storage units included in the storage chip.
The method according to any one of claims 1 to 4 is characterized in that the first storage unit is a part of the storage units included in the storage chip.
The method according to claim 6 is characterized in that the first storage unit is a storage unit in the storage chip whose number of read operations and write operations within a specified time is less than a number threshold.
The method according to claim 6 is characterized in that the first storage unit is a storage unit in the storage chip that has not been subjected to a read operation and a write operation within a specified time period.
A memory chip, characterized in that the memory chip comprises a peripheral circuit and a plurality of memory cells, the peripheral circuit is connected to each memory cell through a word line and a bit line in the memory chip, each memory cell comprises a bidirectional threshold switch OTS and a storage medium, the OTS has a threshold transition voltage, and a read/write voltage is applied to the memory cell according to the threshold transition voltage to perform a read/write operation on the storage medium;

The peripheral circuit is used to: apply a reset voltage to a first storage cell among the multiple storage cells when a preset condition is detected, and when the first storage cell among the multiple storage cells is a storage cell in a low-resistance state, the reset voltage turns on the OTS of the first storage cell to reduce the threshold transition voltage of the OTS of the first storage cell.
The memory chip according to claim 9, wherein the reset voltage is greater than a read voltage of the memory chip.
The memory chip according to claim 9 or 10 is characterized in that the detection of the preset condition includes detecting a preset time, and the preset time is the time after the specified time interval arrives.
The memory chip according to claim 9 or 10, wherein the preset condition is detection of a reset request.
The memory chip according to any one of claims 9 to 12, wherein the first memory unit is all memory units included in the memory chip.
The memory chip according to any one of claims 9 to 12, characterized in that the first memory unit is a part of the memory units included in the memory chip.
The memory chip according to claim 14 is characterized in that the first memory cell is a memory cell in the memory chip whose number of read operations and write operations performed within a specified time is less than a number threshold.
The memory chip according to claim 14, wherein the first memory cell is a memory cell in the memory chip that has not been subjected to a read operation or a write operation within a specified time period.
A storage system, characterized in that the storage system comprises:

One or more memory chips according to any one of claims 9 to 16;

A storage controller connected to the storage chip and used for controlling the storage chip.