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WO2024173204A1 - Low-temperature single-crystal 2d materials growth using trench patterns - Google Patents

Low-temperature single-crystal 2d materials growth using trench patterns Download PDF

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Publication number
WO2024173204A1
WO2024173204A1 PCT/US2024/015324 US2024015324W WO2024173204A1 WO 2024173204 A1 WO2024173204 A1 WO 2024173204A1 US 2024015324 W US2024015324 W US 2024015324W WO 2024173204 A1 WO2024173204 A1 WO 2024173204A1
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trench
low temperature
oxide
growth
mask material
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PCT/US2024/015324
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French (fr)
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Kim JEEHWAN
Kim KISEOK
Lee DOYOON
Seo SEUNGHWAN
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Massachusetts Institute Of Technology
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Publication of WO2024173204A1 publication Critical patent/WO2024173204A1/en

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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/04—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings of inorganic non-metallic material
    • C—CHEMISTRY; METALLURGY
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/04—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings of inorganic non-metallic material
    • C23C28/042—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings of inorganic non-metallic material including a refractory ceramic layer, e.g. refractory metal oxides, ZrO2, rare earth oxides
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    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
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    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H01L21/02642—Mask materials other than SiO2 or SiN
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

Definitions

  • TMDs transition metal dichalcogenides
  • a common method of constructing 2D heterostructures is mechanical exfoliation and stacking of 2D flakes, which is a trial-and-error-based operation and thus suffers from severe size limits on the structures that can be produced. It also takes a long time to make 2D heterostructures using mechanical exfoliation and stacking.
  • Embodiments of the present invention are an improvement over prior art systems and methods.
  • the present invention provides a method comprising the steps of: (a) providing a substrate of a first material; (b) depositing a mask material on the substrate; (c) forming a trench on the mask material, the trench having a trench geometry having lateral dimensions of I x w, where each of I and w is picked to have a maximum dimension of 2 pm and the trench having an exposed portion of the substrate surrounded by sidewalls formed of the mask material; (d) depositing, at a low temperature, an adatom of a second material on the exposed portion of the substrate; (e) allowing the adatom to selectively nucleate at the low temperature into a nucleus within the trench; and (f) growing the nucleus within the trench at the low temperature; and wherein the lateral dimensions associated with the trench geometry and the low temperature limit growth of the nucleus to a single-domain monolayer of the second material, and wherein the low temperature is less than 400 °C, and wherein the trench geometry and the low temperature
  • the present invention provides a method comprising the steps of: (a) providing a substrate of a first material; (b) depositing a first mask material on the substrate; (c) forming a first trench in the first mask material, the first trench having a first trench geometry having lateral dimensions of h x wi, where each of h and wi is picked to have a maximum dimension of 2 m and the first trench having a first exposed portion of the substrate surrounded by sidewalls formed of the first mask material; (d) depositing, at a low temperature, a first adatom of a second material on the first exposed portion of the substrate; (e) allowing the first adatom to selectively nucleate at the low temperature into a first nucleus within the first trench; (f) growing the first nucleus within the first trench at the low temperature, wherein the lateral dimensions associated with the first trench geometry and the low temperature limit growth of the first nucleus to a first single-domain monolayer of the second material; (g) waiting for
  • FIG. 1 A illustrates a conventional process for growing transition metal dichalcogenides (TMDs).
  • FIG. 1 B illustrates an inventive confined-growth process for selective singledomain synthesis of single-domain ML TMD that addresses the limitations of conventional TMD growth processes.
  • FIG. 10 illustrates fabrication of single-domain MoS2-WSe2 heterostructures by confined growth of a second M0S2 layer on the WSe2 ML in each trench in an array of trenches.
  • FIG. 1 D shows a calculation of binding energy of W3O9, Se2, and WsSee clusters on C-AI2O3, a-HfC>2, and a-SiC>2 substrates.
  • FIGS. 2(A)-(B) illustrate one embodiment of the present invention depicting the process of manufacturing a vertical complementary metal-oxide-semiconductor (CMOS).
  • CMOS complementary metal-oxide-semiconductor
  • FIGS. 3(A)-(I) illustrate one embodiment of the present invention showing the vertical CMOS process flow for WSe 2 stack over M0S2.
  • FIGS. 4(A)-4(D) illustrate low temperature 2D materials growth of M0S2.
  • FIG. 5 illustrates a SEM image showing a single crystal M0S2 grown below 400 °C in a SiO2 trench.
  • FIGS. 6(A) through 6(B) illustrates the binding character of WSe2 on HfO2 based on DFT calculations.
  • FIGS. 7(A)-(D) illustrate low-temperature growth of single-crystalline WSe 2 .
  • FIG. 1A shows a conventional transition metal dichalcogenide (TMD) growth process.
  • TMD transition metal dichalcogenide
  • a first set of TMD adatoms 12 is introduced onto the surface of a substrate 10 (top).
  • the TMD adatoms 12 nucleate to form nuclei 14 on the substrate 10.
  • the orientations of these nuclei 14 are random as the nuclei 14 are not typically aligned with the substrate 10.
  • nuclei 14 grow laterally to meet each other (middle) they form grains 16 that merge with each other, resulting in a continuous polycrystalline layer due to the random orientations of the nuclei 14.
  • This polycrystalline growth eventually degrades the intrinsic properties of the TMDs.
  • additional nucleation 18 may occur on some grains 16 (bottom). Without control of the additional nucleation, this process repeats, resulting in the growth of TMD layers with irregular thicknesses due to the overlapping grains 16 and nucleation of a second set of nuclei 18 on the initial layer of grains 16.
  • FIG. 1 B illustrates a confined growth process that addresses these issues by precisely controlling the thickness and crystallinity of TMD growth.
  • c-plane AI2O3, HfO2, or another material with relatively low Gibbs free energy such as amorphous or crystalline metal oxide
  • amorphous or crystalline metal oxide is deposited on Si wafers to form a substrate 100 upon which the TMD is grown.
  • suitable substrate materials include graphene, hexagonal boron nitride (hBN), hafnium zirconium oxide (HZO), TiO2, ZnO, Fe2Oa, SnO2, NiO, CuO, or TMD-coated materials.
  • a thin layer e.g., 5 nm, 10 nm, 50 nm, 100 nm, or even hundreds of nanometers thick; possibly up to 250 nm, 500 nm, 750 nm, or 1 pm thick
  • Suitable mask materials include materials with relatively high Gibbs free energy, such as amorphous SiC>2 (a-SiC>2), a-Si, a-SiN x , and a-carbon.
  • confined growth areas 102 also called recesses, pockets, trenches, wells, or cavities, each with lateral dimensions of tens of nanometers up to about 2 microns, are patterned in the thin layer 110 of a-SiCh.
  • the patterned a-SiC>2 layer 110 is also called a mask or mask layer.
  • These pockets 102 can be any suitable shape (e.g., squares, rectangles, triangles, or circles) and can be formed in a 1 D or 2D array (e.g., a square, rectangular, or hexagonal array).
  • the pockets 102 can extend all the way through the a- SiC>2 layer 110 to expose a portion of the AI2O3 or HfC>2 surface of the substrate 100 surrounded by a-SiC>2 sidewalls 112.
  • the pockets 102 may even extend partway (e.g., a few nanometers) into the c-plane AI2O3 or HfC>2 (FIG. 1 B, top).
  • a 2D material adatom 120 is introduced into each pocket (top).
  • a 2D material adatom 120 is introduced into each pocket (top).
  • Suitable 2D materials include semiconducting TMDs, such as WSe 2 (this example), M0S2, MoSe2, and WS2.
  • suitable 2D materials include but are not limited to graphene, carbon nanotubes (CNTs), hBN, metallic TMDs (e.g., VS2, VSe2, C0S2, CoSe2, TiS2, TiSe2), and high-k 2D materials (e.g., Bi2SeOs, Sb20s).
  • each pocket 102 The size of each pocket 102 is small enough that only a single nucleation (represented by a single triangle in FIG. 1 B) 122 occurs in each pocket (middle). Each nucleation 122 grows on the exposed c-plane AI2O3 or HfO2 at the bottom of its pocket 102 until it reaches the a-SiCh sidewalls 112 and fills up the entire trench 102 to form a TMD film 124 (bottom). Each TMD film 124 is single-domain and also a ML (bottom, inset). [0029] FIG. 10 shows how the adatom introduction, nucleation, and single-crystalline growth steps of the process in FIG.
  • MLs 124 of WSe 2 have been formed in pockets 102, M0S2 adatoms 130 are introduced into the cavities 102 on the WSe 2 MLs 124 (FIG. 1C, top).
  • M0S2 adatoms 130 undergo nucleation to form nuclei 132 (middle) and growth (bottom) to form single-crystalline M0S2 MLs 134 on the WSe2 MLs 124 (bottom inset), resulting in a MoS2/WSe2 heterostructure 140 in each pocket 102. DFT calculations confirm this growth selectivity.
  • WSe2 adatoms can be deposited on the WSe2 MLs and undergo nucleation and growth to form singledomain BLs of WSe2.
  • the method depicted in FIGS. 1(B) and 1(C) is performed at a low temperature that is less than 705 °C and is preferably around 400 °C.
  • the low temperature and the trench geometry confine growth of the MLs within the trenches and prevent the growth of any material outside the trenches.
  • FIG. 1 D shows the binding energies of the WSe 2 precursors WO3 and Se as well as the product WSe 2 clusters on C-AI2O3, a-HfO2, and a-SiO2 calculated from DFT.
  • WO3 clusters W3O9, left
  • Se clusters Se2, middle
  • WSe2 clusters W 3 Se 6 , right
  • the clusters preferentially bind with the substrate surfaces at the bottoms of the pockets rather than the a-SiCh sidewalls of the pockets, leading to a selective WSe2 growth within the pockets.
  • the trench size is selected to allow only single-domain, ML WSe2 formation and depends on both the lateral growth rate of WSe2 and the second nucleation incubation period.
  • the measured lateral growth rate of WSe 2 and the incubation period of the second nucleation were ⁇ 0.4 pm/minute and 5 minutes, respectively. This suggests that each trench should be no more than about 2 pm wide to avoid the nucleation of a second layer of WSe 2 . It is possible to control the lateral growth rate or incubation period (and hence the maximum trench width) by changing the content of TMD powder, gas ratio (Ar/H2), and growth temperature.
  • control may be affected by changing the content of S/Se powder between 100 mg to 1500 mg, or by changing the content of OO3/WO3 powder between 10 mg to 100 mg.
  • gas ratio of the percentage of Argon (Ar) to the percentage of hydrogen (H 2 ) may be adjustable between Ar-100%/H 2 -0% and Ar- 0%/H 2 -100%.
  • the growth temperature may be adjustable between 200 C and 1000 C.
  • FIGS. 2(A)-(B) depict an embodiment of the present invention.
  • the method comprising the steps of: (a) providing a substrate (230) of a first material - step 202; (b) growing a trench buffer layer (232) (e.g., HfC>2, AI2O3, SiN x , h-BN, etc.) - step 204 and depositing a first mask material on the substrate (230) - step 206; (c) and forming a first trench (via, for example, etching) in the first mask material - step 208, the first trench having a first trench geometry having lateral dimensions of h x wi, where each of h and wi is picked to have a maximum dimension of 2 pm and the first trench having a first exposed portion of the growth buffer layer (232) over a portion of the substrate (230) surrounded by sidewalls formed of the first mask material; (d) depositing, at a low temperature, a first adatom of a second
  • FIGS. 3(A)-(I) depict the various resulting structures formed as part of the steps of the present invention’s method as described in FIG. 2(A).
  • a trench buffer layer 132 (e.g., HfC ) is grown on a substrate 130.
  • a first mask material such as, but not limited to, SiC>2, is deposited on substrate 230 and a first trench 254 is formed (via, for example, etching) in the first mask material.
  • the first trench 254 has a first trench geometry having lateral dimensions of h x wi, where each of h and wi is picked to have a maximum dimension of 2 pm, and the first trench 254 having a first exposed portion of the growth buffer layer over a portion of the substrate surrounded by sidewalls formed of the first mask material.
  • the height of the first trench may be between 5 and 100 nm.
  • a first adatom of a second material is deposited at a low temperature on the first exposed portion of the growth buffer layer over a portion of the substrate 230.
  • the first adatom is allowed to selectively nucleate at the low temperature into a first nucleus within the first trench.
  • the first nucleus is grown within the first trench at the low temperature, wherein the lateral dimensions associated with the first trench geometry and the low temperature limit growth of the first nucleus to a first single-domain monolayer 250 of the second material.
  • a waiting time period or an incubation period is executed.
  • a first source electrode contact (234 or 236) is formed on one side of the first trench and a first drain electrode contact (236 or 234) is formed on another side of the first trench.
  • a first dielectric layer 238 is deposited on top of the structure in FIG. 3(D) and a gate electrode 240 is formed in the first dielectric layer 238.
  • a second dielectric layer 242 is deposited on top of the gate electrode 240.
  • a second mask material 243 is deposited on the second dielectric layer 242 and a second trench (via, for example, etching) is formed in the second mask material 243.
  • the second trench has a second trench geometry having lateral dimensions of I2 x W2, where each of I2 and W2 is picked to have a maximum dimension of 2 pm, and the second trench having a second exposed portion of the second mask material surrounded by sidewalls formed of the second mask material.
  • a second adatom of a third material is deposited at the low temperature on the second exposed portion of the second mask material, and the second adatom is allowed to selectively nucleate at the low temperature into a second nucleus within the second trench, wherein the lateral dimensions associated with the second trench geometry and the low temperature limit growth of the second nucleus to a second single-domain monolayer 252 of the third material.
  • the second nucleus is grown within the second trench at the low temperature.
  • a second source electrode contact 244 or 246 is formed on one side of the second trench and a second drain electrode contact 246 or 244 is formed on another side of the second trench.
  • an encapsulation layer 248 is formed on top of the structure of FIG. 3(H).
  • the first single-domain monolayer 250 and the second single-domain monolayer 252 form a bilayer at the low temperature.
  • the method of FIGS. 3(A)-(I) may be performed at low temperatures, i.e., the temperature is less than 705 °C, wherein the low temperature and the first trench geometry confine growth of the second material as a single crystal within the first trench and prevents growth of the second material outside the first trench, and the low temperature and the second trench geometry confine growth of the third material as another single crystal within the second trench and prevents growth of the third material outside the second trench.
  • the first material has a first Gibbs free energy and the mask material has a second Gibbs free energy, wherein the second Gibbs free energy is higher than the first Gibbs free energy.
  • the first material comprises one of hafnium oxide (HfG>2), aluminum oxide (AI2O3), hafnium zirconium oxide (HZO), titanium dioxide (TiO2), zinc oxide (ZnO), iron oxide (Fe2C>3), tin oxide (SnO2), nickel oxide (NiO), or copper oxide (CuO).
  • either the second material or the third material is picked from any of, or a combination of, the following: graphene, carbon nanotube (CNT), hexagonal boron nitride (h-BN), metallic transition-metal dichalcogenide (e.g., vanadium disulfide (VS2), vanadium diselenide (VSe 2 ), cobalt sulfide (C0S2), cobalt selenide (CoSe 2 ), titanium disulfide (TiS2), or titanium diselenide (TiSe 2 )), semiconducting transition-metal dichalcogenide (e.g., molybdenum disulfide (M0S2), molybdenum diselenide (MoSe 2 ), tungsten disulfide (WS2), or tungsten diselenide (WSe2)), or high-k material (e.g., Bi2SeOs or Sb 2 O3).
  • CNT carbon nanotube
  • h-BN
  • the first mask material or the second mask material is picked from any of, or a combination of, the following: amorphous silicon dioxide (a-SiO2), amorphous silicon (a-Si), amorphous silicon nitride (a-SiN x ), amorphous carbon (a- carbon), hafnium oxide (HfC>2), aluminum oxide (AI2O3), hafnium zirconium oxide (HfZrO), titanium dioxide (TiOz), zinc oxide (ZnO), iron oxide (FezCh), tin oxide (SnOz), nickel oxide (NiO), or copper oxide (CuO).
  • amorphous silicon dioxide a-SiO2
  • a-Si amorphous silicon dioxide
  • a-Si amorphous silicon
  • a-SiN x amorphous silicon nitride
  • a- carbon a- carbon
  • hafnium oxide HfC>2
  • aluminum oxide AI2O3
  • the bilayer is a heterojunction bilayer where the second material and third material are different from each other.
  • the bilayer is a homojunction bilayer where the second material and third material are similar to each other.
  • the low temperature is about 385 °C.
  • the method comprises forming a semiconductor device (e.g., valleytronics device, a Forksheet field-effect transistor (FET), or a complementary FET) comprising the first single-domain monolayer and the second single-domain monolayer.
  • a semiconductor device e.g., valleytronics device, a Forksheet field-effect transistor (FET), or a complementary FET
  • FIGS. 4(A)-4(B) shows a photograph and a schematic image of HfOz deposited on a Si wafer in a pocket with lateral dimensions of 1 pm (scale bar: 5 pm).
  • a single-crystal MoSz was synthesized at low temperature (385 °C) after fabricating SiO 2 trenches on HfO 2 -coated silicon wafers.
  • FIGS. 4(A)-(D) illustrate low- temperature growth of single-crystalline MoS 2 .
  • FIG. 4(A) depicts a schematic diagram illustrating that nucleation predominantly initiates at edge of SiO 2 trenches on HfOz substrate, rather than in regions without SiOz trenches.
  • FIG. 4(B) depicts a microscopic image showing formed SiOz trench on HfOz substrate, where scale bar denotes 5 pm.
  • FIG. 4(C) illustrates a Raman spectra investigated outside the trench and inside the trench, where the Raman spectra confirms the nucleation and formation of MoSz as occurring only within trench interiors.
  • FIG. 4(A) depicts a schematic diagram illustrating that nucleation predominantly initiates at edge of SiO 2 trenches on HfOz substrate, rather than in regions without SiOz trenches.
  • FIG. 4(B) depicts a microscopic image showing formed SiOz trench on HfOz substrate, where scale bar denotes 5
  • FIG. 5 depicts an image depicting the confined growth of monolayer (ML) M0S2 on a HfO2 layer.
  • M0S2 was not grown at a low temperature (-400 °C) where there was no SiO2 trench (outside pocket), but single crystal M0S2 was grown inside the SiO2 trench (inside pocket).
  • Raman and photoluminescence (PL) analysis confirmed that M0S2 was grown as a single crystal as shown in FIGS. 4(C)-(D).
  • FIGS. 6(A) through 6(B) illustrate the binding character of WSe2 on HfO2 based on such DFT calculations.
  • FIG. 6(A) depicts a plot of calculated binding energy of between WSe2 and a-HfC>2 or c-HfO2 with respect to WSe2 side length.
  • FIG. 6(A) depicts a plot of calculated binding energy of between WSe2 and a-HfC>2 or c-HfO2 with respect to WSe2 side length.
  • FIG. 6(B) depicts a schematic showing two nucleation scenario: i) Basal contact with a-HfO2 + Edge contact with SiO2, and ii) Only basal contact with a-HfO2 (see top panel), with the graph showing the calculated binding energy with respect to WSe 2 side length under edge and center contacted condition (see top panel). DFT analysis revealed that the amorphous nature of HfO2 at temperatures below 400 °C enhances nucleation at the edges of the trenches.
  • FIG. 6(A) illustrates that the binding of TMDs on amorphous a-HfO2 is notably weaker than on crystalline (c)-HfO2. Consequently, nucleation at the edges of SiO2 is further stimulated, resulting in a 35% increase in binding energy at the edges, as depicted in the graph of FIG. 6(B).
  • FIGS. 7(A)-(C) illustrate low-temperature growth of single-crystalline WSe2.
  • FIG. 7(A) shows experimental results of the nucleation tendencies of WSe2 at 700 °C. Dramatic transition of nucleation from the center to the edge occurs at 485 °C as shown in FIG. 7(B).
  • FIG. 7(D) illustrates an SEM image of singlecrystalline confined WSe2 grown at 385 °C.
  • FIG. 7(D) further growth at such low temperatures results in the production of confined single-domain TMDs, as the trench size remains small enough to complete lateral TMD growth within a very short timeframe before secondary nucleation occurs.
  • the quality of TMDs remains even at 385 °C due to their single-crystalline nature, and this temperature is low enough to preserve the performance of modern electronic logic and memory circuitry.
  • inventive embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed.
  • inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and/or method described herein.
  • inventive concepts may be embodied as one or more methods, of which an example has been provided.
  • the acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.
  • a reference to “A and/or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.
  • the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements.
  • This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified.
  • “at least one of A and B” can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

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Abstract

What is described is a method of growing a two-dimensional (2D) material on a substrate, the method comprising: (a) forming a mask layer on the substrate; (b) forming a trench in the mask layer, the trench having sidewalls formed in the mask layer surrounding an exposed portion of the substrate; and (c) depositing a nucleus of the 2D material on the exposed portion of the substrate and growing the nucleus into a single-domain monolayer of the 2D material, wherein the depositing and the growing of the nucleus is performed at a temperature less than 705 °C.

Description

LOW-TEMPERATURE SINGLE-CRYSTAL 2D MATERIALS GROWTH
USING TRENCH PATTERNS
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the priority benefit, under 35 U.S.C. 119(e), of U.S. Application No. 63/484,989, filed February 14, 2023, which is incorporated herein by reference in its entirety for all purposes.
[0002] United States Provisional Application No. 63/374,090 filed on 08/31/2022, entitled “Confined Growth of 2D Materials and Their Heterostructures” and Kim, et al., 2023, Nature, 614 (7946), 81-87, are hereby incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
[0003] Two-dimensional (2D) transition metal dichalcogenides (TMDs) and their heterostructures are a promising platform for next-generation electronics, spintronics, valleytronics, and optoelectronics. So far, however, the integration of semiconducting 2D heterostructures onto industrial platforms has been challenging because of limited scalability. A common method of constructing 2D heterostructures is mechanical exfoliation and stacking of 2D flakes, which is a trial-and-error-based operation and thus suffers from severe size limits on the structures that can be produced. It also takes a long time to make 2D heterostructures using mechanical exfoliation and stacking.
[0004] Recently, substantial progress has been made in improving scalability using an epitaxial growth method to obtain single-crystalline monolayer (ML) TMDs on singlecrystalline hexagonal substrates, such as sapphire. However, there still exist major challenges in growing large-scale 2D heterostructures due to the lack of strategies for layer-by-layer growth of single-domain TMDs. Moreover, some current growth methods involve the undesirable steps of infusing 2D materials into silicon devices as they are grown on hexagonal, non-silicon substrates. Single-domain TMD arrays can also be grown through laser irradiation of the nucleation spots. However, there are challenges with growth through laser irradiation because the second hetero-layer is likely to be nucleated at the edge of the first single-domain patches. To date, there is no feasible solution for obtaining single-domain 2D heterostructures at wafer scale.
[0005] Embodiments of the present invention are an improvement over prior art systems and methods.
SUMMARY OF THE INVENTION
[0006] This Summary introduces a selection of concepts in simplified form that are described further below in the Detailed Description. This Summary neither identifies key or essential features, nor limits the scope, of the claimed subject matter.
[0007] In one embodiment, the present invention provides a method comprising the steps of: (a) providing a substrate of a first material; (b) depositing a mask material on the substrate; (c) forming a trench on the mask material, the trench having a trench geometry having lateral dimensions of I x w, where each of I and w is picked to have a maximum dimension of 2 pm and the trench having an exposed portion of the substrate surrounded by sidewalls formed of the mask material; (d) depositing, at a low temperature, an adatom of a second material on the exposed portion of the substrate; (e) allowing the adatom to selectively nucleate at the low temperature into a nucleus within the trench; and (f) growing the nucleus within the trench at the low temperature; and wherein the lateral dimensions associated with the trench geometry and the low temperature limit growth of the nucleus to a single-domain monolayer of the second material, and wherein the low temperature is less than 400 °C, and wherein the trench geometry and the low temperature confines growth of the second material as a single crystal within the trench and prevents growth of the second material outside the trench.
[0008] In another embodiment, the present invention provides a method comprising the steps of: (a) providing a substrate of a first material; (b) depositing a first mask material on the substrate; (c) forming a first trench in the first mask material, the first trench having a first trench geometry having lateral dimensions of h x wi, where each of h and wi is picked to have a maximum dimension of 2 m and the first trench having a first exposed portion of the substrate surrounded by sidewalls formed of the first mask material; (d) depositing, at a low temperature, a first adatom of a second material on the first exposed portion of the substrate; (e) allowing the first adatom to selectively nucleate at the low temperature into a first nucleus within the first trench; (f) growing the first nucleus within the first trench at the low temperature, wherein the lateral dimensions associated with the first trench geometry and the low temperature limit growth of the first nucleus to a first single-domain monolayer of the second material; (g) waiting for an incubation period; (h) forming a first source electrode contact on one side of the first trench and forming a first drain electrode contact on another side of the first trench; (i) depositing a first dielectric layer on top of the structure formed in steps (a) through (h); (j) forming a gate electrode in the first dielectric layer; (k) depositing a second dielectric layer on top of the structure formed in steps (a) through (j); (I) depositing a second mask material on the second dielectric layer; (m) forming a second trench in the second mask material, the second trench having a second trench geometry having lateral dimensions of l2 x w2, where each of l2 and w2 is picked to have a maximum dimension of 2 pm and the second trench having a second exposed portion of the second mask material surrounded by sidewalls formed of the second mask material; (n) depositing, at the low temperature, a second adatom of a third material on the second exposed portion of the second mask material; (o) allowing the second adatom to selectively nucleate at the low temperature into a second nucleus within the second trench; (p) growing the second nucleus within the second trench at the low temperature, wherein the lateral dimensions associated with the second trench geometry and the low temperature limit growth of the second nucleus to a second single-domain monolayer of the third material; wherein the first single-domain monolayer and the second single- domain monolayer form a bilayer at the low temperature; and wherein the low temperature is less than 400 °C, and wherein the low temperature and the first trench geometry confines growth of the second material as a single crystal within the first trench and prevents growth of the second material outside the first trench, and the low temperature and the second trench geometry confines growth of the third material as another single crystal within the second trench and prevents growth of the third material outside the second trench.
[0009] The following Detailed Description references the accompanying drawings which form a part this application, and which show, by way of illustration, specific example implementations. Other implementations may be made without departing from the scope of the disclosure.
BRIEF DESCRIPTION OF FIGURES
[0010] The present disclosure, in accordance with one or more various examples, is described in detail with reference to the following figures. The drawings are provided for purposes of illustration only and merely depict examples of the disclosure. These drawings are provided to facilitate the reader's understanding of the disclosure and should not be considered limiting of the breadth, scope, or applicability of the disclosure. It should be noted that for clarity and ease of illustration these drawings are not necessarily made to scale.
[0011] FIG. 1 A illustrates a conventional process for growing transition metal dichalcogenides (TMDs).
[0012] FIG. 1 B illustrates an inventive confined-growth process for selective singledomain synthesis of single-domain ML TMD that addresses the limitations of conventional TMD growth processes. [0013] FIG. 10 illustrates fabrication of single-domain MoS2-WSe2 heterostructures by confined growth of a second M0S2 layer on the WSe2 ML in each trench in an array of trenches.
[0014] FIG. 1 D shows a calculation of binding energy of W3O9, Se2, and WsSee clusters on C-AI2O3, a-HfC>2, and a-SiC>2 substrates.
[0015] FIGS. 2(A)-(B) illustrate one embodiment of the present invention depicting the process of manufacturing a vertical complementary metal-oxide-semiconductor (CMOS).
[0016] FIGS. 3(A)-(I) illustrate one embodiment of the present invention showing the vertical CMOS process flow for WSe2 stack over M0S2.
[0017] FIGS. 4(A)-4(D) illustrate low temperature 2D materials growth of M0S2.
[0018] FIG. 5 illustrates a SEM image showing a single crystal M0S2 grown below 400 °C in a SiO2 trench.
[0019] FIGS. 6(A) through 6(B) illustrates the binding character of WSe2 on HfO2 based on DFT calculations.
[0020] FIGS. 7(A)-(D) illustrate low-temperature growth of single-crystalline WSe2.
DETAILED DESCRIPTION
[0021] While this invention is illustrated and described in a preferred embodiment, the invention may be produced in many different configurations. There is depicted in the drawings, and will herein be described in detail, a preferred embodiment of the invention, with the understanding that the present disclosure is to be considered as an exemplification of the principles of the invention and the associated functional specifications for its construction and is not intended to limit the invention to the embodiment illustrated. Those skilled in the art will envision many other possible variations within the scope of the present invention. [0022] Note that in this description, references to “one embodiment” or “an embodiment” mean that the feature being referred to is included in at least one embodiment of the invention. Further, separate references to “one embodiment” in this description do not necessarily refer to the same embodiment; however, neither are such embodiments mutually exclusive, unless so stated and except as will be readily apparent to those of ordinary skill in the art. Thus, the present invention can include any variety of combinations and/or integrations of the embodiments described herein.
[0023] FIG. 1A shows a conventional transition metal dichalcogenide (TMD) growth process. Initially, a first set of TMD adatoms 12 is introduced onto the surface of a substrate 10 (top). The TMD adatoms 12 nucleate to form nuclei 14 on the substrate 10. The orientations of these nuclei 14 are random as the nuclei 14 are not typically aligned with the substrate 10. While nuclei 14 grow laterally to meet each other (middle), they form grains 16 that merge with each other, resulting in a continuous polycrystalline layer due to the random orientations of the nuclei 14. This polycrystalline growth eventually degrades the intrinsic properties of the TMDs. In addition, additional nucleation 18 may occur on some grains 16 (bottom). Without control of the additional nucleation, this process repeats, resulting in the growth of TMD layers with irregular thicknesses due to the overlapping grains 16 and nucleation of a second set of nuclei 18 on the initial layer of grains 16.
[0024] FIG. 1 B illustrates a confined growth process that addresses these issues by precisely controlling the thickness and crystallinity of TMD growth. First, c-plane AI2O3, HfO2, or another material with relatively low Gibbs free energy, such as amorphous or crystalline metal oxide, is deposited on Si wafers to form a substrate 100 upon which the TMD is grown. Other suitable substrate materials include graphene, hexagonal boron nitride (hBN), hafnium zirconium oxide (HZO), TiO2, ZnO, Fe2Oa, SnO2, NiO, CuO, or TMD-coated materials. [0025] Then a thin layer (e.g., 5 nm, 10 nm, 50 nm, 100 nm, or even hundreds of nanometers thick; possibly up to 250 nm, 500 nm, 750 nm, or 1 pm thick) of mask material 110 is coated onto the c-plane AI2O3 or HfC>2 surface of the substrate 100. Suitable mask materials include materials with relatively high Gibbs free energy, such as amorphous SiC>2 (a-SiC>2), a-Si, a-SiNx, and a-carbon.
[0026] Next, confined growth areas 102, also called recesses, pockets, trenches, wells, or cavities, each with lateral dimensions of tens of nanometers up to about 2 microns, are patterned in the thin layer 110 of a-SiCh. The patterned a-SiC>2 layer 110 is also called a mask or mask layer. These pockets 102 can be any suitable shape (e.g., squares, rectangles, triangles, or circles) and can be formed in a 1 D or 2D array (e.g., a square, rectangular, or hexagonal array). The pockets 102 can extend all the way through the a- SiC>2 layer 110 to expose a portion of the AI2O3 or HfC>2 surface of the substrate 100 surrounded by a-SiC>2 sidewalls 112. The pockets 102 may even extend partway (e.g., a few nanometers) into the c-plane AI2O3 or HfC>2 (FIG. 1 B, top).
[0027] Once pockets 102 have been formed in the a-SiO2 layer 110, a 2D material adatom 120 is introduced into each pocket (top). As an example, it was noted that within a 1 nm x 1 nm area, there are 42 (W and Se) adatoms. Accordingly, within a 2 pm x 2 pm trench, for each pocket, there would be 84,000 adatoms required for a monolayer and 168,000 adatoms for a bilayer. Suitable 2D materials include semiconducting TMDs, such as WSe2 (this example), M0S2, MoSe2, and WS2. Other suitable 2D materials include but are not limited to graphene, carbon nanotubes (CNTs), hBN, metallic TMDs (e.g., VS2, VSe2, C0S2, CoSe2, TiS2, TiSe2), and high-k 2D materials (e.g., Bi2SeOs, Sb20s).
[0028] The size of each pocket 102 is small enough that only a single nucleation (represented by a single triangle in FIG. 1 B) 122 occurs in each pocket (middle). Each nucleation 122 grows on the exposed c-plane AI2O3 or HfO2 at the bottom of its pocket 102 until it reaches the a-SiCh sidewalls 112 and fills up the entire trench 102 to form a TMD film 124 (bottom). Each TMD film 124 is single-domain and also a ML (bottom, inset). [0029] FIG. 10 shows how the adatom introduction, nucleation, and single-crystalline growth steps of the process in FIG. 1 B can be repeated to obtain single-domain oS2/WSe2 heterostructures or single-domain homo-bilayers (BLs) of WSe2. (A BL can be thought of as two MLs combined by van der Waals interaction.) Once MLs 124 of WSe2 have been formed in pockets 102, M0S2 adatoms 130 are introduced into the cavities 102 on the WSe2 MLs 124 (FIG. 1C, top). These M0S2 adatoms 130 undergo nucleation to form nuclei 132 (middle) and growth (bottom) to form single-crystalline M0S2 MLs 134 on the WSe2 MLs 124 (bottom inset), resulting in a MoS2/WSe2 heterostructure 140 in each pocket 102. DFT calculations confirm this growth selectivity. Alternatively, WSe2 adatoms can be deposited on the WSe2 MLs and undergo nucleation and growth to form singledomain BLs of WSe2.
[0030] The method depicted in FIGS. 1(B) and 1(C) is performed at a low temperature that is less than 705 °C and is preferably around 400 °C. The low temperature and the trench geometry confine growth of the MLs within the trenches and prevent the growth of any material outside the trenches.
[0031] FIG. 1 D shows the binding energies of the WSe2 precursors WO3 and Se as well as the product WSe2 clusters on C-AI2O3, a-HfO2, and a-SiO2 calculated from DFT. These DFT calculations show that WO3 clusters (W3O9, left), Se clusters (Se2, middle), and WSe2 clusters (W3Se6, right) have stronger binding interactions with C-AI2O3 and a-HfO2 than with the surface of SiCh. This indicates that the clusters preferentially bind with the substrate surfaces at the bottoms of the pockets rather than the a-SiCh sidewalls of the pockets, leading to a selective WSe2 growth within the pockets.
[0032] Simultaneous growth of WSe2 on AI2O3, HfO2, and SiO2 substrates under the same CVD growth conditions confirm this selectivity. Atomic force microscopy (AFM) images show that WSez nucleates only on the AI2O3 and HfC>2 instead of SiC>2 during 20 minutes of growth. This led to a successful selective confined growth of WSe2 on the exposed substrate surface of the micropatterned SiC>2 trench arrays.
[0033] The trench size is selected to allow only single-domain, ML WSe2 formation and depends on both the lateral growth rate of WSe2 and the second nucleation incubation period. The measured lateral growth rate of WSe2 and the incubation period of the second nucleation were ~0.4 pm/minute and 5 minutes, respectively. This suggests that each trench should be no more than about 2 pm wide to avoid the nucleation of a second layer of WSe2. It is possible to control the lateral growth rate or incubation period (and hence the maximum trench width) by changing the content of TMD powder, gas ratio (Ar/H2), and growth temperature. For example, such control may be affected by changing the content of S/Se powder between 100 mg to 1500 mg, or by changing the content of OO3/WO3 powder between 10 mg to 100 mg. Also, the gas ratio of the percentage of Argon (Ar) to the percentage of hydrogen (H2) may be adjustable between Ar-100%/H2-0% and Ar- 0%/H2-100%. Also, the growth temperature may be adjustable between 200 C and 1000 C.
[0034] FIGS. 2(A)-(B) depict an embodiment of the present invention. In this embodiment, the method comprising the steps of: (a) providing a substrate (230) of a first material - step 202; (b) growing a trench buffer layer (232) (e.g., HfC>2, AI2O3, SiNx, h-BN, etc.) - step 204 and depositing a first mask material on the substrate (230) - step 206; (c) and forming a first trench (via, for example, etching) in the first mask material - step 208, the first trench having a first trench geometry having lateral dimensions of h x wi, where each of h and wi is picked to have a maximum dimension of 2 pm and the first trench having a first exposed portion of the growth buffer layer (232) over a portion of the substrate (230) surrounded by sidewalls formed of the first mask material; (d) depositing, at a low temperature, a first adatom of a second material on the first exposed portion of the growth buffer layer over a portion of the substrate - step 210; (e) allowing the first adatom to selectively nucleate at the low temperature into a first nucleus within the first trench - step 210; (f) growing the first nucleus within the first trench at the low temperature, wherein the lateral dimensions associated with the first trench geometry and the low temperature limit growth of the first nucleus to a first single-domain monolayer (250) of the second material - step 210; (g) waiting for an incubation period; (h) forming a first source electrode contact (234 or 236) on one side of the first trench and forming a first drain electrode (236 or 234) contact on another side of the first trench - step 212; (i) depositing a first dielectric layer (238) on top of the structure formed in steps (a) through (h) - step 214; (j) forming a gate electrode (240) in the first dielectric layer (238) - step 216; (k) depositing a second dielectric layer (242) on top of the structure formed in steps (a) through (j) - step 218; (I) depositing a second mask material (243) on the second dielectric layer (242) - step 220; (m) forming a second trench (via, for example, etching) in the second mask material (243) - step 222, the second trench having a second trench geometry having lateral dimensions of l2 x w2, where each of l2 and w2 is picked to have a maximum dimension of 2 pm and the second trench having a second exposed portion of the second mask material surrounded by sidewalls formed of the second mask material; (n) depositing, at the low temperature, a second adatom of a third material on the second exposed portion of the second mask material - step 224; (o) allowing the second adatom to selectively nucleate at the low temperature into a second nucleus within the second trench - step 224, wherein the lateral dimensions associated with the second trench geometry and the low temperature limit growth of the second nucleus to a second single-domain monolayer (252) of the third material; (p) growing the second nucleus within the second trench at the low temperature - step 224, (q) forming a second source electrode contact (244 or 246) on one side of the second trench and forming a second drain electrode contact (246 or 244) on another side of the second trench - step 226; (r) forming an encapsulation layer (248) on top of the structure formed in (a) through (q) - step 228; wherein the first singledomain monolayer (250) and the second single-domain monolayer (252) form a bilayer at the low temperature; and wherein the low temperature is less than 705 °C, and wherein the low temperature and the first trench geometry confines growth of the second material as a single crystal within the first trench and prevents growth of the second material outside the first trench, and the low temperature and the second trench geometry confines growth of the third material as another single crystal within the second trench and prevents growth of the third material outside the second trench. The height of each trench may be between 5 and 100 nm.
[0035] FIGS. 3(A)-(I) depict the various resulting structures formed as part of the steps of the present invention’s method as described in FIG. 2(A). In FIG. 3(A), a trench buffer layer (132) (e.g., HfC ) is grown on a substrate 130.
[0036] In FIG. 3(B), a first mask material, such as, but not limited to, SiC>2, is deposited on substrate 230 and a first trench 254 is formed (via, for example, etching) in the first mask material. The first trench 254 has a first trench geometry having lateral dimensions of h x wi, where each of h and wi is picked to have a maximum dimension of 2 pm, and the first trench 254 having a first exposed portion of the growth buffer layer over a portion of the substrate surrounded by sidewalls formed of the first mask material. The height of the first trench may be between 5 and 100 nm.
[0037] In FIG. 3(C), a first adatom of a second material is deposited at a low temperature on the first exposed portion of the growth buffer layer over a portion of the substrate 230. The first adatom is allowed to selectively nucleate at the low temperature into a first nucleus within the first trench. The first nucleus is grown within the first trench at the low temperature, wherein the lateral dimensions associated with the first trench geometry and the low temperature limit growth of the first nucleus to a first single-domain monolayer 250 of the second material. Next, a waiting time period or an incubation period is executed. [0038] In FIG. 3(D), a first source electrode contact (234 or 236) is formed on one side of the first trench and a first drain electrode contact (236 or 234) is formed on another side of the first trench.
[0039] In FIG. 3(E), a first dielectric layer 238 is deposited on top of the structure in FIG. 3(D) and a gate electrode 240 is formed in the first dielectric layer 238. Next, a second dielectric layer 242 is deposited on top of the gate electrode 240.
[0040] In FIG. 3(F), a second mask material 243 is deposited on the second dielectric layer 242 and a second trench (via, for example, etching) is formed in the second mask material 243. The second trench has a second trench geometry having lateral dimensions of I2 x W2, where each of I2 and W2 is picked to have a maximum dimension of 2 pm, and the second trench having a second exposed portion of the second mask material surrounded by sidewalls formed of the second mask material.
[0041] In FIG. 3(G), a second adatom of a third material is deposited at the low temperature on the second exposed portion of the second mask material, and the second adatom is allowed to selectively nucleate at the low temperature into a second nucleus within the second trench, wherein the lateral dimensions associated with the second trench geometry and the low temperature limit growth of the second nucleus to a second single-domain monolayer 252 of the third material. The second nucleus is grown within the second trench at the low temperature.
[0042] In FIG. 3(H), a second source electrode contact 244 or 246 is formed on one side of the second trench and a second drain electrode contact 246 or 244 is formed on another side of the second trench.
[0043] In FIG. 3(l), an encapsulation layer 248 is formed on top of the structure of FIG. 3(H).
[0044] The first single-domain monolayer 250 and the second single-domain monolayer 252 form a bilayer at the low temperature. [0045] The method of FIGS. 3(A)-(I) may be performed at low temperatures, i.e., the temperature is less than 705 °C, wherein the low temperature and the first trench geometry confine growth of the second material as a single crystal within the first trench and prevents growth of the second material outside the first trench, and the low temperature and the second trench geometry confine growth of the third material as another single crystal within the second trench and prevents growth of the third material outside the second trench.
[0046] In one embodiment, the first material has a first Gibbs free energy and the mask material has a second Gibbs free energy, wherein the second Gibbs free energy is higher than the first Gibbs free energy.
[0047] In one embodiment, the first material comprises one of hafnium oxide (HfG>2), aluminum oxide (AI2O3), hafnium zirconium oxide (HZO), titanium dioxide (TiO2), zinc oxide (ZnO), iron oxide (Fe2C>3), tin oxide (SnO2), nickel oxide (NiO), or copper oxide (CuO).
[0048] In one embodiment, either the second material or the third material is picked from any of, or a combination of, the following: graphene, carbon nanotube (CNT), hexagonal boron nitride (h-BN), metallic transition-metal dichalcogenide (e.g., vanadium disulfide (VS2), vanadium diselenide (VSe2), cobalt sulfide (C0S2), cobalt selenide (CoSe2), titanium disulfide (TiS2), or titanium diselenide (TiSe2)), semiconducting transition-metal dichalcogenide (e.g., molybdenum disulfide (M0S2), molybdenum diselenide (MoSe2), tungsten disulfide (WS2), or tungsten diselenide (WSe2)), or high-k material (e.g., Bi2SeOs or Sb2O3).
[0049] In one embodiment, the first mask material or the second mask material is picked from any of, or a combination of, the following: amorphous silicon dioxide (a-SiO2), amorphous silicon (a-Si), amorphous silicon nitride (a-SiNx), amorphous carbon (a- carbon), hafnium oxide (HfC>2), aluminum oxide (AI2O3), hafnium zirconium oxide (HfZrO), titanium dioxide (TiOz), zinc oxide (ZnO), iron oxide (FezCh), tin oxide (SnOz), nickel oxide (NiO), or copper oxide (CuO).
[0050] In one embodiment, the bilayer is a heterojunction bilayer where the second material and third material are different from each other.
[0051] In one embodiment, the bilayer is a homojunction bilayer where the second material and third material are similar to each other.
[0052] In one embodiment, the low temperature is about 385 °C.
[0053] In one embodiment, the method comprises forming a semiconductor device (e.g., valleytronics device, a Forksheet field-effect transistor (FET), or a complementary FET) comprising the first single-domain monolayer and the second single-domain monolayer.
[0054] In one embodiment, =l2 and wi=w2.
[0055] FIGS. 4(A)-4(B) shows a photograph and a schematic image of HfOz deposited on a Si wafer in a pocket with lateral dimensions of 1 pm (scale bar: 5 pm). As disclosed herein, a single-crystal MoSz was synthesized at low temperature (385 °C) after fabricating SiO2 trenches on HfO2-coated silicon wafers.
[0056] FIGS. 4(A)-(D) illustrate low- temperature growth of single-crystalline MoS2. FIG. 4(A) depicts a schematic diagram illustrating that nucleation predominantly initiates at edge of SiO2 trenches on HfOz substrate, rather than in regions without SiOz trenches. FIG. 4(B) depicts a microscopic image showing formed SiOz trench on HfOz substrate, where scale bar denotes 5 pm. FIG. 4(C) illustrates a Raman spectra investigated outside the trench and inside the trench, where the Raman spectra confirms the nucleation and formation of MoSz as occurring only within trench interiors. FIG. 4(D), photoluminescence (PL) spectra investigated on single-crystalline MoSz grown at 700 °C and 385 °C. The PL spectra of MoSz grown at 385 °C is almost similar to that of MoSz grown at 700 °C, showing that it is a single-crystalline. [0057] Such low-temperature manufacturing of structures enables the present invention’s techniques to be used to manufacture next-generation semiconductor devices (e.g., gate- all-around (GAA), Forksheet, complementary FET (CFET), and multi-bridge channel FET (MBCFET).
[0058] FIG. 5 depicts an image depicting the confined growth of monolayer (ML) M0S2 on a HfO2 layer. As shown in the OM image, M0S2 was not grown at a low temperature (-400 °C) where there was no SiO2 trench (outside pocket), but single crystal M0S2 was grown inside the SiO2 trench (inside pocket). Raman and photoluminescence (PL) analysis confirmed that M0S2 was grown as a single crystal as shown in FIGS. 4(C)-(D).
[0059] In order to verify the nucleation dynamics on structured surfaces, we conducted density functional theory (DFT) calculations. FIGS. 6(A) through 6(B) illustrate the binding character of WSe2 on HfO2 based on such DFT calculations. FIG. 6(A) depicts a plot of calculated binding energy of between WSe2 and a-HfC>2 or c-HfO2 with respect to WSe2 side length. FIG. 6(B) depicts a schematic showing two nucleation scenario: i) Basal contact with a-HfO2 + Edge contact with SiO2, and ii) Only basal contact with a-HfO2 (see top panel), with the graph showing the calculated binding energy with respect to WSe2 side length under edge and center contacted condition (see top panel). DFT analysis revealed that the amorphous nature of HfO2 at temperatures below 400 °C enhances nucleation at the edges of the trenches. FIG. 6(A) illustrates that the binding of TMDs on amorphous a-HfO2 is notably weaker than on crystalline (c)-HfO2. Consequently, nucleation at the edges of SiO2 is further stimulated, resulting in a 35% increase in binding energy at the edges, as depicted in the graph of FIG. 6(B).
[0060] FIGS. 7(A)-(C) illustrate low-temperature growth of single-crystalline WSe2. SEM images depicting initial nucleation of single-crystalline WSe2 within patterned SiO2 pockets formed on HfO2 substrate under TgrOwth of 700 °C (FIG. 7(A)), 485 °C (FIG. 7(B)), and 385 °C (FIG. 7(C)) conditions, respectively, highlighting increase in initial nucleation probability near edge of pocket with decreasing TgrOwth. FIG. 7(A) shows experimental results of the nucleation tendencies of WSe2 at 700 °C. Dramatic transition of nucleation from the center to the edge occurs at 485 °C as shown in FIG. 7(B). Finally, all nuclei form at the edges of SiC>2 trenches at 385 °C (FIG. 7(C)). FIG. 7(D) illustrates an SEM image of singlecrystalline confined WSe2 grown at 385 °C. In FIG. 7(D), further growth at such low temperatures results in the production of confined single-domain TMDs, as the trench size remains small enough to complete lateral TMD growth within a very short timeframe before secondary nucleation occurs. Notably, the quality of TMDs remains even at 385 °C due to their single-crystalline nature, and this temperature is low enough to preserve the performance of modern electronic logic and memory circuitry.
[0061] It should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific implementations described above. The specific implementations described above are disclosed as examples only.
[0062] While various inventive embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the function and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the inventive embodiments described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and/or configurations will depend upon the specific application or applications for which the inventive teachings is/are used. Those skilled in the art will recognize or be able to ascertain, using no more than routine experimentation, many equivalents to the specific inventive embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and/or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and/or methods, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure.
[0063] Also, various inventive concepts may be embodied as one or more methods, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.
[0064] All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and/or ordinary meanings of the defined terms.
[0065] The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”
[0066] The phrase “and/or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e. , elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and/or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and/or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and/or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.
[0067] As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and/or” as defined above. For example, when separating items in a list, “or” or “and/or” shall be interpreted as being inclusive, i.e. , the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of” or “exactly one of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e., “one or the other but not both”) when preceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of.” “Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.
[0068] As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a nonlimiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and/or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.
[0069] In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of” and “consisting essentially of’ shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.
CONCLUSION [0070] A system and method have been shown in the above embodiments for the effective implementation of a low-temperature single-crystal 2D materials growth using trench patterns. While various preferred embodiments have been shown and described, it will be understood that there is no intent to limit the invention by such disclosure, but rather, it is intended to cover all modifications falling within the spirit and scope of the invention, as defined in the appended claims.

Claims

WHAT IS CLAIMED IS:
1. A method comprising the steps of:
(a) providing a substrate of a first material;
(b) depositing a mask material on the substrate;
(c) forming a trench on the mask material, the trench having a trench geometry having lateral dimensions of I x w, where each of / and w is picked to have a maximum dimension of 2 m and the trench having an exposed portion of the substrate surrounded by sidewalls formed of the mask material;
(d) depositing, at a low temperature, an adatom of a second material on the exposed portion of the substrate;
(e) allowing the adatom to selectively nucleate at the low temperature into a nucleus within the trench; and
(f) growing the nucleus within the trench at the low temperature; and wherein the lateral dimensions associated with the trench geometry and the low temperature limit growth of the nucleus to a single-domain monolayer of the second material, and wherein the low temperature is less than 705 °C, and wherein the trench geometry and the low temperature confines growth of the second material as a single crystal within the trench and prevents growth of the second material outside the trench.
2. The method of claim 1 , wherein the low temperature is below 400 °C.
3. The method of claim 1 , wherein the method comprises forming a semiconductor device comprising the single-domain monolayer.
4. The method of claim 3, wherein the semiconductor device comprises one of a valleytronics device, a forksheet field-effect transistor (FET), a complementary FET, a gate-all- around FET (GAAFET), or a multi-bridge channel (MBCFET).
5. The method of claim 1 , wherein a first binding energy between the first material and the second material is greater than a second binding energy between the mask material and the second material.
6. The method of claim 1 , wherein the first material comprises one of hafnium oxide (HfC>2), aluminum oxide (AI2O3), hafnium zirconium oxide (HZO), titanium dioxide (TiC>2), zinc oxide (ZnO), iron oxide (Fe2C>3), tin oxide (SnC>2), nickel oxide (NiO), or copper oxide (CuO).
7. The method of claim 1 , wherein the second material comprises one of graphene, carbon nanotube (CNT), hexagonal boron nitride (h-BN), metallic transition-metal dichalcogenide, semiconducting transition-metal dichalcogenide, or high-k material.
8. The method of claim 7, wherein the metallic transition-metal dichalcogenide is one of vanadium disulfide (VS2), vanadium diselenide (VSe2), cobalt sulfide (C0S2), cobalt selenide (CoSe2), titanium disulfide (TiS2), or titanium diselenide (TiSe2).
9. The method of claim 7, wherein the semiconducting transition-metal dichalcogenide is one of molybdenum disulfide (M0S2), molybdenum diselenide (MoSe2), tungsten disulfide (WS2), or tungsten diselenide (WSe2).
10. The method of claim 7, wherein the high-k material is one of Bi2SeOs or Sb20s.
11. The method of claim 1 , wherein the mask material comprises at least one of amorphous silicon dioxide (a-SiO2), amorphous silicon (a-Si), amorphous silicon nitride (a-SiNx), amorphous carbon (a-carbon), hafnium oxide (HfC>2), aluminum oxide (AI2O3), hafnium zirconium oxide (HfZrO), titanium dioxide (TiC>2), zinc oxide (ZnO), iron oxide (Fe2O3), tin oxide (SnO2), nickel oxide (NiO), or copper oxide (CuO).
12. A method comprising the steps of:
(a) providing a substrate of a first material;
(b) depositing a first mask material on the substrate; (c) forming a first trench in the first mask material, the first trench having a first trench geometry having lateral dimensions of h x wi, where each of h and wi is picked to have a maximum dimension of 2 m and the first trench having a first exposed portion of the substrate surrounded by sidewalls formed of the first mask material;
(d) depositing, at a low temperature, a first adatom of a second material on the first exposed portion of the substrate;
(e) allowing the first adatom to selectively nucleate at the low temperature into a first nucleus within the first trench;
(f) growing the first nucleus within the first trench at the low temperature, wherein the lateral dimensions associated with the first trench geometry and the low temperature limit growth of the first nucleus to a first single-domain monolayer of the second material;
(g) waiting for an incubation period;
(h) forming a first source electrode contact on one side of the first trench and forming a first drain electrode contact on another side of the first trench;
(i) depositing a first dielectric layer on top of the structure formed in steps (a) through (h);
(j) forming a gate electrode in the first dielectric layer;
(k) depositing a second dielectric layer on top of the structure formed in steps (a) through 0);
(l) depositing a second mask material on the second dielectric layer;
(m) forming a second trench in the second mask material, the second trench having a second trench geometry having lateral dimensions of I2 x W2, where each of l2 and W2 is picked to have a maximum dimension of 2 pm and the second trench having a second exposed portion of the second mask material surrounded by sidewalls formed of the second mask material;
(n) depositing, at the low temperature, a second adatom of a third material on the second exposed portion of the second mask material; (o) allowing the second adatom to selectively nucleate at the low temperature into a second nucleus within the second trench;
(p) growing the second nucleus within the second trench at the low temperature, wherein the lateral dimensions associated with the second trench geometry and the low temperature limit growth of the second nucleus to a second single-domain monolayer of the third material;
(q) forming a second source electrode contact on one side of the second trench and forming a second drain electrode contact on another side of the second trench;
(r) forming an encapsulation layer on top of the structure formed in (a) through (q); wherein the first single-domain monolayer and the second single-domain monolayer form a bilayer at the low temperature; and wherein the low temperature is less than 400 °C, and wherein the low temperature and the first trench geometry confines growth of the second material as a single crystal within the first trench and prevents growth of the second material outside the first trench, and the low temperature and the second trench geometry confines growth of the third material as another single crystal within the second trench and prevents growth of the third material outside the second trench.
13. The method of claim 12, wherein the first material has a first Gibbs free energy and the mask material having a second Gibbs free energy, wherein the second Gibbs free energy higher than the first Gibbs free energy.
14. The method of claim 12, wherein the first material comprises one of hafnium oxide (HfO2), aluminum oxide (AI2O3), hafnium zirconium oxide (HZO), titanium dioxide (TO2), zinc oxide (ZnO), iron oxide (Fe2O3), tin oxide (SnCh), nickel oxide (NiO), or copper oxide (CuO).
15. The method of claim 12, wherein either the second material or the third material is picked from any of, or a combination of, the following: graphene, carbon nanotube (CNT), hexagonal boron nitride (h-BN), metallic transition-metal dichalcogenide, semiconducting transition-metal dichalcogenide, or high-k material.
16. The method of claim 15, wherein the metallic transition-metal dichalcogenide is one of vanadium disulfide (VS2), vanadium diselenide (VSe2), cobalt sulfide (C0S2), cobalt selenide (CoSe2), titanium disulfide (TiS2), or titanium diselenide (TiSe2).
17. The method of claim 15, wherein the semiconducting transition-metal dichalcogenide is one of molybdenum disulfide (M0S2), molybdenum diselenide (MoSe2), tungsten disulfide (WS2), or tungsten diselenide (WSe2).
18. The method of claim 15, wherein the high-k material is one of Bi2SeO5 or Sb2C>3.
19. The method of claim 12, wherein either the first mask material or the second mask material is picked from any of, or a combination of, the following: amorphous silicon dioxide (a- SiC>2), amorphous silicon (a-Si), amorphous silicon nitride (a-SiNx), amorphous carbon (a- carbon), hafnium oxide (HfCh), aluminum oxide (AI2O3), hafnium zirconium oxide (HfZrO), titanium dioxide (TiCh), zinc oxide (ZnO), iron oxide (Fe2C>3), tin oxide (SnCh), nickel oxide (NiO), or copper oxide (CuO).
20. The method of claim 12, wherein the bilayer is a heterojunction bilayer where the second material and third material are different from each other.
21. The method of claim 12, wherein the bilayer is a homojunction bilayer where the second material and third material are similar to each other.
22. The method of claim 12, wherein the method comprises forming a semiconductor device comprising the first single-domain monolayer and the second single-domain monolayer.
23. The method of claim 22, wherein the semiconductor device comprises one of a valleytronics device, a forksheet field-effect transistor (FET), a complementary FET, a gate-all- around FET (GAAFET), or a multi-bridge channel (MBCFET).
24. The method of claim 12, wherein li=h and wi=W2.
PCT/US2024/015324 2023-02-14 2024-02-12 Low-temperature single-crystal 2d materials growth using trench patterns WO2024173204A1 (en)

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