WO2024150370A1 - Insulated substrate and semiconductor device - Google Patents

Abstract

The purpose of the present invention is to provide a technology that makes it possible, in a semiconductor device, to minimize insulating failure such as short-circuiting between circuit patterns and deterioration in appearance quality caused by a plating residue. An insulated substrate (2) comprises: a ceramic substrate (2b); and a circuit pattern (2a) which is joined to the surface of the ceramic substrate (2b) and on which a semiconductor element (3) is mounted. At the back surface side of the outer peripheral part of the circuit pattern (2a) joined to the ceramic substrate (2b), a dug part (8) which is not in contact with the surface of the ceramic substrate (2b) is formed.

Description

Insulating substrate and semiconductor device

This disclosure relates to insulating substrates and semiconductor devices.

For example, Patent Document 1 proposes a semiconductor device that can improve the reliability of the connection between the circuit pattern and the semiconductor element.

　Insulating substrates mounted on semiconductor devices undergo a plating process aimed at soldering the semiconductor element to the circuit pattern formed on the surface of the ceramic substrate contained in the insulating substrate, as well as a plating stripping process. In the plating process, plating is applied to the entire insulating substrate. In the plating stripping process, only the areas necessary for soldering are masked with a resist material, and the plating is dissolved and removed from areas that do not require plating using a stripping solution, after which the plating residue is removed with an air blower.

JP 2007-311527 A

However, during the manufacture of the circuit pattern, small sagging parts may form on the outer periphery of the bonding surface of the circuit pattern with the ceramic substrate. Because the sagging parts are poorly exposed to the air blow, plating residue is likely to remain in the sagging parts even after the plating removal process. When manufacturing a semiconductor device with plating residue remaining, there is a risk that the plating residue that has remained in the sagging parts will flow out due to the thermal load during soldering and the flow of the sealing resin, degrading the external appearance quality of the semiconductor device. Furthermore, if the plating residue flows across circuit patterns, there is a risk of causing insulation failure such as a short circuit between the circuit patterns.

In the technology described in Patent Document 1, a solder reservoir recess is formed on the outer periphery of the circuit pattern, but the solder reservoir recess has only the function of storing the solder material used to join the semiconductor element and the circuit pattern, and does not take into consideration problems caused by plating residue.

The present disclosure therefore aims to provide a technology that can suppress deterioration of appearance quality and insulation defects such as short circuits between circuit patterns caused by plating residue in semiconductor devices.

The insulating substrate according to the present disclosure comprises a ceramic substrate and a circuit pattern bonded to the surface of the ceramic substrate and on which a semiconductor element is to be mounted, and a recessed portion that does not come into contact with the surface of the ceramic substrate is formed on the back side of the outer periphery of the circuit pattern that is bonded to the ceramic substrate.

According to the present disclosure, in the plating stripping process carried out before bonding the circuit pattern to the semiconductor element, the stripping solution is more easily absorbed into the back side of the outer periphery of the circuit pattern, and the air blowing for removing the plating residue is more effectively applied, making it possible to more effectively remove the unnecessary plating residue. This makes it possible to suppress deterioration of the appearance quality and insulation defects such as short circuits between circuit patterns caused by plating residue in semiconductor devices.

　Objectives, features, aspects, and advantages of this disclosure will become more apparent from the following detailed description and accompanying drawings.

1 is a cross-sectional view of a semiconductor device according to a first embodiment; FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment. FIG. 11 is a cross-sectional view of a semiconductor device according to a third embodiment. FIG. 13 is a cross-sectional view of a semiconductor device according to a first modification of the third embodiment. FIG. 13 is a cross-sectional view of a semiconductor device according to a second modification of the third embodiment. 13A to 13C are a top view, a cross-sectional view along line AA, and a cross-sectional view along line BB of a semiconductor device according to a fourth embodiment of the present invention, viewed from above a semiconductor element. FIG. 13 is a top view of a part of a semiconductor device according to a first modification of the fourth embodiment, viewed from above a semiconductor element. FIG. 13 is a top view of a part of a semiconductor device according to a second modification of the fourth embodiment, viewed from above a semiconductor element. FIG. 13 is a top view of a part of a semiconductor device according to a third modification of the fourth embodiment, viewed from above a semiconductor element.

<First embodiment>
First Embodiment A first embodiment will be described below with reference to the drawings. Fig. 1 is a cross-sectional view of a semiconductor device 100 according to a first embodiment.

As shown in FIG. 1, the semiconductor device 100 includes a base plate 1, an insulating substrate 2, a semiconductor element 3, a main terminal 4, a resin case 5, and a sealing resin 6.

The base plate 1 has a rectangular shape when viewed from above, and is made of a material with relatively high thermal conductivity, such as copper, a copper alloy, aluminum, or an aluminum alloy.

The insulating substrate 2 has _a front circuit pattern 2a, a ceramic substrate 2b, and a back circuit pattern 2c. The ceramic substrate 2b is made of ceramics such as _Al2O3 , _AlN , and _Si3N4 . The front circuit pattern 2a and the back circuit pattern 2c are made of metals mainly composed of Cu. The front circuit pattern 2a and the back circuit pattern 2c are respectively joined to the front and back surfaces of the ceramic substrate 2b by brazing material (not shown). The front circuit pattern 2a is a circuit pattern on which the semiconductor element 3 is to be mounted, and is selectively patterned. That is, a plurality of front circuit patterns 2a are formed, and the circuits required for the semiconductor device 100 are formed.

The semiconductor element 3 is mounted on the front circuit pattern 2a by bonding the back electrode (e.g., collector electrode) of the semiconductor element 3 via a bonding material 7 made of lead-free solder such as Sn-Ag. The semiconductor element 3 is a power semiconductor element made of, for example, Si, SiC, or GaN, and since power semiconductor elements generate high temperatures during operation, it is important to ensure high heat dissipation. Note that although two semiconductor elements 3 are shown in FIG. 1, the number is not limited to two and may be one or more.

The main terminal 4, which is mainly composed of Cu, is bonded to the surface electrode (e.g., emitter electrode or gate electrode) of the semiconductor element 3 via a bonding material 7 to form various wiring, thereby forming the circuits required for the semiconductor device 100.

The resin case 5 is formed into a rectangular frame shape when viewed from above, using a high heat resistant resin such as PPS. The resin case 5 is fixed to the outer periphery of the base plate 1 with an adhesive (not shown) or the like so as to surround the circuit including the semiconductor element 3. The inside of the resin case 5 is filled with a sealing resin 6 such as an epoxy resin, protecting the circuit including the semiconductor element 3.

Next, we will explain the problems that occur when manufacturing the insulating substrate 2. The manufacturing process for the insulating substrate 2 includes a plating process for soldering the surface circuit pattern 2a to the semiconductor element 3, and a plating stripping process. In the plating process, plating is applied to the entire insulating substrate 2. In the plating stripping process, only the areas necessary for soldering are masked with a resist material, and in areas that do not require plating, the plating is dissolved and removed with a stripping solution, and the plating residue is then removed with an air blower.

When manufacturing the surface circuit pattern 2a, small sagging parts may form on the outer periphery of the joint surface of the surface circuit pattern 2a with the ceramic substrate 2b. Because the sagging parts are poorly exposed to the air blow, plating residue is likely to remain in the sagging parts even after the plating removal process. When manufacturing the semiconductor device 100 with plating residue remaining, there is a risk that the plating residue that has remained in the sagging parts will flow out due to the thermal load during soldering and the flow of the sealing resin 6, degrading the appearance quality of the semiconductor device 100. Furthermore, if the plating residue flows across the surface circuit patterns 2a, there is a risk of causing insulation failure such as a short circuit between the surface circuit patterns 2a.

In contrast, in the first embodiment, as shown in FIG. 1, a recessed portion 8 that does not come into contact with the surface of the ceramic substrate 2b is formed on the back side of the outer periphery of the front circuit pattern 2a that is joined to the ceramic substrate 2b. The recessed portion 8 is formed around the entire periphery of the front circuit pattern 2a.

The recessed portion 8 is provided as an opening larger than the small sagging portion in the area where the sagging portion is formed, which allows sufficient penetration of the plating remover solution to the back side of the outer periphery of the front circuit pattern 2a, and improves the air blowing effect. This makes it possible to reduce plating residue.

As described above, the semiconductor device 100 according to the first embodiment includes an insulating substrate 2, a semiconductor element 3 mounted on the surface of the surface circuit pattern 2a, and a base plate 1 joined to the back side of the ceramic substrate 2b.

The insulating substrate 2 also includes a ceramic substrate 2b and a surface circuit pattern 2a that is bonded to the surface of the ceramic substrate 2b and on which a semiconductor element 3 is to be mounted. A recessed portion 8 that does not come into contact with the surface of the ceramic substrate 2b is formed on the back side of the outer periphery of the surface circuit pattern 2a that is bonded to the ceramic substrate 2b.

Therefore, in the plating stripping process carried out before bonding the surface circuit pattern 2a to the semiconductor element 3, the stripping solution is more easily absorbed into the back side of the outer periphery of the surface circuit pattern 2a, and the air blowing for removing the plating residue is improved, making it possible to more effectively remove unnecessary plating residue. This makes it possible to suppress deterioration of the appearance quality and insulation defects such as short circuits between the surface circuit patterns 2a caused by plating residue in the semiconductor device 100.

As a result, it is possible to improve the durability of the insulating substrate 2 and the semiconductor device 100, and to improve the yield.

<Embodiment 2>
Next, a semiconductor device 200 according to a second embodiment will be described. Fig. 2 is a cross-sectional view of the semiconductor device 200 according to the second embodiment. Note that in the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 2, in the second embodiment, the recessed portion 8 is not formed in the surface circuit pattern 2a, but the recessed portion 9 is formed in the ceramic substrate 2b.

The recessed portion 9 is formed so as to be recessed downward in a portion of the ceramic substrate 2b adjacent to the outer periphery of the surface circuit pattern 2a. Specifically, the recessed portion 9 is formed from a portion of the ceramic substrate 2b facing the entire periphery of the surface circuit pattern 2a toward the outer periphery. Due to the recessed portion 9 being formed, the outer periphery of the surface circuit pattern 2a does not come into contact with the surface of the ceramic substrate 2b.

The recessed portion 9 is provided as an opening larger than the sagging portion in the portion adjacent to the portion where the minute sagging portion is formed, which allows sufficient penetration of the plating remover solution to the back side of the outer periphery of the front circuit pattern 2a and improves the air blowing effect. This makes it possible to reduce plating residue.

As described above, in the semiconductor device 200 according to the second embodiment, the insulating substrate 2 includes a ceramic substrate 2b and a surface circuit pattern 2a bonded to the surface of the ceramic substrate 2b and on which a semiconductor element 3 is to be mounted. A recessed portion 9 recessed downward is formed in a portion of the ceramic substrate 2b adjacent to the outer periphery of the surface circuit pattern 2a.

Therefore, in the plating stripping process carried out before bonding the surface circuit pattern 2a to the semiconductor element 3, the stripping solution is more likely to penetrate the back side of the outer periphery of the surface circuit pattern 2a, and the air blowing for removing the plating residue is improved, making it possible to more effectively remove unnecessary plating residue. This makes it possible to suppress deterioration of the appearance quality and insulation defects such as short circuits between the surface circuit patterns 2a caused by plating residue in the semiconductor device 200.

<Third embodiment>
Next, a semiconductor device 300 according to a third embodiment will be described. Fig. 3 is a cross-sectional view of the semiconductor device 300 according to the third embodiment. Note that in the third embodiment, the same components as those described in the first and second embodiments are denoted by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 3, in the third embodiment, the recessed portions 8 and 9 are not formed, and the outer periphery of the surface circuit pattern 2a is formed in a tapered shape 10 in which the width of the surface circuit pattern 2a narrows from the back surface bonded to the ceramic substrate 2b toward the front surface on which the semiconductor element 3 is mounted. The tapered shape 10 is formed around the entire periphery of the surface circuit pattern 2a.

By forming the outer periphery of the surface circuit pattern 2a into a tapered shape 10, the outer periphery of the surface circuit pattern 2a faces upward, making it easier for the stripping solution to penetrate the entire outer periphery of the surface circuit pattern 2a, and improving the airflow for removing plating residue, making it possible to more effectively remove unnecessary plating residue.

As described above, in the semiconductor device 300 according to the third embodiment, the insulating substrate 2 includes a ceramic substrate 2b and a surface circuit pattern 2a bonded to the surface of the ceramic substrate 2b, on which the semiconductor element 3 is to be mounted. The outer periphery of the surface circuit pattern 2a is formed in a tapered shape 10 in which the width of the surface circuit pattern 2a narrows from the back surface bonded to the ceramic substrate 2b toward the front surface on which the semiconductor element 3 is to be mounted.

Therefore, in the plating stripping process carried out before bonding the surface circuit pattern 2a to the semiconductor element 3, the stripping solution is more likely to penetrate the entire outer periphery of the surface circuit pattern 2a, and the air blowing for removing the plating residue is improved, making it possible to more effectively remove unnecessary plating residue. This makes it possible to suppress deterioration of the appearance quality and insulation defects such as short circuits between the surface circuit patterns 2a caused by plating residue in the semiconductor device 300.

<Modification of the Third Embodiment>
Next, first and second modifications of the third embodiment will be described. Fig. 4 is a cross-sectional view of a semiconductor device 400 according to a first modification of the third embodiment. Fig. 5 is a cross-sectional view of a semiconductor device 500 according to a second modification of the third embodiment.

As shown in FIG. 4, the tapered shape 11 of the outer periphery of the surface circuit pattern 2a may be formed in a curved shape. Also, as shown in FIG. 5, the tapered shape 12 of the outer periphery of the surface circuit pattern 2a may be formed in a stepped shape. In these cases, the same effect as in the third embodiment can be obtained.

<Fourth embodiment>
Next, a semiconductor device 600 according to a fourth embodiment will be described. Fig. 6(a) is a top view of the semiconductor device 600 according to the fourth embodiment, viewed from above the semiconductor element 3. Fig. 6(b) is a cross-sectional view taken along line A-A in Fig. 6(a), and Fig. 6(c) is a cross-sectional view taken along line B-B in Fig. 6(a). Note that in the fourth embodiment, the same components as those described in the first to third embodiments are denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 6(a), in the fourth embodiment, cutout portions 13 are formed in place of the recessed portions 8 and 9 and the tapered shapes 10, 11, and 12. A plurality of cutout portions 13 are formed continuously around the entire periphery of the outer periphery of the surface circuit pattern 2a. Specifically, the cutout portions 13 have a rectangular shape when viewed from above, and two are formed on each side of the surface circuit pattern 2a.

As shown in Figures 6(a), (b), and (c), the cutout portion 13 is formed to the same thickness as the thickness of each surface circuit pattern 2a. Also, as shown in Figures 6(a) and (b), the portion of each surface circuit pattern 2a without the cutout portion 13 has the same width d2 as the conventional structure without the cutout portion 13.

In a conventional structure without the notch 13, the width of one side at the outer periphery of each surface circuit pattern 2a is d2, and if plating residue with a length equivalent to d2 remains, there is a possibility that the plating residue will flow across the length d1 between adjacent surface circuit patterns 2a during the manufacture of the semiconductor device, and there is a risk that the plating residue will cause insulation defects such as short circuits between the surface circuit patterns 2a. Here, d2≧d1.

In contrast, in the fourth embodiment, the width d3 of one side at the outer periphery of each surface circuit pattern 2a, which is the length between adjacent cutout portions 13 on the outer periphery of each surface circuit pattern 2a, is formed to be sufficiently shorter than the length d1 between adjacent surface circuit patterns 2a (d3<d1). Therefore, even if plating residue having a length equivalent to d3 remains and flows across the length d1 between the surface circuit patterns 2a during the manufacture of the semiconductor device 600, it is possible to prevent the plating residue from coming into contact with the adjacent surface circuit patterns 2a.

As described above, in the semiconductor device 600 according to the fourth embodiment, the insulating substrate 2 includes a ceramic substrate 2b and a surface circuit pattern 2a that is bonded to the surface of the ceramic substrate 2b and on which a semiconductor element 3 is to be mounted. A plurality of continuous cutout portions 13 are formed on the outer periphery of the surface circuit pattern 2a. Furthermore, each cutout portion 13 is formed in a rectangular shape when viewed from above.

Therefore, even if plating residue flows across adjacent surface circuit patterns 2a during the manufacture of the semiconductor device 600, it is possible to prevent the plating residue from coming into contact with the adjacent surface circuit patterns 2a. This makes it possible to prevent deterioration of the appearance quality and insulation defects such as short circuits between the surface circuit patterns 2a in the semiconductor device 600, which are caused by plating residue.

<Modification of the Fourth Embodiment>
Next, modified examples 1 to 3 of the fourth embodiment will be described. Fig. 7 is a top view of a portion of a semiconductor device 700 according to modified example 1 of the fourth embodiment, viewed from above the semiconductor element 3. Fig. 8 is a top view of a portion of a semiconductor device 800 according to modified example 2 of the fourth embodiment, viewed from above the semiconductor element 3. Fig. 9 is a top view of a portion of a semiconductor device 900 according to modified example 3 of the fourth embodiment, viewed from above the semiconductor element 3.

As shown in FIG. 7, each cutout 14 may be formed in a triangular shape when viewed from above. Also, as shown in FIG. 8, each cutout 15 may be formed in a stepped shape when viewed from above. Also, as shown in FIG. 9, each cutout 16 may be formed in an arc shape when viewed from above. In these cases, the same effect as in embodiment 4 can be obtained.

Although this disclosure has been described in detail, the above description is illustrative in all respects and is not limiting. It is understood that countless variations not illustrated can be envisioned.

In addition, each embodiment can be freely combined, modified, or omitted as appropriate.

1 base plate, 2 insulating substrate, 2a surface circuit pattern, 2b ceramic substrate, 3 semiconductor element, 8, 9 recessed portion, 10 tapered shape, 11 curved shape, 12 stepped shape, 13, 14, 15, 16 notched portion, 100, 200, 300, 400, 500, 600, 700, 800, 900 semiconductor device.

Claims (9)

A ceramic substrate;
A circuit pattern bonded to a surface of the ceramic substrate and on which a semiconductor element is to be mounted;
an insulating substrate, wherein a recessed portion is formed on the outer periphery of the circuit pattern on the back side bonded to the ceramic substrate, the recessed portion not in contact with the front surface of the ceramic substrate; A ceramic substrate;
A circuit pattern bonded to a surface of the ceramic substrate and on which a semiconductor element is to be mounted;
an insulating substrate, wherein a recessed portion recessed downward is formed in a portion of the ceramic substrate adjacent to an outer periphery of the circuit pattern; A ceramic substrate;
A circuit pattern bonded to a surface of the ceramic substrate and on which a semiconductor element is to be mounted;
An insulating substrate, wherein the outer periphery of the circuit pattern is formed in a tapered shape in which the width of the circuit pattern narrows from the back surface joined to the ceramic substrate toward the front surface on which the semiconductor element is to be mounted. The insulating substrate according to claim 3, wherein the tapered shape of the outer periphery of the circuit pattern is formed into a curved shape. The insulating substrate according to claim 3, wherein the tapered shape of the outer periphery of the circuit pattern is formed into a stepped shape. A ceramic substrate;
A circuit pattern bonded to a surface of the ceramic substrate and on which a semiconductor element is to be mounted;
The insulating substrate has a plurality of continuous cutouts formed in an outer periphery of the circuit pattern. The insulating substrate according to claim 6, wherein each of the cutouts is formed in a rectangular shape, a triangular shape, a stepped shape, or an arc shape when viewed from above. A plurality of the circuit patterns are provided,
8. The insulating substrate according to claim 6, wherein a length between adjacent said cutout portions in said outer periphery of each said circuit pattern is shorter than a length between adjacent said circuit patterns. An insulating substrate according to any one of claims 1 to 8;
The semiconductor element mounted on a surface of the circuit pattern;
A base plate joined to the rear surface side of the ceramic substrate;
A semiconductor device comprising:

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