WO2024148127A1

WO2024148127A1 - Substrate encapsulation

Info

Publication number: WO2024148127A1
Application number: PCT/US2024/010245
Authority: WO
Inventors: Jeb H. Flemming; Timothy J. MEZEL
Original assignee: 3D Glass Solutions, Inc.
Priority date: 2023-01-06
Filing date: 2024-01-04
Publication date: 2024-07-11

Abstract

Provided herein are device structures and methods of using SiO2. SiOx / SiNy, and SiN structures for encapsulation of a substrate to isolate the constituents of the substrate from contaminating semiconductor material and/or semiconductor devices.

Description

SUBSTRATE ENCAPSULATION

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Application Serial No. 63/478,797, filed January 6, 2023, the entire contents of which are incorporated herein by reference.

STATEMENT OF FEDERALLY FUNDED RESEARCH

[0002] None.

TECHNICAL FIELD OF THE INVENTION

[0003] The present invention relates in general to the field of creating an encapsulated structure on a glass or glass ceramic surface to prevent migration or cross contamination from the glass or glass ceramic to semiconductor devices that may be in direct contact with glass or glass ceramic substrate, where these active semiconductor devices are used in systems used in RF microwave, millimeter wave, high-speed computing, and optical connectivity applications. Encapsulation prevents damage from mobile ions, moisture, and gases from affecting performance and device/system lifetime.

BACKGROUND OF THE INVENTION

[0004] Without limiting the scope of the invention, its background is described in connection with encapsulating a glass, ceramic, or glass/ceramic substrate active- semi conductor devices to prevent damage due to physical diffusion mobile ions, and or exposure to moisture and gases.

[0005] Glass, ceramic or glass/ceramic materials are used to make substrates in printed circuit boards and advance packaging applications. The glass, ceramic, or glass/ceramic substrates are comprised of elements that can damage or reduce the lifetime of the semiconductor device. These elements/ions can move from substrate to semiconductor device interface with an electric field or thermal gradient during the system lifetime between vias and other structures and the substrate used for RF microwave, millimeter wave, high-speed computing, and optical connectivity applications. The fundamental problem is the metal interconnect for high-speed electronics and computers is generally copper and requires an adhesion layer to a PCB, PTFE, Glass, Glass composite, or ceramic substrate. [0006] Even copper is being evaluated as a performance/lifetime limiting contamination in silicon devices; see, e.g., “First-principles study of copper contamination in silicon semiconductor” by Chen et al. (www.sciencedirect.com/science/article/abs/pii/S2468023022003522). Copper (Cu) has been widely used as an interconnect material in the semiconductor industry, due to its advantages of high electrical and thermal conductivities, good electro-migration resistance, and low cost. Cu is very reactive, and contamination such as physical diffusion from Cu to silicon (Si) and the chemical combination between Cu and Si is commonly observed and detrimental to Si semiconductor devices. Cu/Si has been shown to have an interfacial diffusion mechanism, including the diffusibility of vacancy and interstitial diffusion.

[0007] What is needed are novel structures and methods for preventing the physical diffusion of mobile ions between semiconductor devices and/or their substrate, and to protect these devices from exposure to moisture and gases.

SUMMARY OF THE INVENTION

[0008] The novel encapsulation layer of the present invention provides a barrier to mobile ions, gases and moisture diffusion that damages the electronics/semiconductor in, e.g., a System in a Package (SiP). The encapsulation layer can be placed in conjunction with active devices and can be combined to make a wide array of RF systems, High Speed Computers, optical, electro-optical and MEMS systems and subsystems including but not limited to: antennas with gain, RF Circulators, RF Isolators, RF Combiners, RF Couplers, RF Splitters, Transformers, High speed CPUs, High speed A to Ds, High speed D to As, Optical Couplers, Optical Modulators, Laser Diode, VECSLS, Switches, Multiplexors, Duplexers, Memories and/or Diplexers that are connected by via(s) and/or metal lines to each other, electrical, optical power and/or electrical ground planes. This invention provides a general solution to the construction of electrical connections from the metal layer to the via metal or electrical conductor, eliminating the random device performance and parasitic across the substrate reducing size and enhancing performance of a SiP.

[0009] As embodied and broadly described herein, an aspect of the present disclosure relates to a device structure comprising an S1O2. SiOx / SiN_y, and SiN structure for encapsulation of a substrate to isolate the constituents of the substrate from contaminating semiconductor material and or semiconductor devices. In one aspect, the substrate is selected from at least one of: a borosilicate glass, a photo-definable glass, a glass/ceramic composite, or a ceramic. In another aspect, the SiCh layer is greater than 20 A and less than 10pm in thickness. In another aspect, the SiOx / SiN_y layer is greater than 20A and less than 10,000 A in thickness. In another aspect, the in the SiOx layer, x ranges from 0.5 to 3. In another aspect, in the SiN_y layer, y ranges from 0.5 to 2. In another aspect, the SiN layer is greater than 20A and less than 10,000 A in thickness. In another aspect, the substrate comprises electrically and thermally conductive structures. In another aspect, the semiconductor devices comprise an RF Circuit that eliminates at least 10% of the RF parasitic signal associated with a transition from the substrate to the electrically and thermally conductive structures. In another aspect, the electrically and thermally conductive structures comprise through-hole vias, blind vias, interconnects or heat spreader elements. In another aspect, the through hole vias, blind vias, interconnects, or heat spreader elements comprise copper or another metal. In another aspect, the device structure is laminated or layered to form an equivalent of a multilayer PCB structure. In another aspect, the semiconductor devices comprise at least one of: microprocessor/CPU, optical, electro-optical, MEMS device, antennas, RF Circulators, RF Isolators, RF Combiners, RF Couplers, RF Splitters, Transformers, A to Ds, high-speed D to As, Optical Couplers, Optical Modulators, Laser Diode, VECSLS, Switches, Multiplexors, Duplexers, Diplexers, Memories and/or Diplexers, RF Filters, RF Circulators, RF Isolators, Antenna, Impedance Matching Elements, 50 Ohm Termination Elements, Integrated Ground Planes, RF Shielding Elements, EMI Shielding Elements, RF Combiners, RF Splitters, Transformers, Switches, power splitters, power combiners, Memory chips, or Microcontrollers.

[0010] As embodied and broadly described herein, an aspect of the present disclosure relates to a method for encapsulation of a substrate to isolate constituents on the substrate from contaminating semiconductor material and or semiconductor devices device structure comprising the steps of: cleaning a surface of the substrate using plasma or other surface treatment process, wherein the substrate has a thickness that ranges from 25pm to 2500 pm; depositing an adhesion layer of SiCh, wherein the layer ranges between 20A to 40,000A and during the deposition of the adhesion layer reducing the oxygen gas and replacing it with nitrogen gas until the nitrogen gas is 100% of the gas to form a transition layer, wherein a region of and wherein the transition layer comprises SiOx / SiNy and is between 20A to 40,000A thick, and once the gas is 100% nitrogen gas transiting the SiOx / SiNy to SiN(z); forming a via mask pattern, etching the encapsulation layer, and exposing the metal connectors and heat spreaders; and attaching or forming one or more semiconductor, passive devices, or MEMS devices on the substrate. In one aspect, the one or more semiconductor, passive devices, or MEMS devices attached to the substrate are an integral part of the substrate. In another aspect, the adhesion layer, transitional layer, and final layer deposited comprises an SiCh, SiOx / SiNy, and SiN structure. In another aspect, the thickness of the substrate is between 100 to 200 pm. In another aspect, a thickness of each of the adhesion layer, transitional layer, and final layer is 100 to 200 pm. In another aspect, a thickness the adhesion layer, transitional layer, and final layer is 100 to 200 pm. In another aspect, the deposition conditions of temperature and plasma density/energy are selected such that the SiN(z) will become stoichiometrically SiN. In another aspect, the substrate is selected from at least one of a borosilicate glass, a photo-definable glass, a glass/ceramic composite, or a ceramic. In another aspect, the SiCh layer is greater than 20A and less than 10pm in thickness. In another aspect, the SiOx / SiNy layer is greater than 20A and less than 10,000 A in thickness. In another aspect, in the SiOx layer, x ranges from 0.5 to 3. In another aspect, in the SiNy layer, y ranges from 0.5 to 2. In another aspect, the SiN layer is greater than 20A and less than 10,000 A in thickness. In another aspect, the substrate comprises electrically and thermally conductive structures. In another aspect, the semiconductor devices comprise an RF Circuit that eliminates at least 10% of the RF parasitic signal associated with a transition from the substrate to the electrically and thermally conductive structures. In another aspect, the electrically and thermally conductive structures comprise through-hole vias, blind vias, interconnects or heat spreader elements. In another aspect, the through-hole vias, blind vias, interconnects, or heat spreader elements comprise copper or another metal. In another aspect, the device structure is laminated or layered to form an equivalent of a multilayer PCB structure. In another aspect, the semiconductor devices comprise at least one of: microprocessor/CPU, optical, electro-optical, MEMS device, antennas, RF Circulators, RF Isolators, RF Combiners, RF Couplers, RF Splitters, Transformers, A to Ds, high-speed D to As, Optical Couplers, Optical Modulators, Laser Diode, VECSLS, Switches, Multiplexors, Duplexers, Diplexers, Memories and/or Diplexers, RF Filters, RF Circulators, RF Isolators, Antenna, Impedance Matching Elements, 50 Ohm Termination Elements, Integrated Ground Planes, RF Shielding Elements, EMI Shielding Elements, RF Combiners, RF Splitters, Transformers, Switches, power splitters, power combiners, Memory chips, or Microcontrollers.

[0011] As embodied and broadly described herein, an aspect of the present disclosure relates to a method for preventing contamination of semiconductor devices comprising: encapsulating a substrate to isolate one or more constituents on the substrate from contaminating semiconductor material and or semiconductor devices device structure, by: cleaning a surface of the substrate using plasma or other surface treatment process, wherein the substrate has a thickness that ranges from 25pm to 2500 pm; depositing an adhesion layer of SiO2, wherein the layer ranges between 20A to 40,000A and during the deposition of the adhesion layer reducing the oxygen gas and replacing it with nitrogen gas until the nitrogen gas is 100% of the gas to form a transition layer, wherein a region of and wherein the transition layer comprises SiOx / SiNy and is between 20A to 40,000A thick, and once the gas is 100% nitrogen gas transiting the SiOx / SiNy to SiN(z); forming a via mask pattern, etching the encapsulation layer, and exposing the metal connectors and heat spreaders; and attaching or forming one or more semiconductor, passive devices, or MEMS devices on the substrate, wherein the substrate is protected from contamination.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] For a more complete understanding of the features and advantages of the present invention, reference is now made to the detailed description of the invention along with the accompanying figures and in which:

[0013] FIG. 1 shows a glass/glass ceramic/ceramic substrate with the deposited SiO2, SiOx/SiNy, and SiN layers.

[0014] FIG. 2 shows a schematic of substrate encapsulation structure (SiO2, SiOx/SiNy, and SiN) on a glass, glass-ceramic, or ceramic substrate with conductive through hole via, conductive blind via, and conductive heat spreader/sink.

[0015] FIG. 3 is a flowchart of an example of a method of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0016] While the production and use of various embodiments of the present invention are discussed in detail below, it should be appreciated that the present invention provides many applicable, inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed herein are merely illustrative of specific ways to make and use the invention and do not delimit the scope of the invention.

[0017] To facilitate the understanding of this invention, a number of terms are defined below. Terms defined herein have meanings as commonly understood by a person of ordinary skill in the areas relevant to the present invention. Terms such as “a”, “an” and “the” are not intended to refer to only a singular entity, but include the general class of which a specific example may be used for illustration. The terminology herein is used to describe specific embodiments of the invention, but their usage does not limit the invention, except as outlined in the claims.

[0018] In one embodiment, the present invention includes a method for encapsulating a substrate, with a SiC>2, SiO_x/SiN_y, and SiN layer where the substrate is boron silicate glass.

[0019] In another embodiment, the present invention includes a method for encapsulating a substrate with a SiCh, SiO_x/SiN_y, and SiN layer where the substrate is a form of gorilla glass.

[0020] In another embodiment, the present invention includes a method for encapsulating a substrate with a SiCh, SiO_x/SiN_y, and SiN layer where the substrate is a form of photo-definable glass.

[0021] In another embodiment, the present invention includes a method for encapsulating a substrate with a SiCh, SiO_x/SiN_y, and SiN layer where the substrate is a form of glass ceramic composite.

[0022] In another embodiment, the present invention includes a method for encapsulating a substrate with a SiCh, SiO_x/SiN_y, and SiN layer where the substrate is a form of ceramic composite.

[0023] In another embodiment, the present invention includes a method for encapsulating a substrate, with a SiO , SiOx/SiNy, and SiN layer where the substrate is boron silicate glass with copper-filled vias and contactors.

[0024] Non-limiting examples of substrates for use with the present invention include a glassceramic (APEX® glass-ceramic). This substrate material can be used with semiconductors, RF electronics, microwave electronics, and optical imaging devices. APEX® glass-ceramic is processed using first-generation semiconductor equipment in a simple three-step process and the final material can be fashioned into either glass, ceramic, or a material containing regions of both glass and ceramic. The APEX® glass ceramic possesses several benefits over current materials, including easily fabricated high density vias, demonstrated microfluidic capability, micro-lens or micro-lens array capability, a high Young’s modulus for stiffer packages, halogen-free manufacturing, and economical manufacturing. Photodefinable glasses such as APEX® have several advantages for the fabrication of a wide variety of microsystems components. Microstructures have been produced relatively inexpensively with these glasses using conventional semiconductor processing equipment.

[0025] In general, glasses have high-temperature stability, good mechanical and electrical properties, and better chemical resistance than plastics and many metals. One example of a glass ceramic includes, for example, silicon oxide (SiO₂) of 75 to 85% by weight, lithium oxide (Li₂O) of 7 to 11% by weight, aluminum oxide (A1₂O₂) of 3 to 6% by weight, sodium oxide (Na₂O) of 1 to 2% by weight, 0.2% to 0.5% by weight of either antimony trioxide (Sb₂O₂), arsenic oxide (As₂O₂) or silver oxide (Ag₂O) of 0.05 to 0.15% by weight, and cerium oxide (CeO₂) of 0.01 to 0.04% by weight. As used herein the terms “APEX® glass ceramic,” “APEX® glass,” or simply “APEX®” are used to denote one embodiment of the glass-ceramic composition for making an apparatus with one or more electronic devices on or in a photodefinable glass substrate that has blind or through openings etched or machined into the photodefinable glass substrate, where the electronic circuit and openings are filled by the use of a standard material and process.

[0026] Any exposed portion of the photodefinable glass substrate in the form of an opening structure is transformed into a crystalline material by heating the glass substrate to a temperature near the glass transformation temperature. When etching the glass substrate in an etchant such as hydrofluoric (HF) acid, the anisotropic-etch ratio of the exposed portion to the unexposed portion is at least 30: 1 when the glass is exposed to a broad spectrum mid-ultraviolet (about 308-312 nm) flood lamp. The exposed glass is then baked typically in a two-step process. First, the exposed glass is heated between 420°C and 520°C for between 10 minutes to 2 hours, to coalesce silver ions into silver nanoparticles and second, the exposed glass is heated between 520°C and 620°C for between 10 minutes and 2 hours, allowing the lithium oxide to form around the silver nanoparticles. The glass plate is then etched. The glass substrate is etched in an etchant of HF solution, typically 5% to 10% by volume, wherein the etch ratio of an exposed portion to that of an unexposed portion can reach, e.g., at least 30: 1.

[0027] FIG. 1 shows a cross-sectional side view schematic of a glass / glass ceramic /ceramic main substrate with the deposited SiCh, SiOx / SiNy, and SiNx layers of the present invention. On the surface of glass / glass ceramic /ceramic main substrate, an SiO₂ layer is formed via PECVD or other depositing method in the presence of oxygen gas. During the deposition of the SiO₂ layer, adding nitrogen gas to the oxygen gas to form a transitional layer of SiOx / SiNy, and finally once the gas reaches 100% nitrogen gas, then forming an SiNx layer.

[0028] FIG. 2 shows a cross-sectional side view schematic of a substrate encapsulation structure (SiCh, SiOx/SiNy, and SiN) on a glass, glass-ceramic, or ceramic substrate with a conductive through-hole via, conductive blind via, and conductive heat spreader/ sink formed on a glass / glass ceramic /ceramic main substrate, and metal interconnect and which shows the position of the SiOs, SiOx/SiNy, and SiN layers in relation to the various interconnects, including the exemplary conductive through-hole via, conductive blind via, metal interconnect, and conductive heat spreader/sink. [0029] Table 1 shows a step-by-step method of making the device of the present invention. The process flow to create an encapsulated glass glass/ceramic or ceramic substrate is as follows:

[0030] FIG. 3 shows an exemplary method of the present invention. In step 10, cleaning the surface of a substrate using plasma or other surface treatment process, where the substrate can range from 25 pm to 2500 pm. In step 20, using a plasma-enhanced chemical vapor deposition (PECVD) or another deposition method to deposit an adhesion layer of SiCh, where the deposition layer can range between 20 A to 40,000A. In step 30, during the deposit of the SiCh reduce the oxygen gas and replace it with nitrogen gas until the nitrogen gas is pure. This will create a region of SiOx / SiNy. The transition layer can range between 20A to 40,000A. In step 40, once the gas is pure nitrogen gas the SiOx / SiNy will transition to SiN(z). Depending on the deposition conditions (temperature and plasma density/ energy) the SiN(z)will become stoichiometrically SiN. In step 50, using the Via mask pattern, etch the encapsulation layer, exposing the metal connectors and heat spreaders. Finally, in step 60, attaching semiconductor and passive devices. In some cases, passive and/or MEMS devices may be an integral part of the substrate.

[0031] It is understood that particular embodiments described herein are shown by way of illustration and not as limitations of the invention. As an example, the metal interconnect may run on the surface of the substrate underneath the SiCh. SiOx / SiNy, and SiN structure, where these substrates can be laminated/layered to form an equivalent of a multilayer PCB structure for RF systems, High Speed Computers, optical, electro-optical and MEMS systems and subsystems including but not limited to: antennas with gain, RF Circulators, RF Isolators, RF Combiners, RF Couplers, RF Splitters, Transformers, High speed CPUs, High speed A to Ds, High speed D to As, Optical Couplers, Optical Modulators, Laser Diode, VECSLS, Switches, Multiplexors, Duplexers, Memories and/or Diplexers.

[0032] In one embodiment, a device structure comprises, consists essentially of, or consists of an SiO2, SiOx / SiNy, and SiN structure for encapsulation of a substrate to isolate the constituents of the substrate from contaminating semiconductor material and or semiconductor devices. In one aspect, the substrate comprises, consists essentially of, or consists of a borosilicate glass. In another aspect, the substrate comprises, consists essentially of, or consists of a phot-definable glass. In another aspect, the substrate comprises the substrate comprises, consists essentially of, or consists of a glass/ceramic composite. In another aspect, the substrate comprises the substrate comprises, consists essentially of, or consists of ceramic. In another aspect, the SiCh layer is greater than 20A and less than 10pm in thickness. In another aspect, the SiOx / SiNy layer is greater than 20A and less than 10,000 A in thickness. In another aspect, in the SiOx layer, x ranges from 0.5 to 3. In another aspect, in the SiNy layer, y ranges from 0.5 to 2. In another aspect, the SiN layer is greater than 20A and less than 10,000 A in thickness. In another aspect, the substrate comprises electrically and thermally conductive structures. In another aspect, the semiconductor devices comprise an RF Circuit that eliminates at least 10% of the RF parasitic signal associated with a transition from the substrate to the electrically and thermally conductive structures. In another aspect, the electrically and thermally conductive structures comprise through-hole vias, blind vias, interconnects, or heat spreader elements. In another aspect, the through hole vias, blind vias, interconnects, or heat spreader elements comprise copper or another metal. In another aspect, the device structure is laminated or layered to form an equivalent of a multilayer PCB structure. In another aspect, the semiconductor devices comprise: microprocessor/CPU, optical, electro-optical, MEMS device, antennas, RF Circulators, RF Isolators, RF Combiners, RF Couplers, RF Splitters, Transformers, A to Ds, high-speed D to As, Optical Couplers, Optical Modulators, Laser Diode, VECSLS, Switches, Multiplexors, Duplexers, Diplexers, Memories and/or Diplexers, RF Filters, RF Circulators, RF Isolators, Antenna, Impedance Matching Elements, 50 Ohm Termination Elements, Integrated Ground Planes, RF Shielding Elements, EMI Shielding Elements, RF Combiners, RF Splitters, Transformers, Switches, power splitters, power combiners, Memory chips, or Microcontrollers.

[0033] As embodied and broadly described herein, an aspect of the present disclosure relates to a method for encapsulation of a substrate to isolate constituents on the substrate from contaminating semiconductor material and or semiconductor devices device structure comprising, consisting essentially of, or consisting of the steps of: cleaning a surface of the substrate using plasma or other surface treatment process, wherein the substrate has a thickness that ranges from 25 pm to 2500 pm; depositing an adhesion layer of SiCh, wherein the layer ranges between 20A to 40,000A and during the deposition of the adhesion layer reducing the oxygen gas and replacing it with nitrogen gas until the nitrogen gas is 100% of the gas to form a transition layer, wherein a region of and wherein the transition layer comprises SiOx / SiNy and is between 20A to 40,000A thick, and once the gas is 100% nitrogen gas transiting the SiOx / SiNy to SiN(z); forming a via mask pattern, etching the encapsulation layer, and exposing the metal connectors and heat spreaders; and attaching or forming one or more semiconductor, passive devices, or MEMS devices on the substrate. In one aspect, the one or more semiconductor, passive devices, or MEMS devices attached to the substrate are an integral part of the substrate. In another aspect, the adhesion layer, transitional layer, and final layer deposited comprises an SiCh, SiOx / SiNy, and SiN structure. In another aspect, the thickness of the substrate is between 100 to 200 pm. In another aspect, a thickness of each of the adhesion layer, transitional layer, and final layer is 100 to 200 pm. In another aspect, a thickness the adhesion layer, transitional layer, and final layer is 100 to 200 pm. In another aspect, the deposition conditions of temperature and plasma density/energy are selected such that the SiN(z) will become stoichiometrically SiN. In another aspect, the substrate is selected from at least one of: a borosilicate glass, a photo-definable glass, a glass/ceramic composite, or a ceramic. In another aspect, the SiCh layer is greater than 20A and less than 10pm in thickness. In another aspect, the SiOx / SiNy layer is greater than 20A and less than 10,000 A in thickness. In another aspect, in the SiOx layer, x ranges from 0.5 to 3. In another aspect, in the SiN_y layer, y ranges from 0.5 to 2. In another aspect, the SiN layer is greater than 20A and less than 10,000 A in thickness. In another aspect, the substrate comprises electrically and thermally conductive structures. In another aspect, the semiconductor devices comprise an RF Circuit that eliminates at least 10% of the RF parasitic signal associated with a transition from the substrate to the electrically and thermally conductive structures. In another aspect, the electrically and thermally conductive structures comprise through-hole vias, blind vias, interconnects or heat spreader elements. In another aspect, the through-hole vias, blind vias, interconnects, or heat spreader elements comprise copper or another metal. In another aspect, the device structure is laminated or layered to form an equivalent of a multilayer PCB structure. In another aspect, the semiconductor devices comprise at least one of: microprocessor/CPU, optical, electro-optical, MEMS device, antennas, RF Circulators, RF Isolators, RF Combiners, RF Couplers, RF Splitters, Transformers, A to Ds, high-speed D to As, Optical Couplers, Optical Modulators, Laser Diode, VECSLS, Switches, Multiplexors, Duplexers, Diplexers, Memories and/or Diplexers, RF Filters, RF Circulators, RF Isolators, Antenna, Impedance Matching Elements, 50 Ohm Termination Elements, Integrated Ground Planes, RF Shielding Elements, EMI Shielding Elements, RF Combiners, RF Splitters, Transformers, Switches, power splitters, power combiners, Memory chips, or Microcontrollers.

[0034] As embodied and broadly described herein, an aspect of the present disclosure relates to a method for preventing contamination of semiconductor devices comprising, consisting essentially of, or consisting of the steps of: encapsulating a substrate to isolate one or more constituents on the substrate from contaminating semiconductor material and or semiconductor devices device structure, by: cleaning a surface of the substrate using plasma or other surface treatment process, wherein the substrate has a thickness that ranges from 25pm to 2500 pm; depositing an adhesion layer of SiO2, wherein the layer ranges between 20A to 40,000A and during the deposition of the adhesion layer reducing the oxygen gas and replacing it with nitrogen gas until the nitrogen gas is 100% of the gas to form a transition layer, wherein a region of and wherein the transition layer comprises SiOx / SiNy and is between 20 A to 40,000A thick, and once the gas is 100% nitrogen gas transiting the SiOx / SiNy to SiN(z); forming a via mask pattern, etching the encapsulation layer, and exposing the metal connectors and heat spreaders; and attaching or forming one or more semiconductor, passive devices, or MEMS devices on the substrate, wherein the substrate is protected from contamination.

[0035] Where the principal features of this invention can be employed in various embodiments without departing from the scope of the invention. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, numerous equivalents to the specific procedures described herein. Such equivalents are considered to be within the scope of this invention and are covered by the claims.

[0036] All publications and patent applications mentioned in the specification are indicative of the level of skill of those skilled in the art to which this invention pertains. All publications and patent applications are herein incorporated by reference to the same extent as if each individual publication or patent application was specifically and individually indicated to be incorporated by reference.

[0037] The use of the word “a” or “an” when used in conjunction with the term “comprising” in the claims and/or the specification may mean “one,” but it is also consistent with the meaning of “one or more,” “at least one,” and “one or more than one.” The use of the term “or” in the claims is used to mean “and/or” unless explicitly indicated to refer to alternatives only or the alternatives are mutually exclusive, although the disclosure supports a definition that refers to only alternatives and “and/or.” Throughout this application, the term “about” is used to indicate that a value includes the inherent variation of error for the device, the method being employed to determine the value, or the variation that exists among the study subjects.

[0038] As used in this specification and claim(s), the words “comprising” (and any form of comprising, such as “comprise” and “comprises”), “having” (and any form of having, such as “have” and “has”), “including” (and any form of including, such as “includes” and “include”) or “containing” (and any form of containing, such as “contains” and “contain”) are inclusive or open- ended and do not exclude additional, unrecited elements or method steps. In embodiments of any of the compositions and methods provided herein, “comprising” may be replaced with “consisting essentially of’ or “consisting of’. As used herein, the phrase “consisting essentially of’ requires the specified integer(s) or steps as well as those that do not materially affect the character or function of the claimed invention. As used herein, the term “consisting” is used to indicate the presence of the recited integer (e.g., a feature, an element, a characteristic, a property, a method/process step or a limitation) or group of integers (e.g., feature(s), element(s), characteristic(s), property(ies), method/process steps or limitation(s)) only.

[0039] The term “or combinations thereof’ as used herein refers to all permutations and combinations of the listed items preceding the term. For example, “A, B, C, or combinations thereof’ is intended to include at least one of: A, B, C, AB, AC, BC, or ABC, and if order is important in a particular context, also BA, CA, CB, CBA, BCA, ACB, BAC, or CAB. Continuing with this example, expressly included are combinations that contain repeats of one or more item or term, such as BB, AAA, AB, BBC, AAABCCCC, CBBAAA, CABABB, and so forth. The skilled artisan will understand that typically there is no limit on the number of items or terms in any combination, unless otherwise apparent from the context.

[0040] As used herein, words of approximation such as, without limitation, “about”, "substantial" or "substantially" refers to a condition that when so modified is understood to not necessarily be absolute or perfect but would be considered close enough to those of ordinary skill in the art to warrant designating the condition as being present. The extent to which the description may vary will depend on how great a change can be instituted and still have one of ordinary skilled in the art recognize the modified feature as still having the required characteristics and capabilities of the unmodified feature. In general, but subject to the preceding discussion, a numerical value herein that is modified by a word of approximation such as “about” may vary from the stated value by at least ±1, 2, 3, 4, 5, 6, 7, 10, 12 or 15%.

[0041] All of the compositions and/or methods disclosed and claimed herein can be made and executed without undue experimentation in light of the present disclosure. While the compositions and methods of this invention have been described in terms of preferred embodiments, it will be apparent to those of skill in the art that variations may be applied to the compositions and/or methods and in the steps or in the sequence of steps of the method described herein without departing from the concept, spirit, and scope of the invention. All such similar substitutes and modifications apparent to those skilled in the art are deemed to be within the spirit, scope, and concept of the invention as defined by the appended claims. [0042] All of the devices and/or methods disclosed and claimed herein can be made and executed without undue experimentation in light of the present disclosure. While the devices and/or methods of this invention have been described in terms of preferred embodiments, it will be apparent to those of skill in the art that variations may be applied to the compositions and/or methods and in the steps or in the sequence of steps of the method described herein without departing from the concept, spirit, and scope of the invention. All such similar substitutes and modifications apparent to those skilled in the art are deemed to be within the spirit, scope, and concept of the invention as defined by the appended claims.

[0043] Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the disclosure. Accordingly, the protection sought herein is as set forth in the claims below.

[0044] Modifications, additions, or omissions may be made to the systems and apparatuses described herein without departing from the scope of the invention. The components of the systems and apparatuses may be integrated or separated. Moreover, the operations of the systems and apparatuses may be performed by more, fewer, or other components. The methods may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order.

[0045] To aid the Patent Office, and any readers of any patent issued on this application in interpreting the claims appended hereto, applicants wish to note that they do not intend any of the appended claims to invoke paragraph 6 of 35 U.S.C. § 112 as it exists on the date of filing hereof unless the words “means for” or “step for” are explicitly used in the particular claim.

[0046] For each of the claims, each dependent claim can depend both from the independent claim and from each of the prior dependent claims for each and every claim so long as the prior claim provides a proper antecedent basis for a claim term or element.

Claims

What is claimed is:

1. A device structure comprising an SiCh, SiOx / SiN_y, and SiN structure for encapsulation of a substrate to isolate the constituents of the substrate from contaminating semiconductor material and or semiconductor devices.

2. The device structure of claim 1, wherein the substrate is selected from at least one of: a borosilicate glass, a photo-definable glass, a glass/ceramic composite, or a ceramic.

3. The device structure of claim 1, wherein the SiCh layer is greater than 20A and less than 10pm in thickness.

4. The device structure of claim 1, wherein the SiOx / SiNy layer is greater than 20A and less than 10,000 A in thickness.

5. The device structure of claim 4, wherein in the SiOx layer, x ranges from 0.5 to 3.

6. The device structure of claim 4, wherein in the SiNy layer, y ranges from 0.5 to 2.

7. The device structure of claim 1, wherein the SiN layer is greater than 20A and less than

10,000 A in thickness.

8. The device structure of claim 1, wherein the substrate comprises electrically and thermally conductive structures.

9. The device structure of claim 8, wherein the semiconductor devices comprise an RF Circuit that eliminates at least 10% of the RF parasitic signal associated with a transition from the substrate to the electrically and thermally conductive structures.

10. The device structure of claim 8, wherein the electrically and thermally conductive structures comprise through hole vias, blind vias, interconnects or heat spreader elements.

11. The device structure of claim 10, wherein the through hole vias, blind vias, interconnects, or heat spreader elements comprise copper or another metal.

12. The device structure of claim 1, wherein the device structure is laminated or layered to form an equivalent of a multilayer PCB structure.

13. The device structure of claim 1, wherein the semiconductor devices comprise: microprocessor/CPU, optical, electro-optical, MEMS device, antennas, RF Circulators, RF Isolators, RF Combiners, RF Couplers, RF Splitters, Transformers, A to Ds, High speed D to As, Optical Couplers, Optical Modulators, Laser Diode, VECSLS, Switches, Multiplexors, Duplexers, Diplexers, Memories and/or Diplexers, RF Filters, RF Circulators, RF Isolators, Antenna, Impedance Matching Elements, 50 Ohm Termination Elements, Integrated Ground Planes, RF Shielding Elements, EMI Shielding Elements, RF Combiners, RF Splitters, Transformers, Switches, power splitters, power combiners, Memory chips, or Microcontrollers.

14. A method for encapsulation of a substrate to isolate constituents on the substrate from contaminating semiconductor material and or semiconductor devices device structure comprising the steps of cleaning a surface of the substrate using plasma or other surface treatment process, wherein the substrate has a thickness that ranges from 25pm to 2500 pm; depositing an adhesion layer of SiCh, wherein the layer ranges between 20A to 40,000A and during the deposition of the adhesion layer reducing the oxygen gas and replacing it with nitrogen gas until the nitrogen gas is 100% of the gas to form a transition layer, wherein a region of and wherein the transition layer comprises SiOx / SiNy and is between 20A to 40,000A thick, and once the gas is 100% nitrogen gas transiting the SiOx / SiNy to SiN(z); forming a via mask pattern, etching the encapsulation layer, and exposing the metal connectors and heat spreaders; and attaching or forming one or more semiconductor, passive devices, or MEMS devices on the substrate.

15. The method of claim 14, wherein the one or more semiconductor, passive devices, or MEMS devices attached to the substrate are an integral part of the substrate.

16. The method of claim 14, wherein the adhesion layer, transitional layer, and final layer deposited comprises an SiCh, SiOx / SiNy, and SiN structure.

17. The method of claim 14, wherein the thickness of the substrate is between 100 to 200 pm.

18. The method of claim 14, wherein a thickness of each of the adhesion layer, transitional layer, and final layer is 100 to 200 pm.

19. The method of claim 14, wherein a thickness the adhesion layer, transitional layer, and final layer is 100 to 200 pm.

20. The method of claim 14, wherein the deposition conditions of temperature and plasma density/energy are selected such that the SiN(z) will become stoichiometrically SiN.

21. The method of claim 14, wherein the substrate is selected from at least one of: a borosilicate glass, a photo-definable glass, a glass/ceramic composite, or a ceramic.

22. The method of claim 14, wherein the SiCh layer is greater than 20A and less than 10pm in thickness.

23. The method of claim 14, wherein the SiOx / SiN_y layer is greater than 20A and less than 10,000 A in thickness.

24. The method of claim 14, wherein in the SiO_x layer, x ranges from 0.5 to 3.

25. The method of claim 14, wherein in the SiNy layer, y ranges from 0.5 to 2.

26. The method of claim 14, wherein the SiN layer is greater than 20A and less than 10,000 A in thickness.

27. The method of claim 14, wherein the substrate comprises electrically and thermally conductive structures.

28. The method of claim 14, wherein the semiconductor devices comprise an RF Circuit that eliminates at least 10% of the RF parasitic signal associated with a transition from the substrate to the electrically and thermally conductive structures.

29. The method of claim 28, wherein the electrically and thermally conductive structures comprise through-hole vias, blind vias, interconnects or heat spreader elements.

30. The method of claim 29, wherein the through-hole vias, blind vias, interconnects, or heat spreader elements comprise copper or another metal.

31. The method of claim 14, wherein the device structure is laminated or layered to form an equivalent of a multilayer PCB structure.

32. The method of claim 14, wherein the semiconductor devices comprise: microprocessor/CPU, optical, electro-optical, MEMS device, antennas, RF Circulators, RF Isolators, RF Combiners, RF Couplers, RF Splitters, Transformers, A to Ds, High speed D to As, Optical Couplers, Optical Modulators, Laser Diode, VECSLS, Switches, Multiplexors, Duplexers, Diplexers, Memories and/or Diplexers, RF Filters, RF Circulators, RF Isolators, Antenna, Impedance Matching Elements, 50 Ohm Termination Elements, Integrated Ground Planes, RF Shielding Elements, EMI Shielding Elements, RF Combiners, RF Splitters, Transformers, Switches, power splitters, power combiners, Memory chips, or Microcontrollers.

33. A method for preventing contamination of semiconductor devices comprising: encapsulating a substrate to isolate one or more constituents on the substrate from contaminating semiconductor material and or semiconductor devices device structure, by: cleaning a surface of the substrate using plasma or other surface treatment process, wherein the substrate has a thickness that ranges from 25pm to 2500 pm; depositing an adhesion layer of SiCh, wherein the layer ranges between 20A to 40,000A and during the deposition of the adhesion layer reducing the oxygen gas and replacing it with nitrogen gas until the nitrogen gas is 100% of the gas to form a transition layer, wherein a region of and wherein the transition layer comprises SiOx / SiNy and is between 20A to 40,000A thick, and once the gas is 100% nitrogen gas transiting the SiOx / SiNy to SiN(z); forming a via mask pattern, etching the encapsulation layer, and exposing the metal connectors and heat spreaders; and attaching or forming one or more semiconductor, passive devices, or MEMS devices on the substrate, wherein the substrate is protected from contamination.