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WO2023037747A1 - Mounting structure - Google Patents

Mounting structure Download PDF

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Publication number
WO2023037747A1
WO2023037747A1 PCT/JP2022/026970 JP2022026970W WO2023037747A1 WO 2023037747 A1 WO2023037747 A1 WO 2023037747A1 JP 2022026970 W JP2022026970 W JP 2022026970W WO 2023037747 A1 WO2023037747 A1 WO 2023037747A1
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WO
WIPO (PCT)
Prior art keywords
layer
less
electronic component
mounting structure
metal
Prior art date
Application number
PCT/JP2022/026970
Other languages
French (fr)
Japanese (ja)
Inventor
明夫 廣瀬
智 小椋
朋己 木村
真之介 木村
千秋 山本
育史 吉田
数基 吉野
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to CN202280060409.5A priority Critical patent/CN117957921A/en
Publication of WO2023037747A1 publication Critical patent/WO2023037747A1/en

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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24Selection of soldering or welding materials proper
    • B23K35/26Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24Selection of soldering or welding materials proper
    • B23K35/30Selection of soldering or welding materials proper with the principal constituent melting at less than 1550 degrees C
    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22CALLOYS
    • C22C13/00Alloys based on tin
    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22CALLOYS
    • C22C9/00Alloys based on copper
    • C22C9/02Alloys based on copper with tin as the next major constituent
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering

Definitions

  • the present disclosure relates to an electronic component and a mounting structure including the electronic component.
  • an electronic component includes a component body and external electrodes provided on the surface thereof.
  • a joint formed by soldering is also referred to herein as a “solder joint”).
  • Patent Document 1 discloses a laminated ceramic capacitor having terminal electrodes (external electrodes) at the ends of a laminate (component body) formed from internal electrode layers and dielectric layers, wherein the terminal electrodes are Ag-based conductor films. (base film), a Ni-plated intermediate layer, and an external plated layer (Sn-plated layer).
  • base film base film
  • Ni-plated intermediate layer an external plated layer
  • an excellent terminal electrode can be formed at a temperature of 270° C. for 10 seconds, for example.
  • a mounting structure in which electronic components are mounted on a substrate is required to withstand use in even harsher temperature environments, such as when used in electronic fuel injection control circuits in automobile engine compartments. ing.
  • Ni contained in the Ni-plated intermediate layer can diffuse (thermally diffuse) into the solder joints at a relatively high speed in the configuration of Patent Document 1.
  • Ag from the Ag-based conductor film (base film) can also diffuse into the solder joint.
  • solder erosion in which Ag is lost from the Ag-based conductor film due to diffusion into the solder joint, can also occur during use of the mounting structure, resulting in damage between the main body of the electronic component and the Ag-based conductor film. The connection between them may become insufficient, and the connection reliability of the electronic components may deteriorate.
  • the present disclosure aims to provide an electronic component that can effectively suppress the diffusion of metal atoms from external electrodes to solder or solder joints even when exposed to a high-temperature environment after mounting the electronic component. aim.
  • a further object of the present disclosure is to provide a mounting structure on which such electronic components are mounted.
  • the present disclosure includes the following aspects.
  • a component body An electronic component comprising an external electrode provided on the surface of the component body, The external electrode includes a laminated structure of M 1 /Cu/antioxidation film, The M 1 is a Group 9-11 metal or an alloy containing a Group 9-11 metal, electronic components.
  • the antioxidant film is a layer of Sn, Ag, Au, or OSP.
  • An electronic component comprising a component body and an external electrode provided on the surface of the component body;
  • a mounting structure comprising a solder joint, The electronic component is joined to another electronic component by a solder joint,
  • the external electrode has an intermetallic compound layer represented by (Cu, M 2 ) x Sn y or Cu x Sn y at the interface with the solder joint, said M 2 is a metal of Groups 9 to 11;
  • the x is 5 or more and 7 or less,
  • the y is 4 or more and 6 or less, Structural implementation.
  • the external electrode includes a laminated structure of M 1 /(Cu, M 2 ) x Sn y or M 1 /Cu x Sn y ,
  • the M 1 is a metal of Groups 9 to 11 or an alloy containing metals of Groups 9 to 11, said M 2 is a metal of Groups 9 to 11;
  • the x is 5 or more and 7 or less,
  • the y is 4 or more and 6 or less,
  • the external electrode includes a laminated structure of M 1 /Cu/(Cu, M 2 ) x Sn y or M 1 /Cu/Cu x Sn y ,
  • the M 1 is a Group 9 to Group 11 metal or an alloy containing a Group 9 to Group 11 metal
  • said M 2 is a metal of Groups 9 to 11
  • the x is 5 or more and 7 or less
  • the y is 4 or more and 6 or less
  • [ 11 ] The above - mentioned [ 10].
  • [12] The mounting structure according to any one of [9] to [11] above, wherein M1 is Ni or an alloy containing Ni , and M2 is Ni.
  • an electronic component that can effectively suppress diffusion of metal atoms from external electrodes to solder joints even when exposed to a high-temperature environment after mounting the electronic component.
  • FIG. 1 is a schematic cross-sectional view of a multilayer ceramic capacitor 1a that is one embodiment of the present disclosure.
  • FIG. 2 is a schematic cross-sectional view of a mounting structure 21 that is one embodiment of the present disclosure.
  • the electronic component of the present disclosure is a component body; An electronic component comprising an external electrode provided on the surface of the component body,
  • the external electrode includes a laminated structure of M 1 /Cu/antioxidation film.
  • M 1 is a group 9-11 metal or an alloy containing a group 9-11 metal.
  • the electronic component of the present disclosure can be the multilayer ceramic capacitor 1a shown in FIG.
  • a multilayer ceramic capacitor 1a has a component body 2 and external electrodes 3a and 3b provided on the surface of the component body.
  • the component body 2 has internal electrodes 5 a and 5 b and a dielectric portion (dielectric layer) 6 .
  • the external electrodes 3a and 3b are respectively composed of base layers 11a and 11b, M1 layers 12a and 12b, Cu layers 13a and 13b, and antioxidant films 14a and 14b.
  • the electronic component of the present disclosure includes a laminate structure of M 1 /Cu/antioxidation film in the external electrode.
  • a laminated structure when the electronic component of the present disclosure is mounted on another electronic component by soldering, intermetallic intermetallics derived from the laminated structure of the M 1 /Cu/antioxidation film are formed at the interface between the external electrode and the solder joint.
  • a compound layer is formed.
  • Such an intermetallic compound layer can function as a barrier film against solder erosion, and can function as a barrier film for a long period of time, particularly during use at high temperatures, thereby increasing reliability.
  • the component body 2 is the body of the capacitor in this embodiment, it is not limited to this as long as external electrodes are provided on its surface.
  • the component body can include electronic component bodies that can be used as inductors, resistors, LC composite components, and the like.
  • the component main body is not particularly limited, and can be configured using a commonly used method.
  • the material of the main part is not particularly limited, and commonly used materials can be used. Examples of materials include ceramics, resins, metals, composites thereof, and more specifically, ceramics.
  • the multilayer ceramic capacitor 1a shown in FIG. 1 has two external electrodes
  • the electronic component of the present disclosure is not limited to this aspect, and three or more external electrodes can be provided.
  • the external electrodes 3a and 3b are respectively composed of underlying layers 11a and 11b, M1 layers 12a and 12b, Cu layers 13a and 13b, and antioxidant films 14a and 14b. That is, the external electrode includes a laminated structure of M 1 /Cu/antioxidation film on the base layer.
  • the underlayer is not particularly limited, it may be Cu, Ag, Ni, Pd, or an alloy layer thereof.
  • the underlayer may preferably be a layer of Cu or Ag, more preferably Cu.
  • the underlayer may be a single layer or two or more layers.
  • the underlayer may contain other materials such as glass.
  • the base layer is provided on the surface of the component body, preferably in contact with the component body.
  • the thickness of the underlayer is not particularly limited, and may be, for example, 1 ⁇ m or more and 500 ⁇ m or less, preferably 3 ⁇ m or more and 300 ⁇ m or less, more preferably 5 ⁇ m or more and 100 ⁇ m or less, for example 5 ⁇ m or more and 50 ⁇ m or less, or 10 ⁇ m or more and 30 ⁇ m or less. obtain.
  • the method of forming the underlayer is not particularly limited, and examples thereof include plating (eg, electrolytic plating or electroless plating), sputtering, applying a paste, and curing or baking.
  • the M1 layer is provided on the underlayer.
  • M 1 is a group 9-11 metal or an alloy containing a group 9-11 metal.
  • M 1 is Ni or an alloy containing Ni.
  • Said alloy is preferably selected from the group consisting of Ni and Zn, W, Re, Os, Mo, Nb, Ir, Ru, Rh, Cr, Pt, Ti, Lu, Pd, Fe, Cu and Co It is an alloy with one or more metals.
  • M 1 is Ni.
  • the thickness of the M1 layer is not particularly limited. It can be 3 ⁇ m or less or 1 ⁇ m or more and 5 ⁇ m or less.
  • the method of forming the M1 layer is not particularly limited, but examples thereof include plating (eg, electrolytic plating or electroless plating), sputtering, and the like.
  • the thickness of the Cu layer is preferably 0.1 ⁇ m or more and 10 ⁇ m or less, more preferably 0.2 ⁇ m or more and 8 ⁇ m or less, and still more preferably 0.3 ⁇ m or more and 5.0 ⁇ m or less.
  • the thickness of the Cu layer is preferably 0.1 ⁇ m or more and 10 ⁇ m or less, more preferably 0.2 ⁇ m or more and 8 ⁇ m or less, and still more preferably 0.3 ⁇ m or more and 5.0 ⁇ m or less.
  • the thickness of the Cu layer By setting the thickness of the Cu layer to 0.1 ⁇ m or more, it becomes easy to form a uniform layer of (Cu, M 2 ) x Sn y or Cu x Sn y , and the effect of suppressing solder erosion is large. Become. It is considered that this is because Cu in the solder is also supplied to the interface if the thickness of the Cu layer is 0.1 ⁇ m or more.
  • the method of forming the Cu layer is not particularly limited, but examples thereof include plating (eg, electrolytic plating or electroless plating), sputtering, and the like.
  • the antioxidant film is preferably a layer of Sn, Ag, Au, or OSP (Organic Solderability Preservative, that is, water-soluble preflux).
  • the anti-oxidation film is preferably a layer of Sn, Ag or Au, more preferably an Sn layer.
  • the thickness of the antioxidant film is not particularly limited, and may be, for example, 0.01 ⁇ m or more and 100 ⁇ m or less, preferably 0.1 ⁇ m or more and 50 ⁇ m or less, more preferably 0.3 ⁇ m or more and 10 ⁇ m or less, for example 0.3 ⁇ m or more. It can be 3 ⁇ m or less or 1 ⁇ m or more and 5 ⁇ m or less.
  • the method for forming the anti-oxidation film is not particularly limited, but examples thereof include plating (eg, electrolytic plating or electroless plating), sputtering, and the like.
  • the thickness of the laminated structure of M 1 /Cu/antioxidation film is preferably 1.0 ⁇ m or more and 300 ⁇ m or less, more preferably 5.0 ⁇ m or more and 100 ⁇ m or less.
  • the M1 layer, the Cu layer, and the anti-oxidation film may each contain other trace substances such as trace atoms that may be unavoidably mixed.
  • the M 1 /Cu/antioxidation film is preferably Ni/Cu/Sn.
  • the electronic component of the present disclosure described above can be mounted on another electronic component using solder, thereby obtaining a mounted structure.
  • the present disclosure also provides mounting structures that include the electronic components of the present disclosure and solder joints.
  • the implementation structure of the present disclosure is: an electronic component comprising a component body and external electrodes provided on the surface of the component body; A mounting structure comprising a solder joint, The electronic component is joined to another electronic component by a solder joint,
  • the external electrode has an intermetallic compound layer represented by (Cu, M 2 ) x Sn y or Cu x Sn y at the interface with the solder joint.
  • M 2 is a group 9 to group 11 metal
  • x is 5 or more and 7 or less
  • y is 4 or more and 6 or less.
  • the mounting structure of the present disclosure can be the mounting structure 21 shown in FIG.
  • the mounting structure 21 includes a laminated ceramic capacitor 1b and solder joints 22a and 22b.
  • the multilayer ceramic capacitor 1b of the mounting structure 21 is soldered to a substrate 23, which is another electronic component.
  • the laminated ceramic capacitor 1b is obtained by soldering the laminated ceramic capacitor 1a to a substrate 23, and is the same as the electronic component described above except that the external electrodes 3a and 3b are changed to external electrodes 3c and 3d. has a configuration of
  • the other electronic component is the substrate 23, but it is not limited to this, and is not particularly limited as long as it is an electronic component that can be soldered to the electronic component of the present disclosure.
  • solder joints 22a and 22b are for joining the substrate 23 and the multilayer ceramic capacitor 1, and specifically, the electrode portions 24a and 24b provided on the surface of the substrate 23 and the external electrodes of the multilayer ceramic capacitor 1b. 3c and 3d are joined.
  • the electrodes 24a and 24b provided on the surface of the substrate are not particularly limited, and commonly used ones can be used.
  • the electrode portion can be formed of, for example, a conductive material such as Ni, Cu, Ag, Sn, Au, Pd, and, in some cases, preflux or the like.
  • solder joints can be formed by a general method, for example, by using solder paste and reflowing.
  • solder is not particularly limited, and commonly used solder can be used.
  • Solders include, for example, Sn—Ag—Cu alloy (SAC), Sn—Zn—Bi alloy, Sn—Cu alloy, Sn—Ag—In—Bi alloy, Sn—Zn—Al alloy, Sn A -Sb alloy or the like can be used.
  • the solder is SAC.
  • the external electrodes 3c and 3d have an intermetallic compound layer represented by (Cu, M2 ) xSny or CuxSny at the interface with the solder joint.
  • the presence of such an intermetallic compound layer can suppress the diffusion of metal atoms from the external electrode to the solder joint, that is, the solder erosion.
  • the intermetallic compound layer exists over the entire interface between the external electrode and the solder joint.
  • the presence of the intermetallic compound layer over the entire interface between the external electrode and the solder joint can more reliably suppress the diffusion of metal atoms from the external electrode to the solder joint.
  • the external electrode in the mounting structure has a laminated structure of M1 /(Cu, M2 ) xSny or CuxSny , or M1 /Cu/(Cu, M2 ) xSny or CuxSny . including.
  • the above M 1 has the same meaning as above, and is a group 9-11 metal or an alloy containing a group 9-11 metal.
  • M2 is a group 9-11 metal.
  • M2 is Ni.
  • the above x is 5 or more and 7 or less, and the above y is 4 or more and 6 or less.
  • x is 5.5 or more and 6.5 or less
  • y is 4.5 or more and 5.5 or less.
  • x+y is preferably 10 or more and 12 or less, more preferably 10.5 or more and 11.5 or less.
  • x is 6 and y is 5.
  • the laminated structure of M 1 /(Cu, M 2 ) x Sn y or Cu x Sn y and M 1 /Cu/(Cu, M 2 ) x Sn y or Cu x Sn y is the laminated ceramic capacitor 1a described above.
  • Sn in the M 1 /Cu/antioxidant film and Sn in the solder are formed by forming an intermetallic compound when soldering to the substrate 23 .
  • the content of M 2 in (Cu, M 2 ) x Sn y is preferably 0.01 at % or more and 25 at % or less, more preferably 0.1 at % or more and 20 at % or less.
  • the thickness of the M1 layer may be preferably 0.1 ⁇ m to 10 ⁇ m, more preferably 0.5 ⁇ m to 8 ⁇ m.
  • the thickness of the Cu layer may preferably be 0.1 ⁇ m or more and 5 ⁇ m or less, more preferably 0.3 ⁇ m or more and 3 ⁇ m or less.
  • the thickness of the (Cu, M 2 ) x Sn y or Cu x Sn y layer may preferably be 0.01 ⁇ m or more and 20 ⁇ m or less.
  • the thickness of the (Cu, M 2 ) x Sn y layer or the Cu x Sn y layer may preferably be 0.01 ⁇ m or more and 20 ⁇ m or less.
  • Examples 1-3 (Production of electronic parts) A chip-shaped ceramic laminate was immersed in a paste in which Cu powder and glass were mixed, and then lifted out to adhere the paste. After that, it was fired at 800° C. to form a composite layer containing Cu and glass as a base layer on the surface of the ceramic laminate. Next, a Ni layer, a Cu layer, and an Sn layer were formed on the underlayer by a sputtering method to obtain samples of Examples 1-3. Table 1 shows the thickness of each layer.
  • Comparative example 1 A sample of Comparative Example 1 was obtained in the same manner as in Examples 1 to 3 above, except that the Cu layer was not formed between the Ni layer and the Sn layer.
  • Examples 4-6 (Fabrication of mounting structure) The samples of Examples 1 to 3 were reflow-mounted on a printed circuit board using SAC solder to obtain mounting structures of Examples 4 to 6. Reflow was performed at a preheating temperature of 150° C. for 60 seconds and then at a maximum temperature of 250° C. for 100 seconds.
  • Comparative example 2 The sample of Comparative Example 1 was reflow-mounted on a printed circuit board using SAC solder to obtain a mounted structure of Comparative Example 2.
  • Test example 1 Regarding the mounting structures of Examples 4 to 6 and Comparative Example 2, the cross section of the external electrode was examined with a scanning electron microscope (FE-SEM/EDX) (manufactured by Hitachi High-Technologies Corporation, FE-SEM: SU8230/EDX: 5060FQ). Observed.
  • FE-SEM/EDX scanning electron microscope
  • Test Example 2 heat resistance test
  • the mounting structures obtained in Examples 4 to 6 and Comparative Example 2 were allowed to stand in an environment at a temperature of 175° C., and observed for the occurrence of solder leaching.
  • the presence or absence of solder leaching was determined by observing the cross section of the external electrode with a scanning electron microscope (FE-SEM/EDX) (manufactured by Hitachi High-Technologies Corporation, FE-SEM: SU8230/EDX: 5060FQ).
  • FE-SEM/EDX scanning electron microscope
  • the reaction rate constant for solder erosion was calculated from the difference between the initial film thickness and the film thickness after standing at 175°C. The results are shown in the table below.
  • the electronic component of the present disclosure is suitably used in applications that require use at high temperatures.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Mechanical Engineering (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

The present invention provides an electronic component comprising a component body and an external electrode provided on a surface of the component body, characterized in that the external electrode comprises an Ni/Cu/Sn stacked structure.

Description

実装構造体implementation structure

 本開示は、電子部品、及び当該電子部品を含む実装構造体に関する。 The present disclosure relates to an electronic component and a mounting structure including the electronic component.

 一般的に、電子部品は、部品本体と、その表面に設けられた外部電極とを含み、電子部品を基板に実装する場合、外部電極が、基板に形成された電極部(例えばランド)にはんだ接合され得る(本明細書において、はんだ接合により形成される接合部を「はんだ接合部」とも言う)。例えば、特許文献1には、内部電極層および誘電体層から形成された積層体(部品本体)の端部に端子電極(外部電極)を有する積層セラミックコンデンサにおいて、端子電極が、Ag系導体膜(下地膜)、Niめっき中間層、および外部めっき層(Snめっき層)から形成されることが記載されている。特許文献1には、Niめっき中間層の厚さを所定厚さ以上とし、かつそのばらつきを低減することにより、はんだ接合時に起こり得るAg系導体膜のはんだ食われを有効に防止でき、耐熱性(例えば270℃で10秒)に優れた端子電極を形成できる旨が開示されている。 In general, an electronic component includes a component body and external electrodes provided on the surface thereof. (A joint formed by soldering is also referred to herein as a “solder joint”). For example, Patent Document 1 discloses a laminated ceramic capacitor having terminal electrodes (external electrodes) at the ends of a laminate (component body) formed from internal electrode layers and dielectric layers, wherein the terminal electrodes are Ag-based conductor films. (base film), a Ni-plated intermediate layer, and an external plated layer (Sn-plated layer). In Patent Document 1, by setting the thickness of the Ni-plated intermediate layer to a predetermined thickness or more and reducing the variation thereof, it is possible to effectively prevent the solder erosion of the Ag-based conductor film that may occur during soldering. It is disclosed that an excellent terminal electrode can be formed at a temperature of 270° C. for 10 seconds, for example.

特開平6-196351号公報JP-A-6-196351

 電子部品を基板に実装した実装構造体は、例えば自動車のエンジンルームの電子燃料噴射制御の回路部に使用される場合のように、より一層過酷な温度環境下での使用に耐えることが求められている。かかる過酷な高温環境下で実装構造体が使用されると、特許文献1のような構成では、Niめっき中間層に含まれるNiがはんだ接合部に比較的大きい速度で拡散(熱拡散)し得、これにより、Ag系導体膜(下地膜)からAgもはんだ接合部に拡散し得る。はんだ接合部への拡散によりAg系導体膜からAgが喪失する「はんだ食われ」は、実装構造体の使用の間にも起こり得、その結果、電子部品の部品本体とAg系導体膜との間の接続が不十分になり、電子部品の接続信頼性が低下し得る。 A mounting structure in which electronic components are mounted on a substrate is required to withstand use in even harsher temperature environments, such as when used in electronic fuel injection control circuits in automobile engine compartments. ing. When the mounting structure is used in such a severe high-temperature environment, Ni contained in the Ni-plated intermediate layer can diffuse (thermally diffuse) into the solder joints at a relatively high speed in the configuration of Patent Document 1. As a result, Ag from the Ag-based conductor film (base film) can also diffuse into the solder joint. "Solder erosion", in which Ag is lost from the Ag-based conductor film due to diffusion into the solder joint, can also occur during use of the mounting structure, resulting in damage between the main body of the electronic component and the Ag-based conductor film. The connection between them may become insufficient, and the connection reliability of the electronic components may deteriorate.

 本開示は、電子部品の実装後に高温環境下に曝した場合にも、外部電極からはんだまたははんだ接合部への金属原子の拡散を効果的に抑制することができる、電子部品を提供することを目的とする。更に、本開示は、かかる電子部品が実装された実装構造体を提供することを目的とする。 The present disclosure aims to provide an electronic component that can effectively suppress the diffusion of metal atoms from external electrodes to solder or solder joints even when exposed to a high-temperature environment after mounting the electronic component. aim. A further object of the present disclosure is to provide a mounting structure on which such electronic components are mounted.

 本開示は以下の態様を含む。
[1] 部品本体と、
 前記部品本体の表面に設けられた外部電極と
を備える電子部品であって、
 前記外部電極は、M/Cu/酸化防止膜の積層構造を含み、
 前記Mは、第9族~第11族の金属、又は第9族~第11族の金属を含む合金である、
電子部品。
[2] 前記Mは、Ni又はNiを含む合金である、上記[1]に記載の電子部品。
[3] 前記Mは、Niである、上記[1]又は[2]に記載の電子部品。
[4] 前記酸化防止膜は、Sn、Ag、Au、又はOSPの層である、上記[1]~[3]のいずれか1項に記載の電子部品。
[5] 前記酸化防止膜は、Sn層である、上記[1]~[4]のいずれか1項に記載の電子部品。
[6] 前記Cu層の厚さは、0.1μm以上10μm以下である、上記[1]~[5]のいずれか1項に記載の電子部品。
[7] 前記Cu層の厚さは、0.3μm以上5μm以下である、上記[1]~[6]のいずれか1項に記載の電子部品。
[8] 部品本体と該部品本体の表面に設けられた外部電極とを備える電子部品と、
 はんだ接合部と
を含む実装構造体であって、
 前記電子部品は、はんだ接合部により他の電子部品に接合されており、
 前記外部電極は、前記はんだ接合部との界面に、(Cu,MSn又はCuSnで表される金属間化合物層をし、
 前記Mは、第9族~第11族の金属であり、
 前記xは、5以上7以下であり、
 前記yは、4以上6以下である、
構造実装体。
[9] 前記外部電極は、M/(Cu,MSn又はM/CuSnの積層構造を含み、
 前記Mは、第9族~第11族の金属、又は第9族~第11族の金属を含む合金であり、
 前記Mは、第9族~第11族の金属であり、
 前記xは、5以上7以下であり、
 前記yは、4以上6以下である、
上記[8]に記載の実装構造体。
[10] 前記外部電極は、M/Cu/(Cu,MSn又はM/Cu/CuSnの積層構造を含み、
 前記Mは、第9族~第11族の金属、又は第9族~第11族の金属を含む合金であり、
 前記Mは、第9族~第11族の金属であり、
 前記xは、5以上7以下であり、
 前記yは、4以上6以下である、
上記[8]に記載の実装構造体。
[11] 前記M/Cu/(Cu,MSn又はM/Cu/CuSnの積層構造におけるCu層の厚さは、0.1μm以上5μm以下である、上記[10]に記載の実装構造体。
[12] 前記Mは、Ni又はNiを含む合金であり、前記Mは、Niである、上記[9]~[11]のいずれか1項に記載の実装構造体。
[13] 前記(Cu,MSn層又はCuSn層の、下層に対する被覆率は、50%以上100%以下である、上記[8]~[12]のいずれか1項に記載の実装構造体。
[14] 前記(Cu,MSn層又はCuSn層の厚みは、0.1μm以上である、上記[8]~[13]のいずれか1項に記載の実装構造体。
[15] x+yは、10以上12以下である、上記[8]~[14]のいずれか1項に記載の実装構造体。
[16] xは6であり、yは5である、上記[8]~[15]のいずれか1項に記載の実装構造体。
The present disclosure includes the following aspects.
[1] a component body;
An electronic component comprising an external electrode provided on the surface of the component body,
The external electrode includes a laminated structure of M 1 /Cu/antioxidation film,
The M 1 is a Group 9-11 metal or an alloy containing a Group 9-11 metal,
electronic components.
[2] The electronic component according to [1] above, wherein the M1 is Ni or an alloy containing Ni.
[3] The electronic component according to [1] or [2] above, wherein M1 is Ni.
[4] The electronic component according to any one of [1] to [3] above, wherein the antioxidant film is a layer of Sn, Ag, Au, or OSP.
[5] The electronic component according to any one of [1] to [4] above, wherein the antioxidant film is a Sn layer.
[6] The electronic component according to any one of [1] to [5] above, wherein the Cu layer has a thickness of 0.1 μm or more and 10 μm or less.
[7] The electronic component according to any one of [1] to [6] above, wherein the Cu layer has a thickness of 0.3 μm or more and 5 μm or less.
[8] An electronic component comprising a component body and an external electrode provided on the surface of the component body;
A mounting structure comprising a solder joint,
The electronic component is joined to another electronic component by a solder joint,
The external electrode has an intermetallic compound layer represented by (Cu, M 2 ) x Sn y or Cu x Sn y at the interface with the solder joint,
said M 2 is a metal of Groups 9 to 11;
The x is 5 or more and 7 or less,
The y is 4 or more and 6 or less,
Structural implementation.
[9] the external electrode includes a laminated structure of M 1 /(Cu, M 2 ) x Sn y or M 1 /Cu x Sn y ,
The M 1 is a metal of Groups 9 to 11 or an alloy containing metals of Groups 9 to 11,
said M 2 is a metal of Groups 9 to 11;
The x is 5 or more and 7 or less,
The y is 4 or more and 6 or less,
The mounting structure according to [8] above.
[10] The external electrode includes a laminated structure of M 1 /Cu/(Cu, M 2 ) x Sn y or M 1 /Cu/Cu x Sn y ,
The M 1 is a Group 9 to Group 11 metal or an alloy containing a Group 9 to Group 11 metal,
said M 2 is a metal of Groups 9 to 11;
The x is 5 or more and 7 or less,
The y is 4 or more and 6 or less,
The mounting structure according to [8] above.
[ 11 ] The above - mentioned [ 10].
[12] The mounting structure according to any one of [9] to [11] above, wherein M1 is Ni or an alloy containing Ni , and M2 is Ni.
[13] Any one of the above [8] to [12], wherein the coverage of the (Cu, M 2 ) x Sn y layer or the Cu x Sn y layer with respect to the lower layer is 50% or more and 100% or less. The implementation struct described in .
[14] The mounting structure according to any one of [8] to [13] above, wherein the (Cu, M 2 ) x Sn y layer or the Cu x Sn y layer has a thickness of 0.1 μm or more. .
[15] The mounting structure according to any one of [8] to [14] above, wherein x+y is 10 or more and 12 or less.
[16] The mounting structure according to any one of [8] to [15] above, wherein x is 6 and y is 5.

 本開示によれば、電子部品の実装後に高温環境下に曝した場合にも、外部電極からはんだ接合部への金属原子の拡散を効果的に抑制することができる電子部品を提供し得る。 According to the present disclosure, it is possible to provide an electronic component that can effectively suppress diffusion of metal atoms from external electrodes to solder joints even when exposed to a high-temperature environment after mounting the electronic component.

図1は、本開示の一の実施形態である積層セラミックコンデンサ1aの概略断面図である。FIG. 1 is a schematic cross-sectional view of a multilayer ceramic capacitor 1a that is one embodiment of the present disclosure. 図2は、本開示の一の実施形態である実装構造体21の概略断面図である。FIG. 2 is a schematic cross-sectional view of a mounting structure 21 that is one embodiment of the present disclosure.

 本開示の電子部品および実装構造体について、以下、図面を参照しながら詳細に説明する。但し、各実施形態の電子部品および実装構造体の形状および配置等は、図示する例に限定されない。 The electronic component and mounting structure of the present disclosure will be described in detail below with reference to the drawings. However, the shape, arrangement, etc. of the electronic component and the mounting structure of each embodiment are not limited to the illustrated example.

 本開示の電子部品は、
 部品本体と、
 上記部品本体の表面に設けられた外部電極と
を備える電子部品であって、
 上記外部電極は、M/Cu/酸化防止膜の積層構造を含む。ここに、前記Mは、第9族~第11族の金属、又は第9族~第11族の金属を含む合金である。
The electronic component of the present disclosure is
a component body;
An electronic component comprising an external electrode provided on the surface of the component body,
The external electrode includes a laminated structure of M 1 /Cu/antioxidation film. Here, M 1 is a group 9-11 metal or an alloy containing a group 9-11 metal.

 本実施形態において、本開示の電子部品は、図1に示す積層セラミックコンデンサ1aであり得る。積層セラミックコンデンサ1aは、部品本体2と、部品本体の表面に設けられた外部電極3a,3bを有する。部品本体2は、内部電極5a,5b、誘電体部分(誘電体層)6を有する。外部電極3a,3bは、それぞれ、下地層11a,11b、M層12a,12b、Cu層13a,13b、及び酸化防止膜14a,14bから成る。 In this embodiment, the electronic component of the present disclosure can be the multilayer ceramic capacitor 1a shown in FIG. A multilayer ceramic capacitor 1a has a component body 2 and external electrodes 3a and 3b provided on the surface of the component body. The component body 2 has internal electrodes 5 a and 5 b and a dielectric portion (dielectric layer) 6 . The external electrodes 3a and 3b are respectively composed of base layers 11a and 11b, M1 layers 12a and 12b, Cu layers 13a and 13b, and antioxidant films 14a and 14b.

 本開示の電子部品は、外部電極に、M/Cu/酸化防止膜の積層構造を含む。かかる積層構造により、本開示の電子部品を他の電子部品にはんだにより実装する際に、外部電極とはんだ接合部の界面に、上記M/Cu/酸化防止膜の積層構造に由来する金属間化合物層が形成される。かかる金属間化合物層は、はんだ食われに対するバリア膜として機能し得、特に高温での使用時においても長期間バリア膜として機能し得ることから、信頼性が高くなる。 The electronic component of the present disclosure includes a laminate structure of M 1 /Cu/antioxidation film in the external electrode. With such a laminated structure, when the electronic component of the present disclosure is mounted on another electronic component by soldering, intermetallic intermetallics derived from the laminated structure of the M 1 /Cu/antioxidation film are formed at the interface between the external electrode and the solder joint. A compound layer is formed. Such an intermetallic compound layer can function as a barrier film against solder erosion, and can function as a barrier film for a long period of time, particularly during use at high temperatures, thereby increasing reliability.

 上記部品本体2は、本実施形態ではコンデンサの本体であるが、その表面に外部電極が設けられるものであればこれに限定されない。例えば、部品本体は、インダクタ、抵抗、LC複合部品等として使用し得る電子部品の本体を挙げることができる。 Although the component body 2 is the body of the capacitor in this embodiment, it is not limited to this as long as external electrodes are provided on its surface. For example, the component body can include electronic component bodies that can be used as inductors, resistors, LC composite components, and the like.

 上記部品本体は、特に限定されず、通常行われる手法を用いて構成し得る。 The component main body is not particularly limited, and can be configured using a commonly used method.

 上記部品本体の材質は、特に限定されず、通常用いられる材質を用いることができる。材質としては、例えば、セラミック、樹脂、金属、それらの複合材等を挙げることができ、具体的には、セラミックを挙げることができる。 The material of the main part is not particularly limited, and commonly used materials can be used. Examples of materials include ceramics, resins, metals, composites thereof, and more specifically, ceramics.

 図1に示す積層セラミックコンデンサ1aは、外部電極を2つ有するが、本開示の電子部品はこの態様に限定されず、3つ以上の外部電極を設けることができる。 Although the multilayer ceramic capacitor 1a shown in FIG. 1 has two external electrodes, the electronic component of the present disclosure is not limited to this aspect, and three or more external electrodes can be provided.

 図1に示されるように、外部電極3a,3bは、それぞれ、下地層11a,11b、M層12a,12b、Cu層13a,13b、及び酸化防止膜14a,14bから成る。即ち、外部電極は、下地層上に、M/Cu/酸化防止膜の積層構造を含む。 As shown in FIG. 1, the external electrodes 3a and 3b are respectively composed of underlying layers 11a and 11b, M1 layers 12a and 12b, Cu layers 13a and 13b, and antioxidant films 14a and 14b. That is, the external electrode includes a laminated structure of M 1 /Cu/antioxidation film on the base layer.

 上記下地層は、特に限定されないが、Cu、Ag、Ni、またはPd、あるいはその合金層であり得る。下地層は、好ましくはCuまたはAg、より好ましくはCuの層であり得る。下地層は、単層であっても、2層以上であってもよい。 Although the underlayer is not particularly limited, it may be Cu, Ag, Ni, Pd, or an alloy layer thereof. The underlayer may preferably be a layer of Cu or Ag, more preferably Cu. The underlayer may be a single layer or two or more layers.

 上記下地層は、他の材料、例えば、ガラスなどを含んでいてもよい。 The underlayer may contain other materials such as glass.

 上記下地層は、部品本体の表面上に設けられ、好ましくは部品本体に接触して設けられる。 The base layer is provided on the surface of the component body, preferably in contact with the component body.

 上記下地層の厚さは、特に限定されず、例えば、1μm以上500μm以下であり得、好ましくは3μm以上300μm以下、より好ましくは5μm以上100μm以下、例えば5μm以上50μm以下または10μm以上30μm以下であり得る。 The thickness of the underlayer is not particularly limited, and may be, for example, 1 μm or more and 500 μm or less, preferably 3 μm or more and 300 μm or less, more preferably 5 μm or more and 100 μm or less, for example 5 μm or more and 50 μm or less, or 10 μm or more and 30 μm or less. obtain.

 上記下地層の形成方法は、特に限定されず、例えばめっき(例えば、電解めっきまたは無電解めっき)、スパッタ、ペーストを塗布し、硬化または焼き付けする方法等が挙げられる。 The method of forming the underlayer is not particularly limited, and examples thereof include plating (eg, electrolytic plating or electroless plating), sputtering, applying a paste, and curing or baking.

 上記M層は、上記下地層上に設けられる。 The M1 layer is provided on the underlayer.

 上記Mは、第9族~第11族の金属、又は第9族~第11族の金属を含む合金である。 M 1 is a group 9-11 metal or an alloy containing a group 9-11 metal.

 一の態様において、Mは、Ni又はNiを含む合金である。 In one aspect, M 1 is Ni or an alloy containing Ni.

 上記合金は、好ましくは、Niと、Zn、W、Re、Os、Mo、Nb、Ir、Ru、Rh、Cr、Pt、Ti、Lu、Pd、Fe、Cu及びCoからなる群から選択される1種又はそれ以上の金属との合金である。 Said alloy is preferably selected from the group consisting of Ni and Zn, W, Re, Os, Mo, Nb, Ir, Ru, Rh, Cr, Pt, Ti, Lu, Pd, Fe, Cu and Co It is an alloy with one or more metals.

 好ましい態様において、Mは、Niである。 In preferred embodiments, M 1 is Ni.

 上記M層の厚さは、特に限定されず、例えば、0.01μm以上100μm以下であり得、好ましくは0.1μm以上50μm以下、より好ましくは0.3μm以上10μm以下、例えば0.3μm以上3μm以下または1μm以上5μm以下であり得る。 The thickness of the M1 layer is not particularly limited. It can be 3 μm or less or 1 μm or more and 5 μm or less.

 上記M層の形成方法は、特に限定されないが、例えばめっき(例えば、電解めっきまたは無電解めっき)、スパッタ等が挙げられる。 The method of forming the M1 layer is not particularly limited, but examples thereof include plating (eg, electrolytic plating or electroless plating), sputtering, and the like.

 上記Cu層の厚さは、好ましくは0.1μm以上10μm以下、より好ましくは0.2μm以上8μm以下、さらに好ましくは0.3μm以上5.0μm以下であり得る。Cu層の厚さを0.3μm以上にすることにより、他の電子部品に実装した際に、より広範囲にわたって、好ましくは電外部極の表面全体にわたって、下記する(Cu,MSn又はCuSnの層が形成され、より確実にはんだ食われを抑制することができる。また、Cu層の厚さを10μm以下とすることにより、小型化が容易になる。Cu層の厚さを0.1μm以上とすることにより、(Cu,MSn又はCuSnの層を一様に形成することが容易になり、はんだ食われ抑制効果が大きくなる。これは、Cu層の厚みが0.1μm以上であれば、はんだ中のCuも界面に供給されるためと考えられる。 The thickness of the Cu layer is preferably 0.1 μm or more and 10 μm or less, more preferably 0.2 μm or more and 8 μm or less, and still more preferably 0.3 μm or more and 5.0 μm or less. By setting the thickness of the Cu layer to 0.3 μm or more, the following (Cu,M 2 ) x Sn y Alternatively, a layer of Cu x Sn y is formed, and solder erosion can be suppressed more reliably. Further, by setting the thickness of the Cu layer to 10 μm or less, miniaturization is facilitated. By setting the thickness of the Cu layer to 0.1 μm or more, it becomes easy to form a uniform layer of (Cu, M 2 ) x Sn y or Cu x Sn y , and the effect of suppressing solder erosion is large. Become. It is considered that this is because Cu in the solder is also supplied to the interface if the thickness of the Cu layer is 0.1 μm or more.

 上記Cu層の形成方法は、特に限定されないが、例えばめっき(例えば、電解めっきまたは無電解めっき)、スパッタ等が挙げられる。 The method of forming the Cu layer is not particularly limited, but examples thereof include plating (eg, electrolytic plating or electroless plating), sputtering, and the like.

 上記酸化防止膜は、好ましくは、Sn、Ag、Au、又はOSP(Organic Solderability Preservative、即ち水溶性プリフラックス)の層である。 The antioxidant film is preferably a layer of Sn, Ag, Au, or OSP (Organic Solderability Preservative, that is, water-soluble preflux).

 上記酸化防止膜は、好ましくはSn、Ag又はAuの層であり、より好ましくはSn層である。 The anti-oxidation film is preferably a layer of Sn, Ag or Au, more preferably an Sn layer.

 上記酸化防止膜の厚さは、特に限定されず、例えば、0.01μm以上100μm以下であり得、好ましくは0.1μm以上50μm以下、より好ましくは0.3μm以上10μm以下、例えば0.3μm以上3μm以下または1μm以上5μm以下であり得る。 The thickness of the antioxidant film is not particularly limited, and may be, for example, 0.01 μm or more and 100 μm or less, preferably 0.1 μm or more and 50 μm or less, more preferably 0.3 μm or more and 10 μm or less, for example 0.3 μm or more. It can be 3 μm or less or 1 μm or more and 5 μm or less.

 上記酸化防止膜の形成方法は、特に限定されないが、例えばめっき(例えば、電解めっきまたは無電解めっき)、スパッタ等が挙げられる。 The method for forming the anti-oxidation film is not particularly limited, but examples thereof include plating (eg, electrolytic plating or electroless plating), sputtering, and the like.

 上記M/Cu/酸化防止膜の積層構造の厚さは、好ましくは1.0μm以上300μm以下、より好ましくは5.0μm以上100μm以下であり得る。 The thickness of the laminated structure of M 1 /Cu/antioxidation film is preferably 1.0 μm or more and 300 μm or less, more preferably 5.0 μm or more and 100 μm or less.

 上記M層、Cu層、及び酸化防止膜は、それぞれ、他の微量物質、例えば、不可避的に混入し得る微量原子等を含んでいてもよい。 The M1 layer, the Cu layer, and the anti-oxidation film may each contain other trace substances such as trace atoms that may be unavoidably mixed.

 上記M/Cu/酸化防止膜は、好ましくはNi/Cu/Snである。 The M 1 /Cu/antioxidation film is preferably Ni/Cu/Sn.

 上記した本開示の電子部品は、はんだを用いて他の電子部品に実装することができ、これにより実装構造体が得られる。本開示は、本開示の電子部品とはんだ接合部を含む実装構造体も提供する。 The electronic component of the present disclosure described above can be mounted on another electronic component using solder, thereby obtaining a mounted structure. The present disclosure also provides mounting structures that include the electronic components of the present disclosure and solder joints.

 本開示の実装構造体は、
 部品本体と該部品本体の表面に設けられた外部電極とを備える電子部品と、
 はんだ接合部と
を含む実装構造体であって、
 上記電子部品は、はんだ接合部により他の電子部品に接合されており、
 上記外部電極は、上記はんだ接合部との界面に、(Cu,MSn又はCuSnで表される金属間化合物層を有する。ここに、上記Mは、第9族~第11族の金属であり、xは、5以上7以下であり、yは、4以上6以下である。
The implementation structure of the present disclosure is:
an electronic component comprising a component body and external electrodes provided on the surface of the component body;
A mounting structure comprising a solder joint,
The electronic component is joined to another electronic component by a solder joint,
The external electrode has an intermetallic compound layer represented by (Cu, M 2 ) x Sn y or Cu x Sn y at the interface with the solder joint. Here, M 2 is a group 9 to group 11 metal, x is 5 or more and 7 or less, and y is 4 or more and 6 or less.

 本実施形態において、本開示の実装構造体は、図2に示す実装構造体21であり得る。実装構造体21は、積層セラミックコンデンサ1b、及びはんだ接合部22a,22bを含む。実装構造体21の積層セラミックコンデンサ1bは、他の電子部品である基板23に、はんだ接合部により接合されている。積層セラミックコンデンサ1bは、上記した積層セラミックコンデンサ1aをはんだにより基板23に接合したものであり、外部電極3a,3bが外部電極3c,3dに変化していること以外は、上記の電子部品と同様の構成を有する。 In this embodiment, the mounting structure of the present disclosure can be the mounting structure 21 shown in FIG. The mounting structure 21 includes a laminated ceramic capacitor 1b and solder joints 22a and 22b. The multilayer ceramic capacitor 1b of the mounting structure 21 is soldered to a substrate 23, which is another electronic component. The laminated ceramic capacitor 1b is obtained by soldering the laminated ceramic capacitor 1a to a substrate 23, and is the same as the electronic component described above except that the external electrodes 3a and 3b are changed to external electrodes 3c and 3d. has a configuration of

 本実施形態において、他の電子部品は基板23であるが、これに限定されず、本開示の電子部品とはんだにより接続される電子部品であれば、特に限定されない。 In the present embodiment, the other electronic component is the substrate 23, but it is not limited to this, and is not particularly limited as long as it is an electronic component that can be soldered to the electronic component of the present disclosure.

 上記はんだ接合部22a,22bは、基板23と積層セラミックコンデンサ1を接合するものであり、具体的には、基板23の表面に設けられた電極部24a,24bと、積層セラミックコンデンサ1bの外部電極3c,3dとを接合する。 The solder joints 22a and 22b are for joining the substrate 23 and the multilayer ceramic capacitor 1, and specifically, the electrode portions 24a and 24b provided on the surface of the substrate 23 and the external electrodes of the multilayer ceramic capacitor 1b. 3c and 3d are joined.

 上記基板の表面に設けられる電極部24a,24bは、特に限定されず、通常用いられるものを使用できる。電極部は、例えば、Ni、Cu、Ag、Sn、Au、Pd等の導電性物質、および場合により、プリフラックス等によって形成され得る。 The electrodes 24a and 24b provided on the surface of the substrate are not particularly limited, and commonly used ones can be used. The electrode portion can be formed of, for example, a conductive material such as Ni, Cu, Ag, Sn, Au, Pd, and, in some cases, preflux or the like.

 上記はんだ接合部は、一般的な方法で形成し得るが、例えば、はんだペーストを用い、リフローすることにより形成され得る。 The solder joints can be formed by a general method, for example, by using solder paste and reflowing.

 本実施態様において、はんだは特に限定されず、通常用いられるものを使用できる。はんだとしては、例えば、Sn-Ag-Cu系合金(SAC)、Sn-Zn-Bi系合金、Sn-Cu系合金、Sn-Ag-In-Bi系合金、Sn-Zn-Al系合金、Sn-Sb系合金等を用いることができる。 In this embodiment, solder is not particularly limited, and commonly used solder can be used. Solders include, for example, Sn—Ag—Cu alloy (SAC), Sn—Zn—Bi alloy, Sn—Cu alloy, Sn—Ag—In—Bi alloy, Sn—Zn—Al alloy, Sn A -Sb alloy or the like can be used.

 好ましい態様において、はんだはSACである。 In a preferred embodiment, the solder is SAC.

 上記外部電極3c,3dは、はんだ接合部との界面に、(Cu,MSn又はCuSnで表される金属間化合物層を有する。かかる金属間化合物層が存在することにより、外部電極からはんだ接合部への金属原子の拡散、即ちはんだ食われを抑制することができる。 The external electrodes 3c and 3d have an intermetallic compound layer represented by (Cu, M2 ) xSny or CuxSny at the interface with the solder joint. The presence of such an intermetallic compound layer can suppress the diffusion of metal atoms from the external electrode to the solder joint, that is, the solder erosion.

 上記金属間化合物層は、外部電極とはんだ接合部との界面全体にわたって存在する。金属間化合物層が外部電極とはんだ接合部との界面全体にわたって存在することにより、より確実に外部電極からはんだ接合部への金属原子の拡散を抑制することができる。 The intermetallic compound layer exists over the entire interface between the external electrode and the solder joint. The presence of the intermetallic compound layer over the entire interface between the external electrode and the solder joint can more reliably suppress the diffusion of metal atoms from the external electrode to the solder joint.

 上記実装構造体における外部電極は、M/(Cu,MSnもしくはCuSn、またはM/Cu/(Cu,MSnもしくはCuSnの積層構造を含む。 The external electrode in the mounting structure has a laminated structure of M1 /(Cu, M2 ) xSny or CuxSny , or M1 /Cu/(Cu, M2 ) xSny or CuxSny . including.

 上記Mは、上記と同意義であり、第9族~第11族の金属、又は第9族~第11族の金属を含む合金である。 The above M 1 has the same meaning as above, and is a group 9-11 metal or an alloy containing a group 9-11 metal.

 上記Mは、第9族~第11族の金属である。 M2 is a group 9-11 metal.

 好ましい態様において、Mは、Niである。 In a preferred embodiment, M2 is Ni.

 上記xは、5以上7以下であり、上記yは、4以上6以下である。 The above x is 5 or more and 7 or less, and the above y is 4 or more and 6 or less.

 一の態様において、xは、5.5以上6.5以下であり、yは、4.5以上5.5以下である。 In one aspect, x is 5.5 or more and 6.5 or less, and y is 4.5 or more and 5.5 or less.

 x+yは、好ましくは10以上12以下、より好ましくは10.5以上11.5以下である。 x+y is preferably 10 or more and 12 or less, more preferably 10.5 or more and 11.5 or less.

 好ましい態様において、xは6であり、yは5である。 In a preferred embodiment, x is 6 and y is 5.

 上記M/(Cu,MSn又はCuSnおよびM/Cu/(Cu,MSn又はCuSnの積層構造は、上記した積層セラミックコンデンサ1aをはんだにより基板23に接合する際に、M/Cu/酸化防止膜中のSn、ならびにはんだ中のSnが金属間化合物を形成することにより形成される。 The laminated structure of M 1 /(Cu, M 2 ) x Sn y or Cu x Sn y and M 1 /Cu/(Cu, M 2 ) x Sn y or Cu x Sn y is the laminated ceramic capacitor 1a described above. Sn in the M 1 /Cu/antioxidant film and Sn in the solder are formed by forming an intermetallic compound when soldering to the substrate 23 .

 上記(Cu,MSn中のM含有量は、好ましくは0.01at%以上25at%以下、より好ましくは0.1at%以上20at%以下であり得る。 The content of M 2 in (Cu, M 2 ) x Sn y is preferably 0.01 at % or more and 25 at % or less, more preferably 0.1 at % or more and 20 at % or less.

 上記M層の厚さは、好ましくは0.1μm以上10μm以下、より好ましくは0.5μm以上8μm以下であり得る。 The thickness of the M1 layer may be preferably 0.1 μm to 10 μm, more preferably 0.5 μm to 8 μm.

 上記Cu層の厚さは、存在する場合、好ましくは0.1μm以上5μm以下、より好ましくは0.3μm以上3μm以下であり得る。 The thickness of the Cu layer, if present, may preferably be 0.1 μm or more and 5 μm or less, more preferably 0.3 μm or more and 3 μm or less.

 上記(Cu,MSn又はCuSn層の厚さは、好ましくは0.01μm以上20μm以下であり得る。(Cu,MSn又はCuSn層の厚さを0.01μm以上とすることにより、より確実に外部電極からはんだ接合部への金属原子の拡散を抑制することができる。(Cu,MSn又はCuSn層の厚さを20μm以下とすることにより、実装構造体をより小型化することができる。 The thickness of the (Cu, M 2 ) x Sn y or Cu x Sn y layer may preferably be 0.01 μm or more and 20 μm or less. By setting the thickness of the (Cu, M 2 ) x Sn y layer or the Cu x Sn y layer to 0.01 μm or more, the diffusion of metal atoms from the external electrode to the solder joint can be suppressed more reliably. By setting the thickness of the (Cu, M 2 ) x Sn y or Cu x Sn y layer to 20 μm or less, the mounting structure can be further miniaturized.

 以下、実施例を用いて本開示の電子部品および実装構造体を具体的に説明するが、本開示の電子部品および実装構造体はこれらの実施例に限定されるものではない。 The electronic component and mounting structure of the present disclosure will be specifically described below using examples, but the electronic component and mounting structure of the present disclosure are not limited to these examples.

 実施例1~3
(電子部品の作製)
 Cu粉とガラスとが混合されたペーストに、チップ状のセラミック積層体を浸漬した後、引き上げ、ペーストを付着させた。その後、800℃で焼成し、セラミック積層体の表面に、下地層としてCuとガラスとを含む複合層を形成した。次いで、上記下地層上に、スパッタ法によりNi層、Cu層、及びSn層を形成し、実施例1~3の試料を得た。各層の厚みを表1に示す。
Examples 1-3
(Production of electronic parts)
A chip-shaped ceramic laminate was immersed in a paste in which Cu powder and glass were mixed, and then lifted out to adhere the paste. After that, it was fired at 800° C. to form a composite layer containing Cu and glass as a base layer on the surface of the ceramic laminate. Next, a Ni layer, a Cu layer, and an Sn layer were formed on the underlayer by a sputtering method to obtain samples of Examples 1-3. Table 1 shows the thickness of each layer.

 比較例1
 Ni層とSn層の間のCu層を形成しないこと以外は、上記実施例1~3と同様にして、比較例1の試料を得た。
Comparative example 1
A sample of Comparative Example 1 was obtained in the same manner as in Examples 1 to 3 above, except that the Cu layer was not formed between the Ni layer and the Sn layer.

Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001

 実施例4~6
(実装構造体の作製)
 上記実施例1~3の試料を、プリント基板にSACはんだを用いてリフロー実装して、実施例4~6の実装構造体を得た。リフローは、予熱温度を150℃とし、60秒間キープした後、最高温度250℃で100秒間行った。
Examples 4-6
(Fabrication of mounting structure)
The samples of Examples 1 to 3 were reflow-mounted on a printed circuit board using SAC solder to obtain mounting structures of Examples 4 to 6. Reflow was performed at a preheating temperature of 150° C. for 60 seconds and then at a maximum temperature of 250° C. for 100 seconds.

 比較例2
 比較例1の試料を、プリント基板にSACはんだを用いてリフロー実装して、比較例2の実装構造体を得た。
Comparative example 2
The sample of Comparative Example 1 was reflow-mounted on a printed circuit board using SAC solder to obtain a mounted structure of Comparative Example 2.

 試験例1
 実施例4~6及び比較例2の実装構造体について、外部電極の断面を走査型電子顕微鏡(FE-SEM/EDX)(株式会社日立ハイテクノロジーズ製、FE-SEM:SU8230/EDX:5060FQ)により観察した。
Test example 1
Regarding the mounting structures of Examples 4 to 6 and Comparative Example 2, the cross section of the external electrode was examined with a scanning electron microscope (FE-SEM/EDX) (manufactured by Hitachi High-Technologies Corporation, FE-SEM: SU8230/EDX: 5060FQ). Observed.

 実施例4~6の実装構造体については、外部電極は、下地層上にNi/(Cu,Ni)Sn層が形成されていることが確認された。一方、比較例2の試料については、下地層上に、Ni/NiSn/(Cu,Ni)Sn層が形成されていることが確認された。 As for the mounting structures of Examples 4 to 6, it was confirmed that the external electrodes had a Ni/(Cu, Ni) 6 Sn 5 layer formed on the underlying layer. On the other hand, for the sample of Comparative Example 2, it was confirmed that a Ni/Ni 3 Sn 4 /(Cu,Ni) 6 Sn 5 layer was formed on the underlayer.

 試験例2(耐熱試験)
 上記実施例4~6および比較例2で得られた実装構造体を、温度175℃の環境下に静置し、はんだ食われの発生の有無について観察した。はんだ食われの発生の有無は、外部電極の断面を走査型電子顕微鏡(FE-SEM/EDX)(株式会社日立ハイテクノロジーズ製、FE-SEM:SU8230/EDX:5060FQ)により観察することにより判断した。また、初期膜厚と175℃で静置した後の膜厚の差から、はんだ食われについての反応速度定数を算出した。結果を、下記表に示す。
Test Example 2 (heat resistance test)
The mounting structures obtained in Examples 4 to 6 and Comparative Example 2 were allowed to stand in an environment at a temperature of 175° C., and observed for the occurrence of solder leaching. The presence or absence of solder leaching was determined by observing the cross section of the external electrode with a scanning electron microscope (FE-SEM/EDX) (manufactured by Hitachi High-Technologies Corporation, FE-SEM: SU8230/EDX: 5060FQ). . Also, the reaction rate constant for solder erosion was calculated from the difference between the initial film thickness and the film thickness after standing at 175°C. The results are shown in the table below.

Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002

 実施例4~6の実装構造体は、500時間経過後もはんだ食われは観察されなかった。一方、比較例2の実装構造体は、局所的にはんだ食われが発生していることが確認された。 No solder erosion was observed in the mounting structures of Examples 4 to 6 even after 500 hours had passed. On the other hand, it was confirmed that the mounting structure of Comparative Example 2 had localized solder erosion.

 本開示の電子部品は、高温での使用が求められる用途において好適に用いられる。 The electronic component of the present disclosure is suitably used in applications that require use at high temperatures.

  1a,1b…積層セラミックコンデンサ
  2…部品本体
  3a,3b…外部電極
  3c,3d…外部電極
  5a,5b…内部電極
  6…誘電体部分(誘電体層)
  11a,11b…下地層
  12a,12b…M
  13a,13b…Cu層
  14a,14b…酸化防止膜
  21…実装構造体
  22a,22b…はんだ接合部
  23…基板
  24a,24b…電極部
DESCRIPTION OF SYMBOLS 1a, 1b... Laminated ceramic capacitor 2... Component body 3a, 3b... External electrode 3c, 3d... External electrode 5a, 5b... Internal electrode 6... Dielectric part (dielectric layer)
DESCRIPTION OF SYMBOLS 11a, 11b... Base layer 12a, 12b... M 1 layer 13a, 13b... Cu layer 14a, 14b... Antioxidation film 21... Mounting structure 22a, 22b... Solder joint part 23... Substrate 24a, 24b... Electrode part

Claims (16)

 部品本体と、
 前記部品本体の表面に設けられた外部電極と
を備える電子部品であって、
 前記外部電極は、M/Cu/酸化防止膜の積層構造を含み、
 前記Mは、第9族~第11族の金属、又は第9族~第11族の金属を含む合金である、
電子部品。
a component body;
An electronic component comprising an external electrode provided on the surface of the component body,
The external electrode includes a laminated structure of M 1 /Cu/antioxidation film,
The M 1 is a Group 9-11 metal or an alloy containing a Group 9-11 metal,
electronic components.
 前記Mは、Ni又はNiを含む合金である、請求項1に記載の電子部品。 The electronic component according to claim 1 , wherein the M1 is Ni or an alloy containing Ni.  前記Mは、Niである、請求項1又は2に記載の電子部品。 The electronic component according to claim 1 or 2, wherein said M1 is Ni.  前記酸化防止膜は、Sn、Ag、Au、又はOSPの層である、請求項1~3のいずれか1項に記載の電子部品。 The electronic component according to any one of claims 1 to 3, wherein the antioxidant film is a layer of Sn, Ag, Au, or OSP.  前記酸化防止膜は、Sn層である、請求項1~4のいずれか1項に記載の電子部品。 The electronic component according to any one of claims 1 to 4, wherein the antioxidant film is a Sn layer.  前記Cu層の厚さは、0.1μm以上10μm以下である、請求項1~5のいずれか1項に記載の電子部品。 The electronic component according to any one of claims 1 to 5, wherein the Cu layer has a thickness of 0.1 µm or more and 10 µm or less.  前記Cu層の厚さは、0.3μm以上5μm以下である、請求項1~6のいずれか1項に記載の電子部品。 The electronic component according to any one of claims 1 to 6, wherein the Cu layer has a thickness of 0.3 µm or more and 5 µm or less.  部品本体と該部品本体の表面に設けられた外部電極とを備える電子部品と、
 はんだ接合部と
を含む実装構造体であって、
 前記電子部品は、はんだ接合部により他の電子部品に接合されており、
 前記外部電極は、前記はんだ接合部との界面に、(Cu,MSn又はCuSnで表される金属間化合物層をし、
 前記Mは、第9族~第11族の金属であり、
 前記xは、5以上7以下であり、
 前記yは、4以上6以下である、
構造実装体。
an electronic component comprising a component body and external electrodes provided on the surface of the component body;
A mounting structure comprising a solder joint,
The electronic component is joined to another electronic component by a solder joint,
The external electrode has an intermetallic compound layer represented by (Cu, M 2 ) x Sn y or Cu x Sn y at the interface with the solder joint,
said M 2 is a metal of Groups 9 to 11;
The x is 5 or more and 7 or less,
The y is 4 or more and 6 or less,
Structural implementation.
 前記外部電極は、M/(Cu,MSn又はM/CuSnの積層構造を含み、
 前記Mは、第9族~第11族の金属、又は第9族~第11族の金属を含む合金であり、
 前記Mは、第9族~第11族の金属であり、
 前記xは、5以上7以下であり、
 前記yは、4以上6以下である、
請求項8に記載の実装構造体。
the external electrode includes a laminated structure of M 1 /(Cu, M 2 ) x Sn y or M 1 /Cu x Sn y ,
The M 1 is a metal of Groups 9 to 11 or an alloy containing metals of Groups 9 to 11,
said M 2 is a metal of Groups 9 to 11;
The x is 5 or more and 7 or less,
The y is 4 or more and 6 or less,
The mounting structure according to claim 8.
 前記外部電極は、M/Cu/(Cu,MSn又はM/Cu/CuSnの積層構造を含み、
 前記Mは、第9族~第11族の金属、又は第9族~第11族の金属を含む合金であり、
 前記Mは、第9族~第11族の金属であり、
 前記xは、5以上7以下であり、
 前記yは、4以上6以下である、
請求項8に記載の実装構造体。
the external electrode includes a laminated structure of M 1 /Cu/(Cu, M 2 ) x Sn y or M 1 /Cu/Cu x Sn y ,
The M 1 is a metal of Groups 9 to 11 or an alloy containing metals of Groups 9 to 11,
said M 2 is a metal of Groups 9 to 11;
The x is 5 or more and 7 or less,
The y is 4 or more and 6 or less,
The mounting structure according to claim 8.
 前記M/Cu/(Cu,MSn又はM/Cu/CuSnの積層構造におけるCu層の厚さは、0.1μm以上5μm以下である、請求項10に記載の実装構造体。 11. The thickness of the Cu layer in the stacked structure of M1 /Cu/(Cu, M2 ) xSny or M1 /Cu/ CuxSny is 0.1 [mu]m or more and 5 [mu]m or less, according to claim 10. The implementation struct of .  前記Mは、Ni又はNiを含む合金であり、前記Mは、Niである、請求項8~11のいずれか1項に記載の実装構造体。 The mounting structure according to any one of claims 8 to 11, wherein said M 1 is Ni or an alloy containing Ni, and said M 2 is Ni.  前記(Cu,MSn層又はCuSn層の、下層に対する被覆率は、50%以上100%以下である、請求項8~12のいずれか1項に記載の実装構造体。 The mounting structure according to any one of claims 8 to 12, wherein the (Cu, M 2 ) x Sn y layer or the Cu x Sn y layer has a coverage rate of 50% or more and 100% or less with respect to the lower layer. .  前記(Cu,MSn層又はCuSn層の厚みは、0.1μm以上である、請求項8~13のいずれか1項に記載の実装構造体。 The mounting structure according to any one of claims 8 to 13, wherein the (Cu, M 2 ) x Sn y layer or the Cu x Sn y layer has a thickness of 0.1 µm or more.  x+yは、10以上12以下である、請求項8~14のいずれか1項に記載の実装構造体。 The mounting structure according to any one of claims 8 to 14, wherein x+y is 10 or more and 12 or less.  xは6であり、yは5である、請求項8~15のいずれか1項に記載の実装構造体。 The mounting structure according to any one of claims 8 to 15, wherein x is 6 and y is 5.
PCT/JP2022/026970 2021-09-08 2022-07-07 Mounting structure WO2023037747A1 (en)

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JP2021027196A (en) * 2019-08-06 2021-02-22 国立大学法人大阪大学 Electronic component and mounting structure
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* Cited by examiner, † Cited by third party
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