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WO2022110567A1 - Procédé d'élimination de conflit d'accès à la mémoire à réutilisation de données pour structure reconfigurable grossière - Google Patents

Procédé d'élimination de conflit d'accès à la mémoire à réutilisation de données pour structure reconfigurable grossière Download PDF

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Publication number
WO2022110567A1
WO2022110567A1 PCT/CN2021/079524 CN2021079524W WO2022110567A1 WO 2022110567 A1 WO2022110567 A1 WO 2022110567A1 CN 2021079524 W CN2021079524 W CN 2021079524W WO 2022110567 A1 WO2022110567 A1 WO 2022110567A1
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reuse
load
data
pair
producer
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PCT/CN2021/079524
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Chinese (zh)
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绳伟光
陈雨歌
蒋剑飞
景乃锋
王琴
毛志刚
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上海交通大学
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • the present application relates to the field of coarse-grained reconfigurable structure compilers, and in particular, to a cyclic transformation model for maximizing effective data reuse for reconfigurable structures and a configuration file modification strategy for the code generation stage.
  • Coarse-Grained Reconfigurable Architecture is a new hardware architecture with higher energy efficiency. It is mainly used for hardware acceleration of computationally intensive applications, such as video processing, neural network operations. After research and investigation, it is found that the application execution time is mainly consumed in the kernel part of the program loop.
  • the reference ADRES[1] model gives a typical CGRA structure, as shown in Figure 1.
  • the compiler abstracts the program loop kernel part as a data flow graph (DFG) and maps it to different processing elements (PE) in the coarse-grained processing element array (PEA), And it is executed through soft water technology.
  • the machine cycle required between two loop iterations is called the initiation interval (II), and the smaller the II, the better the acceleration performance.
  • One of the main goals of a compiler for coarse-grained reconfigurable architectures is to efficiently choose scheduling and mapping strategies to minimize the II of the loop kernel.
  • ORF on-chip register file
  • the ORF is connected to each column of PEA through the crossbar and the column bus, and different PEs can access each storage bank of the on-chip memory through the column bus where they are located.
  • multiple operations occupy the same hardware resources at the same time in the same cycle (such as accessing the same bank of multi-bank on-chip memory at the same time, or accessing on-chip memory through the column bus exceeds the bandwidth limit of the column bus), it will cause the soft pipeline to stall, resulting in II Increase.
  • the cyclic transformation based on the polyhedral model is a new cyclic optimization method. Compared with the traditional unimodular matrix model, which uses affine transformation as the cyclic transformation, it has a wide range of applications, strong expressive ability, and large optimization space. advantage.
  • Today's compilers in various fields such as Google MLIR[2], Polly[3], TVM[4] all use the polyhedron model. But less work has been done to apply the polyhedral compilation model to the compilation process for coarse-grained reconfigurable architectures.
  • the PolyMap proposed in reference [5] utilizes the polyhedron compilation model, adjusts the hierarchical structure of the loop kernel through the analysis of the entire mapping flow, and realizes the parallelization of the loop unrolling in the inner layer of the loop kernel.
  • Reference [6] will use the polyhedron model to represent the program and the program transformation process, and use the genetic algorithm to perform cyclic transformation to achieve higher computational efficiency.
  • none of the above studies considered the application of the polyhedron model to increase data reuse between loop iterations to reduce the number of redundant memory access operations.
  • Reference [7] divides the data into multiple clusters, so that the probability of different clusters being accessed is as equal as possible. This approach resolves conflicts at the high level of the array, and the coarse-grained approach results in limited optimization effects.
  • Reference [8] analyzes all memory access addresses to a single array by the loop kernel in a single control cycle, and uses linear transformation to map different addresses to different storage locations in different on-chip memories.
  • Reference [9] further subdivides the structure of the storage bank on the basis of reference [8], adds data partitions on the block, and increases the flexibility of linear transformation.
  • Reference [10] upgrades the selection of linear transformation parameters from the analysis of single array access in a single control cycle to different array accesses in different control cycles, further reducing multi-bank conflicts.
  • a memory bank merging algorithm is proposed to improve the area-performance ratio of the memory bank.
  • Reference [11], on the basis of Reference [10] changes the execution time of each access operator in the scheduling process to further reduce access conflicts.
  • a dual-forced scheduling scheme is proposed, and then the memory access operations are divided into different control cycles as much as possible.
  • none of the above studies consider the method of reducing the number of memory access operations to reduce memory access conflicts.
  • the purpose of this application is to develop a new method based on the CGRA architecture, in the compilation stage, the software loop code is compiled and optimized to maximize the data available between iterations during the program running process. Reuse, and a method for eliminating redundant fetches in data-reuse pairs, thereby reducing fetch conflicts during loop execution.
  • Step 1 Use the CGRA compiler front-end to compile the loop kernel part of the source program into the first intermediate representation
  • Step 2 performing a cyclic transformation of effective data reuse between iterations to obtain a transformed second intermediate representation
  • Step 3 Generate a data flow graph to obtain a mapping result
  • Step 4 Select a modification strategy for data reuse
  • Step 5 Generate a configuration file
  • the step 2 further includes:
  • Step 2.1 analyze the dependency relationship and data reuse relationship in the original code, and obtain the dependency set and the reuse set; wherein, the reuse relationship means that two operations in different iterations access the same location in the memory, then the two operations are reused relationship; the two operations in the reuse relationship form a producer/consumer pair that includes a producer and a consumer, and the type of the producer/consumer pair includes a Load-Load reuse pair , Load-Store reuse pair, Store-Load reuse pair and Store-Store reuse pair;
  • Step 2.2 Constrain the search space of the innermost time vector according to the dependency set; search the remaining search spaces that meet the constraints in turn, and find the innermost time vector with the largest number of effective reuses in the reuse set; according to the obtained optimal innermost time vector layer time vector, recursively get the outer layer time vector;
  • Step 2.3 generating the second intermediate representation according to the time vector of each layer
  • Described step 4 further comprises:
  • Step 4.1 Analyze the data reuse relationship in the loop kernel to obtain different data reuse sets available; check whether each reuse relationship satisfies the hardware constraints in turn, and record the final available data reuse relationship in the producer and consumer nodes of the reuse relationship information;
  • Step 4.2 When the configuration file is generated, select the corresponding modification strategy according to the reuse relationship to which the node belongs.
  • a local register LRF (Local register file) is used to buffer the output of the producer, and the consumer loads data from the LRF.
  • a global register GRF global register file
  • step 2 a method based on affine transformation is used to arrange the execution sequence of the loop iteration.
  • a first strategy is used to select cyclic transformations, wherein the first strategy refers to a strategy for narrowing the selection range of optional cyclic transformations based on dependencies, which includes the following steps:
  • cone(M R ) represents a vertebral body formed by MR elements
  • cone( MR -ir ) represents a vertebral body formed by elements other than i r
  • formula (1) represents the currently selected time vector The line where it is located cannot be in the vertebral body composed of dependency vectors
  • formula (2) means that the currently selected time vector can be collinear with a vector on the vertebral body surface composed of all dependency vectors, and the dependency vector must be greater than or equal to the time vector, i.e. where c is a real number and the value range of c is 0 ⁇ c ⁇ 1.
  • step 2.2 the innermost time vector is iteratively selected using the first strategy from the innermost loop; after selecting an innermost time vector, all the dependency vectors are projected onto the normal plane of the time vector, and iteratively choose the next dependency vector; finally get a cyclic transformation that satisfies the cyclic dependency.
  • step 2.2 includes a second strategy, and the second strategy refers to a strategy for selecting cyclic transformations to maximize effective data reuse, which includes the following steps:
  • a memory fetch operation p is represented as Indicates that the memory fetch operation p accessed on-chip memory in iteration i address; given a reuse pair It is valid when the corresponding following formula (3) holds; where c is a constant threshold to help select valid reuse pairs:
  • Each reuse pair has a corresponding formula (3), so that as many reuse pairs as possible are valid, that is, the innermost time vector that makes formula (3) true as much as possible is the optimal time vector; the optimal transformation search algorithm first searches The optimal time vector of the innermost layer, and then the time vector of the outer layer is recursively calculated according to the time vector of the inner layer using formula (2).
  • modifying the strategy includes:
  • the Store-Store reuse pair is not limited by the interval iteration between producer and consumer, the producer in this reuse relationship pair is eliminated.
  • the modification strategy includes:
  • data is transferred from producers to consumers using interconnected resources.
  • the modification strategy includes:
  • the modification strategy includes:
  • the clock cycle I(r) between the producer and the consumer satisfies 1 ⁇ I(r)>0, and there is an interconnection resource connection between the PE where the producer is located and the PE where the consumer is located, then the reused Consumers are translated into routing operations that access data from the producer's output registers.
  • the modification strategy includes:
  • the clock cycle I(r)>1 between the producer and the consumer uses register resources to temporarily store data.
  • the modification strategy includes:
  • the reused data is stored in the LRF, and the consumer is transformed into a routing operation that obtains data from the LRF, where II is the start interval of the software pipeline;
  • pe(s) and pe(t) represent the PE where the producer and consumer are located, respectively.
  • modification strategy includes:
  • GRF is then used to temporarily store data.
  • modification strategy includes:
  • the output operation sends data to the input operation according to the modification policy of the Store-Load reuse pair, and memory access operations during accumulation are converted to no-ops.
  • the modification strategy includes:
  • modification strategy includes:
  • GRF is then used to temporarily store data.
  • modification strategy includes:
  • the output operation sends data to the input operation according to the modification policy of the Store-Load reuse pair, and memory access operations during accumulation are converted to no-ops.
  • the present application innovatively uses the data reuse relationship between loops to modify the configuration file in the configuration file generation stage to reduce the number of memory access operations of the CGRA operation loop kernel, thereby avoiding Fetch conflict.
  • This method is orthogonal to the existing methods for scheduling and mapping phase and data rearrangement and storage, and has strong scalability. It can simply work with the existing data placement scheme, scheduling and mapping scheme to achieve better results. High application speedup.
  • Fig. 1 is a typical architecture diagram of a 4x4 CGRA in the prior art
  • FIG. 2 is a schematic diagram of a compiler backend flow diagram of an embodiment of the present application
  • Fig. 3 is the cyclic transformation model process of the embodiment of the present application.
  • FIG. 4 is a schematic diagram of a configuration file modification strategy according to an embodiment of the present application.
  • Figure 5 is the running time of an embodiment of the present application under 22 kernels on a 4x4 PEA.
  • FIG. 2 a schematic diagram of a compiler back-end flow according to an embodiment of the present application, wherein,
  • Step 201 adopts the CGRA compiler front-end based on LLVM (Low Level Virtual Machine) to compile the loop kernel part of the source program into the form of intermediate representation (IR);
  • LLVM Low Level Virtual Machine
  • Steps 202-204 for the IR generated by the front-end, using the cyclic transformation model that maximizes effective data reuse between iterations proposed by the present application, obtain a new affine-transformed cyclic kernel IR;
  • Step 202 analyze the dependency relationship and data reuse relationship in the original code to obtain a dependency set and a reuse set;
  • Step 203 Constrain the search space of the innermost time vector according to the dependency set; search the remaining search spaces that meet the constraints in turn, and find the innermost time vector with the largest number of effective reuses in the reuse set; The inner time vector, recursively get the outer time vector;
  • Step 204 generating a new intermediate representation according to each layer time vector
  • a data flow graph is generated through the modified intermediate representation, and a mapping result is obtained by using the existing scheduling, data differentiation, and spatial mapping schemes in the prior art; wherein, the existing scheduling, data Discrimination and spatial mapping schemes can be obtained from documents [12] and [13], that is, documents [12] and [13] are incorporated into this application by reference, and documents [12] and [13] are listed in the detailed description end of section
  • Steps 211-212 selecting a modification strategy by adopting the configuration file modification scheme considering data reuse proposed in this application;
  • Step 211 analyze all data reuse relationships in the loop kernel, and obtain different data reuse sets available; check whether each reuse relationship satisfies hardware constraints in turn, and record the finally available data reuse relationship in the producer and consumer of the reuse relationship.
  • User node information
  • Step 212 when the configuration file is generated, select a corresponding modification strategy according to the reuse relationship to which the node belongs;
  • Step 213 generating a configuration file according to the previous modification policy.
  • the method of reducing the number of redundant memory access operations is adopted to reduce the number of memory access conflicts during the execution of the loop kernel, which is the difference between the present application and other studies.
  • the present application can be orthogonally combined with the existing scheduling, data placement, and mapping strategies to further improve the The performance of existing optimization work.
  • the use of the optimization method for reducing memory access conflicts for the front-end loop transformation and configuration file generation stages enables the present application to be combined with most existing methods for reducing memory access conflicts, which is another difference between the present application and other researches.
  • Reuse pairs can be divided into four categories, namely Load-Load (two load operations), Load-Store (load first, then write), Store-Load (write first, then load), and Store-Store (two write operations) reuse.
  • LRF local register file
  • GRF global register file
  • our compiler should guarantee that the reused data can be successfully preserved for the lifetime of the LRF or GRF. Therefore, the goal of our loop transformation model is to use an affine transformation-based approach to orchestrate the execution order of loop iterations to minimize the lifetime of reusing data between iterations.
  • step 203 shown in FIG. 2 the present application proposes a strategy for narrowing the selection range of optional cyclic transformations according to dependencies.
  • cone( MR ) represents a vertebral body formed by elements of MR
  • cone( MR - ir ) represents a vertebral body formed by elements other than ir .
  • Formula (1) indicates that the line where the currently selected time vector is located cannot be in the vertebral body composed of the dependency vectors; formula (2) indicates that the currently selected time vector can be collinear with a vector on the surface of the vertebral body composed of all dependent vectors, And the dependency vector must be greater than or equal to the time vector, that is where c is a real number and the value range of c is 0 ⁇ c ⁇ 1.
  • the present application iteratively uses this strategy to select the legal innermost time vector from the innermost loop. After selecting an innermost time vector, all dependency vectors can be projected onto the time vector normal plane, and the next dependency vector can be selected iteratively. Finally, a cyclic transformation that satisfies the cyclic dependency can be obtained.
  • step 203 shown in FIG. 2 the present application proposes a strategy for selecting cyclic transformations to maximize effective data reuse. Whether a Load-Load or Store-Load reuse pair is valid depends on the innermost time vector when searching for optimal transitions.
  • a fetch operation p can be represented as Indicates that the memory fetch operation p accessed on-chip memory in iteration i address. given reuse pair It is valid when the corresponding following formula (3) holds.
  • c is a constant threshold used to help select valid reuse pairs.
  • Each reused pair has a corresponding formula (3), so that as many reused pairs as possible are valid, that is, the innermost time vector for which formula (3) is established as much as possible is the optimal time vector.
  • the optimal transform search algorithm first searches for the optimal time vector of the innermost layer, and then uses formula (2) to recursively calculate the time vector of the outer layer according to the time vector of the inner layer.
  • FIG. 3 in order to further illustrate the above-mentioned cyclic transformation method, the program shown in FIG. 3( a ) is taken as an example.
  • the goal of the optimization problem is to maximize the number of equations established in Figure 3(e).
  • the nodes in Fig. 3(g) represent the innermost candidate time vectors, where the feasible solutions to the optimization problem are nodes, highlighted as gray nodes.
  • Figure 3(f) shows the time vector for each recurrent layer.
  • Figure 3(h) shows the transformed program, while the innermost loop is split into two layers in order to traverse all iterations.
  • FIG. 4(a) is a representation of the PE structure, where Op represents an operation placed on the PE, including P represents a producer in a reused pair, C represents a consumer, and R represents a routing node.
  • the LRF owned by each PE is also marked, and the LRF mark drawn with a diagonal pattern indicates that the LRF stores data.
  • Store-Store reuse is not limited by interval iterations between producers and consumers. If such a reuse relationship exists, the producer in the reuse relationship pair needs to be eliminated.
  • Figure 4(b) shows the modification strategy for Store-Store reuse.
  • interconnect resources or registered resources should be used to move data from producers to consumers.
  • r ⁇ s,t,d>, where s is the producer in the reused pair, t is the consumer in the reused pair, and d is the interval iteration number between s and t.
  • I(r) d ⁇ II+(time(t)-time(s)), where II is the start interval of software pipeline.
  • register resources When I(r)>1, register resources must be used to temporarily store data.
  • the selected strategy will be recorded, and in the configuration file generation stage of step 213, the generated configuration file will be modified through the selected strategy.
  • the test integrates the cyclic transformation model and configuration file modification strategy proposed in this application in 22 typical calculation-intensive application test sets
  • 22 Compute-intensive cores are selected from datasets derived from digital signal processing, computer vision, and dynamic programming, such as existing benchmarks such as EEMBC, Polybench, and Machsuite.
  • Figure 5 shows the integrated modulo scheduling compiler of the present application and the original compiler (that is, not using the present application, but using the compilation flow based on the following references [12] and [13], denoted as THP+DP) generation
  • THP+DP compilation flow based on the following references [12] and [13], denoted as THP+DP
  • Table 1 shows the comparison of the number of memory access operations before and after the implementation of the solution described in this application:

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Abstract

Procédé d'élimination de conflit d'accès à la mémoire à réutilisation de données pour une structure reconfigurable grossière. L'invention concerne un modèle de transformation de boucle qui est appliqué à un noyau de boucle imbriquée parfaite et est utilisé pour maximiser la réutilisation de données efficace de façon à maximiser la réutilisation de données disponible entre des itérations dans un processus d'exécution de programme et une stratégie de changement de fichier de configuration dans un étage de génération de code. Une opération d'accès à la mémoire redondante dans une paire de réutilisation de données est éliminée, et les conflits d'accès à la mémoire dans le processus d'exécution de boucle sont réduits.
PCT/CN2021/079524 2020-11-30 2021-03-08 Procédé d'élimination de conflit d'accès à la mémoire à réutilisation de données pour structure reconfigurable grossière WO2022110567A1 (fr)

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