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WO2021082066A1 - 一种显示面板及其制作方法 - Google Patents

一种显示面板及其制作方法 Download PDF

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Publication number
WO2021082066A1
WO2021082066A1 PCT/CN2019/116965 CN2019116965W WO2021082066A1 WO 2021082066 A1 WO2021082066 A1 WO 2021082066A1 CN 2019116965 W CN2019116965 W CN 2019116965W WO 2021082066 A1 WO2021082066 A1 WO 2021082066A1
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WIPO (PCT)
Prior art keywords
main
light
layer
sub
grid
Prior art date
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Ceased
Application number
PCT/CN2019/116965
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English (en)
French (fr)
Inventor
刘念
卢马才
温雷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/624,932 priority Critical patent/US11360591B2/en
Publication of WO2021082066A1 publication Critical patent/WO2021082066A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/431—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
    • H10F30/20—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
    • H10F30/21—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation
    • H10F30/28—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices being characterised by field-effect operation, e.g. junction field-effect phototransistors
    • H10F30/282—Insulated-gate field-effect transistors [IGFET], e.g. MISFET [metal-insulator-semiconductor field-effect transistor] phototransistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/107—Integrated devices having multiple elements covered by H10F30/00 in a repetitive configuration, e.g. radiation detectors comprising photodiode arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices

Definitions

  • the present invention relates to the field of display technology, in particular to a display panel and a manufacturing method thereof. .
  • the current touch technology includes on-cell and in-cell two.
  • On-cel1 installs the sensors corresponding to touch and fingerprint recognition independently of the display panel, so fixed-point sensing on the display panel cannot be achieved.
  • the in-cell is a touch technology that embeds the touch function into the liquid crystal pixel.
  • the current method mainly uses the top illumination (top) method, it is easily affected by the channel area and back channel defects, resulting in photocurrent Lower, thus reducing the sensitivity and accuracy of the touch function.
  • the purpose of the present invention is to provide a display panel and a manufacturing method thereof, which can increase the photocurrent, thereby improving the sensitivity and accuracy of the touch function.
  • the present invention provides a manufacturing method of a display panel, including:
  • a first metal layer is fabricated on the main light-transmitting portion, the secondary light-transmitting portion, and the glass substrate, and the first metal layer is patterned to obtain a first grid portion and a second grid portion ,
  • the main grid includes a first grid portion and a main light-transmitting portion
  • the sub-grid includes a second grid portion and a secondary light-transmitting portion, wherein a position corresponding to the secondary light-transmitting portion forms a light-transmitting portion area;
  • fabricating a semiconductor layer on the gate insulating layer performing a patterning process on the semiconductor layer to obtain a main active layer and a secondary active layer, and the position of the secondary active layer corresponds to the position of the light-transmitting region;
  • the sub-gate, sub-active layer, and sub-source and drain constitute sub-thin film transistors
  • the present invention provides a manufacturing method of a display panel, including:
  • fabricating a semiconductor layer on the gate insulating layer performing a patterning process on the semiconductor layer to obtain a main active layer and a secondary active layer, and the position of the secondary active layer corresponds to the position of the light-transmitting region;
  • a second metal layer is formed on the main active layer, the secondary active layer, and the gate insulating layer, and the second metal layer is patterned to obtain a primary source drain and a secondary source drain.
  • the present invention also provides a display panel, which includes:
  • the main grid and the sub-grid spaced apart are both provided on the glass substrate; at least a part of the sub-grid has a light-transmitting area;
  • a gate insulating layer is provided on the main gate, the secondary gate and the glass substrate;
  • the primary active layer and the secondary active layer are both provided on the gate insulating layer; the position of the secondary active layer corresponds to the position of the light-transmitting region;
  • Main source and drain electrodes are provided on the main active layer and the gate insulating layer;
  • the secondary source and drain are arranged on the secondary active layer and the gate insulating layer.
  • the main grid and the sub-grid are made at intervals on a glass substrate, wherein at least part of the sub-grid has a light-transmitting area;
  • a gate insulating layer is fabricated on the gate and the glass substrate;
  • a semiconductor layer is fabricated on the gate insulating layer, and the semiconductor layer is patterned to obtain a primary active layer and a secondary active layer.
  • the position of the secondary active layer Corresponding to the position of the light-transmitting area; forming a second metal layer on the main active layer, the secondary active layer, and the gate insulating layer, and patterning the second metal layer to obtain Primary source and drain and secondary source and drain; since the gate corresponding to the secondary active layer is a light-transmitting area, the photosensitive area of the secondary thin film transistor is increased, thereby increasing the light current, and thus improving the sensitivity of the touch function And accuracy.
  • FIG. 1 is a first step-by-step schematic diagram of the first step of the manufacturing method of the display panel according to the first embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a second sub-step structure of the first step of the manufacturing method of the display panel according to the first embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of the first sub-step of the second step of the manufacturing method of the display panel according to the first embodiment of the present invention.
  • FIG. 4 is a schematic diagram of the second sub-step structure of the second step of the manufacturing method of the display panel according to the first embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of the third step of the manufacturing method of the display panel according to the first embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of the fourth step of the manufacturing method of the display panel according to the first embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of the fifth step of the manufacturing method of the display panel according to the first embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of the sixth step of the manufacturing method of the display panel according to the first embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of the seventh step of the manufacturing method of the display panel according to the first embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a display panel according to the second embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of a display panel according to the third embodiment of the present invention.
  • FIG. 12 is a graph of the current and voltage of the sub-thin film transistor of the present invention under different illumination.
  • the present invention provides a method for manufacturing a display panel including:
  • a main grid and a sub-grid are formed spaced apart on the glass substrate 11.
  • the main grid includes a first grid portion 131 and a main grid.
  • the light-transmitting portion 121 includes a second gate portion 132 and a secondary light-transmitting portion 122, wherein a light-transmitting area (not shown in the figure) is formed at a position corresponding to the secondary light-transmitting portion 122.
  • the main gate may not include the main light-transmitting portion, that is, the entire main gate is a light-impermeable area.
  • the entire sub-gate may be a light-transmitting area.
  • a gate insulating layer 14 is formed on the main gate and the secondary gate.
  • the material of the gate insulating layer 14 may be at least one of SiNx and SiOx, or it may be a single layer or a SiOx/SiNx stacked layer.
  • a semiconductor layer 15 is fabricated on the gate insulating layer 14, and the semiconductor layer 15 is patterned to obtain a primary active layer 151 and a secondary active layer 152.
  • the secondary active layer The position of 152 corresponds to the position of the light-transmitting area; that is, it corresponds to the position of the secondary light-transmitting portion.
  • a second metal layer 16 is formed on the main active layer 151, the secondary active layer 152, and the gate insulating layer 14, and the second metal layer 16 is patterned.
  • the main source drain 161 and the secondary source drain 162 are obtained.
  • the material structure of the second metal layer 16 may be a Mo/Al or Mo/Cu stack.
  • the main gate, the main active layer, and the main source and drain constitute the main thin film transistor, that is, the switching thin film transistor (the TFT on the left); the secondary gate, the secondary active layer, and the secondary source and drain constitute the secondary thin film transistor (right TFT on the side), which is equivalent to the sensor.
  • FIG. 1 is a first step-by-step structure diagram of the first step of the manufacturing method of the display panel according to the first embodiment of the present invention.
  • an entire transparent conductive layer 12 is fabricated on a glass substrate 11, and the transparent electrode layer 12 is patterned to obtain a primary light-transmitting portion 121 and a secondary light-transmitting portion 122.
  • the material of the transparent electrode 12 may include at least one of indium tin oxide (ITO), Ag nanowires, and AZO (aluminum-doped zinc oxide).
  • a first metal layer 13 is formed on the main light-transmitting portion 121 and the secondary light-transmitting portion 122, and the first metal layer 13 is patterned to obtain a first gate electrode. 131 and a second gate 132.
  • the material structure of the first metal layer 13 may be Mo/Al, Mo/Cu, or the like.
  • the first gate portion 131 covers the main light-transmitting portion 121 to obtain a main gate.
  • the second gate portion 132 may be located on both sides of the sub-transmissive portion 122 to obtain a sub-gate.
  • the second gate portion 132 includes a first portion 31 and a second portion 32, and the first portion 31 and the second portion 32 are respectively located on both sides of the secondary light transmission portion 122.
  • the position corresponding to the secondary light-transmitting portion 122 forms the light-transmitting area.
  • the main grid includes a first grid portion 131 and a main light-transmitting portion 121
  • the sub-grid portion includes a second grid portion 132 and a secondary light-transmitting portion 122, which corresponds to the secondary light-transmitting portion 122
  • the position forms a light-transmitting area (not shown in the figure).
  • a gate insulating layer 14 is deposited on the main gate and the secondary gate.
  • the material of the gate insulating layer 14 may be at least one of SiNx and SiOx, or it may be a single layer or a SiOx/SiNx stacked layer.
  • S104 Fabricate a semiconductor layer on the gate insulating layer, perform a patterning process on the semiconductor layer to obtain a main active layer and a secondary active layer, and the position of the secondary active layer corresponds to the position of the light-transmitting region ;
  • a semiconductor layer 15 is fabricated on the gate insulating layer 14, and the semiconductor layer 15 is patterned to obtain a primary active layer 151 and a secondary active layer 152.
  • the secondary active layer The position of 152 corresponds to the position of the light-transmitting area; that is, it corresponds to the position of the secondary light-transmitting portion.
  • the mask used in the patterning of the transparent electrode layer is the same as the mask used in the patterning of the semiconductor layer, so that The position of the main active layer 151 may correspond to the position of the main light-transmitting portion 121, thereby saving the number of masks and reducing the production cost.
  • the material of the semiconductor layer 15 may include at least one of oxide semiconductor, amorphous silicon, polysilicon, and organic semiconductor.
  • a second metal layer 16 is formed on the main active layer 151, the secondary active layer 152, and the gate insulating layer 14, and the second metal layer 16 is patterned.
  • the main source drain 161 and the secondary source drain 162 are obtained.
  • the material structure of the second metal layer 16 may be a Mo/Al or Mo/Cu stack.
  • the main gate, the main active layer, and the main source and drain constitute the main thin film transistor, that is, the switching thin film transistor (the TFT on the left); the secondary gate, the secondary active layer, and the secondary source and drain constitute the secondary thin film transistor (right TFT on the side), which is equivalent to the sensor.
  • a first current is generated; when the top of the sub-thin film transistor is illuminated, a second current is generated, and the first current is greater than the second current. And the first current is greater than or equal to 5 times the second current.
  • the above method may also include:
  • a passivation layer 17 is deposited on the main source and drain electrodes 161 and the secondary source and drain electrodes 162, and the passivation layer 17 is provided with via holes (not shown in the figure).
  • the material structure of the passivation layer 17 can be a SiNx, SiOx/SiNx stack.
  • a transparent electrode layer is fabricated and deposited on the passivation layer 17 and in the via hole, and then patterned to obtain a pixel electrode 18, wherein the pixel electrode 18 passes through the via hole and Main drain connection.
  • this embodiment also provides a display panel, which includes a glass substrate 11, a main gate and a sub-gate, a gate insulating layer 14, a main active layer 151 and a sub-active layer 152, and a main source and drain. Pole 161 and secondary source and drain 162.
  • the main gate and the sub-gate are spaced apart, and the main gate and the sub-gate are both disposed on the glass substrate 11.
  • the main gate includes a first gate portion 131 and a main gate.
  • the sub-gate includes a sub-transmissive portion 122 and a second gate portion 132, and the sub-transparent portion 122 corresponds to the position of the transmissive region.
  • the second gate portion 132 may include a first portion 31 and a second portion 32, and the first portion 31 and the second portion 32 are respectively located on both sides of the secondary light transmission portion 122.
  • the second gate portion 132 may also be located on one side of the secondary light-transmitting portion 122.
  • the gate insulating layer 14 is provided on the main gate and the sub-gate.
  • the main active layer and the secondary active layer are both provided on the gate insulating layer 14; the position of the secondary active layer 152 corresponds to the position of the light-transmitting area;
  • the main source and drain electrodes 161 are arranged on the main active layer 151 and the gate insulating layer 14;
  • the secondary source and drain electrodes 162 are provided on the secondary active layer 152 and the gate insulating layer 14.
  • a passivation layer 17 and a pixel electrode 18 may also be included.
  • the part of the sub-gate has a light-transmitting area, and the light-transmitting area corresponds to the position of the sub-active layer, that is, the light-transmitting area is made of a transparent conductive layer, so the photosensitive area of the sub-thin film transistor can be increased. Increase the light current, thereby improving the sensitivity and accuracy of the touch function.
  • FIG. 10 is a schematic structural diagram of a display panel according to the second embodiment of the present invention.
  • a transparent electrode layer is fabricated on the glass substrate 11, and the transparent electrode layer 12 is patterned to obtain the secondary light-transmitting portion 122. That is, in this embodiment, the thin film transistor on the left does not include the main light-transmitting part. That is, the mask used in this step is different from the mask used in the manufacturing process of the active layer.
  • a first metal layer 13 is formed on the secondary light-transmitting portion 122, and the first metal layer 13 is patterned to obtain a first gate portion 131 and a second gate portion 132.
  • the material structure of the first metal layer 13 may be Mo/Al, Mo/Cu, or the like.
  • the first gate portion 131 forms a main gate. That is, the main gate does not include the main light-transmitting portion, that is, the entire main gate is an opaque area.
  • the sub-gate portion includes a second gate portion 132 and a sub-transmitting portion 122, wherein a position corresponding to the sub-transmitting portion 122 forms the translucent area, in other words the sub-transmitting portion 122 Corresponds to the position of the light-transmitting area (not shown in the figure).
  • the main gate of this embodiment is the first gate portion 131, that is, it does not include the main light-transmitting portion.
  • FIG. 11 is a schematic structural diagram of a display panel according to a third embodiment of the present invention.
  • the difference between the manufacturing method of this embodiment and the first embodiment is that the entire sub-gate is a light-transmitting area, and the second step of the previous embodiment Can be replaced by:
  • a first metal layer 13 is formed on the primary light-transmitting portion 121 and the secondary light-transmitting portion 122, and the first metal layer 13 is patterned to obtain a first gate portion 131 ,
  • the main gate includes a first gate portion 131 and a main light-transmitting portion 121
  • the sub-grid is a sub-light-transmitting portion 122
  • a position corresponding to the sub-light-transmitting portion 122 forms a light-transmitting area ( Figure Not shown in).
  • the secondary light-transmitting portion 122 covers the secondary source and drain. That is, the thin film transistor on the right side of this embodiment does not include the second gate portion. That is, the entire sub-gate is a light-transmitting area.
  • the sub-gate of this embodiment is the sub-transmissive portion 122, that is, it does not include the second gate portion.
  • the thickness of the active layer is 40nm
  • the abscissa represents the voltage
  • the ordinate represents the current
  • 101, 102, and 103 respectively represent the illumination at the bottom and the top
  • the main grid and the sub-grid are made at intervals on a glass substrate, wherein at least part of the sub-grid has a light-transmitting area;
  • a gate insulating layer is fabricated on the gate and the glass substrate;
  • a semiconductor layer is fabricated on the gate insulating layer, and the semiconductor layer is patterned to obtain a primary active layer and a secondary active layer.
  • the position of the secondary active layer Corresponding to the position of the light-transmitting region; forming a second metal layer on the main active layer, the secondary active layer, and the gate insulating layer, and patterning the second metal layer to obtain Primary source drain and secondary source drain; since the gate corresponding to the secondary active layer is a light-transmitting area, the photosensitive area of the secondary thin film transistor is increased, thereby increasing the light current, thereby improving the sensitivity and sensitivity of the touch function accuracy.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)

Abstract

一种显示面板及其制作方法，该方法包括：在玻璃基板（11）上制作主栅极和次栅极，其中至少部分次栅极具有透光区域；在主栅极、次栅极上依次制作栅绝缘层（14）、半导体层（15）以及第二金属层（16），对半导体层（15）进行图案化处理得到主有源层（151）和次有源层（152），对第二金属层（16）进行图案化处理，得到主源漏极（161）和次源漏极（162）。

Description

一种显示面板及其制作方法 技术领域
本发明涉及显示技术领域，特别是涉及一种显示面板及其制作方法。。
 背景技术
目前的触控技术包括on-cell和in-cell两种，on-cel1是将触控、指纹识别对应的传感器独立安装在显示面板外，因而无法做到在显示面板上的定点感应。
 技术问题
而in-cell是将触摸功能嵌入到液晶像素中的触控技术，但是由于目前这种方式主要使用顶部照光（top）的方式，容易受到沟道面积及背沟道缺陷的影响，导致光电流较低，因此降低了触控功能的灵敏性和准确性。
因此，有必要提供一种显示面板及其制作方法，以解决现有技术所存在的问题。
 技术解决方案
本发明的目的在于提供一种显示面板及其制作方法，能够增大光电流，从而提高了触控功能的灵敏性和准确性。
为解决上述技术问题，本发明提供一种显示面板的制作方法，包括：
在玻璃基板上制作透明电极层，对所述透明电极层进行图案化处理，得到主透光部和次透光部；
在所述主透光部、所述次透光部以及所述玻璃基板上制作第一金属层，对所述第一金属层进行图案化处理，得到第一栅极部和第二栅极部，其中所述主栅极包括第一栅极部和主透光部，所述次栅极包括第二栅极部和次透光部，其中与所述次透光部对应的位置形成透光区域；
在所述主栅极、所述次栅极以及所述玻璃基板上制作栅绝缘层；
在所述栅绝缘层上制作半导体层，对所述半导体层进行图案化处理得到主有源层和次有源层，所述次有源层的位置与所述透光区域的位置对应；以及
在所述主有源层、所述次有源层以及所述栅绝缘层上制作第二金属层，对所述第二金属层进行图案化处理，得到主源漏极和次源漏极；
其中次栅极、次有源层以及次源漏极组成次薄膜晶体管；
当对所述次薄膜晶体管的底部进行光照时，产生第一电流；当对所述次薄膜晶体管的顶部进行光照时，产生第二电流，所述第一电流大于所述第二电流。
本发明提供一种显示面板的制作方法，包括：
在玻璃基板上制作间隔设置的主栅极和次栅极，其中至少部分所述次栅极具有透光区域；
在所述主栅极、所述次栅极以及所述玻璃基板上制作栅绝缘层；
在所述栅绝缘层上制作半导体层，对所述半导体层进行图案化处理得到主有源层和次有源层，所述次有源层的位置与所述透光区域的位置对应；
在所述主有源层、所述次有源层以及所述栅绝缘层上制作第二金属层，对所述第二金属层进行图案化处理，得到主源漏极和次源漏极。
本发明还提供一种显示面板，其包括：
玻璃基板；
间隔设置的主栅极和次栅极，均设于所述玻璃基板上；至少所述次栅极的部分具有透光区域；
栅绝缘层，设于所述主栅极、所述次栅极以及所述玻璃基板上；
主有源层和次有源层，均设于所述栅绝缘层上；所述次有源层的位置与所述透光区域的位置对应；
主源漏极，设于所述主有源层和所述栅绝缘层上；
次源漏极，设于所述次有源层和所述栅绝缘层上。
 有益效果
本发明的显示面板及其制作方法，通过在玻璃基板上制作间隔设置的主栅极和次栅极，其中至少部分所述次栅极具有透光区域；在所述主栅极、所述次栅极以及玻璃基板上制作栅绝缘层；在所述栅绝缘层上制作半导体层，对所述半导体层进行图案化处理得到主有源层和次有源层，所述次有源层的位置与所述透光区域的位置对应；在所述主有源层、所述次有源层以及所述栅绝缘层上制作第二金属层，对所述第二金属层进行图案化处理，得到主源漏极和次源漏极；由于与次有源层对应的栅极为透光区域，因此增加了次薄膜晶体管的感光面积，因而增大了光照电流，进而提高了触控功能的灵敏性和准确性。
 附图说明
图1为本发明实施例一的显示面板的制作方法的第一步的第一分步结构示意图。
图2为本发明实施例一的显示面板的制作方法的第一步的第二分步结构示意图。
图3为本发明实施例一的显示面板的制作方法的第二步的第一分步的结构示意图。
图4为本发明实施例一的显示面板的制作方法的第二步的第二分步的结构示意图。
图5为本发明实施例一的显示面板的制作方法的第三步的结构示意图。
图6为本发明实施例一的显示面板的制作方法的第四步的结构示意图。
图7为本发明实施例一的显示面板的制作方法的第五步的结构示意图。
图8为本发明实施例一的显示面板的制作方法的第六步的结构示意图。
图9为本发明实施例一的显示面板的制作方法的第七步的结构示意图。
图10为本发明实施例二的显示面板的结构示意图。
图11为本发明实施例三的显示面板的结构示意图。
图12为本发明的次薄膜晶体管在不同光照下的电流与电压之间的曲线图。
 本发明的实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
请参照图1至11，本发明提供一种显示面板的制作方法包括：
S11、在玻璃基板上制作间隔设置的主栅极和次栅极，其中至少部分所述次栅极具有透光区域；
如图4所示，在一实施方式中，在玻璃基板11上制作间隔设置的主栅极和次栅极，在一实施方式中，其中所述主栅极包括第一栅极部131和主透光部121，所述次栅极部包括第二栅极部132和次透光部122，其中与所述次透光部122对应的位置形成透光区域（图中未示出）。当然可以理解的，如图10所示，主栅极也可不包括主透光部，也即整个主栅极都为不透光区域。如图11所示，整个次栅极可都为透光区域。
S12、在所述主栅极和所述次栅极上制作栅绝缘层；
如图5所示，在所述主栅极和所述次栅极上制作栅绝缘层14。栅极绝缘层14的材料可为SiNx、SiOx中的至少一种，也即可为单层或者SiOx/SiNx叠层。
S13、在所述栅绝缘层上制作半导体层，对所述半导体层进行图案化处理得到主有源层和次有源层，所述次有源层的位置与所述透光区域的位置对应；
例如，如图6所示，在所述栅绝缘层14上制作半导体层15，对所述半导体层15进行图案化处理得到主有源层151和次有源层152，所述次有源层152的位置与所述透光区域的位置对应；也即与次透光部的位置对应。
S14、在所述主有源层、所述次有源层以及栅绝缘层上制作第二金属层，对所述第二金属层进行图案化处理，得到主源漏极和次源漏极。
例如，如图7所示，在所述主有源层151、所述次有源层152和栅绝缘层14上制作第二金属层16，对所述第二金属层16进行图案化处理，得到主源漏极161和次源漏极162。第二金属层16的材料结构可为Mo/Al或者Mo/Cu叠层。
其中主栅极、主有源层以及主源漏极组成主薄膜晶体管，也即开关薄膜晶体管（左侧的TFT）；次栅极、次有源层以及次源漏极组成次薄膜晶体管（右侧的TFT），也即相当于传感器。
请参照图1至8，图1为本发明实施例一的显示面板的制作方法的第一步的第一分步结构示意图。
本实施例的显示面板的制作方法包括：
S101、在玻璃基板上制作透明电极层，对所述透明电极层进行图案化处理，得到主透光部和次透光部；
例如，如图1和2所示，在玻璃基板11上制作整层透明导电层12，对所述透明电极层12进行图案化处理，得到主透光部121和次透光部122。其中为了增大光照电流，所述透明电极12的材料可包括氧化铟锡（ITO，Indium tin oxide）、Ag纳米线以及AZO（铝掺杂的氧化锌）中的至少一种。
S102、在所述主透光部、次透光部和玻璃基板上制作第一金属层，对所述第一金属层进行图案化处理，得到第一栅极部和第二栅极部；
例如，如图3和4所示，在所述主透光部121和次透光部122上制作第一金属层13，对所述第一金属层13进行图案化处理，得到第一栅极部131和第二栅极部132。第一金属层13的材料结构可为Mo/Al、Mo/Cu等。
其中，所述第一栅极部131包覆所述主透光部121，以得到主栅极。为了简化制程工艺，所述第二栅极部132可位于所述次透光部122的两侧，以得到次栅极。其中所述第二栅极部132包括第一部分31和第二部分32，所述第一部分31和第二部分32分别位于所述次透光部122的两侧。与所述次透光部122对应的位置形成所述透光区域。
其中所述主栅极包括第一栅极部131和主透光部121，所述次栅极部包括第二栅极部132和次透光部122，其中与所述次透光部122对应的位置形成透光区域（图中未示出）。
S103、在所述主栅极和所述次栅极上制作栅绝缘层；
例如，如图5所示，在所述主栅极和所述次栅极上沉积栅绝缘层14。栅极绝缘层14的材料可为SiNx、SiOx中的至少一种，也即可为单层或者SiOx/SiNx叠层。
S104、在所述栅绝缘层上制作半导体层，对所述半导体层进行图案化处理得到主有源层和次有源层，所述次有源层的位置与所述透光区域的位置对应；
例如，如图6所示，在所述栅绝缘层14上制作半导体层15，对所述半导体层15进行图案化处理得到主有源层151和次有源层152，所述次有源层152的位置与所述透光区域的位置对应；也即与次透光部的位置对应。
其中，在一实施方式中，所述对所述透明电极层进行图案化处理中所采用的掩膜板与所述对所述半导体层进行图案化处理中所采用的掩膜板相同，进而使得主有源层151的位置可与主透光部121的位置对应，从而节省掩膜板的数量，降低生产成本。
其中所述半导体层15的材料可包括氧化物半导体、非晶硅、多晶硅以及有机物半导体中的至少一种。
S105、在所述主有源层、所述次有源层以及栅绝缘层上制作第二金属层，对所述第二金属层进行图案化处理，得到主源漏极和次源漏极。
例如，如图7所示，在所述主有源层151、所述次有源层152和栅绝缘层14上制作第二金属层16，对所述第二金属层16进行图案化处理，得到主源漏极161和次源漏极162。第二金属层16的材料结构可为Mo/Al或者Mo/Cu叠层。
其中主栅极、主有源层以及主源漏极组成主薄膜晶体管，也即开关薄膜晶体管（左侧的TFT）；次栅极、次有源层以及次源漏极组成次薄膜晶体管（右侧的TFT），也即相当于传感器。
当对所述次薄膜晶体管的底部进行光照时，产生第一电流；当对所述次薄膜晶体管的顶部进行光照时，产生第二电流，所述第一电流大于所述第二电流。且第一电流大于等于第二电流的5倍。
上述方法还可包括：
S107、在所述主源漏极和所述次源漏极上形成钝化层，所述钝化层上设置有过孔；
如图8所示，在所述主源漏极161和所述次源漏极162上沉积钝化层17，所述钝化层17上设置有过孔（图中未示出）。钝化层17的材料结构可为SiNx、SiOx/SiNx叠层。
S108、在所述钝化层上以及所述过孔内制作像素电极，其中所述像素电极通过所述过孔与主漏极连接。
如图9所示，在所述钝化层17上以及所述过孔内制作沉积透明电极层，然后对其进行图案化处理得到像素电极18，其中所述像素电极18通过所述过孔与主漏极连接。
如图9所示，本实施例还提供一种显示面板，其包括玻璃基板11、主栅极和次栅极、栅绝缘层14、主有源层151和次有源层152、主源漏极161和次源漏极162。
主栅极和次栅极之间间隔设置，且主栅极和次栅极均设于所述玻璃基板11上；在一实施方式中，所述主栅极包括第一栅极部131和主透光部121，其中所述第一栅极部131可包覆所述主透光部121。
所述次栅极包括次透光部122和第二栅极部132，所述次透光部122与所述透光区域的位置对应。结合图4，其中所述第二栅极部132可包括第一部分31和第二部分32，所述第一部分31和第二部分32分别位于所述次透光部122的两侧。当然，所述第二栅极部132也可位于所述次透光部122的一侧。
栅绝缘层14设于所述主栅极、所述次栅极上。
主有源层和次有源层，均设于所述栅绝缘层14上；所述次有源层152的位置与所述透光区域的位置对应；
主源漏极161，设于所述主有源层151和栅绝缘层14上；
次源漏极162，设于所述次有源层152和栅绝缘层14上。
此外还可包括钝化层17和像素电极18。
由于次栅极的部分具有透光区域，且透光区域与次有源层的位置对应，也即该透光区域是采用透明导电层制作得到，因此可以增加了次薄膜晶体管的感光面积，因而增大了光照电流，进而提高触控功能的灵敏性和准确性。
请参照图10，图10为本发明实施例二的显示面板的结构示意图。
当然，如图10所示，在上一实施例的基础上，本实施例的制作方法与上一实施例的区别在于，主栅极的结构与上一实施例不同，具体是将上一实施例的第一步和第二步分别替换为：
S201、在玻璃基板上制作透明电极层，对所述透明电极层进行图案化处理，得到次透光部；
如图10所示，在玻璃基板11上制作透明电极层，对所述透明电极层12进行图案化处理，得到次透光部122。也即在本实施例中，左侧的薄膜晶体管不包括主透光部。也即本步骤中所采用的掩膜板与有源层制作过程中采用的掩膜板不同。
S202、在所述次透光部和玻璃基板上制作第一金属层，对所述第一金属层进行图案化处理，得到主栅极和第二栅极部。
例如，在所述次透光部122上制作第一金属层13，对所述第一金属层13进行图案化处理，得到第一栅极部131和第二栅极部132。第一金属层13的材料结构可为Mo/Al、Mo/Cu等。
其中，所述第一栅极部131形成主栅极。也即所述主栅极不包括主透光部，也即整个主栅极为不透区域。所述次栅极部包括第二栅极部132和次透光部122，其中与所述次透光部122对应的位置形成所述透光区域，换句话讲所述次透光部122与透光区域（图中未示出）的位置对应。
本实施例的显示面板与上一实施例的区别在于：本实施例的所述主栅极为第一栅极部131，也即不包括主透光部。
请参照图11，图11为本发明实施例三的显示面板的结构示意图。
当然，如图11所示，在第一实施例的基础上，本实施例的制作方法与第一实施例的区别在于，整个次栅极都为透光区域，上一实施例的第二步可替换为：
S302、在所述主透光部和次透光部上制作第一金属层，对所述第一金属层进行图案化处理，得到第一栅极部，其中所述主栅极包括第一栅极部和主透光部，所述次栅极为次透光部。
例如，如图11所示，在所述主透光部121和次透光部122上制作第一金属层13，对所述第一金属层13进行图案化处理，得到第一栅极部131，其中所述主栅极包括第一栅极部131和主透光部121，所述次栅极为次透光部122，其中与所述次透光部122对应的位置形成透光区域（图中未示出）。其中次透光部122覆盖次源漏极。也即本实施例的右侧的薄膜晶体管不包括第二栅极部。也即整个次栅极都为透光区域。
本实施例的显示面板与第一实施例的区别在于：本实施例的所述次栅极为次透光部122，也即不包括第二栅极部。
如图12所示，以有源层的材料为非晶硅为例，有源层的厚度为40nm，横坐标表示电压，纵坐标表示电流，其中101、102、103分别表示在底部光照、顶部光照以及无光照情况下的次薄膜晶体管的电流和电压之间的关系图，可见对所述次薄膜晶体管的底部进行光照时产生的电流大于对所述次薄膜晶体管的顶部进行光照时产生的电流。
本发明的显示面板及其制作方法，通过在玻璃基板上制作间隔设置的主栅极和次栅极，其中至少部分所述次栅极具有透光区域；在所述主栅极、所述次栅极以及玻璃基板上制作栅绝缘层；在所述栅绝缘层上制作半导体层，对所述半导体层进行图案化处理得到主有源层和次有源层，所述次有源层的位置与所述透光区域的位置对应；在所述主有源层、所述次有源层以及所述栅绝缘层上制作第二金属层，对所述第二金属层进行图案化处理，得到主源漏极和次源漏极；由于与次有源层对应的栅极为透光区域，因此增加了次薄膜晶体管的感光面积，因而增大了光照电流，进而提高触控功能的灵敏性和准确性。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板的制作方法，其包括：
    在玻璃基板上制作透明电极层，对所述透明电极层进行图案化处理，得到主透光部和次透光部；
    在所述主透光部、所述次透光部以及所述玻璃基板上制作第一金属层，对所述第一金属层进行图案化处理，得到第一栅极部和第二栅极部，其中所述主栅极包括第一栅极部和主透光部，所述次栅极包括第二栅极部和次透光部，其中与所述次透光部对应的位置形成透光区域；
    在所述主栅极、所述次栅极以及所述玻璃基板上制作栅绝缘层；
    在所述栅绝缘层上制作半导体层，对所述半导体层进行图案化处理得到主有源层和次有源层，所述次有源层的位置与所述透光区域的位置对应；以及
    在所述主有源层、所述次有源层以及所述栅绝缘层上制作第二金属层，对所述第二金属层进行图案化处理，得到主源漏极和次源漏极；
    其中次栅极、次有源层以及次源漏极组成次薄膜晶体管；
    当对所述次薄膜晶体管的底部进行光照时，产生第一电流；当对所述次薄膜晶体管的顶部进行光照时，产生第二电流，所述第一电流大于所述第二电流。
  2. 根据权利要求1所述的显示面板的制作方法，其中
    所述次透光部未覆盖所述第二栅极部。
  3. 根据权利要求2所述的显示面板的制作方法，其中所述第二栅极部包括第一部分和第二部分，所述第一部分和第二部分分别位于所述次透光部的两侧。
  4. 根据权利要求3所述的显示面板的制作方法，其中所述主透光部与所述主有源层的位置对应，且所述第一栅极部包覆所述主透光部。
  5. 根据权利要求1所述的显示面板的制作方法，其中所述对所述透明电极层进行图案化处理中所采用的掩膜板与所述对所述半导体层进行图案化处理中所采用的掩膜板相同。
  6. 根据权利要求1所述的显示面板的制作方法，其中所述方法还包括：
    在所述主源漏极和所述次源漏极上形成钝化层，所述钝化层上设置有过孔；
    在所述钝化层上以及所述过孔内制作像素电极，其中所述像素电极通过所述过孔与主漏极连接。
  7. 根据权利要求1所述的显示面板的制作方法，其中
    所述透明电极的材料包括ITO、Ag纳米线以及AZO中的至少一种。
  8. 一种显示面板的制作方法，其包括：
    在玻璃基板上制作间隔设置的主栅极和次栅极，其中至少部分所述次栅极具有透光区域；
    在所述主栅极、所述次栅极以及所述玻璃基板上制作栅绝缘层；
    在所述栅绝缘层上制作半导体层，对所述半导体层进行图案化处理得到主有源层和次有源层，所述次有源层的位置与所述透光区域的位置对应；以及
    在所述主有源层、所述次有源层以及所述栅绝缘层上制作第二金属层，对所述第二金属层进行图案化处理，得到主源漏极和次源漏极。
  9. 根据权利要求8所述的显示面板的制作方法，其中所述在玻璃基板上制作间隔设置的主栅极和次栅极的步骤包括：
    在玻璃基板上制作透明电极层，对所述透明电极层进行图案化处理，得到主透光部和次透光部；
    在所述主透光部、次透光部以及所述玻璃基板上制作第一金属层，对所述第一金属层进行图案化处理，得到第一栅极部和第二栅极部，其中所述主栅极包括第一栅极部和主透光部，所述次栅极包括第二栅极部和次透光部，其中与所述次透光部对应的位置形成所述透光区域。
  10. 根据权利要求9所述的显示面板的制作方法，其中所述次透光部未覆盖所述第二栅极部。
  11. 根据权利要求10所述的显示面板的制作方法，其中所述第二栅极部包括第一部分和第二部分，所述第一部分和第二部分分别位于所述次透光部的两侧。
  12. 根据权利要求11所述的显示面板的制作方法，其中所述主透光部与所述主有源层的位置对应，且所述第一栅极部包覆所述主透光部。
  13. 根据权利要求9所述的显示面板的制作方法，其中所述对所述透明电极层进行图案化处理中所采用的掩膜板与所述对所述半导体层进行图案化处理中所采用的掩膜板相同。
  14. 根据权利要求8所述的显示面板的制作方法，其中次栅极、次有源层以及次源漏极组成次薄膜晶体管；
    当对所述次薄膜晶体管的底部进行光照时，产生第一电流；当对所述次薄膜晶体管的顶部进行光照时，产生第二电流，所述第一电流大于所述第二电流。
  15. 根据权利要求8所述的显示面板的制作方法，其中所述方法还包括：
    在所述主源漏极和所述次源漏极上形成钝化层，所述钝化层上设置有过孔；
    在所述钝化层上以及所述过孔内制作像素电极，其中所述像素电极通过所述过孔与主漏极连接。
  16. 根据权利要求8所述的显示面板的制作方法，其中
    所述透明电极的材料包括ITO、Ag纳米线以及AZO中的至少一种。
  17. 一种显示面板，其包括：
    玻璃基板；
    间隔设置的主栅极和次栅极，均设于所述玻璃基板上；至少所述次栅极的部分具有透光区域；
    栅绝缘层，设于所述主栅极、所述次栅极以及所述玻璃基板上；
    主有源层和次有源层，均设于所述栅绝缘层上；所述次有源层的位置与所述透光区域的位置对应；
    主源漏极，设于所述主有源层和所述栅绝缘层上；以及
    次源漏极，设于所述次有源层和所述栅绝缘层上。
  18. 根据权利要求17所述的显示面板，其中所述次栅极包括次透光部和第二栅极部，与所述次透光部对应的位置形成所述透光区域。
  19. 根据权利要求18所述的显示面板，其中所述第二栅极部包括第一部分和第二部分，所述第一部分和第二部分分别位于所述次透光部的两侧。
  20. 根据权利要求17所述的显示面板，其中所述透明电极的材料包括ITO、Ag纳米线以及AZO中的至少一种。
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