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WO2021066001A1 - Dispositif de traitement d'informations et procédé de commutation de communication - Google Patents

Dispositif de traitement d'informations et procédé de commutation de communication Download PDF

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Publication number
WO2021066001A1
WO2021066001A1 PCT/JP2020/037125 JP2020037125W WO2021066001A1 WO 2021066001 A1 WO2021066001 A1 WO 2021066001A1 JP 2020037125 W JP2020037125 W JP 2020037125W WO 2021066001 A1 WO2021066001 A1 WO 2021066001A1
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WIPO (PCT)
Prior art keywords
physical layer
layer device
switching
bus
cpu
Prior art date
Application number
PCT/JP2020/037125
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English (en)
Japanese (ja)
Inventor
剛 小宮山
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2021551368A priority Critical patent/JP7052929B2/ja
Priority to PH1/2022/550550A priority patent/PH12022550550A1/en
Publication of WO2021066001A1 publication Critical patent/WO2021066001A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/323—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the physical layer [OSI layer 1]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Definitions

  • This disclosure relates to an information processing device that switches between a data bus, a control bus, and an interrupt bus, and a communication switching method.
  • the CPU board is composed of a carrier board that provides an external interface and one or two CPU boards mounted on the carrier board.
  • the CPU board is used for the following purposes (1) and (2), for example.
  • Device control Two communication paths are required in order to mount one CPU board and communicate with the host device and each part in the device.
  • Signal processing Two CPU boards are mounted to perform signal processing in parallel, and each CPU requires one communication path to transmit and receive processing data to and from a host device.
  • the CPU board is equipped with MAC (Media Access Control), which is two LAN (Local Area Network) controllers, as a communication function.
  • the LAN controller provides a communication function by connecting to a LAN connector via a physical layer device, which is a circuit on which a physical layer (PHY) function is mounted, formed on a carrier board. ..
  • PHY physical layer
  • Patent Document 1 discloses a technique relating to switching between a CPU and a communication path.
  • Patent Document 1 provides a mechanism for switching between two CPUs and external communication, there is a problem that the mechanism for switching the following three buses is not mentioned. That is, for the connection between the MAC and the PHY, there are three types of buses: a data bus for transmitting and receiving communication data, a control bus for controlling the PHY from the MAC, and an interrupt bus for notifying the CPU of an interrupt from the PHY. It is necessary, and you need to switch between them at the same time to change the connection.
  • This disclosure is made in order to solve the above-mentioned problems, and obtains an information processing device and a communication switching method that can easily perform data bus switching, control bus switching, and interrupt bus switching at the same timing.
  • the purpose is.
  • the connection destination with the second physical layer device by the data bus is switched to either the second LAN controller or the third LAN controller, and the second physical layer is used.
  • the control bus is switched so that either the first LAN controller or the third LAN controller accesses the second physical layer device according to the connection destination by the data bus (second data bus) of the layer device, and the second physical layer device is switched.
  • the interrupt bus is switched according to the connection destination by the data bus (second data bus) of the above, and the interrupt processing to the first CPU is sent from both the first physical layer device and the second physical layer device, or the first It is characterized in that it notifies the first CPU whether or not it is sent only from the physical layer device.
  • data bus switching, control bus switching, and interrupts are performed by performing control bus switching and interrupt bus switching according to the connection destination of the second physical layer device by the second data bus. It is possible to obtain an information processing device and a communication switching method that facilitate bus switching at the same timing.
  • FIG. It is a functional block diagram of the information processing apparatus (CPU board part) which concerns on Embodiment 1.
  • FIG. It is a functional block diagram of the information processing apparatus (CPU board part) which concerns on Embodiment 1.
  • FIG. It is a connection table of the information processing apparatus (CPU board part) which concerns on Embodiment 1.
  • FIG. It is a functional block diagram of the control bus switching part of the information processing apparatus (CPU board part) which concerns on Embodiment 1.
  • FIG. It is a functional block diagram of the interrupt bus switching part of the information processing apparatus (CPU board part) which concerns on Embodiment 1.
  • FIG. 1 It is a functional block diagram of the interrupt bus switching part of the information processing apparatus (CPU board part) which concerns on Embodiment 1.
  • FIG. It is a flowchart which shows the processing step of the communication switching method which concerns on Embodiment 1. It is a functional block diagram of the information processing apparatus which concerns on Embodiment 1.
  • FIG. 1 It is a functional block diagram of the interrupt bus switching part of the information processing apparatus (CPU board part) which concerns on Embodiment 1.
  • the information processing device means a CPU board 100 or a device 110 in which a plurality of CPU boards 100 are incorporated for device control and signal processing. That is, when referring only to the CPU board 100, the information processing device 100 is used, and when referring to a device in which a plurality of CPU boards 100 (for example, CPU board 101 and CPU board 102) are incorporated for device control and signal processing, the information processing device 100 is used. It becomes the information processing device 110.
  • the first CPU board 1 is formed with a first CPU 10, a first LAN controller 11 (first MAC 11), and a second LAN controller 12 (second MAC 12).
  • the second CPU board 2 is formed with a second CPU 20 and a third LAN controller 21 (third MAC 21). As shown in the figure, the second CPU board 2 may have a fourth LAN controller 22 (fourth MAC 22) formed therein.
  • the carrier substrate 3 is a first physical layer device 30 (first PHY 30) for communicating with the outside, preferably a first LAN connector 31, and a second physical layer for communicating with the outside.
  • a device 32 (second PHY 32) and preferably a second LAN connector 33 are formed.
  • the switching unit 4 switches the connection between the first CPU board 1 and the second CPU board 2 and the first physical layer device 30 and the second physical layer device 32.
  • the switching unit 4 includes a data bus switching unit 40, a control bus switching unit 41, and an interrupt bus switching unit 42.
  • the switching portion 4 may be formed on the carrier substrate 3 as shown in the figure.
  • the first data bus 5 connects the first physical layer device 30 and the first LAN controller 11.
  • the second data bus 6 connects the second physical layer device 30 to either the second LAN controller 12 or the third LAN controller 21.
  • the control bus 7 and the interrupt bus 8 will be described later.
  • FIG. 1 is a functional block diagram of the information processing device (CPU board 100) according to the first embodiment.
  • FIG. 2 is a functional block diagram of the information processing device (CPU board 100) according to the first embodiment, and shows an example of a suitable internal configuration of the switching unit 4.
  • the CPU board 100 is composed of two CPU boards, a first CPU board 1, a second CPU board 2, and a carrier board 3. That is, the CPU board 100 is composed of a combination of two types of boards, a CPU board (first CPU board 1 and second CPU board 2) and a carrier board 3.
  • the first CPU board 1 is equipped with a CPU (first CPU 10) and LAN controllers (first MAC 11 and second MAC 12) that control LAN communication.
  • the second CPU board 2 is equipped with a CPU (second CPU 20) and a LAN controller (third MAC21, fourth MAC22) that controls LAN communication.
  • the carrier board 3 is equipped with a physical layer device (first PHY30, second PHY32) and a LAN connector (first LAN connector 31, second LAN connector 33) that perform LAN communication with the outside.
  • the first embodiment includes a case where one CPU board 100 is a combination of one carrier board 3 and one or more CPU boards (in the case of only the first CPU board 1 described above). In this case, that is, the case where the second CPU board 2 is not mounted will be described later.
  • the CPU board 100 shown in FIGS. 1 and 2 is a combination of one carrier board 3 and two CPU boards (first CPU board 1 and second CPU board 2) will be described as a typical example. ..
  • Two MACs are mounted on the CPU board, and since the two CPU boards are mounted on the CPU board 100 in FIGS. 1 and 2, the LAN controller (MAC) is the first MAC11, the second MAC12, the third MAC21, and the fourth MAC22. There are a total of four.
  • the carrier board 3 is equipped with two systems of a physical layer device and a LAN connector (a system of the first PHY 30 and the first LAN connector 31 and a system of the second PHY 32 and the second LAN connector 33). Therefore, by connecting the LAN controller (MAC) of the CPU board and the physical layer device of the carrier board 3, the CPU board 100 can perform LAN communication of a maximum of 2 ports.
  • a physical layer device and a LAN connector a system of the first PHY 30 and the first LAN connector 31 and a system of the second PHY 32 and the second LAN connector 33. Therefore, by connecting the LAN controller (MAC) of the CPU board and the physical layer device of the carrier board 3, the CPU board 100 can perform LAN communication of a maximum of 2 ports.
  • the switching unit 4 has a plurality of physical layer devices (PHY) for performing LAN communication with the outside and the outside via the physical layer device (PHY). It is a circuit for connecting to a LAN controller (MAC) that performs LAN communication.
  • the LAN controller-physical layer device controls the data bus (first data bus 5, second data bus 6) and physical layer device (first PHY30, second PHY32) that input and output communication data.
  • the data buses (first data bus 5 and second data bus 6) are shown by thick solid lines
  • the control bus 7 is shown by a thin solid line as compared with the thick solid line
  • the interrupt bus 8 is shown by a thick solid line. It is shown by a relatively thin broken line.
  • the switching unit 4 includes a total of three LAN controllers (MAC) of the first MAC 11 and the second MAC 12 of the first CPU board 1, the third MAC 21 of the second CPU board 2, and the first PHY 30 of the carrier board 3. Alternatively, it has a function of switching the connection between the second PHY 32. Specifically, the switching unit 4 switches between the second data bus 6, the control bus 7, and the interrupt bus 8 by using the same selection signal as a trigger.
  • the data bus switching unit 40, the control bus switching unit 41, and the interrupt bus switching unit 42, which are a part of the switching unit 4, will be described below with reference to the drawings.
  • the switching unit 4 is mounted on, for example, the carrier substrate 3.
  • the data bus switching unit 40 switches the connection destination of the second data bus 6 with the second physical layer device 32 to either the second LAN controller 12 or the third LAN controller 21.
  • the control bus switching unit 41 either one of the first LAN controller 11 and the third LAN controller 21 accesses the second physical layer device 32 according to the connection destination of the second physical layer device 32 by the second data bus 6.
  • the control bus 7 is switched to.
  • the interrupt bus switching unit 42 switches the interrupt bus 8 according to the connection destination of the second physical layer device 32 by the second data bus 6, and interrupt processing to the first CPU 10 is performed on the first physical layer device 30 and the second. It notifies the first CPU 10 whether it is sent from both the physical layer devices 32 or only from the first physical layer device 30.
  • connection destination of the second physical layer device 32 by the second data bus 6 is, for example, an example of correspondence between the connection between the LAN controller and the physical layer device (between MAC and PHY) and the selection signal shown in FIG. 3, which will be described later. It means to refer to the connection table shown.
  • the switching unit 4 includes a data bus switching unit 40 for switching the connection of the second data bus 6 between the CPU side data port 34 and the physical layer side data bus 35, and the CPU side control port 36.
  • a control bus switching unit 41 for switching the control bus 7 between the physical layer side control bus 37, and an interrupt bus switching unit 42 for switching the interrupt bus 8 between the CPU side interrupt port 38 and the physical layer side interrupt bus 39.
  • a part of the configuration of the port and the bus is also shown in FIG.
  • the information processing device (CPU board 100) may further include a switching control unit 9 that generates a selection signal. That is, the information processing device according to the first embodiment provides the switching control unit 9 for selecting the connection destination and the selection signal to the data bus switching unit 40, the control bus switching unit 41, and the interrupt bus switching unit 42.
  • the CPU board 100) may be included.
  • the switching control unit 9 outputs a selection signal according to an instruction from the first CPU 10, and switches the connection between the LAN controller and the physical layer device (between MAC and PHY) in each switching unit (data bus switching unit 40, control bus switching unit). 41. Notify (instruct) the interrupt bus switching unit 42).
  • the selection signal may be one that the switching control unit 9 sends to the switching unit 4 as a first signal or a second signal. In the present application, the first signal is set to "0" and the second signal is set to "1".
  • the switching control unit 9 generates a selection signal of "0" or "1" (first signal or second signal) according to an instruction (instruction signal) from the first CPU 10.
  • the flow of the instruction signal is shown by a thin dotted line (from the first CPU 10 to the switching control unit 9) as compared with the thick solid line of the data bus. That is, it can be said that this thin dotted line has a finer pitch than the thin broken line showing the interrupt bus 8 in FIG.
  • a thin dotted line from the switching control unit 9 to the data bus switching unit 40 indicates a selection signal sent from the switching control unit 9 to the data bus switching unit 40, and the switching control unit 9 to the control bus switching unit 41.
  • the thin dotted line toward the interrupt bus switching unit 42 indicates the selection signal sent from the switching control unit 9 to the control bus switching unit 41, and the thin dotted line toward the interrupt bus switching unit 42 from the switching control unit 9 indicates the interrupt bus switching unit 42 from the switching control unit 9. Indicates the selection signal sent to.
  • FIG. 3 is a connection table showing an example of correspondence between the connection between the LAN controller and the physical layer device (between MAC and PHY) and the selection signal.
  • the rows indicate the LAN controller (MAC) and the columns indicate the selection signal.
  • the switching control unit 9 may be formed on the carrier substrate 3 as shown in the figure. Of course, at least one of the switching unit 4 and the switching control unit 9 may be formed on the carrier substrate 3.
  • the switching control unit 9 sets the selection signal "0" (first). Signal) is output.
  • one LAN communication port is used for each of the first CPU board 1 and the second CPU board 2, that is, when the first MAC 11 and the first PHY 30 of the first CPU board 1 and the third MAC 21 and the second PHY 32 of the second CPU board 2 are connected, switching is performed.
  • the control unit 9 outputs the selection signal “1” (second signal).
  • a communication path through which CPUs (first CPU 10 and second CPU 20) can communicate with each other is provided on the carrier board 3, and the communication path is used.
  • the first CPU 10 confirms whether or not the second CPU board 2 is mounted by using a method such as the first CPU 10 accessing the second CPU 20.
  • the first CPU 10 confirms whether or not the second CPU board 2 is mounted, and if it is not mounted, 0 is selected as the selection signal so that the first CPU board 1 can use all the LAN communication ports, and the second CPU. If the board 2 is mounted, "1" is selected as the selection signal so that both the first CPU board 1 and the second CPU board 2 can use one LAN communication port.
  • This combination may be another combination depending on the purpose. That is, when it can be confirmed that the second CPU board 2 is mounted, the selection signal "0" or the selection signal "1" may be generated as necessary.
  • the information processing device (CPU board 100) includes a first CPU board 1, a carrier board 3, a first CPU board 1, and an external board (which can be selected to be mounted or not mounted).
  • a switching unit 4 for switching the connection between the first PHY 30 and the second PHY 32 is provided, and the first PHY 30 is connected to the first MAC 11 by the first data bus 5, and when the second CPU board 2 is connected as an external board, It can be said that the operation of the switching unit 4 (data bus switching unit 40, control bus switching unit 41, interrupt bus switching unit 42) described so far is performed.
  • the switching control unit 9 may be provided.
  • the data bus switching unit 40, the control bus switching unit 41, and the interrupt bus switching unit 42 which are three systems of buses, will be described.
  • the data bus switching unit 40, the control bus switching unit 41, and the interrupt bus switching unit 42 receive the selection signals from the switching control unit 9, respectively, in accordance with FIG. 3, the second data bus 6, the control bus 7, and the control bus 7. It switches the connection of the interrupt bus 8.
  • FIG. 4 shows the configuration of the data bus switching unit 40.
  • the first data bus 5 may be formed outside in the data bus switching unit 40.
  • the data bus switching unit 40 receives the selection signal “0” (first signal)
  • the data bus switch 400 is switched by the second data bus 6 to the second physical layer device 32 and the second LAN.
  • the controller 12 is connected and the selection signal "1" (second signal) is received
  • the data bus switch 400 is connected by the second data bus 6 to the second physical layer device 32 and the third LAN controller 21. It is something to do.
  • the data bus switch 400 will not operate if it is arranged on the desired side when the selection signal is received, but this is also included in the switching for convenience.
  • the signal quality may be improved by the buffer 401.
  • the communication speed of LAN communication exceeds 1 Gbps
  • high-speed serial transmission using a differential signal is generally used for the data bus (first data bus 5, second data bus 6) because the data communication is high speed. ..
  • the CPU board first CPU board 1, second CPU board 2
  • the carrier board 3 are connected via the connector, and the bus is switched by the switch, so that the signal quality may deteriorate. Therefore, as shown in FIG.
  • the buffer 401 in the data bus switching unit 40, the buffer 401 is inserted into the data bus (first data bus 5, second data bus 6), and the signal deteriorated by the connector between MAC and PHY and the changeover switch. The signal quality can be ensured by improving.
  • the buffer 401 formed in the first data bus 5 in the data bus switching unit 40 may be formed outside together with the first data bus 5.
  • FIG. 5 shows the configuration of the control bus switching unit 41.
  • the control bus switching unit 41 receives the selection signal “0” (first signal)
  • the control bus switch 403 and the control bus switch 404 are set to the first LAN among the three bus switches.
  • the controller 11 switches to access the second physical layer device 32 and receives the selection signal "1" (second signal)
  • the control bus switch 403 and the control bus switch 404 are switched among the three bus switches.
  • the third LAN controller 21 switches to access the second physical layer device 32. In either case, since the control bus switch 402 is always selected, "1" is input to the enable signal without connecting the selection signal.
  • the control bus 7 is a bus for controlling the operation of the PHY by performing register operations of the PHY (first PHY 30, second PHY 32) from the first CPU 10 or the second CPU 20 via the first MAC 11 or the third MAC 21.
  • the second PHY 32 is accessed from either the first CPU board 1 or the second CPU board 2 according to the switching.
  • the control bus switches 402, 403, and 404 which are the above-mentioned bus switches, are used, and the control bus switch 403 and the control bus switch 404 are exclusively selected for switching.
  • control bus switches 402, 403, and 404 are equipped with a voltage conversion function and are compatible with open drain. Therefore, the I / O voltage may be different between the CPU board (first CPU board 1, second CPU board 2) and the carrier board 3. Further, since it is an open drain, the control bus signal after switching can be Wired-OR and connected to the second PHY 32.
  • the Wired-OR is a logical OR in which a plurality of output signals are connected.
  • FIGS. 6 and 7. The configuration of the interrupt bus switching unit 42 is shown in FIGS. 6 and 7. The configuration of FIG. 7 will be described later.
  • the interrupt bus switching unit 42 receives the selection signal “0” (first signal)
  • the interrupt bus switch 405 is controlled so that the interrupt processing to the first CPU 10 is performed by the first physical layer.
  • the first CPU 10 is notified that it is from both the layer device 30 and the second physical layer device 32, and when the selection signal "1" (second signal) is received, the interrupt bus switch 405 is controlled to the first CPU 10. Notifies the first CPU 10 that the interrupt processing of is only the first physical layer device 30.
  • the fact that the interrupt processing to the first CPU 10 is only the first physical layer device 30 means that there is no interrupt processing from the second physical layer device 32 to the first CPU 10, and the interrupt processing from other than the second physical layer device 32 to the first CPU 10 is performed. It does not mean that interrupt processing is limited to that from the first physical layer device 30.
  • interrupt processing to the second CPU 20 is performed only by the second physical layer device 32, but when the interrupt bus switching unit 42 receives the selection signal "0" (first signal), the second data bus is connected. Since it has not been processed, it notifies that there is no interrupt processing. On the other hand, when the interrupt bus switching unit 42 receives the selection signal "1" (second signal), it notifies that there is interrupt processing because the second data bus is connected. Of course, if there is no interrupt processing, it is possible not to notify.
  • the interrupt bus switch 405 illustrates the configurations of FIGS. 6 and 7, FIG. 7 is a different configuration example of the interrupt bus switching unit 42, and the interrupt bus switching unit 42 is configured as shown in FIG. May be good.
  • FIG. 6 the one in which the logical sum of the interrupt buses from the plurality of PHYs (first PHY30, second PHY32) is taken is switched, but in FIG. 7, the logical sum of the switched signals is taken and the CPU (first CPU, second CPU) is switched. Output to.
  • the interrupt bus 8 changes the connection state of the cable connected to the LAN connector (first LAN connector 31, second LAN connector 33) from the PHY (first PHY 30, second PHY 32) to the CPU (first CPU 10, second CPU 20). Is used to notify and request the execution of interrupt processing accordingly. For example, when the CPUs (first CPU10, second CPU20) are notified that the cable is connected, the CPUs (first CPU10, second CPU20) set themselves so that communication can be started. When the selection signal is set to "0" in FIG. 3, since both interrupts of the first PHY30 and the second PHY32 are notified to the first CPU10, the interrupt signal is not a switch but an interrupt bus from the first PHY30 and an interrupt bus from the second PHY32. Use logical sum.
  • interrupt processing includes not only irregular ones but also those executed in a predetermined cycle. That is, the interrupt processing of the present application may be read as polling processing.
  • the polling process may simply be called polling. Therefore, the interrupt bus 8, the CPU side interrupt port 38, the physical layer side interrupt bus 39, and the interrupt bus switch 45 are the polling bus 8, the CPU side polling port 38, the physical layer side polling bus 39, and the polling bus switch 45, respectively. Can be read as.
  • the communication switching method according to the first embodiment is an operation (processing step) of the switching unit 4 of the information processing apparatus according to the first embodiment, or the switching unit 4 and the switching control unit 9 (which may include the first CPU 10). It is a method related to. Therefore, the communication switching method according to the first embodiment is described by the switching unit 4 of the information processing apparatus according to the first embodiment, or the switching unit 4 and the switching control unit 9 (which may include the first CPU 10). May be omitted in the second embodiment. Further, the contents described in the information processing apparatus according to the first embodiment can be applied to the communication switching method according to the first embodiment.
  • the processing step shown in the flowchart of FIG. 8 is a data bus switching step (STEP 11), a control bus switching step (STEP 12), and an interrupt bus switching step (STEP 13), which are basic processing steps of the communication switching method according to the first embodiment. ) Is shown.
  • the communication switching method according to the first embodiment is characterized in that the data bus switching step, the control bus switching step, and the interrupt bus switching step are performed by the same trigger.
  • the processing step of this trigger is shown in FIG. 8 as STEP1.
  • the trigger referred to here is information on whether to connect the second data bus 6 to the second physical layer device 32 to either the second LAN controller 12 or the third LAN controller 21 (second LAN controller 12 and third LAN). (Switching information of the controller 21). The acquisition or determination of this switching information is a trigger.
  • the communication switching method according to the first embodiment may include the mounting confirmation step (STEP0) and the switching control step (STEP1).
  • the mounting confirmation step and the switching control step will be described after the description of the basic processing steps shown in FIG.
  • the switching control step (STEP1) has the same STEP1 processing step name because it is an example of the trigger processing step shown in FIG.
  • the data bus switching step is a processing step in which the data bus switching unit 40 switches the connection destination (FIG. 3) with the second PHY 32 by the second data bus 6 to either the second MAC 12 or the third MAC 21.
  • the control bus switching unit 41 accesses the second PHY 32 by either the first MAC 11 or the third MAC 21 according to the connection destination (FIG. 3) by the second data bus 6 of the second PHY 32.
  • This is a processing step for switching 7.
  • the interrupt bus switching unit 42 switches the interrupt bus 8 according to the connection destination (FIG.
  • the switching control step will be described as an example for executing the data bus switching step, the control bus switching step, and the interrupt bus switching step with the same trigger. Since the switching control step corresponds to the processing step in the previous stage of STEP11, STEP12, and STEP13, it can be said to be STEP1. That is, the switching control step is a first signal and a second signal that are triggers for determining the connection destination in the data bus switching step at a timing prior to the execution of the data bus switching step, the control bus switching step, and the interrupt bus switching step. (Selection signal) is generated by the switching control unit 9.
  • the switching control unit 9 generates a second signal, which is an instruction to perform.
  • the first CPU 10 further includes a mounting confirmation step (STEP0) for confirming whether or not the second CPU board 2 is mounted at a timing prior to the execution of the switching control step (STEP1). You may be. Since the mounting confirmation step is a processing step prior to the switching control step and is a processing step before switching, it can be said to be STEP 0. In order to confirm whether or not the second CPU board 2 is mounted in the mounting confirmation step, in the switching control step, if it is confirmed in the mounting confirmation step that the second CPU board 2 is not mounted, the first signal (selection signal "0"" is used. ) Only needs to be generated. On the other hand, when it is confirmed in the mounting confirmation step that the second CPU board 2 is mounted, the switching control step performs the first signal (selection signal "0") or the second signal (selection signal "1") as necessary. ”) May be generated.
  • FIG. 9 is an example of a CPU board 110 (CPU board 101, CPU board 102) which is a signal processing device to which the information processing device (communication switching method) according to the first embodiment is applied.
  • the CPU board 101 is the CPU board 100 itself.
  • the CPU board 102 corresponds to a CPU board 101 (CPU board 100) on which the second CPU board 2 is not mounted (non-mounted).
  • the switching hub 103 connects the CPU board 101 and the CPU board 102 so that they can communicate with each other, and relays communication.
  • the switching hub 103 is connected to the first LAN connector 31 of the CPU board 101, the second LAN connector 33 of the CPU board 101, and the second LAN connector 33 of the CPU board 102, respectively.
  • the first LAN connector 31 of the CPU board 102 is connected to the host device.
  • FIG. 9 shows an example of the information processing device 110, which includes a device control CPU board 102 on which one CPU board (first CPU board 1) is mounted, and a CPU board (first CPU board 1, first CPU board 1, first). It is composed of two types of information processing devices 110 of a signal processing CPU board 101 on which two 2 CPU boards 2) are mounted.
  • the device control CPU board 102 one CPU (first CPU 10) performs two LAN communications, one is communication with the host device and the other is communication with the signal processing CPU board 101.
  • the signal processing CPU board 101 performs signal processing by two CPUs (first CPU 10, second CPU 20), and the processing result is transmitted from each CPU board (first CPU board 1, second CPU board 2) via LAN communication via a switching hub 103. , Transmit to the device control CPU board 102.
  • the circuit constituting the switching unit 4 is an FPGA (Field-Programmable Gate Array) used to realize other functions on the board except for the buffer 401 used for the data bus (first data bus 5 and second data bus 6). ), Etc., can be implemented with a small number of additional components.
  • the buffer 401 used for the data bus (first data bus 5, second data bus 6) may also be a general IC (Integrated Circuit) compatible with high-speed serial transmission.
  • the carrier having a switching unit that simultaneously switches the three buses required for communication between the MAC (LAN controller) and the PHY (physical layer device).
  • the optimum LAN communication port configuration according to the CPU board is realized. This eliminates the need to prepare two types of carrier boards having different connections between the MAC (LAN controller) and the PHY (physical layer device) depending on the purpose, so that the cost of the device can be reduced.
  • the information processing device and the communication switching method according to the first embodiment relate to switching the connection between the MAC and the PHY according to the purpose, and simultaneously switch the three types of buses between the MAC and the PHY. Is also easy.
  • 1 1st CPU board 10 1st CPU, 11 1st LAN controller (1st MAC), 12 2nd LAN controller (2nd MAC), 2 2nd CPU board, 20 2nd CPU, 21 3rd LAN controller (3rd MAC), 22 4th LAN controller (4th MAC), 3 carrier board, 30 1st physical layer device (1st PHY), 31 1st LAN connector, 32 2nd physical layer device (2nd PHY), 33 2nd LAN connector, 34 CPU side data port, 35 physical layer side data bus, 36 CPU side control port, 37 Physical layer side control bus, 38 CPU side interrupt port, 39 Physical layer side interrupt bus, 4 Switching part, 40 data bus switching unit, 41 control bus switching unit, 42 interrupt bus switching unit, 400 data bus switch, 401 buffer, 402 Control bus switch (bus switch), 403 Control bus switch (bus switch), 404 Control bus switch (bus switch), 405 Interrupt bus switch, 5 1st data bus, 6 2nd data bus, 7 control bus, 8 interrupt bus, 9 Switching control unit, 100 CPU board, 101 CPU board,

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Television Receiver Circuits (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Communication Control (AREA)
  • Small-Scale Networks (AREA)

Abstract

La présente invention porte sur un dispositif de traitement d'informations qui est caractérisé en ce que : une destination de connexion avec une seconde couche physique (PHY) (32) au moyen d'un second bus de données (6) est commutée entre un deuxième MAC (12) et un troisième MAC (21) ; un bus de commande (7) est commuté selon la destination de connexion de la seconde PHY (32) au moyen du second bus de données (6), de telle sorte que soit un premier MAC (11), soit le troisième MAC (21) accède à la seconde PHY (32) ; un bus d'interruption (8) est commuté selon la destination de connexion de la seconde PHY (32) au moyen du second bus de données (6) ; une première CPU (10) est notifiée quant à savoir si un processus d'interruption à la première CPU (10) doit être envoyé depuis une première PHY (30) et la seconde PHY (32), ou uniquement depuis la première PHY (30).
PCT/JP2020/037125 2019-10-02 2020-09-30 Dispositif de traitement d'informations et procédé de commutation de communication WO2021066001A1 (fr)

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JP2021551368A JP7052929B2 (ja) 2019-10-02 2020-09-30 情報処理装置及び通信切替方法
PH1/2022/550550A PH12022550550A1 (en) 2019-10-02 2020-09-30 Information processing device, and communication switching method

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JP2019-181850 2019-10-02

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011086990A (ja) * 2009-10-13 2011-04-28 Fuji Xerox Co Ltd 情報処理装置及び画像形成装置
JP2013503385A (ja) * 2009-08-28 2013-01-31 アドヴァンスド グリーン コンピューティング マシーンズ ‐ アイピー リミテッド 統合された共有リソースを有する高密度マルチノードコンピュータ

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013503385A (ja) * 2009-08-28 2013-01-31 アドヴァンスド グリーン コンピューティング マシーンズ ‐ アイピー リミテッド 統合された共有リソースを有する高密度マルチノードコンピュータ
JP2011086990A (ja) * 2009-10-13 2011-04-28 Fuji Xerox Co Ltd 情報処理装置及び画像形成装置

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JPWO2021066001A1 (fr) 2021-04-08
JP7052929B2 (ja) 2022-04-12

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