WO2020013665A1 - Quantum computer - Google Patents

Abstract

The present technology calculates probabilities of the states of 0 and 1 of each qubit and minimum information for the probabilities only and stores same in each qubit, rather than storing "quantum state vectors" consisting of information on qubits which are the basis of a quantum computer. Also, the present technology reads the probabilities of each qubit if necessary. The present technology provides the advantages of implementing a quantum computer with a small memory capacity in comparison with conventional technologies, foreseeing the relation between probabilities of each qubit and an input of a quantum circuit from an output, and thus quickly knowing outputs of the quantum computer.

Description

Quantum computer

The technology relates to quantum computer implementations.

When implementing a quantum computer with conventional software or a semiconductor CMOS circuit, it is necessary to store state vectors, thus using excessive memory. For example, in the case of 64 qubits, the total number of states to be stored is 264. That is, as the number of qubits increases, the amount of memory required increases exponentially as the number of states to be stored increases exponentially.

The present technology is to solve the difficulty of the quantum computer according to the prior art, and the present technology solves the difficulty of the quantum computer according to the prior art, which requires a large memory capacity, and uses a phase locked loop and / or a delay locked loop. Providing is one of the main goals.

This technology calculates and tracks the probabilities of any one of the states 1 and 0 of the qubits instead of storing the "quantum state vector" consisting of the information of the qubits that form the basis of the quantum computer. Save it. Also read the probabilities by qubit if necessary.

According to the present technology, it is possible to implement a quantum computer with a smaller memory capacity than the prior art. According to one aspect of the present technology, an output is provided in which a relationship between a probability of each qubit and an input of a quantum circuit is known in advance, so that an output of a quantum computer can be quickly known.

1 is a diagram for explaining a qubit.

2 shows an example of applying 2 qubits to superdense coding.

3 is a schematic diagram of a Hadamard gate for explaining the present embodiment.

4 is a schematic diagram of a CNOT gate for explaining the present embodiment.

5 is a diagram showing an outline of Embodiment 3. FIG.

Example  One

In this embodiment, instead of storing a "quantum state vector" consisting of qubit (quantum bit) information that forms the basis of a quantum computer, each qubit stores the probability of any one of states 1 and 0. do. In one embodiment, each qubit may further store connection relationship information for calculating a probability. It also reads probabilities for each qubit as output.

For example, the qubit may be represented by a circle having a radius of 1 between a real axis and an imaginary axis, as illustrated in FIG. 1A, and may theoretically display infinite information. The square of the abscissa component x and the square of the ordinate component y represent the probabilities, respectively, and the sum of x2 and y2 is one. FIG. 1 (b) shows the qubit of the 0 state, and FIG. 1 (c) shows the qubit of the 1 state.

The quantum computer according to the present embodiment calculates and traces a zero state probability or a one state probability to perform a desired operation. As described above, since the sum of the zero state probability and the one state probability of the qubit is 1, the probability of the other state can be known by tracking only one state probability.

If one phase passes the gate for quantum operation, the probability of each qubit component is calculated and stored for each phase. Referring to FIG. 2, the present technology tracks and stores only probabilities of the zero states of q # 1 and q # 2 in each phase. In this embodiment, since it is not necessary to store all the quantum states for output, information to be stored for each qubit can be reduced.

That is, when storing quantum state vectors according to the prior art, the number of memories required is 2N. In other words, if 64 qubits, a memory capable of storing 264 states is required. However, according to the present technology, nN memory is sufficient. For example, if N = 64 and n is information for tracking one qubit probability, 64 n of memory is sufficient. In one embodiment, the information for tracking one qubit probability may include connection information by a gate or the like in a previous phase.

2 illustrates an example in which two qubits q # 1 and q # 2 are applied to superdense coding. Referring to FIG. 2, a1 and b1 are components of qubit # 1 (q # 1), and a2 and b2 are components of qubit # 2 (q # 2). After the phase 0 (p-0), the information of each qubit is shown in Equation 1 below. In qubit # 1, the values of a, b (in the states 1 and 0) change to a 'and b' as they pass through the Hadamard gate. Since it is before entering quantum entanglement (CNOT), qubit # 2 remains unchanged. Therefore, only the a and b values of each qubit may be stored.

In this embodiment, as described above, one of the zero state probability and the one state probability of the qubit is tracked and stored for each phase.

3A is a schematic diagram of the Hadamard gate H for explaining the present embodiment, and Equations 2 and 3 below are equations for explaining the Hadamard gate H. FIG. When a cubit having (cosθ _i and sinθ _i ) is provided as an input to the Hadamard gate, the output of the Hadamard gate is expressed by Equation 2 below.

In this case, the a _i component may be expressed as in Equation 3 below.

That is, the Hadamard gate may be represented by a 45 degree shift of the qubit zero component. For example, if a zero state input is input to the Hadamard gate H, the zero state probability value output is 1/2.

FIG. 3B is a schematic diagram of an X gate for explaining the present embodiment, and Equation 4 below is an expression representing an input / output relationship between the X gates.

Referring to Equation 4, the X gate is a gate that exchanges components of the input. Given the (a, b) input to the X gate, the zero state probability of the X gate output is b ² .

FIG. 3C is a schematic diagram of an R gate for explaining the present embodiment, and Equation 5 below is an equation representing an input / output relationship between R gates.

In one embodiment, the qubit may store the θ value of the R gate.

The embodiment illustrated by FIG. 2 includes a CNOT gate. When the cubit # 2 of (a2, b2) is CNOT calculated with the cubit # 1 of (a1, b1) by the illustrated CNOT gate, the output of the CNOT gate is expressed by Equation 6 below.

Accordingly, the zero state probability of qubit # 1 is a ₁ ² , and the zero state probability of qubit # 2 is a ₁ ² a ₂ ² + b ₁ ² b ₂ ² . For example, if the cubit # 2 of the zero component input is CNOT calculated by the qubit # 1 of the zero component input, the probability value of the zero component to be output is 1 ² * 1 ² +0 = 1.

Table 1 is a table showing a zero state probability stored in each qubit after each phase indicated in the embodiment of FIG. 2.

p-0 p-1 p-2 p-3 p-4 q # 1 a ₁ ` <sup>2</sup> a <sub>1</sub> ` ² b ₁ ` <sup>2</sup> b <sub>1</sub> ` ² (a ₁ ` + b <sub>1</sub> `) ² q # 2 a ₂ ` <sup>2 <sub>a 1 `2 a 2` 2</sub></sup> + b <sub>1 <sup>`2</sup></sub> b ^{2` 2 <sub>a 1 `2 a 2` 2</sub></sup> + b <sub>1 <sup>`2}</sub> b ^{2` 2} b ₂ ² b ₂ ²

As can be seen from the table above, the present embodiment tracks and stores only one component (eg, 0 state) probability of qubit # 1 and qubit # 2 for each phase. By this method, it is possible to minimize the information to be stored for each qubit, and the output probability can be obtained from this.

Table 2 below illustrates the probability of a zero state component that each qubit should store when a zero state input is provided to qubit # 1 and a zero state input to qubit # 2 in the embodiment illustrated in FIG. 2.

0 One 2 3 4 q # 1 | 0> 1/2 1/2 1/2 1/2 One | 0> q # 2 | 0> One 1 / 2Х1 + 1 / 2Х0 = 1/2 1/2 0 0 | 0>

이며, 0 상태 확률은 1/2이다. 페이즈 0에서 큐빗 #2의 성분은 입력과 동일하게 (1,0)이므로, 0 상태 확률은 1이다. Referring to Table 2, in the case where 0 state input (| 0>) is provided to both qubit # 1 and qubit # 2, at phase 0 (p-0), the Hadamard gate (H) returns the input component. Also, since the component of qubit # 1 output by the Hadamard gate H is

The zero state probability is 1/2. At phase 0, the component of qubit # 2 is (1,0) equal to the input, so the zero state probability is one.

이며, 0 상태 확률은 1/2이다. 그러나, 큐빗 #2는 큐빗 #1에 의하여 CNOT 연산이 수행되므로, 0상태 확률은

이다. In phase 1 (p-1), qubit # 1 is not affected by the CNOT gate. Therefore, the component of qubit # 1 is

The zero state probability is 1/2. However, since cubit # 2 performs a CNOT operation by qubit # 1, the zero state probability is

to be.

이며, 큐빗 #2의 성분은 변화하지 않는다. 따라서, 페이즈 2(p-2)에서의 큐빗 #1의 0 상태 확률 및 큐빗 #2의 0 상태 확률은 모두 1/2이다.In phase 2 (p-2), the X gate swaps the zero state component and one state component of qubit # 1, so in phase 2 the component of qubit # 1 is

The component of qubit # 2 does not change. Therefore, the zero state probability of qubit # 1 and the zero state probability of qubit # 2 in phase 2 (p-2) are both 1/2.

이다. 큐빗 #2은 큐빗 #1에 의하여 CNOT 연산이 이루어지며, 0 상태 확률은

이다.In phase 3 (p-3), qubit # 1 is not affected by the CNOT gate, so the component of qubit # 1 is

to be. Qubit # 2 is a CNOT operation by qubit # 1, and the 0 state probability

to be.

In phase 4 (p-4), qubit # 1 is rotated 45 degrees by the Hadamard (H) gate. As a result, the zero state probability of qubit # 1 is 1 or 1 because the component of qubit # 1 is (1,0). , The zero state probability of qubit # 2 is zero.

As illustrated in Tables 1 and 2, the quantum computer according to the present embodiment can obtain and output the zero state probability or the one state probability for each phase of the qubits even without using a quantum state vector.

Example  2

This embodiment uses a phase locked loop (PLL) and a delay locked loop (DLL) as a method of calculating or storing the probability of each qubit. For example, the zero component of each qubit is cosθ _i (i: cubit number). This can reduce computation time rather than software operation.

4 is a schematic diagram of a CNOT (control NOT) gate for explaining the present embodiment, and Equation 5 shows a probability of the a (α in the figure) component of the j bit controlled by the i-th qubit.

Therefore, the probability of the a (Fig. 3 (b) α) component of the j bit controlled by the i th qubit may be expressed as twice the θ component, and may be implemented by an electronic circuit such as a phase locked loop or a delay locked loop. Can be.

Example  3

5 is a diagram showing an outline of Embodiment 3. FIG. Referring to FIG. 5, Example 3 includes three qubits, and performs CNOT operation on phase 1 with cubit # 2 and CNOT operation on phase 2 with qubit # 1. In this embodiment, each qubit may further store a connection relationship by a CNOT gate for each phase.

The zero state probability of qubit # 1 is a ₁ ^{2 since it} is not affected by the CNOT operation of phase 2. In addition, since the CNOT operation is performed by the qubit # 2 by the qubit # 2, the zero state probability of the qubit # ² is calculated as a ₁ ² a ₂ ² + b ₁ ² b ₂ ² . In addition, since the CNOT operation is performed by the qubit # 3, the zero state probability of the qubit # 3 is calculated as a ₂ ² a ₃ ² + b ₂ ² b ₃ ² .

According to the prior art, two or ^three state changes for ^three qubits should be tracked, but according to the present embodiment, the zero state probability of each qubit is traced to obtain an output simply and easily.

In the quantum computer described above, a plurality of inputs I ₁ (a ₁ , b ₁ ), I ₂ (a ₂ , b ₂ ), ..., I _N (a _N , b _N ) result in a plurality of probability values O ₁ , O ₂ , ..., O _K Output The quantum computer according to the present embodiment may display the output probability of each desired qubit as a function of the value of the input qubit, and the relation at this time is expressed by the following equation. In the following equation, O represents the probability of having zero of each qubit.

Provide new inputs to the quantum computer as needed, rather than calculating all of the quantum states required by a lot of memory, input new variables into the function (F), and perform calculations to obtain the desired probability of each qubit as the output. Can be. Therefore, the operation of the quantum computer can be made faster.

Furthermore, the conventional quantum computer using the quantum spin and the like can acquire the output value and at the same time the output value is destroyed to ensure the safety of the information. Similarly, the quantum computer according to the present embodiment can provide an output and at the same time, erase the output value, the buffer, and the operation result stored in the memory to maintain information safety.

In one embodiment, the quantum computer according to the present technology may be implemented in software or a semiconductor CMOS circuit.

Listed above.

Claims (14)

With quantum computer, The quantum computer A quantum computer that tracks and stores any one of the probabilities of 1 and 0 states of a qubit to calculate and output a probability value. The method of claim 1, The quantum computer includes a plurality of phases, A quantum computer in which a qubit stores one of the probabilities of states 1 and 0 for each phase. The method of claim 2, And a quantum computer in which the connection relationship of the CNOT gate is further stored in the qubit. The method of claim 1, The quantum computer comprises a Hadamard gate, If a qubit of 0 state is provided to the input of the Hadamard gate, Wherein said Hadamard gate provides a one-half zero state probability as an output. The method of claim 1, The quantum computer includes a controlled NOT gate, When the CNOT operation is performed on the second qubit of the component (a2, b2) with the first qubit of the component (a1, b1), And the CNOT gate outputs a ₁ ² a ₂ ² + b ₁ ² b ₂ ² with a 0 state probability. The method of claim 1, Includes an X gate, The X gate is the equation

A quantum computer having an input-output relationship defined by. (X: characteristic matrix of the X gate,

: input) The method of claim 6, Given the (a, b) input to the X gate, A quantum computer where the zero state probability of the X gate output is b ² . The method of claim 1, Including an R gate, The R gate is

A quantum computer having an input-output relationship defined by. (R: characteristic matrix of R gate,

: input) The method of claim 8, If the (a, b) input is given to the R gate, A quantum computer where the zero state probability of the R gate output is a ² . The method of claim 9, The qubit also stores the [theta] value. The method of claim 1, The quantum computer is represented by a function that computes a first output for a first input, The quantum computer is configured to compute the second output by providing the second input to the function during a second output operation on a second input. The method of claim 1, The quantum computer Memory, A quantum computer for deleting information stored in the memory after outputting the probability value. The method of claim 1, The quantum computer, A quantum computer that further stores the connection state by the CNOT gate. The method of claim 1, The quantum computer is implemented by software or semiconductor CMOS circuit.

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