+

WO2019113844A1 - Procédé de génération de nombre aléatoire, puce et dispositif électronique - Google Patents

Procédé de génération de nombre aléatoire, puce et dispositif électronique Download PDF

Info

Publication number
WO2019113844A1
WO2019113844A1 PCT/CN2017/115956 CN2017115956W WO2019113844A1 WO 2019113844 A1 WO2019113844 A1 WO 2019113844A1 CN 2017115956 W CN2017115956 W CN 2017115956W WO 2019113844 A1 WO2019113844 A1 WO 2019113844A1
Authority
WO
WIPO (PCT)
Prior art keywords
random number
chip
seed
kth
generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/115956
Other languages
English (en)
Chinese (zh)
Inventor
严可
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Goodix Technology Co Ltd
Original Assignee
Shenzhen Goodix Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Goodix Technology Co Ltd filed Critical Shenzhen Goodix Technology Co Ltd
Priority to PCT/CN2017/115956 priority Critical patent/WO2019113844A1/fr
Priority to CN201780002236.0A priority patent/CN110249299A/zh
Publication of WO2019113844A1 publication Critical patent/WO2019113844A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators

Definitions

  • the present invention relates to the field of information technology, and more particularly to a method, a chip and an electronic device for generating a random number by a chip.
  • Random numbers have a wide range of applications in radar systems, secure communication systems, and simulations.
  • Random numbers are an important part of the cryptosystem and are the cornerstone of many applications such as private key generation, signature, key negotiation, and challenge authentication.
  • Microsoft's research on cryptosystems such as Bitcoin, Secure Shell (SSH), Transport Layer Security (TLS) and Australian electronic ID cards
  • random number generation is a weak link in the above applications. Breaking the random number means breaking the entire cryptosystem. Therefore, the quality of random number generation directly determines the security of the cryptosystem.
  • Embedded security encryption chips are limited by size, power consumption and computing resources, and cannot implement complex physical or chemical entropy sources.
  • the signal noise of integrated circuits is used to generate physical random numbers, such as direct amplifiers, oscillatory samples, and discrete chaotic systems.
  • the security of the physical random number generated by the above method is affected by the working state of the component, the circuit and the environment, and the security of the generated physical random number is difficult to meet the requirements of the cryptographic system application.
  • the present application provides a method, a chip and an electronic device for generating a random number, which can improve the random number quality of the chip.
  • a method of generating a random number comprising:
  • the entropy source including physical random numbers and chip information
  • a random number is generated based on the random number seed and the encryption algorithm of the chip.
  • the technical solution of the embodiment of the present invention uses a physical random number as an entropy source, generates a random number seed by using chip information, and generates a random number based on a chip encryption algorithm, which can improve the random number quality of the chip without adding an additional circuit. Thereby, the efficiency of generating a random number can be improved.
  • generating a random number includes:
  • a random number is generated based on the random number seed, the historical random number information, and the encryption algorithm.
  • the encryption algorithm is a secure hash algorithm SHA or an advanced encryption standard AES.
  • the encryption algorithm value r k when the kth generation random number is generated according to the following equation is obtained,
  • SHA256() represents the SHA function
  • represents splicing
  • r k-1 represents the encryption algorithm value when the k-1th generation random number is generated
  • seed k represents the random number seed when the kth generation random number is generated
  • the kth random number is generated according to r k .
  • the encryption algorithm value r k when the kth generation random number is generated according to the following equation is obtained,
  • AES key () represents the AES function
  • represents splicing
  • r k-1 represents the encryption algorithm value when the k-1th generation random number is generated
  • seed k represents the random number seed when the kth generation random number is generated
  • the kth random number is generated according to r k .
  • the kth random number s k is generated according to the following equation,
  • the information of the chip includes at least one of an identifier ID, a name, and a description.
  • the random number seed seed k when the kth generation of the random number is generated according to the following equation is generated,
  • b i represents the i-th block divided by a predetermined number of bytes
  • N represents the total number of blocks
  • represents splicing
  • ID represents splicing
  • ID represents the ID, name and description of the chip.
  • p k represents the physical random number when the random number is generated for the kth time.
  • a chip comprising:
  • An entropy source acquiring unit configured to acquire an entropy source, where the entropy source includes physical random numbers and chip information;
  • a random number seed generating unit configured to generate a random number seed according to the entropy source
  • a processing unit configured to generate a random number according to an encryption algorithm of the random number seed and the chip.
  • the technical solution of the embodiment of the present invention uses a physical random number as an entropy source, generates a random number seed by using chip information, and generates a random number based on a chip encryption algorithm, which can improve the random number quality of the chip without adding an additional circuit. Thereby, the efficiency of generating a random number can be improved.
  • the processing unit is specifically configured to generate a random number according to the random number seed, the historical random number information, and the encryption algorithm.
  • the encryption algorithm is a secure hash algorithm SHA or an advanced encryption standard AES.
  • the processing unit is specifically configured to: obtain an encryption algorithm value r k when the kth generation random number is generated according to the following equation,
  • SHA256() represents the SHA function
  • represents splicing
  • r k-1 represents the encryption algorithm value when the k-1th generation of the random number is generated
  • seed k represents the random number seed when the kth generation of the random number is generated
  • the kth random number is generated based on the r k .
  • the processing unit is specifically configured to: obtain an encryption algorithm value r k when the kth generation random number is generated according to the following equation,
  • AES key () represents an AES function
  • represents splicing
  • r k-1 represents an encryption algorithm value when k-1th generation of a random number
  • seed k represents a random number seed when a k-th generation of a random number is generated; The kth random number is generated according to r k .
  • the processing unit is specifically configured to: generate a kth random number s k according to the following equation,
  • the information of the chip includes at least one of an identifier ID, a name, and a description.
  • the random number seed generating unit is specifically configured to: generate a random number seed seed k when generating the random number for the kth time according to the following equation,
  • b i represents the i-th block divided by a predetermined number of bytes
  • N represents the total number of blocks
  • represents splicing
  • ID, Name ID and Description ID respectively represent the ID, name and description of the chip.
  • the exclusive OR is expressed, and p k represents the physical random number when the random number is generated for the kth time.
  • a chip including a memory and a processor, is provided that can perform the method of the first aspect described above or any possible implementation thereof.
  • an electronic device comprising the chip in the second aspect or any possible implementation thereof, or the chip of the third aspect.
  • a computer storage medium having stored therein program code, the program code being operative to indicate a method of performing the first aspect described above or any possible implementation thereof.
  • a computer program product comprising instructions, when executed on a computer, causes the computer to perform the method of the first aspect described above or any of its possible implementations.
  • FIG. 1 is a schematic diagram of an application scenario of a technical solution according to an embodiment of the present invention.
  • FIG. 2 is a schematic flow chart of a method for generating a random number according to an embodiment of the present invention.
  • FIG. 3 is a schematic flowchart of a method for generating a random number according to still another embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a chip according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural view of a chip according to still another embodiment of the present invention.
  • the quality of the random number generation directly determines the security of the cryptosystem. Subsequent processing of physical random numbers is an important means to guarantee the quality of random numbers. Algorithm selection needs to have the characteristics of forward unpredictability, backward unpredictability, independent and identical distribution.
  • the embedded security encryption chip usually has encryption, hash and other arithmetic modules with the above characteristics.
  • the physical random number is used as the entropy source, supplemented by the information of the embedded security encryption chip (such as ID, device name, etc.), based on the basic computing functions provided by the existing module of the embedded security encryption chip.
  • the existing modules are used to generate random numbers.
  • the generated random numbers have the characteristics of forward unpredictability, backward unpredictability, independent and identical distribution, which can improve the random number quality of the embedded security encryption chip.
  • the technical solution of the embodiment of the present invention does not need to add additional circuits, so that fast, efficient, low-cost, high-quality random number generation can be realized.
  • FIG. 1 is a schematic diagram of an application scenario of a technical solution according to an embodiment of the present invention.
  • the electronic device 100 in FIG. 1 may be an electronic device that uses an embedded secure encryption chip.
  • the electronic device 100 may include other modules or units in addition to the embedded security encryption chip 120, which is not specifically limited in the present invention.
  • the embedded secure encryption chip 120 can process the input data 110 to obtain output data 130.
  • the embedded secure encryption chip 120 can encrypt the input data 110 through its internal cryptographic module.
  • the embedded security encryption chip 120 may also apply the technical solution of the embodiment of the present invention to generate a random number.
  • FIG. 2 shows a schematic flow diagram of a method 200 of generating a random number in accordance with an embodiment of the present invention.
  • the method can be performed by the electronic device 100 or the embedded secure encryption chip 120 of FIG.
  • An entropy source is obtained in S210, in which a physical random number is utilized, supplemented by information of the chip.
  • the physical random number (circuit noise collected by the physical device) is implemented by using an oscillation sampling method.
  • the jitter of a typical clock is about one thousandth of a clock cycle, so a low-frequency clock is used to sample an independent clock source with a frequency of more than 1000 times to generate a physical random number.
  • a low frequency 32K clock may be used to sample the high frequency 48M clock in S210, and there is a probability of sampling to a high level or a low level of the high frequency clock to generate 1 bit. 1 or 0 of (bit), by splicing, the generated physical random number is 32 bits.
  • the generation of the random number is 32 bits as an example and is not limited.
  • each time a random number is generated the physical random number is updated. Therefore, as the number of random number generation increases, the randomness of the physical random number input in the system entropy source is stronger.
  • the information of the chip may include at least one of an ID, a name, and a description of the chip, which is not limited by the embodiment of the present invention.
  • the random number seed is a random number with the random number (seed) as the initial condition with the random number as the object, by using a true random number (seed) as the initial condition, and then using a certain algorithm to generate the random number.
  • General computer random numbers are pseudo-random numbers. Real random numbers are generated by physical processes rather than computer programs to generate random numbers, for example, based on microscopic phenomena that generate low-level, statistically random "noise" signals, such as thermodynamic noise. , photoelectric effect and quantum phenomenon. These physical processes are theoretically completely unpredictable and have been confirmed by experiments. Random hardware
  • the number generator is usually composed of a transducer, an amplifier, and an analog to digital converter.
  • the transducer is used to convert some effects of the physical process into electrical signals
  • the amplifier and its circuitry are used to amplify the amplitude of the random disturbance to the macro level
  • the analog to digital converter is used to convert the output into a digital, usually Binary zero and one.
  • information of the chip is first spliced and segmented by a predetermined number of bytes.
  • the information of the chip includes related information such as the ID, name and description of the chip.
  • a block of 4 bytes is taken as an example:
  • the random number seed seed k when generating the random number for the kth time is:
  • b i denotes the i-th block divided by 4 bytes
  • N denotes the total number of blocks
  • denotes splicing
  • p k represents the physical random number when the random number is generated for the kth time.
  • the final output random number seed is a random number seed after the physical random number and the chip information are spliced.
  • the 4 byte block mentioned in this embodiment is only a specific embodiment, specifically, the block is divided according to a preset byte, and the preset byte is not specifically limited in the present invention.
  • the finally output random number seed is an exclusive OR of the information of the chip spliced by the preset byte and the physical random number when the kth generation of the random number is generated, and each time the random number is generated, The physical random number will be updated, so as the number of generations increases, the randomness of the system gradually increases.
  • the existing encryption algorithm of the chip is used to generate a random number, that is, an existing module in the multiplexing chip, so that no additional circuit is needed to implement other algorithms.
  • a random number may be generated according to the random number seed, the historical random number information, and the chip encryption algorithm.
  • the historical random number information is information when a random number was previously generated.
  • the historical random number information can be saved for subsequent generation of random numbers, thereby increasing the entropy of the newly generated random numbers.
  • One embodiment of the present invention may utilize one of the encryption algorithms.
  • the following is a Secure Hash Algorithm (SHA) and high
  • SHA Secure Hash Algorithm
  • AES Advanced Encryption Standard
  • the encryption algorithm value r k when the k-th generation random number is generated can be obtained according to the following equation.
  • SHA256() represents the SHA function
  • represents the splicing
  • r k-1 represents the encryption algorithm value when the k-1th generation of the random number is generated
  • seed k represents the random number seed when the k-th generation of the random number is generated.
  • r k-1 can be saved in the chip.
  • SHA256() is only one of the SHA functions, and is merely by way of example and not limitation in the embodiments of the present invention.
  • the output of the function SHA2-256 is 256 bits, that is, 8 blocks, each block is 4 bytes, so that the i-th block is r k,i , then
  • r k (r k,1 ,r k,2 ,r k,3 ,r k,4 ,r k,5 ,r k,6 ,r k,7 ,r k,8 ) (4)
  • the kth random number s k can be generated according to the following equation:
  • the technical solution of the embodiment of the present invention can significantly improve the quality of random number generation. Moreover, the technical solution of the embodiment of the present invention does not need to add a new hardware circuit, and generates a random number by using a module that is provided by the security encryption chip, which has high efficiency.
  • the encryption algorithm value r k at the kth generation of the random number can be obtained according to the following equation,
  • AES key () indicates the AES function
  • indicates splicing
  • r k-1 indicates the encryption algorithm value when the k-1th generation random number is generated
  • seed k indicates the random number seed when the k-th generation random number is generated.
  • each newly generated entropy source (newly acquired physical random number) is generated by each random number generation, and the information of the previous entropy source is saved by using the encryption module, so that the generated random number has backward unpredictability.
  • the physical random number is not directly output, and the attacker cannot design the attack algorithm by collecting physical random numbers.
  • the characteristics of the cryptographic module in the embodiment of the present invention ensure that even if the input physical random number does not have the independent and identical distribution property, the generated random number has the independent and identical distribution property. Therefore, the random number generated by the technical solution of the embodiment of the present invention has higher quality.
  • the basic algorithm based on the existing modules in the chip is used to multiplex the corresponding algorithm, and the random number is generated according to the random number seed and the corresponding algorithm, which can achieve fast, effective, and low cost. , the generation of high quality random numbers.
  • the technical solution of the embodiment of the present invention uses the physical random number as the entropy source, supplements the information of the chip to generate a random number seed, and generates a random number based on the chip encryption algorithm, thereby improving the chip.
  • the quality of the random number and the need to add additional circuitry can increase the efficiency of generating random numbers.
  • FIG. 3 is a schematic flowchart of a method 300 for generating a random number by a chip according to still another embodiment of the present invention.
  • FIG. 3 is a schematic flowchart of a method 300 for generating a random number by a chip according to still another embodiment of the present invention.
  • 310, 320 is a source of entropy for obtaining input.
  • S210 the related description of S210 in the foregoing embodiment.
  • the previous random number information can be used to generate a random number subsequently.
  • FIG. 4 is a schematic structural view of a chip 400 according to an embodiment of the present invention. As shown in FIG. 4, the chip 400 includes:
  • An entropy source acquiring unit 410 configured to acquire an entropy source; the entropy source includes information of a physical random number and a chip;
  • a random number seed generating unit 420 configured to generate a random number seed according to the entropy source
  • the processing unit 430 is configured to generate a random number according to an encryption algorithm of the random number seed and the chip.
  • a random number is generated by using a physical random number as an entropy source, supplemented by chip information (such as ID, device name, etc.), and a chip-based encryption algorithm. That is to say, the processing unit 430 multiplexes the existing modules in the chip, and utilizes the existing algorithm to realize fast, efficient, low-cost, high-quality random number generation without adding additional circuits.
  • the chip of the embodiment of the present invention uses the physical random number as the entropy source, supplements the chip information to generate a random number seed, and generates a random number based on the chip encryption algorithm, which can improve the random number quality of the chip without adding an additional circuit. , thereby improving the efficiency of generating random numbers.
  • the entropy source obtaining unit 410 is specifically configured to:
  • the entropy source including physical random numbers and chip information
  • the information of the chip includes at least one of an identification ID, a name, and a description.
  • the random number seed generating unit 420 is specifically configured to:
  • b i represents the i-th block divided by a predetermined number of bytes
  • N represents the total number of blocks
  • represents splicing
  • ID represents splicing
  • ID represents the ID, name and description of the chip.
  • p k represents the physical random number when the random number is generated for the kth time.
  • the processing unit 430 is specifically configured to:
  • a random number is generated according to the random number seed, the historical random number information, and the chip encryption algorithm.
  • the processing unit 430 may multiplex modules in the chip, and may determine an encryption algorithm according to the corresponding module.
  • the random hash function SHA may be used to process the random number seed and generate a random number of the encryption chip
  • the random number seed can be processed by the advanced encryption standard AES and a random number of the encryption chip is generated.
  • Processing unit 430 multiplexes existing modules in the chip without adding additional circuitry.
  • the hash module and the encryption module (AES module) in the embodiment of the present invention are not specifically limited.
  • the processing unit 430 may reuse other modules and utilize the algorithm provided by the module.
  • the processing unit 430 can multiplex the hash module.
  • the processing unit 430 is specifically configured to:
  • SHA256() represents the SHA function
  • represents splicing
  • r k-1 represents the encryption algorithm value when the k-1th generation random number is generated
  • seed k represents the random number seed when the kth generation random number is generated
  • the processing unit 430 can reuse the AES module.
  • the processing unit 430 is specifically configured to:
  • AES key () represents the AES function
  • represents splicing
  • r k-1 represents the encryption algorithm value when the k-1th generation random number is generated
  • seed k represents the random number seed when the kth generation random number is generated
  • FIG. 5 shows a schematic structural view of a chip 500 according to still another embodiment of the present invention.
  • the chip 500 can include a processor 510 and a memory 520.
  • the memory 520 is for storing computer executable instructions.
  • the processor 510 is configured to access the memory 520 and execute the computer executable instructions to perform the operations in the methods of the various embodiments of the present invention described above.
  • An embodiment of the present invention further provides an electronic device, which may include the chip of the various embodiments of the present invention described above.
  • the embedded security encryption chip in the embodiment of the present invention is only an example, and may also be other chips.
  • the encryption module may also be other operation modules, as long as the operation module has forward unpredictability and backward direction. Unpredictability, independent and identical distribution.
  • the size of the sequence numbers of the processes does not imply a sequence of executions, and the order of execution of the processes should be determined by its function and internal logic, and should not be construed as an embodiment of the present invention.
  • the implementation process constitutes any limitation.
  • the term "and/or” is merely an association describing the associated object, indicating that there may be three relationships.
  • a and/or B may indicate that A exists separately, and A and B exist simultaneously, and B cases exist alone.
  • the character "/" in this article generally indicates that the contextual object is an "or" relationship.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or an electrical, mechanical or other form of connection.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • the technical solution of the present invention contributes in essence or to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Storage Device Security (AREA)

Abstract

L'invention concerne un procédé de génération d'un nombre aléatoire, une puce et un dispositif électronique. Le procédé comprend : l'obtention d'une source d'entropie, la source d'entropie comprenant un nombre aléatoire physique et des informations d'une puce (S210) ; la génération d'un germe de nombre aléatoire en fonction de la source d'entropie (S220) ; et la génération d'un nombre aléatoire en fonction du germe de nombre aléatoire et d'un algorithme de chiffrement de la puce (S230). Le procédé peut améliorer la qualité d'un nombre aléatoire généré par une puce.
PCT/CN2017/115956 2017-12-13 2017-12-13 Procédé de génération de nombre aléatoire, puce et dispositif électronique Ceased WO2019113844A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2017/115956 WO2019113844A1 (fr) 2017-12-13 2017-12-13 Procédé de génération de nombre aléatoire, puce et dispositif électronique
CN201780002236.0A CN110249299A (zh) 2017-12-13 2017-12-13 生成随机数的方法、芯片和电子设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2017/115956 WO2019113844A1 (fr) 2017-12-13 2017-12-13 Procédé de génération de nombre aléatoire, puce et dispositif électronique

Publications (1)

Publication Number Publication Date
WO2019113844A1 true WO2019113844A1 (fr) 2019-06-20

Family

ID=66819814

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/115956 Ceased WO2019113844A1 (fr) 2017-12-13 2017-12-13 Procédé de génération de nombre aléatoire, puce et dispositif électronique

Country Status (2)

Country Link
CN (1) CN110249299A (fr)
WO (1) WO2019113844A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI806804B (zh) * 2021-12-23 2023-06-21 國立陽明交通大學 具有自單一ｐｕｆ電路來源所得多重硬體簽章之裝置及相關方法、系統與應用

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112115508B (zh) * 2020-09-07 2024-07-12 翰顺联电子科技(南京)有限公司 应用于区块链的乱数产生方法、装置及乱数产生器
CN113411268B (zh) * 2021-05-24 2022-08-12 深圳市元征未来汽车技术有限公司 一种数据传输方法、数据传输装置及电子设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020124033A1 (en) * 2001-03-01 2002-09-05 Takahashi Richard J. Pipelined digital randomizer based on permutation and substitution using data sampling with variable frequency and non-coherent clock sources
CN103782304A (zh) * 2011-07-27 2014-05-07 塞尔蒂卡姆公司 用于制造期间预配置密钥的方法
CN104660398A (zh) * 2015-01-28 2015-05-27 北京深思数盾科技有限公司 一种加密密钥的生成方法
US20150160925A1 (en) * 2013-12-06 2015-06-11 Sonic Ip, Inc. Methods, Systems, and Media for Generating Random Numbers
CN105027073A (zh) * 2013-03-12 2015-11-04 高通股份有限公司 中断驱动硬件随机数产生器
CN105912301A (zh) * 2015-02-24 2016-08-31 英飞凌科技股份有限公司 随机数生成器

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4868407B2 (ja) * 2007-03-30 2012-02-01 東芝情報システム株式会社 乱数生成システム、乱数生成方法及びコンピュータシステム
CN102279908B (zh) * 2010-06-08 2014-03-12 安凯(广州)微电子技术有限公司 一种数字内容的保护方法及系统
US8682948B2 (en) * 2011-01-06 2014-03-25 Microsoft Corporation Scalable random number generation
CN103366103B (zh) * 2013-06-13 2016-02-10 广东岭南通股份有限公司 读卡器的应用程序加密保护方法
CN104461452A (zh) * 2013-09-17 2015-03-25 航天信息股份有限公司 片上系统中生成真随机数的方法及装置
CN104579630A (zh) * 2013-10-25 2015-04-29 上海华力创通半导体有限公司 系统随机数生成方法
US9329836B2 (en) * 2014-04-17 2016-05-03 International Business Machines Corporation Extracting entropy from the vibration of multiple machines
JP6348019B2 (ja) * 2014-08-28 2018-06-27 ルネサスエレクトロニクス株式会社 通信システム、通信装置、自動車および通信方法
CN104317551A (zh) * 2014-10-17 2015-01-28 北京德加才科技有限公司 一种超高安全的真随机数生成方法及真随机数生成系统
CN104615407B (zh) * 2015-01-19 2017-10-10 中国科学院信息工程研究所 一种基于闪存产生满熵随机数的方法和装置
KR101837589B1 (ko) * 2016-02-05 2018-03-12 국민대학교산학협력단 컴퓨터 실행 가능한 난수 생성 방법 및 이를 수행하는 난수 생성 장치
CN106980488A (zh) * 2017-03-14 2017-07-25 腾讯科技（深圳）有限公司 随机数生成方法及装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020124033A1 (en) * 2001-03-01 2002-09-05 Takahashi Richard J. Pipelined digital randomizer based on permutation and substitution using data sampling with variable frequency and non-coherent clock sources
CN103782304A (zh) * 2011-07-27 2014-05-07 塞尔蒂卡姆公司 用于制造期间预配置密钥的方法
CN105027073A (zh) * 2013-03-12 2015-11-04 高通股份有限公司 中断驱动硬件随机数产生器
US20150160925A1 (en) * 2013-12-06 2015-06-11 Sonic Ip, Inc. Methods, Systems, and Media for Generating Random Numbers
CN104660398A (zh) * 2015-01-28 2015-05-27 北京深思数盾科技有限公司 一种加密密钥的生成方法
CN105912301A (zh) * 2015-02-24 2016-08-31 英飞凌科技股份有限公司 随机数生成器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI806804B (zh) * 2021-12-23 2023-06-21 國立陽明交通大學 具有自單一ｐｕｆ電路來源所得多重硬體簽章之裝置及相關方法、系統與應用

Also Published As

Publication number Publication date
CN110249299A (zh) 2019-09-17

Similar Documents

Publication Publication Date Title
JP6208586B2 (ja) 検索可能暗号処理システムおよび検索可能暗号処理方法
CN108604987B (zh) 将布尔掩码值转换为用于加密操作的算术掩码值
CN107004084B (zh) 用于加密操作的乘法掩码
US8681976B2 (en) System and method for device dependent and rate limited key generation
US10417442B2 (en) Server device, data search system, search method, and recording medium for extracting concealed data
Garipcan et al. A TRNG using chaotic entropy pool as a post-processing technique: analysis, design and FPGA implementation
CN106375079A (zh) 一种语音信息的混沌加密方法
US11101981B2 (en) Generating a pseudorandom number based on a portion of shares used in a cryptographic operation
US11438137B2 (en) Encryption device, decryption device, encryption method, decryption method, and computer readable medium
CN114175572A (zh) 利用拟群运算对加密数据实行相等和小于运算的系统和方法
WO2019113844A1 (fr) Procédé de génération de nombre aléatoire, puce et dispositif électronique
US20190260583A1 (en) Encryption device, search device, computer readable medium, encryption method, and search method
CN109683851A (zh) 随机数的生成方法、随机数生成装置、计算机存储介质
US8824677B1 (en) Provably secure and efficient pseudorandom number generation
GB2540220A (en) Distributed encryption system and method
Haroun et al. Real-time image encryption using a low-complexity discrete 3D dual chaotic cipher
CN111191253B (zh) 一种数据加密组合方法
CN111931204A (zh) 用于分布式系统的加密去重存储方法、终端设备
CN113794706B (zh) 数据的处理方法、装置、电子设备及可读存储介质
CN111066076A (zh) 登记终端、检索终端、检索服务器、检索系统、登记程序和检索程序
CN117725598A (zh) 安卓端数据加解密方法、装置、设备及介质
CN115021923A (zh) 基于变化因子的协作式解密信息的处理方法及装置
Siddhardha et al. An efficient implementation of the novel data encryption standard (DES) algorithm with improved key generation method compared with Viterbi decoder
Liu et al. A parallel encryption algorithm for dual-core processor based on chaotic map
US11360978B2 (en) Search device, tag generation device, query generation device, searchable encryption system and computer readable medium

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17935025

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17935025

Country of ref document: EP

Kind code of ref document: A1

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载