WO2019179259A1

WO2019179259A1 - Chip heat dissipating structure, chip structure, circuit board, and computing device

Info

Publication number: WO2019179259A1
Application number: PCT/CN2019/075041
Authority: WO
Inventors: Lei Zhang; Tong Zou
Original assignee: Bitmain Technologies Inc.
Priority date: 2018-03-21
Filing date: 2019-02-14
Publication date: 2019-09-26

Abstract

A circuit board includes a printed circuit board ("PCB"). The circuit board also includes a first plurality of chips mounted to a first side of the printed circuit board. The circuit board also includes a second plurality of chips mounted to a second side of the printed circuit board opposite the first side. The circuit board also includes at least one first heat sink mounted to the first plurality of chips. The circuit board further includes at least one second heat sink mounted to the second plurality of chips.

Description

CHIP HEAT DISSIPATING STRUCTURE, CHIP STRUCTURE, CIRCUIT BOARD, AND COMPUTING DEVICE

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Chinese Patent Application No. 201821786217. X, filed on October 31, 2018, Chinese Patent Application No. 201810550736.4, filed on May 31, 2018, Chinese Patent Application No. 201821942992. X, filed on November 23, 2018, and Chinese Patent Application No. 201820388242.6, filed March 21, 2018, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to the technology field of computers and more particularly, to a chip heat dissipating structure, a chip structure, a circuit board, and a computing device.

BACKGROUND

As technologies advance, demands for higher computing capabilities are also increasing. The computing industry has been pursuing higher computing density (e.g., computing capability per unit volume, or hash rate per unit volume in Terahash/Liter or TH/L) , and lower energy efficiency ratio (e.g., energy consumption per unit computing capability, or energy consumption per unit hash rate in Joule/Terahash or J/TH) . When the computing density increases, the volumetric power density increases, which means tremendous heat is generated. If the heat is not dissipated efficiently, the operating frequency of the chips may be limited, causing degradation in chip performance and increasing the risk of having instability issues. Most computing circuit boards in the current market has a computing density of about 5.5 TH/L, and a volumetric power density of about 350 Watt/Liter or W/L.

In the currently available technologies, such as currently available artificial intelligence solutions, to satisfy the demand for accelerated processing of big data, computer engineers have attempted to place an increasing number of chips on a circuit board in order to increase the computing density. A computing device may include one or more such circuit boards. However, increasing the number of chips on a circuit board and the number of circuit boards in a computing device also increases the heat generated by the chips. Heat dissipation has become a bottle neck that prevents further increase to the computing density through increasing the number of chips on a circuit board.

FIG. 1A, 1B, and 1C show a conventional circuit board 1 having a plurality of chips 3 connected in series. The circuit board 1 generally includes the chips uniformly distributed and mounted on a single side of a printed circuit board ( “PCB” ) 2. The PCB 2 may include

heat sinks

4A and 4B mounted on both sides to dissipate heat generated by the chips 3. The heat sinks 4A provided on a top side of the PCB 2 may function as a primary heat dissipation path for dissipating heat generated by the chips 3 from an effective heat dissipation space in which the chips 3 are disposed. The heat sink 4B provided on a bottom side of the PCB 2 may provide auxiliary heat dissipation functions. However, because a large number of chips (e.g., 10, 20, 30, 40, 50, 60, etc. ) may be mounted on the top side of the PCB, a large amount of heat is generated by the chips when the chips are performing computation tasks. This results in a high volumetric power density and a low heat dissipation efficiency due to limited heat dissipation capability provided by conventional heat sinks.

Therefore, there is a need to develop a heat dissipating structure having a high heat dissipation efficiency, and a circuit board having a large number of chips mounted on both sides of the board and having the capability to efficiently dissipate a large amount of heat generated by the large number of chips.

SUMMARY

An embodiment of the present disclosure provides a circuit board. The circuit board includes a printed circuit board ( “PCB” ) . The circuit board also includes a first plurality of chips mounted to a first side of the printed circuit board. The circuit board also includes a second plurality of chips mounted to a second side of the printed circuit board opposite the first side. The circuit board also includes at least one first heat sink mounted to the first plurality of chips. The circuit board further includes at least one second heat sink mounted to the second plurality of chips.

An embodiment of the present disclosure provides a method for arranging chips to a printed circuit board ( “PCB” ) . The method includes mounting a first plurality of chips to a first side of the PCB. The method also includes mounting a second plurality of chips to a second side of the PCB opposite the first side. The method also includes mounting at least one first heat sink to the first plurality of chips. The method further includes mounting at least one second heat sink to the second plurality of chips.

An embodiment of the present disclosure provides a computing device. The computing device includes a housing. The computing device also includes a circuit board disposed inside the housing. The circuit board includes a printed circuit board ( “PCB” ) . The circuit board also includes a first plurality of chips mounted to a first side of the printed circuit board. The circuit board also includes a second plurality of chips mounted to a second side of the printed circuit board opposite the first side. The circuit board also includes at least one first heat sink mounted to the first plurality of chips. The circuit board further includes at least one second heat sink mounted to the second plurality of chips.

An embodiment of the present disclosure provides a computing device. The computing device includes a housing including a first cut-out hole and a second cut-out hole, the first cut-out hole located at a first end of the housing and the second cut-out hole located at a second end of the housing, the first end opposite the second end. The computing device also includes a circuit board disposed inside the housing. The circuit board includes a signal interface and a power interface, the signal interface located at a first end of the circuit board and the power interface located at a second end of the circuit board, the first end of the circuit board opposite the second end of the circuit board. The signal interface is exposed through the first cut-out hole and the power interface is exposed through the second cut-out hole.

An embodiment of the present disclosure provides a circuit board. The circuit board includes a signal interface configured to connect with a controller to receive signals from the controller. The circuit board also includes a power interface configured to connect with a power source. The signal interface is located at a first end of the circuit board, and the power interface is located at a second end of the circuit board, the first end opposite the second end.

An embodiment of the present disclosure provides a chip heat dissipating structure mountable on a chip to dissipate heat generated by the chip. The chip heat dissipating structure includes a coating disposed over the chip. The coating includes at least one metal-based layer.

An embodiment of the present disclosure provides a chip structure. The chip structure includes a chip and a chip heat dissipating structure mounted to the chip. The chip heat dissipating structure includes a coating disposed over the chip. The coating includes at least one metal-based layer.

An embodiment of the present disclosure provides a circuit board. The circuit board includes a printed circuit board. The circuit board also includes at least one chip structure mounted to the printed circuit board. Each chip structure includes a chip and a chip heat dissipating structure mounted to the chip. The chip heat dissipating structure includes a coating disposed over the chip. The coating includes at least one metal-based layer.

An embodiment of the present disclosure provides a supercomputing device. The supercomputing device includes a housing and at least one circuit board disposed inside the housing. Each circuit board includes a printed circuit board. Each circuit board also includes at least one chip structure mounted to the printed circuit board. Each chip structure includes a chip and a chip heat dissipating structure mounted to the chip. The chip heat dissipating structure includes a coating disposed over the chip. The coating includes at least one metal-based layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features of the present disclosure are set forth with particularity in the appended claims. A better understanding of the features and advantages of the present disclosure will be obtained by referencing to the following detailed description that sets forth illustrative embodiments, in which the principles of the present disclosure are utilized, and the accompanying drawings of which:

FIG. 1A is a side view in a width direction of a conventional circuit board, in accordance with an embodiment of the present disclosure.

FIG. 1B is a top view of the conventional circuit board shown in FIG. 1A, in accordance with an embodiment of the present disclosure.

FIG. 1C is a schematic diagram of the conventional circuit board shown in FIG. 1A, in accordance with an embodiment of the present disclosure.

FIG. 2A is a side view in a width direction of a circuit board, in accordance with an embodiment of the present disclosure.

FIG. 2B is a top view of the circuit board shown in FIG. 2A, in accordance with an embodiment of the present disclosure.

FIG. 2C is a back view of the circuit board shown in FIG. 2A, in accordance with an embodiment of the present disclosure.

FIG. 2D is a side view in a width direction of a circuit board, in accordance with an embodiment of the present disclosure.

FIG. 3A is a side view in a length direction of a circuit board, in accordance with another embodiment of the present disclosure.

FIG. 3B is a top view of the circuit board shown in FIG. 3A, in accordance with an embodiment of the present disclosure.

FIG. 3C is a bottom view of the circuit board shown in FIG. 3A, in accordance with an embodiment of the present disclosure.

FIG. 3D is a side view in the length direction of a circuit board, in accordance with an embodiment of the present disclosure.

FIG. 4 is a side view of an example first heat sink, in accordance with an embodiment of the present disclosure.

FIG. 5 is a flow chart illustrating a method for arranging chips, in accordance with an embodiment of the present disclosure.

FIG. 6 is a schematic diagram of a computing device, in accordance with an embodiment of the present disclosure.

FIG. 7 is a perspective view of a structure of a cryptocurrency mining computing device, in accordance with an embodiment of the present disclosure.

FIG. 8 is a top view of the structure of the cryptocurrency mining computing device shown in FIG. 7, in accordance with an embodiment of the present disclosure.

FIG. 9 is a bottom view of the structure of the cryptocurrency mining computing device shown in FIG. 7, in accordance with an embodiment of the present disclosure.

FIG. 10 is a back view of the structure of the cryptocurrency mining computing device shown in FIG. 7, in accordance with an embodiment of the present disclosure.

FIG. 11 is a top view of a circuit board shown in FIG. 7, in accordance with an embodiment of the present disclosure.

FIG. 12 is a schematic diagram of a chip heat dissipating structure, in accordance with an embodiment of the present disclosure.

FIG. 13 is a schematic diagram of a chip heat dissipating structure, in accordance with another embodiment of the present disclosure.

FIG. 14 is a schematic diagram of a chip heat dissipating structure, in accordance with another embodiment of the present disclosure.

FIG. 15 is a schematic diagram of a heat sink, in accordance with an embodiment of the present disclosure.

FIG. 16 is a schematic diagram of a chip heat dissipating structure, in accordance with another embodiment of the present disclosure.

FIG. 17 is a schematic diagram of a chip heat dissipating structure, in accordance with another embodiment of the present disclosure.

FIG. 18 is a schematic diagram of a chip heat dissipating structure, in accordance with another embodiment of the present disclosure.

FIG. 19 is a schematic diagram of a chip heat dissipating structure, in accordance with another embodiment of the present disclosure.

FIG. 20 is a schematic diagram of a chip heat dissipating structure, in accordance with another embodiment of the present disclosure.

FIG. 21 is a schematic diagram of a chip heat dissipating structure, in accordance with another embodiment of the present disclosure.

FIG. 22 is a schematic diagram of a chip heat dissipating structure, in accordance with an embodiment of the present disclosure.

FIG. 23 is a schematic diagram of a chip heat dissipating structure, in accordance with an embodiment of the present disclosure.

FIG. 24 is a schematic diagram of a chip heat dissipating structure, in accordance with an embodiment of the present disclosure.

FIG. 25 illustrates a step of a process for manufacturing the chip heat dissipating structure, in accordance with an embodiment of the present disclosure.

FIG. 26 illustrates another step of the process for manufacturing the chip heat dissipating structure, in accordance with another embodiment of the present disclosure.

FIG. 27 illustrates another step of the process for manufacturing the chip heat dissipating structure, in accordance with another embodiment of the present disclosure.

FIG. 28 illustrates another step of the process for manufacturing the chip heat dissipating structure, in accordance with another embodiment of the present disclosure.

FIG. 29 illustrates another step of the process for manufacturing the chip heat dissipating structure, in accordance with another embodiment of the present disclosure.

FIG. 30 illustrates another step of the process for manufacturing the chip heat dissipating structure, in accordance with another embodiment of the present disclosure.

FIG. 31 illustrates another step of the process for manufacturing the chip heat dissipating structure, in accordance with another embodiment of the present disclosure.

FIG. 32 is a schematic diagram of a chip structure, in accordance with an embodiment of the present disclosure.

FIG. 33 is a schematic diagram of a chip structure, in accordance with another embodiment of the present disclosure.

FIG. 34 is a schematic diagram of a circuit board, in accordance with an embodiment of the present disclosure.

FIG. 35 is a schematic diagram of a supercomputing device, in accordance with an embodiment of the present disclosure.

FIG. 36 is a schematic diagram of a conventional circuit board.

FIG. 37 is a schematic diagram of a circuit board, in accordance with an embodiment of the present disclosure.

FIG. 38 is a schematic diagram of a circuit board, in accordance with another embodiment of the present disclosure.

FIG. 39 is a schematic diagram of a circuit board having four copper layers, in accordance with an embodiment of the present disclosure.

FIG. 40 is a schematic side view of a housing for a computing device, in accordance with an embodiment of the present disclosure.

FIG. 41 is a perspective view of a housing for a computing device, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION

Technical solutions of the present disclosure will be described in detail with reference to the drawings. It will be appreciated that the described embodiments represent some, rather than all, of the embodiments of the present disclosure. Other embodiments conceived or derived by those having ordinary skills in the art based on the described embodiments without inventive efforts should fall within the scope of the present disclosure. Example embodiments will be described with reference to the accompanying drawings, in which the same numbers refer to the same or similar elements unless otherwise specified.

As used herein, the terms “top” and “bottom” refer to different locations or portions of an item. The terms “top” and “bottom” may be defined in a local perspective rather than a global perspective. For example, a top surface or portion of an item may be located higher than a bottom surface or portion of the item. However, when the item is disposed upside down, the top surface or portion of the item may be located lower than the bottom surface or portion of the item from a global perspective. In a local perspective, however, the surface that is lower may still be referred to as a top surface, and the surface that is higher may still be referred to as a bottom surface. For example, when a chip is mounted to a bottom surface of a board, the chip is disposed upside down. The chip has a top surface and a bottom surface, with the bottom surface contacting the board. In this situation, the bottom surface of the chip is located higher than the top surface of the chip.

When a first item is mounted “on” or “over” a second item, the terms “on” or “over” do not necessarily mean that the first item is located higher than the second item. In some situations, the first item may be located higher than second item. In some situations, when a first item is mounted “on” or “over” a lower surface of a second item (e.g., a bottom surface of a board) , the first item may be located below the lower surface of the second item.

When a first item is mounted “to” a second item, the first item may be mounted to the second item from any suitable directions, such as from above the second item, from below the second item, from the left side of the second item, or from the right side of the second item.

As used herein, when a first item (or unit, element, member, part, piece) is referred to as “coupled, ” “mounted, ” “fixed, ” “secured, ” “connected, ” to or with a second item, it is intended that the first item may be directly coupled, mounted, fixed, secured, or connected to or with the second item, or may be indirectly coupled, mounted, fixed, secured, or connected to or with the second item via another intermediate item. The terms “coupled, ” “mounted, ” “fixed, ” “secured, ” and “connected” do not necessarily imply that a first item is permanently coupled with a second item. The first item may be detachably coupled with the second item when these terms are used. In some situations, the terms “coupled” and “connected” may encompass mechanical, electrical, or both mechanical and electrical coupling and connections. The connection may be permanent or detachable. The electrical connection may be wired or wireless.

When a first item is fixedly coupled, mounted, or connected to a second item, the term “fixedly” means “securely, ” and is relative to movably. When the first item is fixedly coupled, mounted, or connected to the second item, the first item does not move relative to the second item. However, the first item may not be permanently coupled to the second item. For example, the first item may still be detachable from the second item.

When a first item is referred to as “disposed, ” “located, ” or “provided” on, in, or inside a second item, the first item may be directly disposed, located, or provided on, in, or inside the second item or may be indirectly disposed, located, or provided on, in, or inside the second item via an intermediate item. When a first item is referred to as disposed, located, or provided “in, ” “within, ” or “inside” a second item, the first item may be partially or entirely disposed, located, or provided in, within, or inside the second item.

The terms “perpendicular, ” “horizontal, ” “left, ” “right, ” “up, ” “upward, ” “down, ” “downward, ” and similar expressions used herein are merely intended for description. The term “communicatively coupled” indicates that related items are coupled through a communication channel, such as a wired or wireless communication channel. The terms “clockwise” and “counter-clockwise” indicate relative directions as viewed from a perspective shown in the figures.

In addition, the singular forms “a, ” “an, ” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. And, the terms “comprise, ” “comprising, ” “include, ” and the like specify the presence of stated features, steps, operations, elements, and/or components but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups. The term “and/or” used herein includes any suitable combination of one or more related items listed.

Unless otherwise defined, all the technical and scientific terms used herein have the same or similar meanings as generally understood by one of ordinary skill in the art. As described herein, the terms used in the specification of the present disclosure are intended to describe example embodiments, instead of limiting the present disclosure.

Further, when an embodiment illustrated in a drawing shows a single element, it is understood that the embodiment may include a plurality of such elements. Likewise, when an embodiment illustrated in a drawing shows a plurality of such elements, it is understood that the embodiment may include only one such element. The number of elements illustrated in the drawing is for illustration purposes only, and should not be construed as limiting the scope of the embodiment.

Moreover, unless otherwise noted, the embodiments shown in the drawings are not mutually exclusive, and they may be combined in any suitable manner. For example, elements shown in one embodiment but not in another embodiment may nevertheless be included in the other embodiment.

The present disclosure does not limit the sequence of execution of steps included in disclosed methods. The sequence of the steps may be any suitable sequence, and certain steps may be repeated, omitted, or added.

The present disclosure provides a chip heat dissipating structure that can dissipate heat efficiently from the chip. The chip heat dissipating structure includes a coating applied to the chip. The coating may be a metal coating, and may include at least one metal-based layer. In some embodiments, the at least one metal-based layer may include a first metal-based layer disposed over the chip and a second metal-based layer disposed over the first metal-based layer. A heat sink can then be mounted to the chip by a welding method. The heat sink may be welded to the coating on the chip through a welding material layer, such as tin. The metal coating has a heat conductivity that may be much greater than epoxy (e.g., 30 times greater) , a typical glue used for gluing the heat sink to the chip in conventional technologies. The combination of the metal coating and the metal welding material layer significantly increases the heat dissipation efficiency, thereby resolving the heat dissipation bottle neck and rendering it practical and cost effective to include a large number of chips on both sides of a circuit board.

The present disclosure also provides a chip structure that includes a chip and the chip heat dissipating structure mounted to the chip for efficiently dissipate heat generated by the chip.

The present disclosure also provides a circuit board that includes a large number of chips mounted on both sides of a printed circuit board ( “PCB” ) . Each chip may have the disclosed chip structure, which includes the disclosed chip heat dissipating structure. Heat generated by the large number of chips may be efficiently dissipated by the disclosed chip heat dissipating structures provided to the chips. Additional heat sinks may be mounted to the PCB at gaps between adjacent chips on each side of the PCB to provide auxiliary heat dissipation functions, thereby further improving the heat dissipation efficiency. The PCB may include a substrate having an excellent heat conductivity, such as aluminum. The PCB may include heat conductive layers provided on both sides of the substrate. Thus, the PCB may also function as a heat conducting board to facilitate a uniform temperature distribution on both sides of the PCB.

The present disclosure also provides a housing for accommodating the circuit board. The housing may include multiple mounting holes for mounting cooling fans. At each mounting hole, one or more cooling fans may be mounted (when multiple fans are mounted, they may be mounted in a stacked configuration) . Each mounting hole may correspond to a heat dissipation region of the circuit board. Thus, a short air flow path may be provided to dissipate heat. Through the multiple mounting holes, fans mounted at the mounting holes, and the corresponding heat dissipation regions, air flow inside the housing may be separated into a plurality of layers of air flow, thereby increasing the air pressure inside the housing and increasing the velocity of the air flow. The housing can further facilitate heat dissipation from the circuit board.

With the disclosed structures, a plurality of chips (e.g., a large number of chips, such as 10, 20, 30, 40, 50, 60, or more) may be mounted to both sides of a PCB on a circuit board. In addition, multiple circuit boards having chips on both sides of the PCB may be provided in a housing of a computing device. The large amount of heat generated by the chips can be efficiently dissipated by the disclosed chip heat dissipating structures provided to the chips and circuit boards and through the efficient short air flow paths provided by the housing that accommodates the circuit boards. As a result, the computing performance of the computing device can be significantly improved.

Circuit Board

FIG. 2A is a side view in a width direction of a circuit board 10, according to an embodiment of the present disclosure. As shown in FIG. 2A, the circuit board 10 may include a printed circuit board ( “PCB” ) 11, a first plurality of chips 12A mounted on or to a first side (which may be referred to as a top side) of the PCB 11, and a second plurality of chips 12B mounted on or to a second side (which may be referred to as a bottom side or back side) of the PCB 11.

A plurality of first heat sinks 13A may be mounted to the first plurality of chips 12A, and a plurality of second heat sinks 13B may be mounted to the second plurality of chips 12B. For example, the plurality of first heat sinks 13A may be mounted on or to top surfaces of the chips 12A, and the plurality of second heat sinks 13B may be mounted to or on top surfaces of the chips 12B. Here, the top surfaces of the chips 12A are surfaces of the chips 12A that face upward, and the top surfaces of the chips 12B are surfaces of the chips 12B that face downward. In other words, the surface of a chip that contacts the PCB 11 or that is closer to the PCB 11 may be referred to as a bottom surface and the surface of the chip that is farther away from the PCB 11 may be referred to as a top surface. Although first heat sinks 13A and second heat sinks 13B are illustrated as individual heat sinks mounted to the top surfaces of the

chips

12A and 12B, respectively, the present disclosure does not limit the type of heat sinks to be individual heat sinks. Other types of heat sinks may also be used. For example, the top surfaces of the first plurality of chips 12A may be mounted with a single integral heat sink that contacts the top surfaces of the chips 12A. Similarly, the top surfaces of the second plurality of chips 12B may be mounted with a single integral heat sink that contacts the top surfaces of the chips 12B. Other types of heat sinks may include heat tubes, uniform temperature board, water cooling devices, etc.

According to the present disclosure, both sides of the PCB 11 are provided with chips. Thus, without increasing the size or volume of the circuit board 10, the number of chips may be increased. The heat generated by the chips is also increased. Heat dissipation space is expanded to both sides of the PCB 11. The present disclosure provides an efficient heat dissipating structure that can efficiently dissipate heat from the heat dissipating spaces around the PCB. Compared to the conventional circuit boards, which include chips provided on only a single side of the PCB, the disclosed circuit board 10 may lower the energy efficiency ratio and _[HY1] increase the overall heat dissipation efficiency. As a result, the computing performance of the circuit board 10 can be significantly increased as compared to a conventional circuit board having chips mounted on a single side of the PCB. In some situations, the computing density of the disclosed circuit board 10 can be increased by 70%or more compared to a comparable conventional circuit board.

In some embodiments, the first plurality of chips 12A and the second plurality of chips 12B may be integrated circuit ( “IC” ) chips, such as Application Specific Integrated Circuit ( “ASIC” ) chips configured for performing various data processing computations. For example, the chips may be used for performing computations for artificial intelligence related supercomputing. In some embodiments, the circuit board 10 may be a circuit board included in a computing device for executing data processing computations, and may also be referred to as a calculating board or computing board.

FIG. 2B is a top view of the circuit board 10 shown in FIG. 2A, according to an embodiment of the present disclosure. FIG. 2C is a back or bottom view of the circuit board 10 shown in FIG. 2A, according to an embodiment of the present disclosure. As shown in FIG. 2B and FIG. 2C, for the convenience of configuring power supplying circuits and signal circuits on the PCB 11, in some embodiments, the first plurality of chips 12A provided on the top side of the PCB 11 and the second plurality of chips 12B provided on the bottom side of the PCB 11 may be arranged in a regular pattern, for example, in an array.

In some embodiments, the first plurality of chips 12A and the second plurality of chips 12B may be arranged in an array that has one or more rows and one or more columns. For example, the array may include a plurality of rows and a plurality of columns. In some embodiments, the array may include uniform rows and uniform columns, where the distances between rows are the same, and distances between columns are the same. In some embodiments, the array may include uniform rows and non-uniform columns, where distances between rows are the same and distances between columns are different. In some embodiments, the array may include non-uniform rows and uniform columns, where distances between rows are different and distances between columns are the same. In some embodiments, when the array includes non-uniform rows and non-uniform columns, the distances between rows may be different and the distances between columns may be different. In some embodiments, a distance between columns may be the same as or different from a distance between rows. In some embodiments, a first distance between a first row and a second row may be different from a second distance between a third row and a fourth row. In some embodiments, a first distance between a first column and a second column may be different from a second distance between a third column and a fourth column. The present disclosure does not limit how the

chips

12A and 12B are arranged.

In some embodiments, as shown in FIG. 2A, mapping locations the first plurality of chips 12A mounted on the top side of the PCB 11 and mapping locations of the second plurality of chips 12B mounted on the bottom side of the PCB 11 do not overlap with one another. The mapping locations of the chips are the locations on the PCB 11 (which can be on either the top side or the bottom side) corresponding to the contacting locations of the chips on the PCB 11. In other words, the first plurality of chips 12A and the second plurality of chips 12B may be disposed on the top side and bottom side of the PCB 11 at locations arranged a staggered pattern, as shown in FIG. 2A. The staggered pattern arrangement of the chips may result in uniform heat dissipation spaces on both sides of the PCB 11, thereby increasing the heat dissipation efficiency.

In some embodiments, when the mapping locations the first plurality of chips 12A mounted on the top side of the PCB 11 and the mapping locations of the second plurality of chips 12B mounted on the bottom side of the PCB 11 do not overlap with one another, the mapping location of each of the second plurality of chips 12B on the PCB 11 may be located between two adjacent mapping locations of two adjacent chips 12A. For example, the mapping locations of the second plurality of chips 12B may be separated by same distances or by different distances in columns. Likewise, the mapping location of each of the first plurality of chips 12A on the PCB 11 may be located between two adjacent mapping locations of two adjacent chips 12B. For example, the mapping locations of the first plurality of chips 12A may be separated by same distances or by different distances in columns.

In some embodiments, the mapping locations of the first plurality of chips 12A mounted on the top side of the PCB 11 and the mapping locations of the second plurality of chips 12B mounted on the bottom side of the PCB 11 overlap with one another, or partially overlap with one another.

Overlapping means the mapping location of each of the first plurality of chips 12A on the PCB 11 corresponds to the mapping location of each of the second plurality of chips 12B on the PCB 11. In other words, a mounting location of each chip 12A on the top surface of the PCB 11 corresponds to a mounting location of each chip 12B on the bottom surface of the PCB 11. In some embodiments, partial overlapping means a portion of the first plurality of chips 12A on the PCB 11 have mapping locations corresponding to mapping locations of a portion of the second plurality of chips 12B on the PCB 11. Such partial overlapping configuration may be based on a relationship between electrical and/or mechanical connections and/or heat dissipation. For example, at locations on the PCB 11 adjacent an air inlet of a cooling fan, the partial overlapping configuration may be used. At locations on the PCB 11 adjacent an air outlet of the cooling fan, the partial overlapping configuration may not be used. In some embodiments, partial overlapping may also mean that at least one of the first plurality of chips 12A has a mapping location (or a mounting location) on the PCB 11 that partially overlaps with a mapping location (or a mounting location) of at least one of the second plurality of chips 12B.

FIG. 2D is a side view in a width direction of a circuit board 10, in accordance with another embodiment of the present disclosure. As shown in FIG. 2D, the first plurality of chips 12A and the second plurality of chips 12B are arranged in a staggered configuration. At each mapping location of each chip 12A on the bottom side of the PCB 11, a third heat sink 14A may be mounted to the PCB 11, and at each mapping location of each chip 12B on the top side of the PCB 11, a fourth heat sink 14B may be mounted to the PCB 11. The third heat sinks 14A and the fourth heat sinks 14B are auxiliary heat sinks disposed on both sides of the PCB 11 at locations where no chips are mounted to provide additional heat dissipation functions, thereby further increasing the heat dissipation efficiency of the circuit board 10.

FIG. 3A is a side view in a length direction of the circuit board 10, in accordance with another embodiment of the present disclosure. FIG. 3B is a top view of the circuit board 10 shown in FIG. 3A. FIG. 3C is a bottom view of the circuit board 10 shown in FIG. 3A. As shown in FIGs. 3A, 3B, and 3C, the mapping locations of the first plurality of chips 12A on the PCB 11 do not overlap with the mapping locations of the second plurality of chips 12B on the PCB 11. The

chips

12A and 12B are arranged as follows: the mapping locations of each row of the second plurality of chips 12B on the PCB 11 are located between the mapping locations of two adjacent rows of the first plurality of chips 12B on the PCB 11. The mapping locations of the rows may be separated by the same distance, or may be separated by different distances.

FIG. 3D is a side view in the length direction of a circuit board 10, in accordance with another embodiment of the present disclosure. As shown in FIG. 3D, at each mapping location of each of the first plurality of chips 12A, a third heat sink 14A may be mounted on the bottom side of the PCB 11. At each mapping location of each of the second plurality of chips 12B, a fourth heat sink 14B may be mounted on the top side of the PCB 11.

The embodiment shown in FIG. 3D includes

auxiliary heat sinks

14A and 14B added to the embodiment shown in FIG. 3A at locations on the PCB 11 where no chips are mounted, thereby increasing the heat dissipation efficiency of the circuit board 10.

FIG. 4 shows a side view of an example first heat sink 13A, in accordance with an embodiment of the present disclosure. The second heat sink 13B, the third heat sink 14A, and the fourth heat sink 14B may each have a structure similar to that of the first heat sink 13A. In some embodiments, the first heat sinks 13A, the second heat sinks 13B, the third heat sinks 14A, and the fourth heat sinks 14B may have the same size or different sizes. When the same size is used, the heat sinks may have the same number of heat dissipating wings and/or same height, width, length, etc.

As shown in FIG. 4, a first heat sink 13A may include a base plate 131 and one or more heat dissipating wings 132 (e.g., a plurality of heat dissipating wings 132) . The base plate 131 may include a first portion 131A located at a central location of the base plate 131. The base plate 131 may also include a second portion 131B extending from a side of the first portion 131A upwardly in a predetermined tilting angle relative to the first portion 131A, and a third portion 131C extending from another side of the first portion 131A upwardly in the predetermined tiling angle relative to the first portion 131A. The predetermined tilt angle may be within 90 degrees and 180 degrees. A bottom surface of the first portion 131a may be fixedly mounted to top surfaces of chips 12A and/or 12B. A plurality of heat dissipating wings 132 may be mounted to or connected with top surfaces of the first portion 131A, the second portion 131B, and the third portion 131C of the base plate 131. In some embodiments, the plurality of heat dissipating wings 132 may be vertically disposed in parallel with one another. The distances between two adjacent heat dissipating wings 132 may be the same or different. The first heat sink 13A may also include a handle 133 disposed at a top portion of one or more of the heat dissipating wings 132 for a user to grab and pull the first heat sink 13A. The handle 133 disposed at the top portion of the one or more heat dissipating wings 132 may include a plate shape, a ring shape, or any other suitable shape. In some embodiments, the various parts of the heat sink 13A may be integrally formed into a single piece.

In some embodiments, methods used for mounting the first heat sink 13A and the second heat sink 13B to the chips may include one or more of a structural fixing method, a gluing method, or a welding method. For example, in the gluing method, a heat conductive glue may be applied to the top surface and/or a bottom surface of the heat sink to glue them together. The welding method may be a soldering method. For example, a back side metal ( “BSM” ) welding methods may be used to weld the heat sinks to the chips. In the BSM welding method, a metal layer or coating may be applied to the wafer of the chips using techniques, such as metal sputtering, to function as a connection material as well as a heat conducting material between the wafer and the heat sink. The heat sink can be welded to the metal layer or coating through a welding material layer between the coating and the heat sink. Thus, the heat sink can be fixedly connected to the chips and heat can be much more efficiently transferred from the chips to the heat sinks through the metal layer or coating and the welding material layer, as compared to the gluing method that may use an epoxy, a typical material for gluing a heat sink to the chip.

In some embodiments, the first heat sink 13A and the second heat sink 13B may be mounted to the chips using different or the same mounting methods. In some embodiments, the third heat sink 14A and the fourth heat sink 14B may be mounting to the PCB 11 using various mounting methods, including, for example, the welding methods. For example, the welding method for mounting the third heat sink 14A and the fourth heat sink 14B may be a soldering method.

FIG. 5 is a flow chart illustrating a method 500 for arranging chips, in accordance with an embodiment of the present disclosure. The method 500 may be implemented for arranging chips on a PCB, such as PCB 11. The method 500 may be performed manually by an operator or automatically by computerized or computer-controlled robot. As shown in FIG. 5, the method 500 for arranging chips on a PCB may include:

Step S501, mounting a first plurality of chips to a first side of a PCB;

Step S502, mounting a second plurality of chips to a second side of the PCB opposite the first side; and

Step S503, mounting a first heat sink and a second heat sink to the first plurality of chips and the second plurality of chips, respectively.

For example, in step S501, a first plurality of chips 12A may be mounted to a top surface of the PCB 11, as shown in FIG. 2A. In step S502, a second plurality of chips 12B may be mounted to a bottom surface of the PCB 11, as shown in FIG. 2A. In step S503, a plurality of heat sinks 13A (which may be collectively referred to as “a first heat sink” in step S503) are mounted to the first plurality of chips 12A, and a plurality of heat sinks 13B (which may be collectively referred to as “a second heat sink” in step S503) are mounted to the second plurality of chips 12B. Here, heat sinks 13B being mounted to the second plurality of chips 12B means heat sinks 13B are mounted to top surfaces of chips 12B, the top surfaces being surfaces opposite bottom surfaces that contact the PCB 11 (or that are closer to the PCB 11) . Because chips 12B are mounted to the bottom surface of the PCB 11, the chips 12B are mounted upside down. Hence, the top surfaces of the chips 12B are the lower surfaces of the chips 12B shown in FIG. 2A, and the bottom surfaces of the chips 12B are the upper surfaces of the chips 12B shown in FIG. 2A that contact (or are closer to) the PCB 11. Thus, when the heat sinks 13B are mounted “on” or to the second plurality of chips 12B, the heat sinks 13B are mounted to the top surfaces (i.e., the lower surfaces shown in FIG. 2A) of chips 12B.

According to the present disclosure, chips are arranged on both of the top surface and the bottom surface of the PCB of a circuit board. As a result, the effective heat dissipation space of the circuit board is expanded from a single space on one side of the PCB to two spaces on both sides of the PCB. The disclosed arrangement of the chips on both sides of the PCB can reduce the energy efficiency ratio of the circuit board, and increase the overall heat dissipation efficiency of the circuit board.

In some embodiments, the first plurality of chips and the second plurality of chips are IC chips, such as ASIC chips configured to execute various data processing computations. The computations may include, but not be limited to, artificial intelligence computations. In some embodiments, the disclosed circuit board may be a circuit board included in a computing device for executing data processing computations, and may also be referred to as a calculating board or computing board.

In some embodiments, the disclosed method further includes: arranging the first plurality of chips and the second plurality of chips on the PCB in arrays, respectively. In some embodiments, arranging the first plurality of chips and the second plurality of chips in arrays may include: arranging the first plurality of chips on a top side of the PCB and arranging the second plurality of chips on a bottom side of the PCB opposite the top side, such that mapping locations the first plurality of chips on the PCB and mapping locations of the second plurality of chips on the PCB do not overlap with one another. In other words, the first plurality of chips and the second plurality of chips are arranged in a staggered configuration. In some embodiments, in the staggered configuration, no chips from the first plurality of chips and the second plurality of chips are mounted at the same location on opposite sides of the PCB. In some embodiments, in the staggered configuration, a significant number of chips from the first plurality of chips and the second plurality of chips may be arranged in a staggered configuration, and a relatively small number of chips from the first plurality of chips and the second plurality of chips may be arranged at the same location on opposite sides of the PCB.

In some embodiments, the disclosed method may also include: mounting a third heat sink at a mapping location on a second side of the PCB, the mapping location being a mapping location of each of the first plurality of chips mounted on a first side of the PCB. The disclosed method may also include: mounting a fourth heat sink at a mapping location on the first side of the PCB, the mapping location being a mapping location of each of the second plurality of chips mounted on the second side of the PCB.

In some embodiments, arranging the first plurality of chips and the second plurality of chips in arrays may include: arranging the first plurality of chips and the second plurality of chips such that mapping locations of the first plurality of chips on the PCB overlap or partially overlap with mapping locations of the second plurality of chips on the PCB.

In some embodiments, the first heat sink and the second heat sink may be mounted onto the chips using any mounting methods, such as one or more of a structural fixing method, a gluing method, and a welding method. In some embodiments, the third heat sink and the fourth heat sink may be mounted to the PCB using any suitable mounting methods, such as soldering methods.

FIG. 6 is a schematic diagram of a computing device 100, in accordance with an embodiment of the present disclosure. As shown in FIG. 6, the computing device 100 may include a housing 50 and at least one circuit board 10 disposed inside the housing 50. The circuit board 10 may include chips, PCB, and heat sinks arranged in the configurations disclosed herein.

It is understood that FIG. 6 only schematically illustrates a computing device 100 including one circuit board 10. In some embodiments, a plurality of circuit boards 10 may be disposed inside the housing 50. In some embodiments, the number of circuit boards 10 may be determined based on the demands on the computing capability (e.g., hash rate) .

The computing device 100 may be any computer or terminal device that can execute computing tasks. The present disclosure does not limit the type of the computing device 100.

The present disclosure provides a circuit board, a method for arranging chips on a PCB, and a computing device. By mounting chips on both sides of the PCB, the effective heat dissipation space of the circuit board is expanded from a single space on one side of the PCB to two spaces on both sides of the PCB. The disclosed arrangement of the chips on the PCB can reduce the energy efficiency ratio of the circuit board, and can increase the overall heat dissipation efficiency of the circuit board.

Housing and Circuit Board

According to an aspect of the present disclosure, the computing device may be cryptocurrency mining computing device. The cryptocurrency mining computing device may include the circuit board disclosed herein. Cryptocurrency mining computing devices are electronic devices configured for earning (or mining) cryptocurrency, such as Bitcoins. When mining for Bitcoins, the computing device may be connected with a power supply and a network, and may perform computations using the circuit boards included the computing device. The computing device may communicate with a remote server to obtain Bitcoins.

In the current market, circuit boards used in cryptocurrency mining computing devices generally include a power interface and a signal interface. The power interface may be connected with a corresponding power interface provided on a housing of the computing device. The power interface of the computer housing may be connected with an external power source. The signal interface of the circuit board may be connected with a corresponding signal interface provided on the housing of the computing device. The signal interface of the housing may be connected with a controller board, such that the controller board may send signals to the circuit board to control the operations of the circuit board, such as the computations performed by the circuit board. However, the power interface and the signal interface of the computing circuit board are generally provided on the same end, and are disposed adjacent one another. This arrangement can cause signal interference, thereby affecting the normal operations of the computing device.

The present disclosure provides a cryptocurrency mining computing device and a circuit board that can eliminate or avoid signal interference, such that the computing device can operate normally.

The technical solutions provided by the present disclosure includes, in one aspect, a cryptocurrency mining computing device including a housing having a first cut-out hole and a second cut-out hole. The first cut-out hole may be provided at a first end of the housing, and the second cut-out hole may be provided at a second end of the housing, the second end being opposite the first end. The computing device may also include a circuit board disposed inside the housing. The circuit board may include a signal interface and a power interface. The signal interface may be located at a first end of the circuit board, and the power interface may be located at a second end of the circuit board, the second end being opposite the first end. When the circuit board is mounted inside the housing, the signal interface may be exposed at the first cut-out hole, and the power interface may be exposed at the second cut-out hole.

In some embodiments, the first cut-out hole and the second cut-out hole may be located at diagonal locations on the housing. In some embodiments, the first cut-out hole and the second cut-out hole may be located on a same side of the housing. In some embodiments, the signal interface and the power interface may be located at diagonal locations on the circuit board. In some embodiments, the signal interface and the power interface may be located at a same side of the circuit board.

In some embodiments, the cryptocurrency mining computing device may also include a mounting mechanism configured to stably mount the circuit board inside the housing. The mounting mechanism may include a first slot and a first raised portion configured to fit with the first slot. The first slot may be provided at a first side of the circuit board. The housing may include a first side panel corresponding to the first side of the circuit board. The first raised portion may be provided on an inner surface of the first side panel. The first raised portion may snap-fit with the first slot when the first raised portion is inserted or pressed into the first slot.

In some embodiments, the mounting mechanism may include a second slot and a second raised portion configured to fit with the second slot. The second slot may be provided at a second side of the circuit board, the second side being opposite the first side of the circuit board. The housing may include a second side panel disposed opposite the first side panel. The second side panel may face the first side panel, and the second raised portion may be provided on an inner surface of the second side panel. In some embodiments, the second raised portion may snap-fit with the second slot when the second raised portion is inserted or pressed into the second slot.

In some embodiments, the first side panel is provided with a plurality of mounting holes separated at a predetermined distance along a length direction. At least one fan may be mounted at each of the mounting hole. In some embodiments, the second side panel may be provided with a plurality of heat dissipation regions separated by a predetermined distance along the length direction. Each heat dissipation region may correspond to at least one fan. Each heat dissipation region may include a plurality of venting holes.

In some embodiments, a plurality of fans may be mounted at each mounting hole. In some embodiments, the plurality of fans may be disposed to at least partially overlap one another.

In some embodiments, the housing may include a plurality of first cut-out holes and a plurality of second cut-out holes distributed along a width direction of the housing.

In some embodiments, a plurality of circuit boards may be disposed inside the housing. Each circuit board may include a signal interface exposed at a corresponding first cut-out hole, and a power interface exposed at a corresponding second cut-out hole.

The present disclosure provides a circuit board, which may be used in the cryptocurrency mining computing device. The circuit board may include a signal interface and a power interface. The signal interface may be located at a first end of the circuit board, and the power interface may be located at a second end of the circuit board, the second end being opposite the first end.

In some embodiments, the signal interface and the power interface of the circuit board may be located at diagonal locations on the circuit board. In some embodiments, the signal interface and the power interface may be located on a same side of the circuit board.

The disclosed cryptocurrency mining computing device and the circuit board may include at least the following advantages. In the present disclosure, the signal interface and the power interface of the circuit board are provided at the first end and the opposite second end of the circuit board, respectively. The first cut-out hole of the housing for exposing the signal interface of the circuit board and the second cut-out hole of the housing for exposing the power interface of the circuit board are provided at a first end and an opposite second end of the housing, respectively. The configuration of the housing and the circuit board effectively increases the distance between the signal interface and the power interface, thereby reducing or eliminating signal interference. In the present disclosure, the signal interface and the power interface of the circuit board are distant from one another inside the housing. This arrangement enables the cryptocurrency mining computing device to operate normally.

Referring back to FIG. 6, FIG. 6 shows a computing device 100 having a housing 50 and a circuit board 10 disposed inside the housing 50. FIGs. 7-11 show an embodiment of the computing device 100, the housing 50, and the circuit board 10. The computing device 100 may be referred to as a cryptocurrency mining computing device 100. The computing device may include the housing 50. The housing 50 may include a first cut-out hole 711 and a second cut-out hole 712. The first cut-out hole 711 may be located at a first end of the housing 50, and the second cut-out hole 712 may be located at a second end of the housing 50, the first end being opposite the second end. The computing device 100 may include a circuit board 10. The circuit board 10 may be disposed inside the housing 50. The circuit board 10 may include a signal interface 721 and a power interface 722. In some embodiments, the signal interface 721 may be located at a first end of the circuit board 10, and the power interface 722 may be located at a second end of the circuit board 10, the second end being opposite the first end. The signal interface 721 may be exposed to an outside environment through the first cut-out hole 711, and the power interface 722 may be exposed to the outside environment through the second cut-out hole 712.

In the cryptocurrency mining computing device 100, the circuit board 10 may be a computing circuit board configured to perform various computations for mining the cryptocurrency. In some embodiments, the first end of the housing 50 may be a top end of the housing 50, and the second end of the housing 50 may be a bottom end of the housing 50, as shown in FIGs. 7-9. In other words, the first cut-out hole 711 may be provided at a top end of the housing 50, and the second cut-out hole 712 may be provided at a bottom end of the housing 50. In this configuration, the circuit board 10 may be vertically disposed inside the housing 50, with the signal interface 721 exposed to the outside environment through the first cut-out hole 711, and the power interface 722 exposed to the outside environment through the second cut-out hole 712. By exposing the signal interface 721 and the power interface 722 through the first cut-out hole 711 and the second cut-out hole 712 located at the top end and the bottom end of the housing 50, the signal interface 721 and the power interface 722 are separated at a greater distance than in a conventional computing device. The portion of the signal interface 721 exposed to the outside environment at the first cut-out hole 711 may be electrically connected to a controller board disposed at the top end of the housing 50 through wires. The portion of the power interface 722 exposed to the outside environment at the second cut-out hole 712 may be electrically connected with a power source. Through these connections, the circuit board 10 may be connected with the controller board and the power source. Such connections significantly reduce or eliminate the signal interference between the power interface 722 and the signal interface 712. A shape of the first cut-out hole 711 may match with a shape of the signal interface 721, and a shape of the second cut-out hole 712 may match with a shape of the power interface 722. The circuit board 10 may be fixedly mounted inside the housing 50 through couplings or fittings between the first cut-out hole 712, the second cut-out hole 722 and the signal interface 721, the power interface 722.

In the disclosed cryptocurrency mining computing device 100, the signal interface 721 and the power interface 722 are respectively disposed at a first end and an opposite second end of the circuit board 10. In addition, the first cut-out hole 711 on the housing 50 for exposing the signal interface 721 and the second cut-out hole 712 for exposing the power interface 722 are respectively disposed at a first end and an opposite second end of the housing 50. This arrangement increases the distance between the signal interface 721 and the power interface 722 on the circuit board 10. Thus, the signal interface 721 and the power interface 722 of the circuit board 10 may be separately disposed in the housing 50 at a greater distance than in conventional circuit boards, thereby significantly reducing or eliminating signal interference, which enables the computing device 100 to operate normally.

In some embodiments, the signal interface 721 and the power interface 722 on the circuit board 10 may be located at diagonal locations on the circuit board 10. The diagonal locations refer to any locations of the signal interface 721 and the power interface 722, which, when connected, are not in parallel with a side edge of the circuit board 10. Correspondingly, the first cut-out hole 711 and the second cut-out hole 712 of the housing 50 may be located at diagonal locations on the housing 50. The diagonal locations of the first cut-out hole 711 and the second cut-out hole 712 refer to locations on the housing 50, which when connected, are not in parallel with a side edge of the housing 50, as long as the locations of the first cut-out hole 711 and the second cut-out hole 712 correspond to the locations of the signal interface 721 and the power interface 722. In some embodiments, for the convenience of connecting the circuit board 10 inside the housing 50, and connecting the interfaces on the housing 50 with external devices, as shown in FIG. 11, the power interface 722 and the signal interface 721 may be located on a same side of the circuit board 10 (still at two ends of the circuit board 10) . Correspondingly, the first cut-out hole 711 and the second cut- out hole 712 of the housing 50 may be located at a same side of the housing 50. The first cut-out hole 711 and the second cut-out hole 712 may be disposed at a rear side of the housing 50. In practical implementations, the locations of the signal interface 721 and the power interface 722 on the circuit board 10 and the locations of the first cut-out hole 711 and the second cut-out hole 712 may be determined based on actual needs.

To stably mount or fix the circuit board 10 inside the housing 50, the cryptocurrency mining computing device 100 may include a mounting mechanism. The mounting mechanism may be configured to stably mount the circuit board 10 inside the housing 50, such that the signal interface 721 is stably connected with the controller board and the power interface 722 is stably connected with the power source, thereby enabling the computing device 100 to operate normally.

In some embodiments, the mounting mechanism can take various structural forms, as long as the mounting mechanism can stably fix or mount the circuit board 10 inside the housing 50. As shown in FIG. 7 and FIG. 11, in some embodiments, the mounting mechanism may include a first slot 723 and a first raised portion (not shown in figures) configured to fit with the first slot 723. The first slot 723 may be located on a first side of the circuit board 10. The housing 50 may include a first side panel 713 corresponding to the first side of the circuit board 10. The first raised portion may be disposed on an inner surface of the first side panel 713. The first raised portion may snap-fit with the first slot 723 when inserted or pressed into the first slot 723. In other words, the mounting mechanism includes the first slot 723 located on a first side of the circuit board 10 and the first raised portion located on the inner surface of the first side panel 713. The first raised portion snap-fits with the first slot 723 when the first raised portion is inserted or pressed into the first slot 723. Through the mounting mechanism, the first side of the circuit board 10 can be connected with the first side panel 713, thereby stably mounting the circuit board 10 inside the housing 50, which enables the cryptocurrency mining computing device 100 to operate normally.

In some embodiments, to further enhance the mounting stability of the circuit board 10 inside the housing 50, as shown in FIG. 7, FIG. 10, and FIG. 11, the mounting mechanism may further include a second slot 724 and a second raised portion (not shown in the figures) configured to fit with the second slot 724. The second slot 724 may be disposed at a second side of the circuit board 10, the second side opposite the first side of the circuit board 10, where the first slot 723 is located. The housing 50 may include a second side panel 714 disposed opposite the first side panel 713. The second side panel 714 corresponds to the second side of the circuit board 10. The second raised portion may be located on an inner surface of the second side panel 714, and may snap-fit with the second slot 724 when inserted or pressed into the second slot 724. In other words, the mounting mechanism may further include the second slot 724 located at the second side of the circuit board 10 and the second raised portion located on the inner surface of the second side panel 714 of the housing 50. The second raised portion snap-fits with the second slot 724, thereby connecting the second side of the circuit board 10 with the second side panel 714 of the housing 50. Thus, in some embodiments, two opposite sides of the circuit board 10 are respectively connected with the housing 50, thereby mounting the circuit board 10 more stably inside the housing 50, which enables the cryptocurrency mining computing device 100 to operate normally. In some embodiments, the mounting mechanism may include a plurality of first slots 723 and a plurality of corresponding first raised portions, and/or a plurality of second slots 724 and a plurality of corresponding second raised portions, which can further enhance the stability of the mounting of the circuit board 10 to the housing 50.

To improve the heat dissipation capability of the cryptocurrency mining computing device 100, as shown in FIG. 7 and FIG. 10, a plurality of mounting holes (not labeled in the figures) separated from one another may be provided on the first side panel 713 of the housing 50 along a length direction of the first side panel 713. In other words, the plurality of mounting holes may be arranged along a height direction of the housing 50. At least one fan 731 may be mounted at each mounting hole. A plurality of heat dissipation regions 741 separated from one another may be provided on the second side panel 714 of the housing 50 in a length direction of the second side panel 714. In other words, the plurality of heat dissipation regions 741 may be arranged in the height direction of the housing 50. Each heat dissipation region 741 may correspond to a mounting hole. Each heat dissipation region 741 may be provided with a plurality of venting holes 742. By providing the plurality of mounting holes mounted with a plurality of fans 731 on the first side panel 713 of the housing 50, and by providing the plurality of heat dissipation regions 741 having a plurality of venting holes 742 on the second side panel 714 of the housing 50, and by positioning each fan 731 correspondingly with each heat dissipation region 741, the air flow inside the housing 50 may be separated into a plurality of layers of air flow, thereby increasing the air pressure inside the housing 50 and increasing the velocity of the air flow inside the housing 50. As a result, the fans 731 may take away more heat from the inner space of the housing 50, thereby enhancing the heat dissipation capability of the cryptocurrency mining computing device 100. In some embodiments, the heat sink disposed on the chips on the circuit board 10 may be positioned corresponding to the second side panel 714, such that the heat from the heat sink can be dissipated outside of the housing 50 through the heat dissipation regions 741 and the venting holes 742.

In some embodiments, to further improve the heat dissipation capability of the cryptocurrency mining computing device 100, as shown in FIG. 7, a plurality of fans 731 may be mounted at each mounting hole. As shown in FIG. 7, two groups of fans 731 are mounted at two mounting holes. At each mounting hole, a group of fans 731 may be mounted in a stacked configuration, as shown in FIG. 7. By providing a plurality of fans 731 in a stacked configuration at each mounting hole, the volume of the air flow inside the housing 50 can be increased, thereby increasing the pressure inside the housing 50 and the velocity of the air flow inside the housing 50. As a result, the fans 731 can take out more heat from the inner space of the housing 50, thereby further enhancing the heat dissipation capability of the cryptocurrency mining computing device. Furthermore, by providing the two mounting holes side by side with each other on a same side panel of the housing 50, the two groups of fans 731 are mounted side by side on the side panel. By providing two groups of fans 731 mounted side by side, the amount of airflow from the inside of the housing to the outside of the housing may be increased as compared to a situation where a single mounting hole is provided on the side panel with multiple fans mounted in a stacked configuration. Moreover, with the fans disposed side by side, the travel distance of the heat dissipating airflow from the circuit boards to the outside of the housing is reduced, and the airflow resistance is also reduced. Therefore, the heat dissipation efficiency may be improved.

In practical implementations, the number of mounting holes, the number of heat dissipation regions 741, and the number of fans 731 mounted at each mounting hole can be determined based on actual heat generated by the computing device 100. For example, in some embodiments, two fans 731 may be mounted at each mounting hole, and two mounting holes and two heat dissipation regions 741 may be provided. The fans 731 may be mounted at the mounting hole through any suitable mounting methods, as long as the fans 731 are mounted stably at the mounting hole. For example, each fan 731 may include one or more first screw holes at a periphery of the fan 731. The first side panel 713 of the housing 50 may be provided with one or more second screw holes at locations corresponding to the locations of the first screw holes. A long screw may be inserted into the first screw holes of the plurality of stacked fans 731 to couple with the second screw hole on the first side panel 713. In this fashion, the fans 731 may be installed, which requires simple structures and is easy to implement.

As shown in FIG. 7, FIG. 8, and FIG. 9, the housing 50 may include a plurality of first cut-out holes 711 and a plurality of second cut-out holes 712. The plurality of first cut-out holes 711 and the plurality of second cut-out holes 712 may be disposed along a width direction of the housing 50, separated from one another. In some embodiments, a plurality of circuit boards 10 may be mounted inside the housing 50. The signal interface 721 of each circuit board 10 may be exposed to the outside environment through a corresponding first cut-out hole 711. The power interface 722 of each circuit board 10 may be exposed to the outside environment through a corresponding second cut-out hole 712. By providing a plurality of first cut-out holes 711 and second cut-out holes 712 on the housing 50, a plurality of circuit boards 10 may be mounted inside the housing 50, which increase the computing capability (e.g., hash rate) of the cryptocurrency mining computing device 100, thereby increasing the performance of the computing device 100. In some embodiments, the number of first cut-out holes 711 and second cut-out holes 712 on the housing 50, and the number of circuit boards 10 may be determined based on the demand for the computing capability (e.g., hash rate) and the size of the housing 50. For example, the housing 50 may include four first cut-out holes 711 and four second cut-out holes 712, and four circuit boards 10 may be mounted inside the housing 50.

As shown in FIG. 11, the circuit board 10 includes the signal interface 721 and the power interface 722. The signal interface 721 may be located at a first end of the circuit board 10, and the power interface 722 may be located at a second end of the circuit board 10, the second end opposite the first end.

The disclosed circuit board may be implemented in a cryptocurrency mining computing device. By providing the signal interface and the power interface at the opposite first end and second end of the circuit board, the first cut-out hole and the second cut-out hole of the housing for exposing the signal interface and the power interface can be provided at a first end and an opposite second end of the housing. This configuration increases the distance between the signal interface and the power interface on the circuit board, as compared to a conventional circuit board. This configuration enables the signal interface and the power interface to be mounted to the housing at a greater distance as compared to the configuration in a conventional computing device, thereby significantly reducing or eliminating the signal interference, which enables the cryptocurrency mining computing device to operate normally.

FIG. 40 is schematic side view of a housing 4010 for a computing device 4000, in accordance with an embodiment of the present disclosure. Computing device 4000 may be an embodiment of any of the computing devices disclosed herein. Housing 4010 may be used for any of the computing devices disclosed herein. In addition, features included in housing 4010 may be included in any other housing disclosed herein.

Housing 4010 may include at least one fan disposed at each end of the housing in a length direction. As shown in FIG. 40, a fan 4030A may be mounted at a first end of the housing 4010, and a fan 4030B may be mounted at a second end of the housing 4010. The fan 4030A may be mounted at an air inlet (opening) of the housing 4010, and the fan 4030B may be mounted at an air outlet (opening) of the housing 4010. The

fans

4030A and 4030B may be operated together to direct air to flow from the air inlet into the inner space of the housing 4010, where the air exchanges heat with the chip heat dissipating structures mounted on chips of one or more circuit boards disposed inside the housing 4010, and to flow from the inner space of the housing 4010 out of the housing through the air outlet. Thus, heat may be dissipated from the circuit board to the outside environment of the housing 4010. In some embodiments, multiple circuit boards may be disposed inside the housing 4010, with each circuit board including multiple (e.g., 20, 30, 40, 50, 60, 100 or more) chips mounted thereon. When the fans are mounted on both ends of the housing in the length direction, the airflow path is long, and traditional heat dissipation may cause relatively large temperature gradient between opposite sides of the housing. To address this issue, in some embodiments of the present disclosure, the inside of the housing 4010 may be divided into a plurality of spaces by physical separators (not shown in figure) , each space defining an airflow channel. In some embodiments, each of the plurality of circuit boards may be disposed in a divided space. In some embodiments, a size of each airflow channel may be determined based on the sizes of the circuit board. For example, when different chips and/or different chip heat dissipating structures are mounted on different circuit boards, the sizes of the circuit boards disposed in parallel inside the housing 4010 may be different. Accordingly, the airflow channels may be defined to have different sizes, which may create a uniform temperature distribution among the airflow channels in the housing 4010.

FIG. 41 is a perspective view of a housing 4110 for a computing device, in accordance with an embodiment of the present disclosure. Housing 4110 may be used for any of the computing devices disclosed herein. In addition, features included in housing 4110 may be included in any other housing disclosed herein. A plurality of circuit boards may be vertically disposed inside the housing 4110. FIG. 41 shoes three

circuit boards

4121, 4122, and 4123 may be disposed inside the housing 4110, although any suitable number of circuit boards may be included. The housing 4110 may include a plurality of mounting holes on a side panel 4130. The

circuit boards

4121, 4122, and 4123 are disposed perpendicular to the side panel 4130. At each mounting hole on the side panel 4130, a fan may be mounted to the housing 4110. FIG. 41 shows two mounting holes on the side panel 4130, and two

fans

4131 and 4132 are mounted at the two mounting holes. Thus, the

fans

4131 and 4132 are disposed side by side with one another. As compared to the fans shown in FIG. 7, the

fans

4131 and 4132 may be different from the fans 731 shown in FIG. 7. The fans 731 included in the housing 50 in FIG. 7 may generate larger air volume and air pressure than the

fans

4131 and 4132 shown in FIG. 41. A larger amount of heat may be dissipated by the fans 731 shown in FIG. 7. The fans 731 shown in FIG. 7 and the

fans

4131, 4132 shown in FIG. 41 may be designed for housings or computing devices of different specified power.

Heat Dissipating Structure

Heat dissipation is an important factor that affects performance of a computing device. In many applications, heat dissipation often becomes the bottle neck that prevents further improvement to the performance of a chip, a computing board, or a computing device. In current market, most computing boards, including those used for cryptocurrency mining, include chips mounted to a single side of a PCB, rather than both side of the PCB, as provided in the present disclosure. Significant additional heat is generated by the additional chips mounted to the other side of the PCB. Conventional technology does not provide an efficient heat dissipation solution to dissipate the additional heat generated by the additional chips mounted on the bottom side of the PCB, particularly when there are a large number of chips on both sides (e.g., 10, 20, 30, 40, 50, etc. ) . For example, in the industry of cryptocurrency mining, no solution has been developed that can make heat dissipation both technically practical and cost effective to justify the placement of chips on both side of a PCB.

In conventional technologies, heat sinks are mounted to top surfaces of chips using a heat conductive glue. However, traditional heat conductive glue has a thermal conductivity of 2 Watt/meter/℃ (or W/ (m·C) ) , which cannot provide effecient heat dissipation when a large number of chips are mounted to both sides of a PCB.

The present disclosure provides a chip heat dissipating structure for dissipating heat generated by chips, a chip structure, a circuit board, and a computing device, such as a supercomputing device. The technical solution provided in the present disclosure overcomes disadvantages of conventional technologies relating to dissipating heat generated by a large number of chips.

In some embodiments, the present disclosure provides a chip heat dissipating structure. The chip heat dissipating structure may be mounted on chips, such as top surfaces of chips that may be mounted on a PCB. The chip heat dissipating structure may include a coating coated on or over a chip (such as a top surface of a chip) . The coating may include at least one metal-based layer. In some embodiments, the at least one metal-based layer may include a first metal-based layer and a second metal-based layer. The chip heat dissipating structure may include a heat sink connected or coupled with the coating. In some embodiments, the first metal-based layer may be coated over the chip, and the second metal-based layer may be coated over the first metal-based layer. In some embodiments, the chip may include a wafer and an encapsulation structure (or a sealing structure) . The coating may be coated over the wafer and the encapsulation structure. In some embodiments, a top surface of the wafer may be exposed (e.g., not covered by the encapsulation structure) .

In some embodiments, an area of the coating may be the same as an area of a top surface of the chip. In some embodiments, the first metal-based layer may include a layer of a metal alloy. In some embodiments, a thickness of the first metal-based layer may be 0.1 –0.5 microns. In some embodiments, the second metal-based layer may include a copper layer. In some embodiments, a thickness of the second metal-based layer may be 2 –6 microns. In some embodiments, an area of the first metal-based layer and an area of the second metal-based layer are the same. In some embodiments, the heat sink is welded to the coating using a welding material layer. In some embodiments, the welding material layer may include metal tin. In some embodiments, a thickness of the welding material layer may be 0.1 –0.15 millimeter (mm) . In some embodiments, an area of the welding material layer and an area of the coating are the same. In some embodiments, an area of the welding material layer is the same as an area of a bottom surface of a heat sink. In some embodiments, if a top surface of the wafer is at the same height as a top surface of the encapsulation structure, then the coating has a uniform thickness. If the top surface of the wafer is lower than the top surface of the encapsulation structure, the coating may fill in a cavity formed by the top surface of the wafer and portions of the encapsulation structure that surround the top surface of the wafer. If the top surface of the wafer is higher than the top surface of the encapsulation structure, the wafer may appear protruding into the coating. In other words, a portion of the coating covering the top surface of the wafer is located higher than other portions of the coating covering the top surface of the encapsulation structure.

The present disclosure provides a chip structure, including a chip and a chip heat dissipating structure mounted to the chip. The present disclosure also provides a circuit board including at least one chip structure disclosed herein. The present disclosure further provides a computing device, such as a supercomputing device. The computing device may include at least one circuit board disclosed herein.

The present disclosure provides a chip heat dissipating structure that includes a coating. The chip heat dissipating structure may be mounted to a chip to dissipate heat generated by the chip. The coating may be disposed over the wafer and the encapsulation structure of the chip to cover the wafer and the encapsulation structure. In some embodiments, the coating may include at least one metal-based layer. In some embodiments, the at least one metal-based layer may include a first metal-based layer and a second metal-based layer. A heat sink may be disposed on (or mounted to) the coating in a suitable manner that can facilitate heat transfer. The two metal-based layers may be deposited onto the top surface of a chip through any suitable method, such as physical sputtering. In some embodiments, the heat sink may be welded to the metal-based layers using a welding material layer, thereby fixedly connecting the heat sink to the top portion of the chip. In some embodiments, metal tin may be a primary material included in the welding material layer. The metal-based layers have a higher thermal conductivity than epoxy, a traditional material for gluing a heat sink to a chip. The disclosed chip heat dissipating structure resolves the bottle neck of heat dissipation, and can significantly improve chip heat dissipation efficiency, thereby eliminating damages to the chips caused by excessive heat.

The technical solutions of the present disclosure can be used not only in the currently available chips, but also in future chips. In conventional chip technologies, an exposed die packaging may be used to package the wafer. The wafer may be exposed to an outer environment, which can achieve better heat dissipation. The wafer may be silicon wafer. In the exposed die packaging, a heat sink may be glued to the top surface of a chip using a traditional heat conductive glue. As discussed above, the traditional heat conductive glue has a low thermal conductivity, which is typically lower than 2 W/ (m·C) . This low thermal conductivity results in inefficient heat dissipation for chips, which becomes a bottle neck for heat dissipation at device or system levels. To achieve better heat dissipation efficiency, if a solder having a high thermal conductivity (typically higher than 60 W (m·C) ) can replace the traditional heat conductive glue, heat dissipation efficiency for the chips can be significantly improved. However, a typical solder cannot be satisfactorily welded to the wafer and the encapsulation structure of the chip.

The chip heat dissipating structure, chip structure, circuit board, and computing device (e.g., supercomputing device) provided in the present disclosure can address the technical disadvantages faced by the conventional technologies.

FIG. 12 is a schematic diagram of a chip heat dissipating structure, in accordance with an embodiment of the present disclosure. FIG. 13 is a schematic diagram of a chip heat dissipating structure, in accordance with another embodiment of the present disclosure. FIG. 14 is a schematic diagram of a chip heat dissipating structure, in accordance with another embodiment of the present disclosure. As shown in FIG. 12, FIG. 13, and FIG. 14, the chip heat dissipating structure may be mounted to a chip to dissipate heat generated by the chip. In some embodiments, the chip heat dissipating structure may include a coating 1201. The coating 1201 may include at least one metal-based layer. In some embodiments, the at least one metal-based layer may include a first metal-based layer 1203 and a second metal-based layer 1204. In some embodiments, the first metal-based layer 1203 may be disposed over the second metal-based layer 1204. In some embodiments, the second metal-based layer 1204 may be disposed over the first metal-based layer 1203. The chip may include a wafer 1208, an encapsulation structure 1210, and a substrate 1211. Any suitable material, such as silica and epoxy resin may be used in the encapsulation structure 1210. The encapsulation structure 1210 may be provided with a cavity, the wafer 1208 may be disposed in the cavity, and the encapsulation structure 1210 may package the wafer 1208. In exposed die packaging, a top surface of the wafer 1208 may be exposed to an outside environment (i.e., not sealed by the encapsulation structure) . The encapsulation structure 1210 may be fixedly mounted to a side of the substrate 1211. Another side of the substrate 1211 may be provided with at least one tin ball 1212 for connecting with a circuit board, such as a printed circuit board, thereby mounting the chip to the printed circuit board.

As discussed above, a typical solder cannot be satisfactorily welded with the wafer 1208 and the encapsulation structure 1210. The technical solutions of the present disclosure provides a coating 1201 over the wafer 1208 and the encapsulation structure 1210, thereby enabling the chip and an external heat sink to be connected through welding.

The wafer 1208 may have any suitable shape, such as a circular shape, a rectangular shape, a square shape, a trapezoidal shape, or other regular or non-regular shape. The present disclosure does not limit the shape of the wafer 1208. In addition, the present disclosure does not limit the material used to produce the wafer 1208.

The present disclosure also does not limit the shape of the encapsulation structure 1210, as long as the encapsulation structure 1210 can package the wafer 1208. In addition, the present disclosure does not limit the material of the encapsulation structure 1210.

In some embodiments, the coating 1201 may include at least one metal-based layer. In some embodiments, the at least one metal-based layer may include a first metal-based layer 1203 and a second metal-based layer 1204. The first metal-based layer 1203 and the second metal-based layer 1204 may use different or the same material. In some embodiments, the thicknesses of the first metal-based layer 1203 and the second metal-based layer 1204 may be the same or different. Areas of the first metal-based layer 1203 and second metal-based layer 1204 may be the same or different.

In some embodiments, the coating 1201 may have a grid shape. In some embodiments, at least one of the first metal-based layer 1203 and the second metal-based layer 1204 may have a grid shape. Grid shapes may reduce the material used in the coating 1201, thereby reducing cost.

In some embodiments, the chip heat dissipating structure may include a heat sink 1202. The coating 1201 may be applied or coated to a chip, such as a top surface of a chip. The coating 1201 may cover the entire top surface of the chip or may cover a substantial portion of the top surface of the chip. In some embodiments, the coating 1201 may cover the wafer 1208 and the encapsulation structure 1210. The heat sink 1202 may be mounted to the coating 1201, for example, through welding. That is, the heat sink 1202 may be welded to the coating 1201. The present disclosure does not limit the shape, size, or type of the heat sink 1202.

FIG. 15 is a schematic diagram of a heat sink 1202, in accordance with an embodiment of the present disclosure. The heat sink 1202 may be an embodiment of other heat sinks disclosed herein, including the

heat sinks

13A, 13B, 14A, and 14B. As shown in FIG. 15, the heat sink 1202 may include a base plate 1205 and at least one heat dissipating wing 1206. Each heat dissipating wing 1206 may be mounted to (e.g., fixedly connected with) the base plate 1205. The base plate 1205 may be mounted to (e.g., connected with) the coating 1201 through welding.

In the present disclosure, the chip heat dissipating structure includes the coating 1201. The chip heat dissipating structure may be mounted on the chip, with the coating 1201 covering the wafer 1208 and the encapsulation structure 1210 of the chip. The coating 1201 includes at least one metal-based layer. In some embodiments, the at least one metal-based layer may include a first metal-based layer 1203 and a second metal-based layer 1204, with the second metal-based layer 1204 disposed over the first metal-based layer 1203. The heat sink 1202 may be disposed on the coating 1201. The two metal-based layers may be deposited onto the top surface of a chip through any suitable method, such as physical sputtering. In some embodiments, the heat sink may be welded to the metal layers using a welding material layer, thereby fixedly connecting the heat sink to the top portion of the chip. In some embodiments, metal tin may be a primary material included in the welding material layer. The metal-based layers have a higher thermal conductivity than epoxy, a traditional material for gluing a heat sink to a chip, and resolve the bottle neck of heat dissipation. The disclosed chip heat dissipating structure can significantly improve chip heat dissipation efficiency, thereby eliminating damages to the chips caused by excessive heat.

FIG. 16 is a schematic diagram of a chip heat dissipating structure, in accordance with another embodiment of the present disclosure. FIG. 17 is a schematic diagram of a chip heat dissipating structure, in accordance with another embodiment of the present disclosure. Based on the embodiment of FIG. 12, as shown in FIG. 16 and FIG. 17, the first metal-based layer 1203 may be coated over a top surface of a chip (thereby covering the top surface of the chip) , and the second metal-based layer 1204 may be coated over the first metal-based layer 1203 (thereby covering the first metal-based layer 1203) . In some embodiments, an area of the coating 1201 is the same as an area of a top surface of the chip. In some embodiments, the first metal-based layer 1203 is a layer of a metal alloy. The thickness of the first metal-based layer 1203 may be 0.1 –0.5 microns. In some embodiments, the second metal-based layer 1204 may be a copper layer. The thickness of the second metal-based layer may be 2 –6 microns. In some embodiments, an area of the first metal-based layer 1203 may be the same as an area of the second metal-based layer 1204. In some embodiments, the heat sink 1202 may be welded to the coating 1201 through a welding material layer 1209. In some embodiments, the welding material layer 1209 may include metal tin. A thickness of the welding material layer 1209 may be 0.1 –0.15 mm. In some embodiments, an area of the welding material layer 1209 and an area of the coating 1 may be the same. In some embodiments, an area of the welding material layer 1209 and an area of a bottom surface of the heat sink 1202 may be the same.

In some embodiments, if a top surface of the wafer 1208 is at the same height as (e.g., flushes with) a top surface of the encapsulation structure 1210, the thickness of the coating 1201 may be uniform. If the top surface of the wafer 1208 is lower than the top surface of the encapsulation structure 1210, the coating 1201 may fill in a cavity formed by the top surface of the wafer 1208 and portions of the encapsulation structure 1210 surrounding the top surface of the wafer 1208. The portions of the encapsulation structure 1210 surrounding the top surface of the wafer 1208 have top surfaces that are higher than the top surface of the wafer 1208. If the top surface of the wafer 1208 is higher than the top surface of the encapsulation structure 1210, the portion of the wafer 1208 that is higher than the top surface of the encapsulation structure 1210 may appear protruding into the coating 1201. In other words, a portion of the coating 1201 covering the top surface of the wafer 1208 is higher than other portions of the coating 1201 covering the top surface of the encapsulation structure 1210.

In some embodiments, on the basis of the embodiment shown in FIG. 12, the first metal-based layer 1203 may be coated to and cover the top surfaces of the wafer 1208 and the encapsulation structure 1210. The second metal-based layer 1204 may be coated to and cover the top surface of the first metal-based layer 1203.

In some embodiments, the material of the first metal-based layer 1203 may include an alloy. That is, the first metal-based layer 1203 may be a layer of a metal alloy, such as a stainless steel layer. In some embodiments, the material of the second metal-based layer 1204 may include copper. That is, the second metal-based layer 1204 may be a copper layer. Thus, the layer of metal alloy may cover the top surfaces of the wafer 1208 and the encapsulation structure 1210, and the copper layer may cover the top surfaces of the layer of metal alloy.

To facilitate the connection between the two metal-based layers and the chip and heat sink 1202, and to facilitate heat conduction of the two metal-based layers and heat dissipation for the chip, the thicknesses of the two metal-based layers may be: 0.1 –0.5 microns for the first metal-based

layer

1203, and 2 –6 microns for the second metal-based layer 1204. In some embodiments, the thickness of the first metal-based layer 1203 may be 0.15 microns. In some embodiments, the thickness of the second metal-based layer 1204 may be 3 microns.

In some embodiments, a welding material layer may be provided onto the coating 1201. For example, the welding material layer 1209 may be provided onto the second metal-based layer 1204. The heat sink 1202 may be welded with the welding material layer 1209. In some embodiments, the material of the welding material layer 1209 may include metal tin. In some embodiments, the thickness of the welding material layer 1209 may be 0.1 –0.15 mm. In some embodiments, the thickness of the welding material layer 1209 may be 0.13 mm. The thermal conductivity of the welding material layer 1209 may be greater than 60 W/ (m·C) , which can increase the heat dissipation efficiency as compared to typical gluing materials used for gluing the heat sink to the chip.

In some embodiments, an area of the coating 1201 may be the same as an area of the top surface of the chip. For example, the area of the coating 1201 may equal to the sum of an area of a top surface of the wafer 1208 and an area of a top surface of the encapsulation structure 1210. In some embodiments, an area of the first metal-based layer 1203 may be the same as an area of the top surface of the chip. As shown in FIG. 17, the area of the first metal-based layer 1203 is the same as the area of the top surface of the chip, and the area of the first metal-based layer 1203 is the same as the area of the second metal-based layer 1204.

FIG. 18 is a schematic diagram of a chip heat dissipating structure, in accordance with another embodiment of the present disclosure. As shown in FIG. 18, the area of the first metal-based layer 1203 is the same as the area of the top surface of the chip. An area of the first metal-based layer 1203 is different from an area of the second metal-based layer 1204.

In some embodiments, the area of the welding material layer 1209 may be provided in different implementation methods. In the first implementation method for providing the area of the welding material layer 1209, as shown in FIG. 17, the area of the first metal-based layer 1203 is the same as the second metal-based layer 1204. In addition, the area of the welding material layer 1209 is the same as the area of the coating 1201.

A second implementation method for providing the area of the welding material layer 1209 is illustrated in FIG. 19. FIG. 19 is a schematic diagram of a chip heat dissipating structure, in accordance with another embodiment of the present disclosure. As shown in FIG. 19, the area of the first metal-based layer 1203 is the same as the area of the second metal-based layer 1204. In addition, the area of the welding material layer 1209 is different from the area of the coating 1201.

A third implementation method for providing the area of the welding material layer 1209 is illustrated in FIG. 20. FIG. 20 is a schematic diagram of a chip heat dissipating structure, in accordance with another embodiment of the present disclosure. As shown in FIG. 20, the area of the first metal-based layer 1203 is the same as the area of the second metal-based layer 1204. In addition, the area of the welding material layer 1209 is the same as the area of the bottom surface of the heat sink 1202. In addition, the area of the welding material layer 1209 is different from the area of the coating 1201. The area of the welding material layer 1209 is the same as the area of the bottom surface of the heat sink 1202, which facilitates excellent connection between the heat sink 1202 and the welding material layer 1209.

A fourth implementation method for providing the area of the welding material layer 1209 is illustrated in FIG. 21. FIG. 21 is a schematic diagram of a chip heat dissipating structure, in accordance with another embodiment of the present disclosure. As shown in FIG. 21, the area of the first metal-based layer 1203 is the same as the area of the second metal-based layer 1204. In addition, the area of the welding material layer 1209 is the same as the area of the bottom surface of the heat sink 1202. The area of the welding material layer 1209 is the same as the area of the coating 1201.

The positional relationship between the coating 1201 and the chip can be implemented using different methods. A first implementation method for providing the positional relationship between the coating 1201 and the chip is illustrated in FIG. 22. FIG. 22 is a schematic diagram of a chip heat dissipating structure in accordance with an embodiment of the present disclosure. As shown in FIG. 22, if the top surface of the wafer 1208 is at the same height as the top surface of the encapsulation structure 1210, then the coating 1201 (for example, including the first metal-based layer 1203 and the second metal-based layer 1204) can be a uniform coating having a uniform thickness.

A second implementation method for providing the positional relationship between the coating 1201 and the chip is illustrated in FIG. 23. FIG. 23 is a schematic diagram of a chip heat dissipating structure in accordance with an embodiment of the present disclosure. As shown in FIG. 23, if the top surface of the wafer 1208 is lower than the top surface of the encapsulation structure 1210, then the thickness of the coating 1201 may not be uniform. A portion of the first metal-based layer 1203 of the coating 1201 may fill in a cavity formed by the top surface of the wafer 1208 and portions of the encapsulation structure 1210 surrounding the top surface of the wafer 1208. The portions of the encapsulation structure 1210 surrounding the top surface of the wafer 1208 have top surfaces that are higher than the top surface of the wafer 1208.

A third implementation method for providing the positional relationship between the coating 1201 and the chip is illustrated in FIG. 24. FIG. 24 is a schematic diagram of a chip heat dissipating structure in accordance with an embodiment of the present disclosure. As shown in FIG. 24, if the top surface of the wafer 1208 is higher than the top surface of the encapsulation structure 1210, then the thickness of the coating 1201 is not uniform. The wafer 1208 appears protruding into the first metal-based layer 1203 of the coating 1201. In other words, a portion of the coating 1201 covering the top surface of the wafer 1208 is higher than other portions of the coating 1201 covering the top surface of the encapsulation structure 1210.

The present disclosure provides a process for manufacturing the chip heat dissipating structure. In a step, a base wafer is cut to produce the wafer 1208. FIG. 25 illustrates a step of the process in which the base wafer is cut. The base wafer may be cut to form the wafer 1208.

In a step, the wafer 1208 is mounted to a substrate. FIG. 26 illustrates a step of the process in which a plurality of wafers are mounted to a plurality of substrates. For example, a plurality of wafers 1208 are mounted to a plurality of substrates 1211.

In a step, the wafer 1208 is encapsulated. FIG. 27 illustrates a step of the process in which a plurality of wafers are encapsulated by a plurality of encapsulation structures. For example, a plurality of wafers 1208 are encapsulated by a plurality of encapsulation structures 1210.

In a step, a tape mount is added. FIG. 28 illustrates a step of the process in which a tape mount is added to the chips and a strip is added to a bottom of the structure formed in the step shown in FIG. 27. For example, a tape mount may be added to each chip. A strip loading process may be applied to the structure. For example, a strip 1250 may be connected to the bottom portion of the structure including the wafers 1208, the substrates 1211, and the encapsulation structures 1210.

In a step, at least one metal-based layer may be applied to the structure including the wafers, substrates, encapsulation structures, and the tape mount. FIG. 29 illustrates a step of the process in which a coating 1201 including at least one metal-based layer is applied to the top surfaces of the wafers 1208 and the encapsulation structures 1210. In some embodiments, the at least one metal-based layer may include a first metal-based layer 1203 and a second metal-based layer 1204. The first metal-based layer 1203 may be first applied to the top surfaces of the wafers 1208 and the encapsulation structures 1210. In some embodiments, the first metal-based layer 1203 may also be applied to the top surface of the tape mount 1250. The second metal-based layer 1204 may be applied over the first metal-based layer 1203. Various methods may be used to apply the first metal-based layer 1203 and the second metal-based layer 1204, such as physical sputtering method or an electrical plating method.

FIG. 30 illustrates a step of the process in which the strip 1250 is separated from the rest of the structure including the wafers 1208, the substrates 1211, and the encapsulation structures 1210.

In a step, a strip singulation is performed. FIG. 31 illustrates a step of the process in which each chip is separated from the structure shown in FIG. 30, to obtain individual chips. The process may be referred to as a strip singulation.

In a step, welding is performed. FIG. 32 illustrates a step of the process in which welding is performed to connect various members. For example, a welding material layer 1209 may be applied to the second metal-based layer 1204 of the coating 1201. Then, a heat sink 1202 may be welded to the welding material layer 1209.

In the present disclosure, the chip heat dissipating structure includes the coating 1201, and the chip heat dissipating structure is mounted on the chip, with the coating 1201 covering the wafer 1208 and the encapsulation structure 1210 of the chip. The heat sink 1202 is welded to the coating 1201 through the welding material layer 1209. The coating 1201 includes at least one metal-based layer. In some embodiments, the at least one metal-based layer may include a first metal-based layer 1203 and a second metal-based layer 1204, with the first metal-based layer 1203 disposed over the wafer 1208 and the encapsulation structure 1210, and the second metal-based layer 1204 disposed over the first metal-based layer 1203. The heat sink 1202 may be disposed on the coating 1201. The two metal-based layers may be deposited onto the top surface of a chip through any suitable method, such as physical sputtering. In some embodiments, the heat sink may be welded to the metal-based layers using a welding material layer, thereby fixedly connecting the heat sink to the top portion of the chip. In some embodiments, metal tin may be a primary material included in the welding material layer. The metal-based layers have a higher thermal conductivity than epoxy, a traditional material for gluing a heat sink to a chip, and resolve the bottle neck of heat dissipation. The metal-based layers and the welding material layer 1209 further facilitate heat dissipation, thereby increasing chip heat dissipation efficiency, and eliminating damages to the chips caused by excessive heat.

FIG. 32 is a schematic diagram of a chip structure in accordance with an embodiment of the present disclosure. FIG. 33 is a schematic diagram of a chip structure in accordance with another embodiment of the present disclosure. As shown in FIG. 32 and FIG. 33, the chip structure includes the chip and the chip heat dissipating structure mounted on the chip. The chip heat dissipating structure may include any embodiment disclosed herein.

In some embodiments, the chip may include the wafer 1208, the encapsulation structure 1210, and the substrate 1211. The encapsulation structure 1210 may include a cavity, the wafer 1208 may be disposed in the cavity, and the encapsulation structure 1210 may package the wafer 1208. A top surface of the wafer 1208 may be exposed to an outside environment (i.e., not sealed by the encapsulation structure) , which is referred to as exposed die packaging. The encapsulation structure 1210 may be fixedly mounted on a side of the substrate 1211. Another side of the substrate 1211 may be provided with at least one tin ball 1212 for connecting with a circuit board, such as a printed circuit board, thereby mounting the chip onto the printed circuit board.

The chip heat dissipating structure may be disposed on the chip. The coating 1201 of the chip heat dissipating structure may be disposed over the wafer 1208 and the encapsulation structure 1210. The structure of the chip heat dissipating structure has been described above.

In some embodiments, the encapsulation structure 1210 may be provided with at least one hole. One or more of the at least one hole may be disposed with a heat conducting structure. In some embodiments, the heat conducting structure may include a metal heat conducting structure or a non-metal heat conducting structure. With such a structure, heat dissipation of the chip structure can be further improved.

In some embodiments, the metal heat conducting structure may include one or more of a copper, aluminum, silver, tin, gold, iron, and aluminum alloy. The non-metal heat conducting structure may include epoxy, ceramic, graphite, graphene, and water.

FIG. 34 is a schematic diagram of a circuit board in accordance with an embodiment of the present disclosure. As shown in FIG. 34, a circuit board 1213 may include at least one chip structure disclosed herein. The circuit board 1213 may be an embodiment of the circuit board 10 disclosed herein.

In some embodiments, the circuit board 1213 may include at least one chip structure disclosed herein. The chip structure may be fixedly connected with the circuit board 1213 through the tin balls.

The present disclosure does not limit the number of chip structures mounted on the circuit board 1213 and the locations of the chip structures. For example, the top surface of the circuit board 1213 may be mounted with at least one chip structure. In some embodiments, the top surface of the circuit board 1213 may be mounted with at least one chip structure, and the bottom surface of the circuit board 1213 may also be mounted with at least one chip structure.

The specific structures of the chip structures mounted on the circuit board 1213 may be the same or may be different. For example, one of the chip structures mounted on the circuit board 1213 may include a wafer having a top surface at the same height as the top surface of the encapsulation structure, and another one of the chip structures mounted on the circuit board 1213 may include a wafer having a top surface lower than the top surface of the encapsulation structure.

In some embodiments, the circuit board 1213 includes at least one chip structure disclosed herein mounted on at least one surface (e.g., top surface, bottom surface, or both) of the circuit board 1213. Chip heat dissipating structures disclosed herein may be mounted on the chip structures. At last one metal-based layer (e.g., one, two, three, or more metal-based layers) may be deposited onto the top surface of a chip through any suitable method, such as physical sputtering. In some embodiments, the heat sink may be welded to the metal layers using a welding material layer, thereby fixedly connecting the heat sink to the top portion of the chip. In some embodiments, metal tin may be a primary material included in the welding material layer. The metal-based layers have a higher thermal conductivity than epoxy, a traditional material for gluing a heat sink to a chip, and resolve the bottle neck of heat dissipation. The metal-based layers and the welding material layer 1209 further facilitate heat dissipation, thereby increasing chip heat dissipation efficiency, and eliminating damages to the chips caused by excessive heat. Further, heat is dissipated from the circuit board 1213, thereby eliminating damages to the circuit board 1213 and electronic components included on the circuit board 1213.

FIG. 35 is a schematic diagram of a supercomputing device 1280 in accordance with an embodiment of the present disclosure. As shown in FIG. 35, the supercomputing device 1280 may include at least one circuit board 1213. In some embodiments, the supercomputing device 1280 includes a plurality of circuit boards 1213 arranged in parallel. In some embodiments, the supercomputing device 1280 includes a housing 50 disclosed herein. The housing 50 may include one or more sliding slots configured to receive the circuit board 1213. The circuit board 1213 may slide into the sliding slot and be connected with the sliding slot. In some embodiments, at least two sides of the housing 50 of the supercomputing device 1280 may be mounted with fans. Heat dissipating wind channels of the fans may be aligned with heat dissipating chambers of the heat sinks mounted on the circuit boards 1213, which enable fast transferring of the heat generated by the circuit board 1213 from inside the housing 50 to outside of the housing 50, thereby improving the performance of the supercomputing device 1280.

In some embodiments, the supercomputing device 1280 may include one or more circuit boards 1213. The circuit boards 1213 may use any of the circuit boards disclosed herein, such as circuit boards 10. The functions and the structures of the circuit boards have been described above.

In some embodiments, a plurality of circuit boards 1213 may be arranged in parallel, and electrically connected in parallel. With such an arrangement, the supercomputing device may be a supercomputing server.

The circuit board 1213 may be connected to the supercomputing device 1280 through fixed connecting methods or slidable connecting methods. For example, in some embodiments, the housing 50 of the supercomputing device 1280 may be provided with one or more sliding slots. The circuit board 1213 may be slidably disposed in the sliding slot.

In some embodiments, when a plurality of circuit boards 1213 are included in the supercomputing device 1280, the structures of the circuit boards 1213 may be the same or different.

Each circuit board 1213 may include at least one chip structure disclosed herein. The chip structure may be fixedly connected with the circuit board 1213 through the tin balls.

The present disclosure provides a supercomputing device including one or more circuit boards 1213 disposed therein. Each circuit board 1213 includes at least one chip structure mounted thereon. A chip heat dissipating structure may be mounted on the chip structure. At least one metal-based layer (e.g., one, two, three, or more metal-based layers) may be deposited onto the top surface of a chip through any suitable method, such as physical sputtering. In some embodiments, the heat sink may be welded to the metal-based layers using a welding material layer, thereby fixedly connecting the heat sink to the top portion of the chip. In some embodiments, metal tin may be a primary material included in the welding material layer. The metal layers have a higher thermal conductivity than epoxy, a traditional material for gluing a heat sink to a chip. The disclosed chip heat dissipating structure resolves the bottle neck of heat dissipation, and can significantly improve chip heat dissipation efficiency, thereby eliminating damages to the chips caused by excessive heat. Further, heat is dissipated from the circuit board 1213, thereby eliminating damages to the circuit board 1213 and electronic components included on the circuit board 1213.

FIG. 36 is a schematic diagram of a circuit board 3600. The circuit board 3600 may include a PCB 3630, which may be made of a suitable material, such as aluminum, a flame retardant material (e.g., FR-4) , copper, etc. The circuit board 3600 may also include a heat conductive material layer 3625 mounted on a top surface of the PCB 3630, and a copper layer 3620 mounted over the heat conductive material layer 3625. A plurality of chips 3615 may be mounted on a top surface of the copper layer 3620. A first heat sink 3610 may be mounted on top surfaces of the chips 3615. On the bottom surface of the PCB 3630, a heat conductive material layer 3635 may be mounted thereon. The heat conductive material layer 3635 may be similar to the heat conductive material layer 3625. A copper layer 3640 may be mounted to the heat conductive material layer 3635, and a second heat sink 3650 may be mounted to the copper layer 3640. When a large number of chips are mounted to the PCB 3630, a significant amount of heat is generated by the chips.

FIG. 37 is a schematic diagram of a circuit board 3700, in accordance with an embodiment of the present disclosure. The circuit board 3700 may be an embodiment of the circuit boards disclosed herein, such as circuit board 10 and circuit board 1213. Circuit board 3700 includes a plurality of chips mounted to both sides of a PCB. As shown in FIG. 37, circuit board 3700 may include a PCB 3730. A first heat conductive material layer 3725 and a second heat conductive material layer 3735 are mounted to the top and bottom surfaces of the PCB 3730. A first copper layer 3720 and a second copper layer 3740 are respectively mounted to the first heat conductive material layer 3725 and the second heat conductive material layer 3735. A first plurality of chips 3715 are mounted to the first copper layer 3720, and a second plurality of chips 3745 are mounted to the second copper layer 3740. Each of the

chips

3715 and 3745 may be have a chip structure disclosed herein. A first heat sink 3710 is mounted to the top surfaces of the first plurality of chips 3715, and a second heat sink 3750 is mounted to the top surfaces of the second plurality of chips 3750. Each of the

heat sinks

3710 and 3750 may be a heat sink disclosed in the embodiments described above.

Each of the

heat sinks

3710 and 3750 may be any embodiment of the heat sinks disclosed herein, including, for example, the

heat sinks

13A and 13B, 14A and 14B, and 1202. Each of the

heat sinks

3710 and 3750 may be part of a chip heat dissipating structure described above. For example, in some embodiments, each of the

heat sinks

3710 and 3750 may be mounted to the chips through a coating coated on the chips, which may include at least one metal-based layer, and a welding material layer. In some embodiments, the at least one metal-based layer may include a first metal-based layer and a second metal-based layer. In some embodiments, the

heat sinks

3710 and 3750 may be welded to the coating on the chips through the welding material layer. Other methods may also be used to mount the

heat sinks

3710 and 3750 to the coating, such as gluing and non-gluing connection methods. In some embodiments, each heat sink can be an individual heat sink mounted to an individual chip. In some embodiments, the heat sink may be an integral heat sink connected to a plurality of chips. In some embodiments, the heat sink may include a heat tube with heat conductive materials disposed in the tube. In some embodiments, the heat sink may include a uniform temperature board. In some embodiments, the heat sink may use water cooling or other type of fluid cooling. The coating provides significantly better thermal conductivity than epoxy, a traditional material for gluing the heat sinks to the PCB. In addition, the welding material layer may also facilitate heat transfer from the coating to the heat sinks. As a result, chip heat dissipation efficiency can be significantly increased with the chip heat dissipating structure of the present disclosure. The performance of the disclosed circuit board 3700 can be significantly enhanced due to the arrangement of chips mounted on both sides of the PCB, and due to the highly efficient heat dissipation of the disclosed chip heat dissipating structures.

In FIG. 37, the first plurality of chips 3715 and the second plurality of chips 3745 are symmetrically disposed relative to the PCB 3730. Other arrangements of the chips are possible. For example, the chips may be arranged in a staggered configuration, as shown in FIG. 38. FIG. 38 is a schematic diagram of a circuit board 3800, in accordance with another embodiment of the present disclosure. The circuit board 3800 includes a PCB 3830, a first heat conductive material layer 3825 and a second heat conductive material layer 3835. The circuit board 3800 also includes a first copper layer 3820 and a second copper layer 3840. The circuit board 3800 further includes a first plurality of chips 3815 and a second plurality of chips 3845. A first heat sink 3810 is mounted to the first plurality of chips 3815 and a second heat sink 3850 is mounted to the second plurality of chips 3845. The circuit board 3800 may be similar to the circuit board 3700, except that the

chips

3815 and 3845 are arranged in a staggered configuration, rather than a symmetric configuration. On the PCB, the plurality of chips may be uniformly distributed or may be non-uniformly distributed. The present disclosure does not limit the fashion the chips are distributed.

Both of the embodiments shown in FIG. 37 and FIG. 38 include two copper layers, one disposed over the top surface of the PCB, and the other disposed over the bottom surface of the PCB. The number of the copper layer can be any suitable number, such as 4, 6, 8, etc. FIG. 39 is a schematic diagram of a circuit board 3900 having four copper layers, in accordance with an embodiment of the present disclosure. The PCB used in the circuit board 3900 is based on FR-4 material. Other materials, such as aluminum, copper, etc., may also be used for the PCB in place of or in combination with the FR-4 material. As shown in FIG. 39, the circuit board 3900 may include a first FR-4 layer 3935. A first copper layer 3930 is placed over the first FR-4 layer 3935. A second FR-4 layer 3925 is placed over the first copper layer 3930. A second copper layer 3920 is placed over the second FR-4 layer 3925. A plurality of chips 3915 are mounted on the second copper layer 3920. A heat sink 3910 is mounted on the plurality of chips 3915. On the bottom side of the first FR-4 layer 3935, a third copper layer 3940 may be mounted to the first FR-4 layer 3935. A third FR-4 layer 3945 may be mounted to the third copper layer 3940. A fourth copper layer 3950 may be mounted to the third FR-4 layer 3945. A second plurality of chips 3955 may be mounted to the fourth copper layer 3950. A second heat sink 3960 may be mounted to the second plurality of chips 3955. The chips and the heat sinks may be similar to the chips and heat sinks included in other embodiments.

Low heat dissipation efficiency has prevented the practical implementation of mounting chips to both sides of a PCB, such as PCB 3630. Embodiments of the present disclosure provide efficient heat dissipation technology that resolve the heat dissipation bottle neck issues in circuit board and computing devices. The technical solutions for heat dissipation in chips and/or circuit boards of the present disclosure can significantly increase the efficiency of heat dissipation in chips. Therefore, the present disclosure provides a circuit board, on which chips are mounted to both sides of a PCB.

In one aspect, the present disclosure provides a chip heat dissipating structure that can dissipate heat efficiently from the chip. The chip heat dissipating structure includes a coating applied to the chip. The coating may be a metal coating, and may include at least one metal-based layer. In some embodiments, the at least one metal based layer may include a first metal-based layer disposed over the chip and a second metal-based layer disposed over the first metal-based layer. A heat sink can then be mounted to the chip by a welding method. The heat sink may be welded to the coating on the chip through a welding material layer, such as tin. The metal coating has a heat conductivity that may be much greater than epoxy (e.g., 30 times greater) , a typical glue used for gluing the heat sink to the chip in conventional technologies. The combination of the metal coating and the metal welding material layer significantly increases the heat dissipation efficiency, thereby resolving the heat dissipation bottle neck and rendering it practical and cost effective to include a large number of chips on both sides of a circuit board.

In another aspect, the present disclosure provides a chip structure that includes a chip and the chip heat dissipating structure mounted to the chip for efficiently dissipate heat generated by the chip.

In a further aspect, the present disclosure provides a circuit board that includes a large number of chips mounted on both sides of a printed circuit board ( “PCB” ) . Each chip may have the disclosed chip structure, which includes the disclosed chip heat dissipating structure. Heat generated by the large number of chips may be efficiently dissipated by the disclosed chip heat dissipating structures provided to the chips. Additional heat sinks may be mounted to the PCB at gaps between adjacent chips on each side of the PCB to provide auxiliary heat dissipation functions, thereby further improving the heat dissipation efficiency. The PCB may include a substrate having an excellent heat conductivity, such as aluminum. The PCB may include heat conductive layers provided on both sides of the substrate. Thus, the PCB may also function as a heat conducting board to facilitate a uniform temperature distribution on both sides of the PCB.

Various embodiments of the present disclosure further provide a housing for accommodating the circuit board. The housing may include multiple mounting holes for mounting cooling fans. At each mounting hole, one or more cooling fans may be mounted (when multiple fans are mounted, they may be mounted in a stacked configuration) . Each mounting hole may correspond to a heat dissipation region of the circuit board. Thus, a short air flow path may be provided to dissipate heat. Through the multiple mounting holes, fans mounted at the mounting holes, and the corresponding heat dissipation regions, air flow inside the housing may be separated into a plurality of layers of air flow, thereby increasing the air pressure inside the housing and increasing the velocity of the air flow. The housing can further facilitate heat dissipation from the circuit board.

While embodiments of the present disclosure have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided to explain the technical solutions of the present disclosure, and do not limit the scope of the present disclosure. Numerous variations, changes, and substitutions will now occur to those skilled in the art without departing from the present disclosure. It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the present disclosure. It is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.

Claims

A circuit board, comprising:

a printed circuit board ( “PCB” ) ;

a first plurality of chips mounted to a first side of the printed circuit board;

a second plurality of chips mounted to a second side of the printed circuit board opposite the first side;

at least one first heat sink mounted over the first plurality of chips; and

at least one second heat sink mounted over the second plurality of chips.
The circuit board of claim 1, wherein the first plurality of chips and the second plurality of chips are arranged in arrays on the PCB.
The circuit board of claim 2, wherein in the arrays of the first plurality of chips and the second plurality of chips, mapping locations of the first plurality of chips on the PCB do not overlap with mapping locations of the second plurality of chips on the PCB.
The circuit board of claim 3, further comprising:

at least one third heat sink mounted to the second side of the PCB at each mapping location of each of the first plurality of chips; and

at least one fourth heat sink mounted to the first side of the PCB at each mapping location of each of the second plurality of chips.
The circuit board of claim 4, wherein the at least one third heat sink and the at least one fourth heat sink are mounted to the PCB via a soldering method.
The circuit board of claim 2, wherein in the arrays of the first plurality of chips and the second plurality of chips, mapping locations of the first plurality of chips on the PCB overlap or partially overlap with mapping locations of the second plurality of chips on the PCB.
The circuit board of claim 1, wherein the at least one first heat sink and the at least one second heat sink are mounted to the first plurality of chips and the second plurality of chips via at least one of a structural fixing method, a gluing method, or a welding method.
A method for arranging chips to a printed circuit board ( “PCB” ) , comprising:

mounting a first plurality of chips to a first side of the PCB;

mounting a second plurality of chips to a second side of the PCB opposite the first side;

mounting at least one first heat sink over the first plurality of chips; and

mounting at least one second heat sink over the second plurality of chips.
The method of claim 8, wherein mounting the first plurality of chips and the second plurality of chips to the PCB comprises mounting the first plurality of chips and the second plurality of chips in arrays on the first side and the second side, respectively.
A computing device, comprising:

a housing; and

a circuit board disposed inside the housing, the circuit board comprising:

a printed circuit board ( “PCB” ) ;

a first plurality of chips mounted to a first side of the printed circuit board;

a second plurality of chips mounted to a second side of the printed circuit board opposite the first side;

at least one first heat sink mounted over the first plurality of chips; and

at least one second heat sink mounted over the second plurality of chips.
A computing device, comprising:

a housing comprising a first cut-out hole and a second cut-out hole, the first cut-out hole located at a first end of the housing and the second cut-out hole located at a second end of the housing, the first end opposite the second end; and

a circuit board disposed inside the housing, the circuit board comprising a signal interface and a power interface, the signal interface located at a first end of the circuit board and the power interface located at a second end of the circuit board, the first end of the circuit board opposite the second end of the circuit board,

wherein the signal interface is exposed through the first cut-out hole and the power interface is exposed through the second cut-out hole.
The computing device of claim 11, wherein the computing device is a cryptocurrency mining computing device.
The computing device of claim 11, wherein:

the first cut-out hole and the second cut-out hole are located at diagonal locations on the housing, and

the signal interface and the power interface are located at diagonal locations on the circuit board.
The computing device of claim 11, wherein:

the first cut-out hole and the second cut-out hole are located at a same side on the housing, and

the signal interface and the power interface are located at a same side on the circuit board.
The computing device of claim 11, further comprising:

a mounting mechanism configured to stably mount the circuit board inside the housing.
The computing device of claim 15, wherein

the mounting mechanism comprises a first slot and a first raised portion configured to fit with the first slot,

the first slot is provided on a first side of the circuit board, and

the housing comprises a first side panel corresponding to the first side of the circuit board, the first raised portion being located on an inner surface of the first side panel.
The computing device of claim 16, wherein the first raised portion is configured to fit with the first slot when inserted into the first slot.
The computing device of claim 16, wherein

the mounting mechanism further comprises a second slot and a second raised portion configured to fit with the second slot,

the second slot is provided on a second side of the circuit board, the second side of the circuit board opposite the first side of the circuit board, and

the housing comprises a second side panel disposed opposite the first side panel, the second side panel corresponds to the second side of the circuit board, and the second raised portion is located on an inner surface of the second side panel.
The computing device of claim 18, wherein the second raised portion is configured to fit with the second slot when inserted into the second slot.
The computing device of claim 18, wherein

the first side panel comprises a plurality of mounting holes separated from one another along a length direction of the first side panel, and at least one fan is mounted at each mounting hole, and

the second side panel comprises a plurality of heat dissipation regions separated from one another along a length direction of the second side panel, each heat dissipation region corresponds to the at least one fan, and each heat dissipation region comprises a plurality of venting holes.
The computing device of claim 20, wherein plurality of fans are mounted at each mounting hole in a stacked configuration.
The computing device of claim 11, wherein

the computing device comprises a plurality of first cut-out holes and a plurality of second cut-out holes, the plurality of first cut-out holes and the plurality of second cut-out holes are disposed along a width direction of the housing, and

the computing device comprises a plurality of circuit boards, each signal interface of each circuit board corresponds to a first cut-out hole, and each power interface of each circuit board corresponds to a second cut-out hole.
A circuit board, comprising:

a signal interface configured to connect with a controller to receive signals from the controller; and

a power interface configured to connect with a power source,

wherein the signal interface is located at a first end of the circuit board, and the power interface is located at a second end of the circuit board, the first end opposite the second end.
The circuit board of claim 23, wherein the signal interface and the power interface are located at diagonal locations on the circuit board.
The circuit board of claim 23, wherein the signal interface and the power interface are located on a same side of the circuit board.
The circuit board of claim 23, further comprising:

a first slot located on a first side of the circuit board, the first slot being configured to couple with a first raised portion provided on a first side panel of a housing of a computing device; and

a second slot located on a second side of the circuit board, the second side opposite the first side, the second slot being configured to couple with a second raised portion provided on a second side panel of the housing of the computing device.
A chip heat dissipating structure mountable on a chip to dissipate heat generated by the chip, comprising:

a coating disposed over the chip,

wherein the coating comprises at least one metal-based layer.
The chip heat dissipating structure of claim 27, wherein the at least one metal-based layer comprises a first metal-based layer and a second metal-based layer.
The chip heat dissipating structure of claim 28, wherein the first metal-based layer is disposed over the chip, and the second metal-based layer is disposed over the first metal-based layer.
The chip heat dissipating structure of claim 27, wherein the chip comprises a wafer and an encapsulation structure, and the coating is disposed over the wafer and the encapsulation structure.
The chip heat dissipating structure of claim 30, wherein a top surface of the wafer is exposed to the coating and is not covered by the encapsulation structure.
The chip heat dissipating structure of claim 27, wherein an area of the coating is the same as an area of a top surface of the chip.
The chip heat dissipating structure of claim 28, wherein the first metal-based layer is a layer of an alloy.
The chip heat dissipating structure of claim 33, wherein a thickness of the first metal-based layer is 0.1 –0.5 microns.
The chip heat dissipating structure of claim 28, wherein the second metal-based layer is a copper layer.
The chip heat dissipating structure of claim 35, wherein a thickness of the second metal-based layer is 2 –6 microns.
The chip heat dissipating structure of claim 28, wherein an area of the first metal-based layer is the same as an area of the second metal-based layer.
The chip heat dissipating structure of claim 28, further comprising a heat sink connected to the coating, wherein the heat sink is welded to the coating through a welding material layer.
The chip heat dissipating structure of claim 38, wherein the welding material layer comprises metal tin.
The chip heat dissipating structure of claim 39, wherein a thickness of the welding material layer is 0.1 –0.15 mm.
The chip heat dissipating structure of claim 38, wherein an area of the welding material layer is the same as an area of the coating.
The chip heat dissipating structure of claim 38, wherein an area of the welding material layer is the same as an area of a bottom surface of the heat sink.
The chip heat dissipating structure of claim 30, wherein,

if a top surface of the wafer is at the same height as a top surface of the encapsulation structure, the coating has a uniform thickness,

if the top surface of the wafer is lower than the top surface of the encapsulation structure, the coating fills in a cavity formed by the top surface of the wafer and portions of the encapsulation structure surrounding the top surface of the wafer, and

if the top surface of the wafer is higher than the top surface of the encapsulation structure, a portion of the coating covering the top surface of the wafer is higher than another portion of the coating covering the top surface of the encapsulation structure.
A chip structure, comprising:

a chip; and

a chip heat dissipating structure mounted to the chip, comprising:

a coating disposed over the chip,

wherein the coating comprises at least one metal-based layer.
The chip structure of claim 44, wherein the at least one metal-based layer comprises a first metal-based layer and a second metal-based layer.
A circuit board, comprising:

a printed circuit board; and

at least one chip structure mounted to the printed circuit board, each chip structure comprising:

a chip; and

a chip heat dissipating structure mounted to the chip, comprising:

a coating disposed over the chip,

wherein the coating comprises at least one metal-based layer.
The circuit board of claim 46, wherein the at least one metal-based layer comprises a first metal-based layer and a second metal-based layer.
The circuit board of claim 46, wherein the at least one chip structure comprises a plurality of chip structures, and wherein the plurality of chip structures are mounted to both sides of the printed circuit board.
A supercomputing device, comprising:

a housing; and

at least one circuit board disposed inside the housing, each circuit board comprising:

a printed circuit board; and

at least one chip structure mounted to the printed circuit board, each chip structure comprising:

a chip; and

a chip heat dissipating structure mounted to the chip, comprising:

a coating disposed over the chip,

wherein the coating comprises at least one metal-based layer.
The supercomputing device of claim 49, wherein at least one circuit board comprises a plurality of circuit boards disposed in parallel inside the housing.
The supercomputing device of claim 49, wherein the at least one metal-based layer comprises a first metal-based layer and a second metal-based layer.