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WO2019168265A1 - Dispositif électronique, procédé de traitement de tâche de dispositif électronique, et support lisible par ordinateur - Google Patents

Dispositif électronique, procédé de traitement de tâche de dispositif électronique, et support lisible par ordinateur Download PDF

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Publication number
WO2019168265A1
WO2019168265A1 PCT/KR2019/000138 KR2019000138W WO2019168265A1 WO 2019168265 A1 WO2019168265 A1 WO 2019168265A1 KR 2019000138 W KR2019000138 W KR 2019000138W WO 2019168265 A1 WO2019168265 A1 WO 2019168265A1
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WO
WIPO (PCT)
Prior art keywords
task
delay time
amount
work
time
Prior art date
Application number
PCT/KR2019/000138
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English (en)
Korean (ko)
Inventor
박대동
김범진
박우진
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Publication of WO2019168265A1 publication Critical patent/WO2019168265A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G06F9/4887—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues involving deadlines, e.g. rate based, periodic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt

Definitions

  • the present disclosure relates to an electronic device, and more particularly, to a technology for adjusting a processing time of a task to be performed based on an amount of a task being performed and a characteristic of a task to be additionally performed.
  • Real-time systems implemented with one or more electronic devices used timer interrupts to perform tasks at precise times.
  • FIG. 1 is a diagram for describing a problem in which time is delayed in performing a task.
  • the task execution time table of FIG. 1 illustrates an operation of a conventional system that sequentially executes four tasks (Task A, Task B, Task C, Task D) at predetermined times.
  • FIG. 1A illustrates an ideal case in which no delay occurs in performing each task
  • FIG. 1B illustrates an actual situation in which a delay occurs in performing each task. Indicates.
  • Task D Delay time incurred in performing may be further increased.
  • an object of the present disclosure is to provide an electronic device, a task processing method, and a computer readable medium having different task processing points according to the situation of an electronic device (or system) and a task to be additionally performed.
  • An electronic device may include a memory and a processor configured to perform a task using the memory, wherein the processor is further configured to delay a start of a subsequent task based on the amount of the task being performed.
  • the processing time of the task is changed based on a delay time corresponding to the amount of work being performed at the time of generating the task.
  • the processor may determine a minimum value of the delay time as the delay time and store it in the memory.
  • the processor may determine whether to perform the monitoring based on the priority of each task included in the task being performed and the task deadline.
  • the processor may process the task based on the delay time calculated for the maximum amount of work among the delay time stored in the memory. You can also change
  • the processor may change the processing time of the task by adding a maximum allowable jitter value of the task to a delay time corresponding to the amount of work being performed at the time of generating the task.
  • the processor may read the maximum allowable jitter value of the task from a task data structure stored in the memory.
  • the amount of the task may be at least one of memory usage, a degree of load on the CPU, and a number of tasks included in the task being performed.
  • a method of processing a task of an electronic device includes monitoring and storing a delay time when starting a subsequent task based on the amount of work being performed in the electronic device, and a task to be executed. When is generated, changing the processing time of the task based on a delay time corresponding to the amount of work being performed at the time of the task occurs.
  • the task processing method may further include determining and storing a minimum value of the delay time when the plurality of delay times are calculated for the same workload during the monitoring.
  • the task processing method may further include determining whether to perform the monitoring based on a priority and a work deadline of each task included in the task performed by the electronic device.
  • the changing of the processing time of the task may include: when the delay time corresponding to the amount of work being performed at the task occurrence time is not calculated, based on the delay time calculated for the maximum amount of work among the stored delay time. You can change the processing time of the task.
  • the processing time of the task may be changed by adding a maximum allowable jitter value of the task to a delay time corresponding to the amount of work being performed at the time of generating the task.
  • the task processing method may further include reading a maximum allowable jitter value of the task from a task data structure when the task occurs.
  • the amount of the task may be at least one of memory usage, a degree of load on the CPU, and a number of tasks included in the task being performed.
  • computer instructions stored in a non-transitory computer readable medium are executed by a processor of an electronic device, and cause the electronic device to be executed based on the amount of work being performed in the electronic device.
  • Monitoring a delay time when starting a subsequent task ; storing the delay time to correspond to the amount of the task being performed; and based on the stored delay time, a timer interrupt for further performing the task (Timer Performing an operation including setting an offset value with respect to an occurrence point of an interrupt.
  • the operation may further include changing a generation time of a timer interrupt for executing the task based on the set offset value when a task to be executed occurs.
  • the minimum value may be stored as a delay time corresponding to the same workload.
  • the operation may further include determining whether to perform the monitoring based on a priority of each task included in the task being performed by the electronic device and a task deadline.
  • the step of changing the occurrence time of the timer interrupt may be performed based on the delay time calculated for the maximum amount of the stored delay time when the delay time corresponding to the amount of work being performed at the task occurrence time is not monitored.
  • the generation time of the timer interrupt for executing the task may be changed based on the set offset value.
  • the offset value may be calculated by adding a maximum allowable jitter value of the task to a delay time corresponding to the amount of work being performed at the time of occurrence of the task.
  • the problem of delay time may be effectively adjusted to various situations. You can solve it.
  • 1 is a view for explaining a problem that the time delay in the process of performing the task
  • FIG. 2 is a block diagram illustrating a configuration of an electronic device according to an embodiment of the present disclosure
  • 3 to 4 are graphs for explaining an embodiment of changing a task processing time point according to an amount of work
  • 5 to 6 are graphs for explaining an embodiment in consideration of the maximum allowable jitter of a task
  • FIG. 7 is a block diagram illustrating a detailed configuration of an electronic device according to various embodiments of the present disclosure.
  • FIG. 8 is a view for explaining the configuration of a server according to an embodiment of the present disclosure.
  • FIG. 9 is a flowchart illustrating a task processing method according to an embodiment of the present disclosure.
  • FIG. 10 is a flowchart further considering a maximum allowable jitter of a task in a task processing method according to an exemplary embodiment. Referring to FIG.
  • ordinal numbers such as “first”, “second”, and the like may be used to distinguish between components. These ordinal numbers are used to distinguish the same or similar components from each other, and the meaning of the terms should not be construed as limited by the use of these ordinal numbers. For example, the components combined with these ordinal numbers should not be limited in order of use or arrangement by the number. If necessary, the ordinal numbers may be used interchangeably.
  • modules such as “module”, “unit”, “part”, and the like are terms for referring to a component that performs at least one function or operation, and such components are referred to as hardware or software. It may be implemented or a combination of hardware and software.
  • a plurality of "modules”, “units”, “parts”, etc. are integrated into at least one module or chip, except that each needs to be implemented with a particular specific hardware, and is at least one processor. It can be implemented as.
  • a part when a part is connected to another part, this includes not only a direct connection but also an indirect connection through another medium.
  • the meaning that a part includes a certain component means that it may further include other components, without excluding other components, unless specifically stated otherwise.
  • FIG. 2 is a block diagram illustrating a configuration of an electronic device 100 according to an embodiment of the present disclosure.
  • the electronic device 100 of FIG. 2 may be implemented as any one of all electronic devices including an electronic circuit. Specifically, it may be implemented as a PC, a server, a terminal device, a mobile phone, a tablet, a laptop PC, and the like.
  • the electronic device 100 includes a memory 110 and a processor 120.
  • the memory 110 may be implemented as a nonvolatile memory (eg, a ROM, a hard disk, a solid state drive (SSD), a flash memory), a volatile memory such as a RAM, or the like.
  • a nonvolatile memory eg, a ROM, a hard disk, a solid state drive (SSD), a flash memory
  • a volatile memory such as a RAM, or the like.
  • the memory 110 may store information about various tasks or applications that the electronic device 100 may perform, and data related to the task execution of the processor 120.
  • a task refers to a basic unit of a program controlled by an operating system of the electronic device 100.
  • the program of one unit corresponding to one task may be an entire program or a call of a subsequent program.
  • a program may make a request to several other utility programs, wherein each of the utility programs may be a separate task, or each of the utility programs may be included in one task as a subtask.
  • the processor 120 may control overall operations of the electronic device 100.
  • the processor 120 may individually control the components of the electronic device 100 including the memory 110 to execute a plurality of tasks simultaneously or alternately.
  • the processor 120 may include a CPU (not shown) and a system bus (not shown). At this time, the CPU of the processor 120 is connected to the RAM and ROM of the memory 110 through a system bus (not shown) to transmit and receive various data or signals.
  • the processor 120 executes an operating system stored in the memory 110 to boot the system.
  • the processor 120 may execute various applications or tasks stored in the memory 110 of the electronic device 100 to perform various operations.
  • the processor 120 delays starting the successor based on the amount of work being performed. The time can be monitored and stored in the memory 110.
  • the amount of work may include at least one of the memory usage, the number of tasks included in the work being performed, and the degree of load on the CPU.
  • the memory usage may refer to a capacity in which the processor 120 uses a main memory including RAM or RAM.
  • the processor 120 may monitor and store in the memory 110 how much delay time for additionally executing a task.
  • the processor 120 may determine whether to perform monitoring based on the priority of each task included in the task being performed and the task deadline.
  • the processor 120 may stop monitoring and perform the tasks included in the task being performed first. have.
  • the processor 120 may monitor the delay time.
  • the processor 120 may store the monitored delay time so as to match the amount of the task being performed, but may not store information on what is additionally executed in the memory 110.
  • the processor 120 may store in the memory 110 all of the delay time taken to perform an arbitrary task according to the amount of work being performed by the processor 120.
  • the processor 120 may determine a task processing time point based on the delay time stored in the memory 110. At this time, to advance the processing time of the task may be to advance the generation time of the timer interrupt signal for executing the task.
  • Interrupt means that if a certain condition is satisfied while the program is running, it temporarily stops the existing program and performs other tasks.
  • the processor 120 when the CPU included in the processor 120 is executing a program, when execution of a new program is required due to a specific input or a specific situation, the processor 120 generates a new signal as an interrupt signal is generated. You can run the program.
  • the interrupt may occur based on a timer (not shown) included in the electronic device 100 or may be generated by the electronic device 100 receiving an interrupt signal from an external device (not shown).
  • the interrupt may occur according to a user's input to the electronic device 100.
  • the interrupt may be generated based on a software control of a user made in an operating system (OS) of the electronic device 100.
  • the software control of the user may be based on an input device (not shown) such as a keyboard, a mouse, or a remote control device connected to the electronic device 100 by wire or wirelessly.
  • a timer interrupt an interrupt that occurs when a specific time.
  • a real time system may use a timer interrupt to perform a specific task at a precise time.
  • 3 to 4 are graphs for comparing an exemplary embodiment of the present invention with a conventional method of changing a task processing time point according to an amount of work.
  • FIG. 3 is a graph for explaining a conventional method of advancing a processing time of a task only by a constant value (fixed offset value) regardless of a situation.
  • FIG. 3 illustrates a result of monitoring a delay time for additionally performing a task according to memory usage at a time when a specific task should be performed. Referring to FIG. 3, it can be seen that a plurality of delay times can be measured even in the same memory usage.
  • the processor 120 may set the smallest value of the measured delay times, that is, the minimum value (min) of the measured delay times when the memory usage is 1, to be a fixed offset value in all cases. have.
  • the processor 120 may advance the processing time of the task by a fixed offset value regardless of which task is performed in which situation.
  • the processor 120 may change the processing time of the task based on a delay time corresponding to the amount of work being performed by the processor 120 at the time when the task occurs.
  • the processor 120 determines a minimum value min among them as a delay time matching the amount of each work.
  • the memory 110 may store the same.
  • the processor 120 may change the offset value for each memory usage at a time when a specific task is to be performed, and the offset value matching the minimum value of the delay time measured for each memory usage for each memory usage. Can be set.
  • the degree of advancing the processing time of the task may be varied according to the amount of work being performed by the processor 120.
  • the processor 120 calculates the delay time calculated for the maximum amount of work among the delay time stored in the memory.
  • the processing time point of the task may be changed based on.
  • the processor 120 may advance the processing time for performing the task A by the measured delay time at 10,000,000 KB which is the maximum memory usage among the measured memory usage delays.
  • the difference between the minimum and maximum values of the delay time measured for each amount of work may increase.
  • the task processing time may be determined based on the maximum allowable jitter value for each task.
  • FIG. 5 is a graph for explaining a problem in which a difference between minimum and maximum values of delay times measured for the same amount of work is large and some delay times exceed an error range at the time of task processing.
  • jitter may refer to a difference occurring between a desired signal and a signal that actually occurs with respect to a specific signal.
  • the maximum allowable jitter value of Task A may be 0.1 second.
  • max delays shown in the graph of FIG. 5 are historical values that have already been measured, the maximum allowable jitter value for these max delays, in view of the additional delays that may occur in the light of the monitoring results. You need to adjust the offset value so that it is located inside.
  • the processor 120 may change the processing time of the corresponding task by a time obtained by adding the maximum allowable jitter value of the task to a delay time corresponding to the amount of work being performed at the time of task occurrence.
  • the processor 120 may advance the processing time of the corresponding task by the "dynamic offset New" value of the dynamic offset value based on the amount of work, plus the maximum allowable jitter value of the task to be additionally performed.
  • the processor 120 may add the dynamic offset value for each memory usage to the "dynamic offset new" value of the task A by the maximum allowed jitter value Za of task A to be additionally performed.
  • the processor 120 may add the dynamic offset value for each memory usage to the "dynamic offset new" value of the task A by the maximum allowed jitter value Za of task A to be additionally performed.
  • the monitored delay time for each memory usage can be included in the widest possible range within the maximum allowable jitter value range of the task, so that future delay times for each memory usage can be included. You can reduce the probability of processing each task out of the error range.
  • the processor 120 may read the maximum allowable jitter value of the generated task from the task data structure stored in the memory 110.
  • the task data structure may include information about one or more tasks that the electronic device 100 may perform.
  • the task data structure may include task ID information, task status information, task relationship information, task scheduling information, and the like.
  • the task data structure may include information about the maximum allowable jitter value for processing each task.
  • the processor 120 may receive a maximum allowable jitter value for each task from a user and store the same in a task data structure included in the memory 110.
  • the processor 120 may receive a maximum allowable jitter value for one or more tasks from an external device such as a server (not shown) and store it in a task data structure included in the memory 110.
  • the processor 120 may change the processing time of the task in consideration of not only the amount of work being performed but also the characteristics of the task to be additionally performed.
  • the processor 120 may reduce the probability of occurrence of a deadline miss for a specific task.
  • the above-described embodiments may not be performed by only one electronic device 100 but may be implemented through a system including one or more electronic devices.
  • the configuration of the electronic device 100 is not necessarily limited thereto and may further include various additional configurations according to the type of the electronic device 100.
  • FIG. 7 is a block diagram illustrating a detailed configuration of an electronic device 100 for describing various embodiments of the present disclosure.
  • the electronic device 100 may further include at least one of the memory 110 and the processor 120 as well as the communication unit 130, the user input unit 140, and the output unit 150.
  • the communication unit 130 is a component for performing data communication wirelessly or by wire with various types of external devices (not shown) according to various types of communication methods.
  • the processor 120 may communicate with various external devices using the communication unit 130.
  • the processor 120 may receive a maximum allowable jitter value for one or more tasks from an external device such as a server (not shown) through a communication unit (130 of FIG. 7A) and may be included in the memory 110. It can also be stored in a task data structure.
  • an external device such as a server (not shown)
  • a communication unit 130 of FIG. 7A
  • the processor 120 may receive information on the monitored delay time for each amount of work being performed from the external device through the communication unit 130.
  • the processor 120 may change a processing time of a task to be performed based on the received information.
  • the processor 120 may build information on the monitored delay time according to the amount of work being performed by using the memory 110 and then transmit the constructed information to the external device through the communication unit 130.
  • the external device may calculate an offset value for changing the processing time of the task to be additionally performed based on the information on the delay time, and then transmit the calculated offset value to the communication unit 130.
  • the processor 120 may change the processing time point for the task to be performed based on the calculated offset value received through the communication unit 130.
  • the user input unit 140 is a component for receiving various user commands and information.
  • the processor 120 may execute a function corresponding to a user command input through the user input unit 140 or store information input through the user input unit 140 in the memory 110.
  • the processor 120 may receive a maximum allowable jitter value for each task from the user through the user input unit 140 of FIG. 7A and store it in a task data structure included in the memory 110.
  • the user input unit 140 may include a microphone (not shown) for receiving a user command in the form of a voice, or together with a display (not shown) of the output unit 150 as a touch screen for receiving a user command by touch. It may be implemented as a separate touch pad (not shown).
  • the user input unit 140 may include an application programming interface (API) for allowing a user to control a function of the electronic device 100, and the user's input to a program that the electronic device 100 may perform. Command or control may be input in an API manner.
  • API application programming interface
  • the user input unit 140 may receive a signal including information about a user command or a task from a separate control device (not shown) for controlling the electronic device 100.
  • the output unit 150 may include a display (not shown), an audio output unit (not shown), and the like.
  • the processor 120 may control the display of the output unit 150 to provide a user with information about a result of monitoring a delay time generated in performing an additional task according to the amount of work being performed.
  • the processor 120 monitors a delay time generated by additionally performing an arbitrary task according to the amount of work being performed, the processor 120 provides the user with information about the state of the electronic device 100 that is monitoring the delay time.
  • the display or audio output of the output unit 150 may be controlled to provide a visual or audio presentation.
  • System 100 ′ may include a server 10 and one or more user devices 20.
  • each of the user devices 20-1, 20-2, ... performs a task based on a request of the server 10. Depending on the amount of work being performed by (7), you can monitor information about the delay time spent.
  • the server 10 may be configured such that each of the user devices 20-1, 20-2,... That have received a task execution request from the server 10 task execution request time starts to perform the corresponding task.
  • the server 10 may determine that each of the user devices 20-1, 20-1, 20-2, ... is based on the amount of work being performed before each of the user devices 20-1, 20-2,..., Receives a request from the server 10. 20-2, 7) can additionally monitor the delay it takes to perform a task.
  • the server 10 based on the monitored delay time and the maximum allowable jitter value for the task to request the user equipment 20-1, 20-2, ... to perform, respectively, the processing time of the task to be requested. You can calculate the offset value to change.
  • the server 10 may advance the time point at which the task execution request is transmitted to each of the user devices 20-1, 20-2, ... by the calculated offset value.
  • FIG. 9 is a flowchart illustrating a task processing method according to an exemplary embodiment.
  • a delay time when starting a subsequent work may be monitored (S810). In other words, it is possible to measure the delay time when the work being performed starts the subsequent work by quantity.
  • the amount of work may include memory usage, a degree of load on the CPU, and the number of tasks included in the work being performed.
  • the electronic device may change whether to perform monitoring based on a priority of each task included in the task being performed and a task deadline.
  • the electronic device may store the monitored delay time (S820).
  • the monitored delay time may be stored such that each delay time matches the measured amount of work.
  • the minimum value may be determined and stored as a delay time matching the workload.
  • the processing time of the task may be changed based on a delay time corresponding to the amount of work being performed at the time of generating the task (S830). In this case, changing the processing time of the task may be to advance the time of generation of the timer interrupt signal for executing the task.
  • the processing time of the task may be advanced by the minimum value of the delay time stored for 10,000 KB of memory usage as a result of the monitoring.
  • a delay time corresponding to the amount of work being performed at the time of task occurrence is not calculated, that is, if it is not included in the monitoring result, it is based on the delay time calculated for the maximum amount of the monitored and stored delay time. You can change the processing time of the task.
  • the characteristics of the task itself may be additionally considered.
  • FIG. 10 is a flowchart for explaining another embodiment of the present disclosure to further consider a maximum allowable jitter of a task.
  • a delay time when starting a subsequent work may be monitored (S910).
  • the monitored delay time may be stored (S920).
  • a maximum allowable jitter value of each of the tasks executable in the electronic device may be input and stored.
  • the electronic device may store a maximum allowable jitter value for each task that is input by itself or received from an external device.
  • the maximum allowable jitter value refers to an error tolerance value in the (+) or (-) direction at the time of processing each task, and specifically, may mean an absolute jitter.
  • the maximum allowable jitter value for each received or input task may be added to the task data structure included in the memory 110.
  • a time obtained by adding a maximum allowable jitter value of the task to be executed to a delay time corresponding to the amount of work being performed at the time of occurrence of the task may be calculated (S940).
  • the maximum allowable jitter value of the task can be read from the task data structure.
  • the processing time of the task to be executed may be changed by the calculated time (S950). Specifically, the processing time of the task to be executed can be advanced by the calculated time.
  • the processing time of the task is changed according to the amount of work performed by the electronic device 100 and the task to be additionally performed, thereby efficiently solving the problem of delay time. Can be.
  • the task processing method described with reference to FIGS. 9 and 10 may be performed in an electronic device having the configuration illustrated and described with reference to FIGS. 2 and 7, but is not limited thereto.
  • various types of electronic devices in which a program for performing the task processing method described with reference to FIGS. 9 and 10 are installed may change a task processing time point to perform a task.
  • Such a program may be distributed in a state stored in a recording medium.
  • the above-described task processing method can be implemented by an apparatus in which a recording medium is connected or mounted.
  • the task processing method described with reference to FIGS. 9 and 10 may be implemented through the server 10 and the one or more user devices 20 included in the system 100 ′ described with reference to FIG. 8.
  • the embodiments described in the present disclosure may include application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), and field programmable gate arrays (FPGAs). ), Processors, controllers, micro-controllers, microprocessors, and other electrical units for performing other functions.
  • ASICs application specific integrated circuits
  • DSPs digital signal processors
  • DSPDs digital signal processing devices
  • PLDs programmable logic devices
  • FPGAs field programmable gate arrays
  • embodiments described herein may be implemented in the processor 120 itself. According to the software implementation, embodiments such as the procedures and functions described herein may be implemented as separate software modules. Each of the software modules described above may perform one or more functions and operations described herein.
  • computer instructions for performing a processing operation in the electronic device 100 according to various embodiments of the present disclosure described above may be stored in a non-transitory computer-readable medium.
  • the computer instructions stored in the non-transitory computer readable medium allow the specific apparatus to perform processing operations in the electronic device 100 according to the above-described various embodiments when executed by a processor of the specific apparatus.
  • a non-transitory computer readable medium refers to a medium that stores data semi-permanently and is readable by a device, not a medium storing data for a short time such as a register, a cache, a memory, and the like.
  • Specific examples of non-transitory computer readable media may include CD, DVD, hard disk, Blu-ray disk, USB, memory card, ROM, and the like.

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Abstract

L'invention concerne un dispositif électronique comprenant une mémoire, et un processeur utilisant la mémoire pour exécuter un travail. Le processeur surveille un temps de retard au début d'un travail subséquent, sur la base de la quantité de travail en cours d'exécution, pour enregistrement en mémoire; et lorsqu'une tâche à exécuter est générée, le processeur modifie un temps de traitement de la tâche en fonction du temps de retard correspondant à la quantité de travail exécutée au moment de la génération de la tâche.
PCT/KR2019/000138 2018-02-27 2019-01-04 Dispositif électronique, procédé de traitement de tâche de dispositif électronique, et support lisible par ordinateur WO2019168265A1 (fr)

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CN112668951B (zh) * 2019-10-16 2024-06-21 北京京东乾石科技有限公司 一种任务处理方法、装置、服务器及存储介质
KR102497257B1 (ko) * 2020-12-15 2023-02-06 현대오토에버 주식회사 오토사 플랫폼의 메인 기능과 태스크의 매핑 방법
KR102582726B1 (ko) * 2022-02-08 2023-09-25 쿠팡 주식회사 배송 업무의 연기와 관련된 정보를 제공하는 전자 장치 및 그 방법
WO2025116345A1 (fr) * 2023-11-30 2025-06-05 삼성전자 주식회사 Dispositif électronique et son procédé de fonctionnement

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