WO2019005167A1

WO2019005167A1 - Dual bottom electrode for memory applications and methods to form the same

Info

Publication number: WO2019005167A1
Application number: PCT/US2017/040510
Authority: WO
Inventors: Nathan STRUTT; Stephen Y. WU; Namrata S. ASURI; Timothy E. Glassman; Oleg Golonzka; Niloy Mukherjee; Dragos SEGHETE; Christopher J. WIEGAND
Original assignee: Intel Corporation
Priority date: 2017-06-30
Filing date: 2017-06-30
Publication date: 2019-01-03

Abstract

An approach for integrating a resistive random access memory (RRAM) device on a dual bottom electrode layer is described. In an example, a resistive random access memory (RRAM) device includes a dual bottom electrode disposed above a substrate. The dual bottom electrode includes a first conductive layer disposed above a substrate, a second conductive layer disposed above the first conductive layer and an intermediate layer between the first conductive layer and the second conductive layer, where the intermediate layer includes oxygen. A switching layer is disposed on the dual bottom electrode layer. An oxygen exchange layer is disposed on the switching layer and a top electrode is disposed on the switching layer.

Description

DUAL BOTTOM ELECTRODE FOR MEMORY APPLICATIONS AND METHODS TO FORM THE SAME TECHNICAL FIELD

Embodiments of the disclosure are in the field of integrated circuit fabrication and, in particular, a dual bottom electrode for memory applications and methods of fabrication.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.

Non-volatile embedded memory with RRAM devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. However, the technical challenges of creating an appropriate stack for fabrication of RRAM devices that exhibit high device endurance, high retention and operability at low voltages and currents presents formidable roadblocks to commercialization of this technology today. Specifically, the objective of memory technology to control tail bit data in a large array of memory bits necessitates tighter control of the variations in metal oxide break down and switching events in individual bits. Furthermore, in filamentary RRAM systems, the latter is dictated by fine tuning oxygen vacancy concentration which is widely understood to drive filament formation and dissolution in metal oxide films As such, significant improvements are still needed in the area of metal oxide stack engineering which rely on material advancements, deposition techniques or a combination of both. This area of process development is an integral part of the non-volatile memory roadmap.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates a cross-sectional view of an electrode structure including a first conductive layer, an intermediate layer and a second conductive layer disposed above a substrate.

Figure 2 illustrates a cross-sectional view of a resistive random access memory (RRAM) device disposed above a conductive interconnect that is disposed in a dielectric layer above a substrate.

Figures 3A-3I illustrate cross sectional views representing various operations in a method of fabricating a resistive random access memory device integrated above a conductive interconnect, which may be used to fabricate a memory device such as described in association with Figure 2, in accordance with an embodiment of the present disclosure.

Figure 3A illustrates a cross sectional view of a first conductive layer, an intermediate via and a passivation layer formed above a conductive interconnect in a device region, and the passivation layer and the first conductive layer formed in a scribeline region in, accordance with an embodiment of the present disclosure.

Figure 3B illustrates the structure of Figure 3A following a planarization process.

Figure 3C illustrates the structure of Figure 3B following a lithography process to define a location for the formation of an alignment mark structure in the scribeline region.

Figure 3D illustrates the structure of Figure 3C following the formation of an alignment mark opening in the scribeline region and the formation of an intermediate layer on the first conductive layer.

Figure 3E illustrates the structure of Figure 3D following the formation of a second conductive layer to form a dual bottom electrode layer.

Figure 3F illustrates the structure of Figure 3E following a blanket formation of an RRAM material layer stack.

Figure 3G illustrates the structure of Figure 3F following the formation of a dielectric hardmask layer and a device resist pattern formed on the dielectric hardmask layer to define a location for the formation of an RRAM device.

Figure 3H illustrates the structure of Figure 3G following an etch process to form an RRAM device.

Figure 31 illustrates the structure of Figure 3H following the formation of a dielectric spacer on sidewalls of the dielectric hardmask, and on sidewalls of the RRAM device.

Figure 4 illustrates a cross-sectional view of an RRAM element coupled to a drain contact of a transistor, in accordance with an embodiment of the present disclosure.

Figure 5 illustrates a computing device in accordance with embodiments of the present disclosure.

Figure 6 illustrates an integrated circuit (IC) structure that includes one or more embodiments of the present disclosure.

DESCRIPTION OF THE EMBODIMENTS

Approaches for a dual bottom electrode for memory applications and method of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as switching operations associated with embedded memory, are described in lesser detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

Integrating a memory array with low voltage logic circuitry, such as logic circuitry operational at a voltage less than or equal to 1 Volt, may be advantageous since it enables higher operation speeds compared to having physically separate logic and memory chips. Additionally, approaches to integrating an RRAM device onto a transistor to create embedded memory presents material challenges that have become far more formidable with scaling. As transistor operating voltages are scaled down in an effort to become energy efficient, RRAM memory devices that are connected in series with such transistors are also required to function at lower voltages and currents.

Memory based on filamentary RRAM devices rely on a high probability of conductive filaments with uniform characteristics forming in a switching layer across a large number such RRAM devices To ensure that conductive filaments are initialized in an RRAM device, a process known as electroforming is performed. Minimizing a spread in the distribution of forming voltage, along with other key electrical parameters such as switching voltage and switching currents is important for enabling embedded memory. Controlling the spread in distribution of electrical parameters is dependent not only on the type of materials chosen for individual layers of the RRAM devices but also on the quality of the layers as they are subjected to various processing operations.

In an embodiment, typical layers for fabrication of an RRAM device are deposited sequentially without breaking vacuum. However, in some cases a break in the deposition process becomes necessary for integration reasons. As an example, in order to create lithographic alignment marks a break in vacuum may be necessary. Such an alignment mark may be used to align RRAM devices to conductive interconnects. When layers utilized in an RRAM device include materials having certain thicknesses that pose challenges for lithographic alignment, a break in the deposition process may be required. In some circumstances, a deposition of a conductive layer may be required before fabrication of the alignment structure. The conductive layer may be subsequently damaged, from processing operations required to fabricate the alignment structure and may not adequately function as an electrode for an RRAM device.

In an embodiment of the present disclosure, an RRAM device includes a dual bottom electrode having a first conductive layer, a second conductive layer and an intermediate layer between the first conductive layer and the second conductive layer, wherein the intermediate layer includes oxygen. The first conductive layer may be a layer that is required for the fabrication of an alignment structure but, may be damaged during the fabrication process. In an embodiment, the first conductive is deposited before the formation of an alignment mark and a second conductive layer is deposited after the formation of the alignment mark. In an embodiment, the second conductive layer is electrically coupled to the first conductive layer in spite of the presence of the intermediate layer, and provides a pristine surface for the formation of an RRAM device. In an embodiment, the dual bottom electrode structure forms a foundation for memory devices other than an RRAM device, such as a magnetic tunnel junction memory device or a spin orbit torque (SOT) memory device.

Figure 1 illustrates a cross-sectional view of an electrode structure 100 disposed above a substrate 102. The electrode structure 100 includes a first conductive layer 104, a second conductive layer 106 disposed above the first conductive layer 104 and an intermediate layer 108 disposed directly between the first conductive layer 104 and the second conductive layer 106, where the intermediate layer 108 includes oxygen.

In an embodiment, the first conductive layer 104 includes a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ta and Ru. In an embodiment, the first conductive layer 104 includes a layer of TiN. In one embodiment, the layer of TiN has concentration of nitrogen that is between 40-50 atomic percent of the total composition of the layer of TiN. In an embodiment, when the first conductive layer 104 includes a layer of TiN having a concentration of nitrogen between 47-50 atomic percent of the total composition of the layer of TiN, the first conductive layer 212 has an electrical resistivity between 100-350 μ-Ω-cm. In an embodiment, the first conductive layer 104 has a thickness between 20nm-50nm. In an exemplary embodiment, the first conductive layer 104 has a thickness of 20nm.

In an embodiment, the second conductive layer 106 includes a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ta and Ru. In an embodiment, the second conductive layer 106 includes a layer of TiN. In one embodiment, the layer of TiN has concentration of nitrogen that is between 47-50 atomic percent of the total composition of the layer of TiN. In an embodiment, when the second conductive layer 106 includes a layer of TiN having a concentration of nitrogen between 47-50 atomic percent of the total composition of the layer of TiN, the second conductive layer 106 has an electrical resistivity between 100-350 μ-Ω-cm. In an embodiment, the second conductive layer 106 has a thickness between 5nm-25nm. In an exemplary embodiment, the second conductive layer 106 has a thickness of lOnm.

In an embodiment, the first conductive layer 104 and the second conductive layer 106 include a same material such as TiN. In an embodiment, the first conductive layer 104 and the second conductive layer 106 include a same material such as TiN, where the concentration of nitrogen in the TiN in the first conductive layer 104 is less than the concentration of nitrogen in the TiN in the second conductive layer 106. In one embodiment, the first conductive layer 104 includes a layer of TiN where the concentration of nitrogen is between 40-45 atomic percent of the total composition of the layer of TiN, and the second conductive layer 106 includes a TiN where the concentration of nitrogen is between 47- 50 atomic percent of the total composition of the layer of TiN. In an embodiment, the first conductive layer 104 and the second conductive layer 106 each include a different material. In an embodiment, the first conductive layer 104 and the second conductive layer 106 each include a different material and have a different thickness. In an embodiment, the first conductive layer 104 includes a layer of TiN and the second conductive layer 106 includes a layer of W.

In an embodiment, the first conductive layer 104 has a thickness that is greater than a thickness of the second conductive layer 106. In an embodiment, the first conductive layer 104 has a thickness between 20nm-30nm and the second conductive layer 106 has a thickness between 10nm-15nm.

Referring again to Figure 1, in an embodiment, the intermediate layer 108 has a nonuniform oxygen composition. In an embodiment, the intermediate layer 108 has a thickness that is non-uniform. In one embodiment, the intermediate layer 108 has portions that are discontinuous in a cross-sectional plane.

In an embodiment, the substrate 102 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, substrates 102 includes other semiconductor materials such as germanium, silicon germanium or a suitable group III-V compound. Logic devices such as MOSFET transistors and access transistors and may be formed on the substrate 102.

Figure 2 illustrates a cross-sectional view of a resistive random access memory (RRAM) device 200 disposed above a conductive interconnect 202 that is disposed in a dielectric layer 203 above a substrate 204. In an embodiment, an intermediate via 206 is disposed directly on a portion of the conductive interconnect 202. In an embodiment, the intermediate via 206 is surrounded by a passivation layer 208. In an embodiment, the passivation layer 208 is disposed on a portion of the conductive interconnect 202 and on the dielectric layer. The RRAM device 200 includes a dual bottom electrode 210 disposed on the intermediate via 206 and on a portion of the passivation layer 208.

The dual bottom electrode 210 includes a first conductive layer disposed above a substrate 204, an intermediate layer disposed on the first conductive layer and a second conductive layer disposed on the intermediate layer. In an embodiment, the intermediate layer includes oxygen. The RRAM device 200 further includes a switching layer disposed on the dual bottom electrode 210 layer, an oxygen exchange layer (OEL) disposed on the switching layer and a top electrode disposed on the switching layer.

In an embodiment, the first conductive layer 212 includes a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ta and Ru. In an embodiment, the first conductive layer 212 includes a layer of TiN. In one embodiment, the layer of TiN has concentration of nitrogen that is between 40-50 atomic percent of the total composition of the layer of TiN. In one embodiment, when the first conductive layer 212 includes a layer of TiN having a concentration of nitrogen between 47-50 atomic percent of the total composition of the layer of TiN, the first conductive layer 212 has an electrical resistivity between 100-350 μ-Ω-cm. In one specific embodiment, when the layer of TiN has concentration of nitrogen that is between 47-50 atomic percent of the total composition of the layer of TiN, the first conductive layer 212 has an electrical resistivity between 100-150 μ-Ω-cm. In another specific embodiment, when the layer of TiN has concentration of nitrogen that is between 47-50 atomic percent of the total composition of the layer of TiN, the first conductive layer 212 has an electrical resistivity between 280-310 μ-Ω-cm In an embodiment, the first conductive layer 212 has a thickness between 20nm-50nm. In an embodiment, the first conductive layer 212 has a thickness of 20nm.

In an embodiment, the second conductive layer 216 includes a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ta and Ru. In an embodiment, the second conductive layer 216 includes a layer of TiN. In one embodiment, when the second conductive layer 216 includes a layer of TiN having a concentration of nitrogen between 47-50 atomic percent of the total composition of the layer of TiN, the second conductive layer 216 has an electrical resistivity between 100-350 μ-Ω-cm. In one specific embodiment, when the layer of TiN has concentration of nitrogen that is between 47-50 atomic percent of the total composition of the layer of TiN, the second conductive layer 216 has an electrical resistivity between 100-150 μ-Ω-cm. In another specific embodiment, when the layer of TiN has concentration of nitrogen that is between 47-50 atomic percent of the total composition of the layer of TiN, the second conductive layer 216 has an electrical resistivity between 280-310 μ-Ω-cm. In an embodiment, the second conductive layer 216 has a thickness between 5nm-25nm. In an embodiment, the second conductive layer 216 has a thickness of l Onm.

In an embodiment, the first conductive layer 212 and the second conductive layer 216 include a same material such as TiN. In an embodiment, the first conductive layer 212 and the second conductive layer 216 each include a layer of TiN, but where the concentration of nitrogen in the TiN in the first conductive layer 212 is less than the concentration of nitrogen in the TiN in the second conductive layer 216. In one embodiment, the first conductive layer 212 includes a layer of TiN where the concentration of nitrogen is between 40-45 atomic percent of the total composition of the layer of TiN, and the second conductive layer 216 includes a TiN where the concentration of nitrogen is between 47- 50 atomic percent of the total composition of the layer of TiN. In an embodiment, the first conductive layer 212 and the second conductive layer 216 each include a different material In an embodiment, the first conductive layer 212 and the second conductive layer 216 each include a different material and have a different thickness. In an embodiment, the first conductive layer 212 includes a layer of titanium nitride and the second conductive layer 216 includes a layer of tungsten.

In an embodiment, the first conductive layer 212 has a thickness that is greater than a thickness of the second conductive layer 216. In an embodiment, the first conductive layer 212 has a thickness between 20nm-30nm and the second conductive layer 216 has a thickness between 5nm-15nm.

Referring again to Figure 2, in an embodiment, the intermediate layer 214 is disposed between the first conductive layer and the second conductive layer 216, wherein the intermediate layer comprises oxygen. In an embodiment, the intermediate layer 214 has a non-uniform oxygen composition. In an embodiment, the intermediate layer has a thickness that is nonuniform. In one embodiment, the intermediate layer has portions that are discontinuous in a cross-sectional plane.

In an embodiment, the dual bottom electrode 210 has a width, WDB. In an embodiment, the dual bottom electrode 210 has a width, WDB, between 10nm-50nm.

In an embodiment, the switching layer 218 is composed of a metal, such as but not limited to, hafnium, tantalum or titanium. When the metal (M) of the switching layer 218 is titanium, hafnium or zirconium having an oxidation state +4, the switching layer 218 has a chemical composition, MOx, where O is oxygen and X is or is substantially close to 2 When the metal (M) of the switching layer 218 is tantalum having an oxidation state +5, the switching layer 218 has a chemical composition, IVhOx, where O is oxygen and X is or is substantially close to 5. In an embodiment, the switching layer 218 also includes an oxide such as aluminum oxide or tungsten oxide. In an embodiment, the switching layer 218 includes a combination of two or more layers of oxide such as but not limited to aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, titanium oxide and tungsten oxide. In an embodiment, the switching layer 218 is fully stoichiometric. In an embodiment, the percentage of missing oxygen atoms is between 0. 1% and 0.3% of the total oxygen atoms in a fully stoichiometric switching layer. In an embodiment, the switching layer 218 is sub-stoichiometric. A switching layer 218, that is sub-stoichiometric, is inherently devoid of oxygen atoms. In an embodiment, the switching layer 218 has a thickness between 2nm - l Onm.

In an embodiment, a portion of the second conductive layer 216 at an interface 217 between the second conductive layer 216 and the switching layer 218 is oxidized. In one such embodiment, the second conductive layer 216 includes tungsten, ruthenium or titanium nitride and an oxidized uppermost portion of the second conductive layer 216 remains conductive.

In an embodiment, the oxygen exchange layer 220 includes a metal that is the same metal (M) in the switching layer 218. In an embodiment, when the switching layer 218 includes an oxide such as HfC , the oxygen exchange layer 220 includes a hafnium metal. In another embodiment, the oxygen exchange layer 220 includes a metal that is different from the metal (M) of the switching layer 218. In an embodiment, when the switching layer 218 includes an oxide such as Hf02, the oxygen exchange layer 220 includes a metal such as Ti, Ta or Hf. In an embodiment, the oxygen exchange layer 220 has a thickness that is at least two times the thickness of the switching layer 218. In another embodiment, the oxygen exchange layer 220 has a thickness that is equal to the thickness of the switching layer 218. In an embodiment, the oxygen exchange layer 220 has a thickness that is equal to the thickness of the switching layer 218 in order to scavenge sufficient O from the switching layer 218. In an embodiment, the switching layer 218 has a thickness between 5nm - 7nm and the oxygen exchange layer 220 has a thickness has a thickness between 5nm - 7nm.

In an embodiment, the top electrode 222 is includes a material such as, but not limited to, titanium nitride, tantalum nitride, tungsten and ruthenium In an embodiment, top electrode 222 and the second conductive layer 216 of the dual bottom electrode 210 are a same material. In an embodiment, the top electrode 222 has a thickness between 30nm- 100 nm. In an embodiment, the composition and thickness of the top electrode 222 are tuned to meet specific device attributes such as series resistance, programming voltage and current.

Referring again to Figure 2, intermediate via 206 includes a material such as but not limited to W, TiN, TaN or Ta. In an embodiment, the intermediate via 206 has a thickness between 10nm-20nm. In an embodiment, the intermediate via 206 has a width, Wiv. In an embodiment, Wiv, of the intermediate via 206 is less than the width, WDB, of the dual bottom electrode 210. In an embodiment, Wiv, of the intermediate via 206 is more than the width, WDB, of the dual bottom electrode 210. In an embodiment, the passivation layer 208 includes a material such as but not limited to silicon nitride, silicon carbide or carbon-doped silicon nitride. In an embodiment, the intermediate via 206 and the passivation layer 208 have uppermost surfaces that are co-planar or substantially co-planar.

Referring again to Figure 2, in an embodiment, the conductive interconnect 202 has an uppermost surface that is coplanar or substantially co-planar with an uppermost surface of the dielectric layer 203. In an embodiment, the conductive interconnect 202 includes a barrier layer 202A, and a fill material 202B disposed on the barrier layer 202A. In an embodiment, the barrier layer includes a material such as but not limited to tantalum nitride, tantalum or ruthenium. In an embodiment, the fill metal includes a metal such as W or Cu. In an embodiment, the conductive interconnect 202 has a width, Wei. In an embodiment, the conductive interconnect 202 has a width, Wei that is greater than the width, Wrv, of the intermediate via 206. In an embodiment, the conductive interconnect 202 has a width, Wei that is greater than the width, WDB, of the dual bottom electrode 210. In an embodiment, the conductive interconnect 202 has a width, Wei that is substantially similar to the width, WDB, of the dual bottom electrode 210. In an embodiment, the conductive interconnect 202 has a width, Wei that is less than the width, WDB, of the dual bottom electrode 210.

In an embodiment, the dielectric layer 203 includes dielectric materials such as but not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. In an embodiment, the total thickness of dielectric layer 203 is between 30nm-100nm.

In an embodiment, the substrate 204 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, substrates 204 includes other semiconductor materials such as germanium, silicon germanium or a suitable group III-V compound Logic devices such as MOSFET transistors and access transistors and may be formed on the substrate 204. Logic devices such as access transistors may be integrated with memory devices such as the RRAM device 200 to form embedded memory. Embedded memory including pSTTM devices and logic MOSFET transistors can be combined to form functional integrated circuits such as a system on chip (SOC) and microprocessors.

Figures 3A-3 J illustrate cross sectional views representing various operations in a method of fabricating a resistive random access memory device integrated above a conductive interconnect, which may be used to fabricate a memory device such as described in association with Figure 2, in accordance with an embodiment of the present disclosure.

Figure 3 A illustrates a cross sectional view of a first conductive layer 302, an intermediate via 304 and a passivation layer 306 formed above a conductive interconnect 308 in a device region 300 and the passivation layer 306 and the first conductive layer 302 formed in a scribeline region 350, in accordance with an embodiment of the present disclosure.

In an embodiment, the conductive interconnect 308 is formed in a dielectric layer 310 above a substrate in the device region 300. In an embodiment, the conductive interconnect 308 is formed by a damascene or a dual damascene process that is well known in the art. In an embodiment, the conductive interconnect 308 is the same as or substantially the same as the conductive interconnect 202 described in association with Figure 2. In an embodiment, the conductive interconnect 308 includes a barrier layer 308A, and a fill material 308B disposed on the barrier layer 308A. In an embodiment, the dielectric layer 310 is the same as or substantially the same as the dielectric layer 203 described in association with Figure 2. The conductive interconnect 308 is formed in the device region 300 and not in the scribeline region 350.

In an embodiment, an intermediate via 304 is formed in the device region 300 by (1) blanket depositing a layer of a metal or a metal alloy on the conductive interconnect 308 and (2) performing a patterning process of the layer of the metal or metal alloy. In an embodiment, the patterning process includes plasma etching the metal or a metal alloy to form the intermediate via 304 over a portion of the conductive interconnect 308 in the device region 300. In an embodiment, the patterning process includes plasma etching the metal or a metal alloy to form the intermediate via 304 over an entire uppermost surface of the conductive interconnect 308 and on a portion of the dielectric layer 310, in the device region 300. In an embodiment, the intermediate via 304 includes a material that is the same as or substantially the same as the material of the intermediate via 206 described in association with Figure 2

In an embodiment, a passivation layer 306 is formed in the device region 300 and in the scribeline region 350 by (1) blanket depositing a layer of an insulating material on the intermediate via 304 and on the dielectric layer 310 and then (2) planarizing the insulating material to expose the intermediate via 304 in the device region 300.

In an embodiment, the planarization process results in the intermediate via 304 having an uppermost surface that is coplanar or substantially coplanar with an uppermost surface of the passivation layer 306. In an embodiment, the planarization process includes a polish process. In an embodiment, the passivation layer 306 includes a material that is the same as or substantially the same as the materials of the passivation layer 208 described in association with Figure 2.

In an embodiment, the first conductive layer 302 is deposited on the uppermost surface of the via and on the uppermost surface of the passivation layer 306 in the device region 300. In an embodiment, the first conductive layer 302 is also deposited on the uppermost surface of the passivation layer 306 in the scribeline region 350. In an embodiment, the first conductive layer 302 is blanket deposited by a physical vapor deposition (PVD), a chemical vapor deposition (CVD), a plasma enhanced chemical vapor deposition (PECVD) or an atomic layer deposition process (ALD). In an embodiment, the first conductive layer 302 includes a metal such as but not limited to W, Ru, Ti or Ta or an alloy such as but not limited to WN, TiN or TaN.

In an embodiment, the first conductive layer 302 includes a layer of TiN. In one embodiment, the layer of TiN is formed by a PVD process. In one embodiment, a layer of TiN deposited by a PVD process results in a layer having low resistivity. In an embodiment, the layer of TiN is deposited by a PVD process has an electrical resistivity between 100-150 μ-Ω- cm. In one embodiment, the layer of TiN, deposited by a PVD process has an electrical resistivity between 125-135 μ-Ω-cm.

In an embodiment, the first conductive layer 302 includes a layer of TiN. In one embodiment, the layer of TiN is deposited with a zero bias voltage during the PVD process. In one embodiment, a layer of TiN, deposited with a zero bias voltage during the PVD process, results in a layer having high resistivity. In an embodiment, the layer of TiN is deposited with a zero voltage bias and has an electrical resistivity between 250-350 μ-Ω-cm. In one specific embodiment, the layer of TiN, deposited with a zero voltage bias, has an electrical resistivity between 290-310 μ-Ω-cm.

In one embodiment, the layer of TiN is deposited to have a concentration of nitrogen that is between 40-50 atomic percent of the total composition of the layer of TiN. In an embodiment, the concentration of nitrogen in the layer of TiN is selected by adjusting a flow rate of nitrogen gas during the deposition process. In an embodiment, when the first conductive layer 302 includes a layer of TiN and formed with a concentration of nitrogen between 47-50 atomic percent of the total composition of the layer of TiN, the first conductive layer 302 has an electrical resistivity between 100-350μ-Ω-αη.

In an embodiment, the first conductive layer 302 is deposited to thickness between 20nm- 50nm. In an embodiment, when the first conductive layer 302 includes a layer of TiN and is blanket deposited by a physical vapor deposition (PVD) process, the layer of TiN is amorphous and an uppermost surface that can have a surface roughness of more than lnm. In an embodiment, the amorphous layer of TiN is deposited to a thickness of 50nm and subsequently planarized to reduce the thickness non-uniformity. In an embodiment, the planarization process reduces the thickness of the amorphous layer of TiN to 20nm.

Figure 3B illustrates the structure of Figure 3A following a planarization process. In an embodiment the planarization process includes a chemical mechanical polish (CMP) process. In an embodiment, the CMP process removes 10nm-30nm of first conductive layer 302. In an embodiment, the CMP process topographically planarizes the uppermost surface of the first conductive layer 302 resulting in a surface roughness of less than lnm. Reducing surface roughness of the first conductive layer 302 using a polishing process may offer advantages during cycling of an RRAM device as it may serve to reduce abrupt filament nucleation and hence lessen variation in cycling voltage in a large device array.

Figure 3C illustrates the structure of Figure 3B following a lithography process to define a location for the formation of an alignment mark structure in the scribeline region 350. In an embodiment, the lithography process involves the formation of a photoresist layer 312 on the planarized surface of the first conductive layer 302 and then exposing the photoresist layer 312 to form an alignment mask opening 314 in the scribeline region 350. In an embodiment, the alignment mask opening 314 will form an alignment mark that will help in a subsequent lithography process utilized to form an RRAM device.

Figure 3D illustrates the structure of Figure 3C following the formation of an alignment mark opening 316 in the first conductive layer 302, in the passivation layer 306 and in the dielectric layer 310 in the scribeline region 350 and the formation of an intermediate layer 320 on the first conductive layer 302. In an embodiment, a plasma etch process is utilized to form the alignment mark opening 3 16. In an embodiment, the plasma etch process etches an opening 317 in the first conductive layer 302, an opening 318 in the passivation layer 306 and an opening

319 in the dielectric layer 310 to form the alignment mask opening 3 14. In an embodiment, the plasma etch process forms an alignment mark opening 316 having a depth between 200nm-

300nm.

In an embodiment, once the alignment mask opening 314 is formed the photoresist is removed. In an embodiment, the photoresist is removed using an ash process. In an embodiment, the ash process may include use of a gas containing O2, H2 N2, and can substantially oxidize the surface of the first conductive layer 302 to form the intermediate layer

320 including oxygen. In an embodiment, the intermediate layer 320 has a thickness between 0.5nm - 1 nm. In an embodiment, the intermediate layer 320 has a thickness that is non-uniform over the surface of the first conductive layer 302. In an embodiment, the intermediate layer 320 has portions that are discontinuous over the surface of the first conductive layer 302.

Figure 3E illustrates the structure of Figure 3D following the formation of a second conductive layer 322 to form a dual bottom electrode layer 324. In an embodiment, the second conductive layer 322 is blanket deposited on the intermediate layer 320 in the device region 300 and in the alignment mark opening 316 on exposed surfaces of the dielectric layer 310 and on exposed sidewall surfaces of the passivation layer 306 and sidewall surfaces of the intermediate layer 320 in the scribeline region 350. In an embodiment, the process of depositing the second conductive layer 322 may include an in-situ sputter cleans to first remove the intermediate layer 320 from an uppermost surface of the first conductive layer 302. In an embodiment, a gas containing Ar is used to energetically bombard the intermediate layer 320. In an embodiment, the intermediate layer 320 becomes thinned as a result of the Ar-bombardment process, but is not fully removed. In an embodiment, some portions of the intermediate layer 320 become discontinuous as a result of the Ar bombardment process.

In an embodiment, the second conductive layer 322 is blanket deposited using a deposition process such as a PVD, CVD or an ALD process described above in connection with the formation of the first conductive layer 302. In an embodiment, the second conductive layer 322 includes a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ta and Ru. In an embodiment, the second conductive layer 322 includes a layer of TiN. In an embodiment, the second conductive layer 322 includes a layer of TiN deposited at a high bias voltage to form a layer of TiN having a resistivity between 100-150 μ-Ω-cm. In an embodiment, the second conductive layer 322 includes a layer of TiN formed with a concentration of nitrogen between 47-50 atomic percent of the total composition of the layer of TiN.

Figure 3F illustrates the structure of Figure 3E following a blanket formation of an RRAM material layer stack 326. In an embodiment, the RRAM material layer stack 326 is blanket deposited on the second conductive layer 322 in the device region 300 and in the alignment mark opening 316 on the second conductive layer 322 in the scribeline region 350.

In an embodiment, the deposition of the RRAM material layer stack 326 begins with a blanket deposition of a switching material layer 328 on the surface of the second conductive layer 322. In an embodiment, the switching material layer 328 is a material having a composition and a thickness such as described above in association with the switching layer 218. In an embodiment, the switching material layer 328 is formed using an ALD process. The ALD process may be characterized by a slow and a highly controlled metal oxide deposition rate. In an embodiment, a pre-clean of the surface of the bottom electrode material is performed immediately prior to deposition of the switching material layer 328. In an embodiment, the switching material layer 328 is formed using a PVD process. In an embodiment, a pre-clean of the surface of the bottom electrode material is performed using an Ar sputter clean immediately prior to deposition of the switching material layer 328.

Referring again to Figure 3F, an oxygen exchange material layer 330 is blanket deposited on the switching material layer 328. In an embodiment, the oxygen exchange material layer 330 is a material having a composition and a thickness such as described above in association with the switching layer 218. In an embodiment, the switching material layer 328 is formed using a PVD process. In one such embodiment, the switching material layer 328 and the oxygen exchange material layer 330 are deposited sequentially in a same chamber or in a same tool without breaking vacuum.

Referring again to Figure 3F, a top electrode layer 332 is deposited on the oxygen exchange material layer. In an embodiment the top electrode layer 332 includes a material that is the same as or substantially the same as the material of the top electrode 222. In an embodiment, the top electrode layer 332 is formed using a PVD process. In an embodiment, the top electrode layer 332 and the oxygen exchange material layer 330 are deposited sequentially in a same chamber or in a same tool without breaking vacuum. By doing so, the oxygen exchange material layer 330 does not become oxidized.

Figure 3G illustrates the structure of Figure 3F following the formation of a dielectric hardmask layer 334 and a device resist pattern 336 formed on the dielectric hardmask layer 334 to define a location for the subsequent formation of an RRAM device.

In an embodiment, the dielectric hardmask layer 334 is blanket deposited on top electrode layer 332 formed in the device region 300 and in the scribeline region 350. In an embodiment, the dielectric hardmask layer 334 is devoid of oxygen. In one embodiment, the dielectric hardmask layer 334 is a material such as, but not limited to, silicon nitride, silicon carbide or carbon-doped silicon nitride. In one embodiment, the dielectric hardmask layer 334 has a thickness approximately in the range of 20nm-50nm.

In an embodiment, a lithographic process utilizes a second lithographic mask to form the device resist pattern 336 on the dielectric hardmask layer 334. In an embodiment, the lithographic process aligns the second lithographic mask to the alignment mark opening 316 formed in the scribeline region 350. The process of aligning the second lithographic mask to the alignment mark opening 316 enables the device resist pattern 336 to be formed with a high degree of accuracy over the conductive interconnect 308 and over the intermediate via 304 in the device region 300.

In one embodiment, the device resist pattern 336 has rectangular shape or a circular shape. In one embodiment, the device resist pattern 336 has a width or a diameter in the range of 10-lOOnm. The device resist pattern 336 may include one or more materials such as an anti-reflective coating (ARC), gap-fill and planarizing material in addition to or in place of a photoresist material. In one embodiment, the device resist pattern 336 is formed to a thickness sufficient to retain its profile during subsequent patterning of the dielectric hardmask layer 334 but not so thick as to prevent lithographic patterning into the smallest dimensions (e.g., critical dimensions) possible with photolithography processing.

Figure 3H illustrates the structure of Figure 3G following an etch process used to transfer the pattern of device resist pattern 336 into (a) the dielectric hardmask layer 334 to form a dielectric hardmask 338, and into (b) the RRAM material layer stack 326 to form an REAM device 340. In an embodiment, an anisotropic plasma etch process is used to pattern dielectric hardmask layer 334 with selectivity to the resist pattern. It is to be appreciated that polymeric films, which may result from the interaction between a photoresist material and etch byproducts during memory device etch, may adhere to the sidewall portions of an etched RRAM material stack. If portions of such polymeric layers have metallic components, device performance may be significantly degraded. In one embodiment, the resist pattern is removed after the dielectric hardmask 338 is patterned but prior to etching RRAM material layer stack 326. In an embodiment, the device resist pattern 336 is removed using an ash process.

In an embodiment, etch process is continued to transfer the dielectric hardmask 338 to pattern the top electrode 342 layer, the oxygen exchange material layer, the switching material layer 328, and the dual bottom electrode layer 324 to form a top electrode 342, an oxygen exchange layer 344, a switching layer 346 and a dual bottom electrode 348. In an embodiment, the plasma etch process exposes an uppermost surface the passivation layer 306 in the device region 300 and in the scribeline region 350. In an embodiment, the plasma etch forms an RRAM sidewall spacer 352 in the alignment mark opening 316 as is depicted in the cross-sectional illustration of Figure 31. In an embodiment, the RRAM sidewall spacer 352 includes, a portion of the top electrode 342 layer, a portion of the oxygen exchange layer 344, portion of the oxygen exchange layer 344, and a portion of the second conductive layer 322

In an embodiment, the RRAM sidewall spacer 352 includes a portion of the as deposited second conductive layer 322 but not the as deposited first conductive layer 302 in the scribeline region. In an embodiment, portions of the dielectric hardmask 338 may remain (not shown) adjacent to the vertical portions of the top electrode 342 in the scribeline region 350.

Figure 31 illustrates the structure of Figure 3H following the formation of a dielectric spacer 354 on an uppermost surface of the top electrode 342, and on sidewalls of the RRAM device 340.

In an embodiment, a dielectric spacer layer is deposited immediately following the plasma etch process without breaking vacuum. In an embodiment, the dielectric spacer layer is deposited in the same tool or chamber used for the etch process. Such a procedure, known in the art, as in-situ deposition, may hermetically seal the device and potentially decrease oxidation of sensitive oxidizable layers. In an embodiment, the dielectric spacer layer includes a material such as but not limited to, silicon nitride, silicon carbide, carbon-doped silicon nitride, or any suitable non-oxygen containing material. In an embodiment, the dielectric spacer layer has a thickness approximately in the range of 10-50nm. In an embodiment, the dielectric spacer layer is etched by a plasma etch process to form a dielectric spacer 354 on sidewalls of the RRAM memory device. In an embodiment, the etch process may cause an uppermost portion of the dielectric hardmask layer 334 to become fully etched as is illustrated in Figure 31.

In an embodiment, the dielectric spacer 354 is formed in the alignment mark opening 316 adjacent to the dielectric hardmask 338 and adjacent to portions of the RRAM sidewall spacer 352, in the scribeline region 350.

Figure 4 illustrates a cross-sectional view of an RRAM device such as the RRAM device 340 formed above a conductive interconnect 402 coupled to an access transistor 408, in accordance with an embodiment. RRAM device 340 is described in association with Figures 3A-3I. RRAM device 340 includes the dual bottom electrode 324, the switching layer 346, the oxygen exchange layer 344, and the top electrode 342 The dual bottom electrode 324 includes the first conductive layer 302, the intermediate layer 320 and the second conductive layer 322. The RRAM device 340 is disposed on an intermediate via 440 and on a portion of a passivation layer 450. In an embodiment, the intermediate via 440 includes a material that is the same as or substantially the same as the material of the intermediate via 304 described in association with Figure 3A. In an embodiment, the passivation layer 450 includes a material that is the same as or substantially the same as the material of the passivation layer 306 described in association with Figure 3A.

In an embodiment, the passivation layer 450 and the intermediate via 440 are disposed on a conductive interconnect 430 that is coupled to a contact structure 404. In an embodiment, contact structure 404 is above and electrically coupled with a drain region 406 of an access transistor 408 disposed above a substrate 410. In an embodiment, the conductive interconnect 430 includes one or more embodiments of the conductive interconnect 202 described in association with Figure 2. In an embodiment, the conductive interconnect 430 is disposed is a via formed in a dielectric layer 403.

In an embodiment, the underlying substrate 410 represents a surface used to manufacture integrated circuits. Suitable substrate 410 includes a material such as single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The substrate 410 may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.

In an embodiment, the access transistor 408 associated with substrate 410 are metal- oxide- semi conductor field-effect transistors (MOSFET or simply MOS transistors), fabricated on the substrate 410. In various implementations of the disclosure, the access transistor 408 may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

In an embodiment, the access transistor 408 of substrate 410 includes a gate stack formed of at least two layers, a gate dielectric layer 414 and a gate electrode layer 412. The gate dielectric layer 414 may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer 414 to improve its quality when a high-k material is used.

The gate electrode layer 412 of the access transistor 408 of substrate 410 is formed on the gate dielectric layer 414 and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer 412 may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer.

For a PMOS transistor, metals that may be used for the gate electrode layer 412 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode layer 412 with a workfunction that is between about 4.9 eV and about 4.2 eV. For an NMOS transistor, metals that may be used for the gate electrode layer 412 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode layer 412 with a workfunction that is between about 3.9 eV and about 4.2 eV.

In some implementations, the gate electrode layer 412 may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode layer 412 may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode layer 412 may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode layer 412 may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some implementations of the disclosure, a pair of sidewall spacers 416 may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers 416 may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source region 418 and drain region 406 are formed within the substrate adjacent to the gate stack of each MOS transistor. The source region 418 and drain region 406 are generally formed using either an implantation/diffusion process or an etching deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source region 418 and drain region 406. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source region 418 and drain region 406. In some implementations, the source region 418 and drain region 406 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source region 418 and drain region 406 may be formed using one or more alternate semiconductor materials such as germanium or a suitable group III-V compound. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source region 418 and drain region 406.

In an embodiment, an RRAM contact 426 is disposed in a second dielectric layer 424 disposed above the passivation layer 450. In an embodiment, second dielectric layer includes a material that is similar to or substantially similar to the material of the dielectric layer 403. In an embodiment, a gate contact 420 and a source contact 422 are disposed in the dielectric layer 403 above the gate electrode layer 412 and source region 418, respectively. In an embodiment, a source conductive interconnect 460 is disposed in a via formed in the second dielectric layer 424 and in the passivation layer 450. The source conductive interconnect 460 is in contact with and coupled with the source contact 422. In an embodiment, a gate conductive interconnect 470 is disposed in a via formed in the second dielectric layer 424 and in the passivation layer 450. The gate conductive interconnect 470 is in contact with and coupled with the gate contact 420.

Figure 5 illustrates a computing device 500 in accordance with one embodiment of the disclosure. The computing device 500 houses a motherboard 502. The motherboard 502 may include a number of components, including but not limited to a processor 504 and at least one communication chip 506. The processor 504 is physically and electrically coupled to the motherboard 502. In some implementations the at least one communication chip 506 is also physically and electrically coupled to the motherboard 502. In further implementations, the communication chip 506 is part of the processsor 504.

Depending on its applications, computing device 500 may include other components that may or may not be physically and electrically coupled to the motherboard 502. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 506 enables wireless communications for the transfer of data to and from the computing device 500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 506 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (ΓΕΕΕ 802.1 1 family), WiMAX (IEEE 802.11 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 500 may include a plurality of communication chips 506. For instance, a first communication chip 506 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 506 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 504 of the computing device 500 includes an integrated circuit die packaged within the processor 504. In some implementations of embodiments of the disclosure, the integrated circuit die of the processor includes one or more memory devices, such as an RRAM device 340 including a dual bottom electrode 326 in accordance with embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 506 also includes an integrated circuit die packaged within the communication chip 506. In accordance with another implementation of an embodiment of the disclosure, the integrated circuit die of the communication chip includes RRAM elements such as RRAM device 340 integrated with access transistors, built in accordance with embodiments of the present disclosure.

In further implementations, another component housed within the computing device 500 may contain a stand-alone integrated circuit memory die that includes one or more memory elements such as RRAM device 340, built in accordance with embodiments of the present disclosure.

In various implementations, the computing device 500 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 500 may be any other electronic device that processes data.

Figure 6 illustrates an integrated circuit (IC) structure 600 that includes one or more embodiments of the disclosure. The integrated circuit (IC) structure 600 is an intervening structure used to bridge a first substrate 602 to a second substrate 604. The first substrate 602 may be, for instance, an integrated circuit die. The second substrate 604 may be, for instance, a memory module, a computer mother, or another integrated circuit die. The memory module may include one or more memory devices such as an RRAM device 200 or an RRAM device 340. Generally, the purpose of an integrated circuit (IC) structure 600 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an integrated circuit (IC) structure 600 may couple an integrated circuit die to a ball grid array (BGA) 606 that can subsequently be coupled to the second substrate 604. In some embodiments, the first and second substrates 602/604 are attached to opposing sides of the integrated circuit (IC) structure 600. In other embodiments, the first and second substrates 602/604 are attached to the same side of the integrated circuit (IC) structure 600. And in further embodiments, three or more substrates are interconnected by way of the integrated circuit (IC) structure 600.

The integrated circuit (IC) structure 600 may be formed of an epoxy resin, a fiberglass- reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the integrated circuit (IC) structure 600 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a

semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The integrated circuit (IC) structure 600 may include metal interconnects 608 and via 610, including but not limited to through-silicon vias (TSVs) 610. The integrated circuit (IC) structure 600 may further include embedded devices 614, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, transistors, one or more RRAM devices such as RRAM device 200 and/or RRAM device 340, sensors, and electrostatic discharge (ESD) devices More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the integrated circuit (IC) structure 600. In accordance with embodiments of the present disclosure, apparatuses or processes disclosed herein may be used in the fabrication of integrated circuit (IC) structure 600.

Thus, embodiments of the present disclosure include a dual bottom electrode for memory applications and methods of fabrication.

Specific embodiments are described herein with respect to memory devices such as resistive random access based memory devices It is to be appreciated that embodiments described herein may also be applicable to other non-volatile memory devices. Such nonvolatile memory devices may include, but are not limited to, magnetic tunnel junction memory (MTJ) devices such as in plane MTJ devices, perpendicular MTJ devices, spin torque transfer memory devices such as in-plane STTM devices and perpendicular STTM devices, and certain class of ferroelectric memory devices or conductive bridge memory devices.

Example 1 : An electrode structure includes a first conductive layer disposed above a substrate. A second conductive layer is disposed above the First conductive layer, and an intermediate layer is disposed between the first conductive layer and the second conductive layer, wherein the intermediate layer includes oxygen.

Example 2: The electrode structure of example 1, wherein the first conductive layer includes a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ta and Ru.

Example 3 : The electrode structure of example 1, wherein second conductive layer includes a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ta and Ru.

Example 4: The electrode structure of example 1 or 3, wherein the first conductive layer and the second conductive layer include a same material. Example 5: The electrode structure of example 1, 2 or 3, wherein the first conductive layer includes a TiN having a first nitrogen concentration, and wherein the second conductive layer includes a TiN having a second nitrogen concentration, wherein the concentration of nitrogen in the second conductive layer is greater than the concentration of nitrogen in the first conductive layer.

Example 6: The electrode structure of example 1, wherein the intermediate layer has a non-uniform oxygen composition.

Example 7: The electrode structure of example 1 or 6, wherein the intermediate layer has a thickness that is non-uniform.

Example 8: The electrode structure of example 1, wherein the intermediate layer has portions that are discontinuous.

Example 9: The electrode structure of example 1, 3, 4 or 5, wherein the first conductive layer has a thickness that is greater than a thickness of the second conductive layer.

Example 10: The electrode structure of example 1 or 2, wherein the first conductive layer has a thickness between lOnm and 50nm.

Example 11 : The electrode structure of example 1 or 3, wherein the second conductive layer has a thickness between lOnm and 25nm.

Example 12: A memory device includes a dual bottom electrode layer disposed above a substrate. The dual bottom electrode includes a first conductive layer disposed above a substrate, a second conductive layer disposed above the first conductive layer and an intermediate layer disposed between the first conductive layer and the second conductive layer, wherein the intermediate layer includes oxygen A switching layer is disposed on the dual bottom electrode layer. An oxygen exchange layer is disposed on the switching layer and a top electrode is disposed on the switching layer.

Example 13 : The memory device of example 12, wherein the first conductive layer includes a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ta and Ru.

Example 14: The memory device of example 12, wherein second conductive layer includes a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ta and Ru.

Example 15 : The memory device of example 12, wherein material of the first conductive layer includes a TiN having a first nitrogen concentration, and wherein the second conductive layer includes a TiN having a second nitrogen concentration, wherein the concentration of nitrogen in the second conductive layer is greater than the concentration of nitrogen in the first conductive layer.

Example 16: The memory device of example 12, wherein the intermediate layer has a non-uniform oxygen composition. Example 17: The memory device of example 12, wherein the intermediate layer has portions that are discontinuous.

Example 18: The memory device of example 12 or 13, wherein the first conductive layer has a thickness between lOnm and 50nm.

Example 19: The memory device of example 12 or 14, wherein the second conductive layer has a thickness between lOnm and 25nm.

Example 20: The memory device of example 12, wherein the switching layer includes an oxide selected from the group consisting of hafnium oxide, tantalum oxide, zirconium oxide, titanium oxide, aluminum oxide and tungsten oxide.

Example 21 : A method of fabricating an electrode structure includes forming a conductive interconnect in a dielectric layer above a substrate. The method further includes forming a first conductive layer disposed above the conductive interconnect. The method further includes planarizing the first conductive layer to form a planarized first conductive layer. The method further includes forming a resist mask on the planarized first conductive layer. The method further includes etching an opening in the planarized first conductive layer and in the dielectric layer. The method further includes performing a plasma ash process to remove the resist mask, where the ashing process oxidizes an uppermost surface of the planarized first conductive layer and forms an intermediate layer including oxygen. The method further includes forming a second conductive layer on the planarized first conductive layer in the opening on sidewall portions of the planarized first conductive layer and in the dielectric layer and patterning the first and second conductive layers to form an electrode.

Example 22: The method of example 21, wherein forming the electrode structure further includes forming a material layer stack for a resistive random access memory (RRAM) device on the second conductive layer and forming a second resist mask on the material layer stack for the RRAM device, prior to patterning the first conductive layer and the second conductive layer

Example 23 : The method of example 22, wherein forming the second mask includes aligning the second mask to the opening in the first conductive layer.

Example 24: The method of example 22, wherein forming the RRAM material layer stack includes depositing the oxygen exchange material layer on the bottom electrode layer, then depositing the switching oxide material layer on the oxygen exchange material layer, and then depositing the top electrode layer on the oxygen exchange material layer.

Example 25 : The method of example 22, wherein forming the electrode structure further includes forming a passivation layer between the conductive interconnect and the first conductive layer and a via in the passivation layer electrically coupling the conductive interconnect and the first conductive layer.

Claims

What is claimed is: 1. An electrode structure comprising:

a first conductive layer above a substrate;

a second conductive layer above the first conductive layer; and

an intermediate layer between the first conductive layer and the second conductive layer, wherein the intermediate layer comprises oxygen.

2. The electrode structure of claim 1, wherein the first conductive layer comprises a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ta and Ru.

3. The electrode structure of claim 1, wherein second conductive layer comprises a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ta and Ru.

4. The electrode structure of claim 3, wherein the first conductive layer and the second conductive layer include a same material.

5. The electrode structure of claim 1, wherein the first conductive layer comprises a TiN having a first nitrogen concentration, and wherein the second conductive layer comprises a TiN having a second nitrogen concentration, wherein the concentration of nitrogen in the second conductive layer is greater than the concentration of nitrogen in the first conductive layer.

6. The electrode structure of claim 1, wherein the intermediate layer has a non-uniform oxygen composition.

7. The electrode structure of claim 1, wherein the intermediate layer has a thickness that is nonuniform

8. The electrode structure of claim 1, wherein the intermediate layer has portions that are discontinuous.

9. The electrode structure of claim 1, wherein the first conductive layer has a thickness that is greater than a thickness of the second conductive layer.

10. The electrode structure of claim 1, wherein the first conductive layer has a thickness between lOnm and 50nm.

11. The electrode structure of claim 1, wherein the second conductive layer has a thickness between lOnm and 25nm.

12. A memory device, comprising:

a dual bottom electrode layer above a substrate, the dual bottom electrode comprising: a first conductive layer above a substrate;

a second conductive layer above the first conductive layer;

an intermediate layer between the first conductive layer and the second conductive layer, wherein the intermediate layer comprises oxygen;

a switching layer on the dual bottom electrode layer;

an oxygen exchange layer on the switching layer; and

a top electrode on the switching layer.

13. The memory device of claim 12, wherein the first conductive layer comprises a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ta and Ru.

14. The memory device of claim 12, wherein second conductive layer comprises a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ta and Ru.

15. The memory device of claim 12, wherein material of the first conductive layer comprises a TiN having a first nitrogen concentration, and wherein the second conductive layer comprises a

TiN having a second nitrogen concentration, wherein the concentration of nitrogen in the second conductive layer is greater than the concentration of nitrogen in the first conductive layer.

16. The memory device of claim 12, wherein the intermediate layer has a non-uniform oxygen composition.

17. The memory device of claim 12, wherein the intermediate layer has portions that are discontinuous.

18. The memory device of claim 12, wherein the first conductive layer has a thickness between lOnm and 50nm.

19. The memory device of claim 12, wherein the second conductive layer has a thickness between lOnm and 25nm.

20. The memory device of claim 12, wherein the switching layer includes an oxide selected from the group consisting of hafnium oxide, tantalum oxide, zirconium oxide, titanium oxide, aluminum oxide and tungsten oxide.

21. A method of fabricating an electrode structure, the method comprising:

forming a conductive interconnect in a dielectric layer above a substrate; forming a first conductive layer above the conductive interconnect;

planarizing the first conductive layer to form a planarized first conductive layer; forming a resist mask on the planarized first conductive layer;

etching an opening in the planarized first conductive layer and into the dielectric layer;

performing a plasma ash process to remove the resist mask, wherein the ashing process oxidizes an uppermost surface of the planarized first conductive layer and forms an intermediate layer comprising oxygen;

forming a second conductive layer on the planarized first conductive layer, in the opening on sidewall portions of the planarized first conductive layer and in the dielectric layer; and

patterning the first and second conductive layers to form an electrode.

22. The method of claim 21, wherein forming the electrode structure further includes forming a material layer stack for a resistive random access memory (RRAM) device on the second conductive layer and forming a second resist mask on the material layer stack for the RRAM device, prior to patterning the first conductive layer and the second conductive layer.

23. The method of claim 22, wherein forming the second mask includes aligning the second mask to the opening in the first conductive layer.

24. The method of claim 22, wherein forming the RRAM material layer stack includes depositing the oxygen exchange material layer on the bottom electrode layer, then depositing the switching oxide material layer on the oxygen exchange material layer, and then depositing the top electrode layer on the oxygen exchange material layer.

25. The method of claim 22, wherein forming the electrode structure further includes forming a passivation layer between the conductive interconnect and the first conductive layer and a via in the passivation layer electrically coupling the conductive interconnect and the first conductive layer.