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WO2019066900A1 - Appareil avec un substrat formé par dépôt autocatalytique de métal en utilisant des polyélectrolytes pour adsorber des ions métalliques dans le substrat - Google Patents

Appareil avec un substrat formé par dépôt autocatalytique de métal en utilisant des polyélectrolytes pour adsorber des ions métalliques dans le substrat Download PDF

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Publication number
WO2019066900A1
WO2019066900A1 PCT/US2017/054299 US2017054299W WO2019066900A1 WO 2019066900 A1 WO2019066900 A1 WO 2019066900A1 US 2017054299 W US2017054299 W US 2017054299W WO 2019066900 A1 WO2019066900 A1 WO 2019066900A1
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WO
WIPO (PCT)
Prior art keywords
metal
polyelectrolyte
ions
substrate
solution
Prior art date
Application number
PCT/US2017/054299
Other languages
English (en)
Inventor
Ali LEHAF
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2017/054299 priority Critical patent/WO2019066900A1/fr
Publication of WO2019066900A1 publication Critical patent/WO2019066900A1/fr

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Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/18—Pretreatment of the material to be coated
    • C23C18/20—Pretreatment of the material to be coated of organic surfaces, e.g. resins
    • C23C18/28—Sensitising or activating
    • C23C18/30—Activating or accelerating or sensitising with palladium or other noble metal
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/18—Pretreatment of the material to be coated
    • C23C18/20—Pretreatment of the material to be coated of organic surfaces, e.g. resins
    • C23C18/2006—Pretreatment of the material to be coated of organic surfaces, e.g. resins by other methods than those of C23C18/22 - C23C18/30
    • C23C18/2046—Pretreatment of the material to be coated of organic surfaces, e.g. resins by other methods than those of C23C18/22 - C23C18/30 by chemical pretreatment
    • C23C18/2073—Multistep pretreatment
    • C23C18/2086—Multistep pretreatment with use of organic or inorganic compounds other than metals, first
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31—Coating with metals
    • C23C18/38—Coating with copper
    • C23C18/40—Coating with copper using reducing agents
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating

Definitions

  • PCB printed circuit board
  • Electroless deposition is routinely employed in the electronic industry to form a seed layer in substrates for subsequent electroless plating of copper or other metals.
  • the resulting metal plating may be used to form metallic interconnects on buildup films/composite polymeric materials of the substrates.
  • Buildup films in semiconductor packaging typically include epoxy resins, surface finish films, molding compounds, photo imageable dielectrics, and other types of organic films.
  • Electroless deposition typically uses a Desmear process to roughen a dielectric onto which copper plating is to be applied. Once applied, ions may be applied to the roughened surface and may sit in the pores created by the roughening for later reducing to be used as a seed layer.
  • FIG. 1 illustrates a cross-section side view of an example integrated circuit (IC) assembly comprising a semiconductor device, in accordance with some embodiments.
  • IC integrated circuit
  • FIG. 2 illustrates an example cross-sectional view of a substrate of a
  • FIG. 3 is an example process flow diagram for provision of a substrate of a semiconductor device, in accordance with some embodiments.
  • FIG. 4 shows example poly electrolytes and seed metals, in accordance with some embodiments.
  • FIG. 5 illustrates an example computing device that may employ the apparatuses and/or methods described herein, according to various embodiments. Detailed Description
  • Embodiments of the present disclosure include techniques and configurations for providing an apparatus with a substrate tuned with charged polyelectrolyte to facilitate metal seeding for subsequent electroless plating.
  • the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus.
  • the metal layer may be provided in response to a treatment of the surface with a polyelectrolyte solution having an electrical charge to provide adsorption of metal ions to the surface, and subsequent electroless plating of the surface with a metal.
  • the adsorbed metal ions are to enhance electroless plating of the surface with the metal.
  • phrase “A and/or B” means (A), (B), (A) or (B), or (A and B).
  • phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
  • Coupled with along with its derivatives, may be used herein.
  • Coupled may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical, electrical, or optical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term “directly coupled” may mean that two or more elements are in direct contact.
  • FIG. 1 illustrates a cross-section side view of an example integrated circuit (IC) assembly comprising a semiconductor device, in accordance with some embodiments.
  • the IC assembly 100 may comprise a semiconductor package device, for example, an integrated circuit (IC), such as a central processing unit (CPU) or a memory unit, and may further comprise a portion of a computing device, such as a graphics device, wireless device, multi-chip package including a combination with other devices, or the like.
  • IC integrated circuit
  • CPU central processing unit
  • memory unit a portion of a computing device, such as a graphics device, wireless device, multi-chip package including a combination with other devices, or the like.
  • the IC assembly 100 may include one or more dies
  • die 102 electrically and/or physically coupled with a package assembly 121 (sometimes referred to as a "package substrate").
  • package assembly 121 may be electrically coupled with a circuit board 122.
  • the die 102 may represent a discrete product made from a semiconductor material (e.g., silicon) using semiconductor fabrication techniques such as thin film deposition, lithography, etching, and the like used in connection with forming complementary metal- oxide-semiconductor (CMOS) devices.
  • CMOS complementary metal- oxide-semiconductor
  • the die 102 may be, include, or be a part of a radio frequency (RF) die.
  • RF radio frequency
  • the die may be, include, or be a part of a processor, memory, system-on-chip (SoC), SiP, or ASIC.
  • SoC system-on-chip
  • an underfill material 108 (sometimes referred to as an
  • the underfill material 108 may be composed of an electrically insulative material and may encapsulate at least a portion of the die 102 and/or the die-level interconnect structures 106. In some embodiments, the underfill material 108 may be in direct contact with the die-level interconnect structures 106.
  • the die 102 can be attached to the package assembly 121 according to a wide variety of suitable configurations including, for example, being directly coupled with the package assembly 121 in a flip-chip configuration, as depicted.
  • an active side, SI of the die 102 including active circuitry is attached to a surface of the package assembly 121 using die-level interconnect structures 106 such as bumps, pillars, or other suitable structures that may also electrically couple the die 102 with the package assembly 121.
  • the active side SI of the die 102 may include transistor devices, and an inactive side, S2, may be disposed opposite to the active side SI .
  • the die 102 may generally include a semiconductor substrate 102a, one or more device layers (hereinafter “device layer 102b"), and one or more interconnect layers (hereinafter “interconnect layer 102c").
  • the semiconductor substrate 102a may be substantially composed of a bulk semiconductor material such as, for example, silicon, in some embodiments.
  • the device layer 102b may represent a region where active devices such as transistor devices are formed on the semiconductor substrate 102a.
  • the device layer 102b may include, for example, structures such as channel bodies and/or source/drain regions of transistor devices.
  • the interconnect layer 102c may include interconnect structures that are configured to route electrical signals to or from the active devices in the device layer 102b.
  • the interconnect layer 102c may include trenches and/or vias to provide electrical routing and/or contacts.
  • the die-level interconnect structures 106 may be configured to route electrical signals between the die 102 and other electrical devices.
  • the electrical signals may include, for example, input/output (I/O) signals and/or power/ground signals that are used in connection with operation of the die 102.
  • the package assembly 121 may include a multi-layer package assembly with integrated components for wireless communication.
  • the wireless communication may include, for example, short range wireless data transfer between portable devices and/or wireless displays or high speed wireless communication between peer devices.
  • the package assembly 121 may include electrical routing features (not shown in FIG. 1) such as, for example, traces, pads, through-holes, vias, or lines configured to route electrical signals to or from the die 102.
  • the package assembly 121 may be configured to route electrical signals between the die 102 and components for wireless communication that are integrated within the package assembly, or between the die 102 and the circuit board 122, or between the die 102 and another electrical component (e.g., another die, interposer, interface, component for wireless communication, etc.) coupled with the package assembly 121.
  • the semiconductor substrate 102a may include a surface 1 10 provided with poly electrolyte and metal ions used to form a metal layer for signal routing for the IC assembly 100 according to various embodiments described herein.
  • the circuit board 122 may be a printed circuit board (PCB) composed of an electrically insulative material such as an epoxy laminate.
  • the circuit board 122 may include electrically insulating layers composed of materials, such as
  • circuit board 122 may be composed of other suitable materials in other embodiments.
  • the circuit board 122 may be a motherboard or other PCB in a computing device (e.g., described in reference to FIG. 5).
  • Package-level interconnects such as solder balls 112 may be coupled with the package assembly 121 and/or the circuit board 122 to form corresponding solder joints that are configured to further route the electrical signals between the package assembly 121 and the circuit board 122.
  • the circuit board 122 may include a substrate 124 with a surface formed with an electroless plating process in accordance with embodiments described herein. Other suitable techniques to physically and/or electrically couple the package assembly 121 with the circuit board 122 may be used in other embodiments.
  • the IC assembly 100 may include a wide variety of other suitable configurations in other embodiments including, for example, suitable combinations of flip-chip and/or wire- bonding configurations, interposers, multi-chip package configurations including system- in-package (SiP) and/or package-on-package (PoP) configurations.
  • SiP system- in-package
  • PoP package-on-package
  • Other suitable techniques to route electrical signals between the die 102 and other components of the IC package assembly 100 may be used in some embodiments.
  • the embodiments described herein provide for modifying a surface charge of a dielectric material or other polymer film material to facilitate adsorption of metal ions on the surface of the material.
  • the metal ions may then act as a seed layer for subsequent electroless plating of the surface of the material.
  • An example polymer film material is solder resist.
  • the dielectric material or polymer film may include solder resist, and may be part of a substrate.
  • Modifying the surface charge may also be referred to as "tuning" a surface charge to facilitate adsorption of metal ions.
  • the process may include dipping and subsequently coating the surface into a positively or negatively charged polyelectrolyte (or polymer) to modify the surface charge.
  • the resulting electrically charged coating may cause metal ions having an opposite charge to be attracted to and adsorbed on the surface of the material.
  • Pd ions that are positively charged can be attracted to a negatively charged coated surface by dipping the material in negatively charged polyelectrolyte. This process can help Pd ions to adsorb more uniformly on the surface, independent of surface roughness. These adsorbed Pd ions can be then reduced in reducer bath to form metal seeds on the surface that are required for subsequent electroless plating of the substrate surface.
  • EMIB electroless copper plating on top of solder resist. Dipping a solder resist panel in negative or charged polyelectrolyte may facilitate the adsorption of metal ion seeds necessary for electroless copper plating independent of roughening the surface.
  • FIG. 2 illustrates an example cross-sectional view of a substrate of a
  • the substrate 230a which may be similar to substrate 102a or the substrate comprising the package assembly 121, may go through different stages 230b-230d as described further below.
  • the substrate 230a may be a surface of some other object, for example a dielectric, solder resist, or a polymer film, to which electroless plating may be applied.
  • substrate 230a may have a polyelectrolyte 232 applied to a surface of the substrate 230a.
  • the polyelectrolyte 232 may include a polymer solution and may be positively charged or negatively charged.
  • Examples of a negatively charged polyelectrolyte 232 may include poly(acrylic acid) (PAA) and poly(styrene sulfonate) (PSS).
  • Examples of a positively charged polyelectrolyte 232 may include poly allyl amine hydrochloride (PAH).
  • the polyelectrolyte 232 may be applied by dipping the substrate 230a into the polyelectrolyte 232.
  • the polyelectrolyte 232 may be applied using other processes, such as spraying, brushing, and the like. As a result, a coating with an electrical charge 23 Obi may adhere to the substrate 230b.
  • coatings of positively charged and negatively charged polyelectrolytes may be interleaved (not shown) on the surface of the substrate 230b. Such interleaving of coatings may provide additional layers to which either positively charged or negatively charged ions may subsequently attach.
  • the coated substrate 230b may then be exposed to an ion solution 234.
  • the ion solution 234 may also be referred to as a transition ion catalyst or an ion catalyst.
  • the ion solution may include ions that are either positively charged or negatively charged.
  • the ion solution 234 may be applied by dipping the substrate 230b into the solution.
  • the ion solution 234 may be applied using other processes, such as spraying and the like.
  • Ions 240 within the ion solution 234 may have either a positive charge or a negative charge.
  • Ions 240 having a positive charge may be attracted to coatings of the substrate 230b that have a negative charge, and ions 240 having a negative charge may be attracted to coatings of the substrate 230 be that have a positive charge.
  • the difference in charges between the ions and the coated substrate may enhance adsorption of the ions into the substrate surface, and result in an ion coated substrate 230c.
  • ion solution 234 may include palladium (Pd) ions 240 that have a positive charge.
  • Pd palladium
  • Pd ions 240 may be attracted to the coated substrate 230b resulting in the Pd ion coated substrate 230c.
  • the ion coated substrate 230c may then be exposed to a reducing agent 236.
  • the reducing agent 236 may be applied by dipping the ion coated substrate 230c into the reducing agent 236.
  • the reducing agent 236 may also be applied using other processes.
  • ions 240 may be converted to metal atoms 242 that are attached to the substrate 230d.
  • Pd ions after exposure to a reducing agent, may be converted to Pd metal atoms.
  • the resulting metal atoms 242 attached to the substrate 230d may be used as a seed metal for subsequent electroless plating process on the surface of the substrate 230d.
  • the electroless plating process may include plating copper metal onto the surface.
  • FIG. 3 is an example process flow diagram for provision of a substrate of a semiconductor device, in accordance with some embodiments.
  • the semiconductor device may comprise a package, a PCB, or other semiconductor device using a polymer film, dielectric material, solder resist, or appropriate material that includes metal plating using an electroless plating process.
  • the process 300 may comport with embodiments described in reference to FIG. 2. The actions described in the process 300 may occur in a different order or in parallel; the order provided below is for purposes of illustration and does not limit this disclosure.
  • the process 300 may begin at block 302 and include performing a polyelectrolyte solution (e.g. polyelectrolyte 232) treatment to a surface of a substrate (e.g. substrate 230a) to create a coating (e.g. 230bl) on the surface having an electrical charge.
  • a polyelectrolyte solution e.g. polyelectrolyte 232
  • a coating e.g. 230bl
  • the electrical charge may be a positive charge or a negative charge depending on the choice of polyelectrolyte 232.
  • the coating 230bl may include multiple coatings of one or more types of polyelectrolyte 232, where different types of polyelectrolyte 232 may have different types of electrical charge.
  • the process may include applying a transition ion catalyst (e.g. ion solution 234) to the coated surface (e.g. 230b) based at least upon the electrical charge of the coating and an electrical charge of ions in the ion catalyst.
  • a transition ion catalyst e.g. ion solution 234
  • the ion catalyst e.g., Pd
  • the ion catalyst may serve to enhance electroless plating of the surface.
  • the process may include exposing the coated surface to a reducing agent (e.g. reducing agent 236) to cause the ions adsorbed into the surface to turn to metal. As described above, this metal may then form seeds to facilitate the electroless plating process.
  • a reducing agent e.g. reducing agent 236
  • the process may include applying an electroless plating process to the surface.
  • the electroless plating process may be used to apply a copper plating to the coated surface using the metal seeds described above.
  • FIG. 4 illustrates an example computing device that may employ the apparatuses and/or methods described herein, according to various embodiments.
  • the motherboard 402 of the computing device 400 may include a number of components, including but not limited to a processor 404 and at least one communication chip 406.
  • the processor 404 may be physically and electrically coupled to the motherboard 402.
  • the communication chip 406 may also be physically and electrically coupled to the motherboard 402.
  • the communication chip 406 may be part of the processor 404.
  • the computing device 400 may further include an antenna 416.
  • the computing device 400 may include other components that may or may not be physically and electrically coupled to the motherboard 402. Some of these components are shown in FIG. 4 for purposes of explanation. These other components may include, but are not limited to, volatile memory (e.g., dynamic random-access memory (DRAM)) 408, static random access memory (SRAM) 409, nonvolatile memory (e.g., read-only memory (ROM)) 410, flash memory 411, a graphics central processing unit (CPU) 412, a digital signal processor 413, a chipset 414, a display (e.g., a touchscreen display) 418, a touchscreen controller 420, a battery 422, an audio codec, a video codec, a power amplifier (not shown), a global positioning system (GPS) device 426, a compass 428, a Geiger counter, an accelerometer, a gyroscope (not shown), a speaker 430, a camera 417, and a mass storage device 432
  • volatile memory
  • At least some of the computing device 400 components may be provided with a substrate provided with a charged surface, in accordance with embodiments of FIGS. 1-3.
  • the communication chip 406 may enable wireless communications for the transfer of data to and from the computing device 400.
  • the communication chip 406 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.7 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as "3GPP2”), etc.).
  • IEEE Institute for Electrical and Electronic Engineers
  • Wi-Fi IEEE 802.7 family
  • IEEE 802.16 standards e.g., IEEE 802.16-2005 Amendment
  • LTE Long-Term Evolution
  • LTE Long-Term Evolution
  • UMB ultra mobile broadband
  • WiMAX WiMAX networks
  • WiMAX Worldwide Interoperability for Microwave Access
  • the communication chip 406 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.
  • GSM Global System for Mobile Communication
  • GPRS General Packet Radio Service
  • UMTS Universal Mobile Telecommunications System
  • High Speed Packet Access HSPA
  • E-HSPA Evolved HSPA
  • LTE LTE network.
  • the communication chip 406 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E- UTRAN).
  • EDGE Enhanced Data for GSM Evolution
  • GERAN GSM EDGE Radio Access Network
  • UTRAN Universal Terrestrial Radio Access Network
  • E- UTRAN Evolved UTRAN
  • the communication chip 406 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • CDMA Code Division Multiple Access
  • TDMA Time Division Multiple Access
  • DECT Digital Enhanced Cordless Telecommunications
  • EV-DO Evolution-Data Optimized
  • derivatives thereof as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the communication chip 406 may operate in accordance with other wireless protocols in other embodiments.
  • the computing device 400 may include a plurality of communication chips 406.
  • a first communication chip 406 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 406 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others.
  • the computing device 400 may be a server, a mobile computing device, a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 400 may be any other electronic device that processes data.
  • Example 1 may be an apparatus, comprising: a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus, wherein the metal layer is provided in response to a treatment of the surface with a poly electrolyte solution having an electrical charge to provide adsorption of metal ions to the surface and subsequent electroless plating of the surface with a metal, wherein the adsorbed metal ions are to enhance electroless plating of the surface with the metal.
  • Example 2 may include the apparatus of example 1, wherein the treatment of the surface with a polyelectrolyte further includes a plurality of treatments of the surface respectively with a plurality of polyelectrolyte solutions, and wherein each of the polyelectrolyte solutions have a positive charge or a negative charge.
  • Example 3 may include the apparatus of example 1, wherein the metal includes copper.
  • Example 4 may include the apparatus of any one of examples 1-3, wherein the polyelectrolyte solution includes poly acrylic acid, polystyrene sulfonate, or poly allylamine hydrochloride.
  • Example 5 may include the apparatus of any one of examples 1-3, wherein the metal ions include palladium (Pd) ions.
  • Example 6 may include the apparatus of any one of examples 1-3, wherein the substrate includes a dielectric material, a polymer film, or solder resist.
  • Example 7 may include the apparatus of any one of examples 1-3, wherein the adsorbtion of metal ions to the surface further includes adsorbtion of metal ions to the surface in response to exposure to a reducing agent.
  • Example 8 may include the apparatus of any one of examples 1-3, wherein the apparatus is an embedded multi-die interconnect bridge (EMIB).
  • EMIB embedded multi-die interconnect bridge
  • Example 9 may be a method for plating, comprising: performing a polyelectrolyte solution treatment to a surface of a substrate to create a coating on the surface having an electrical charge; and applying a transition ion catalyst to the coated surface based at least upon the electrical charge of the coating and an electrical charge of ions in the ion catalyst.
  • Example 10 may include the method of example 9, further comprising conducting electroless plating of the surface with a metal, wherein the transition metal catalyst is to enhance electroless plating of the substrate surface.
  • Example 11 may include the method of example 9, wherein applying an ion catalyst to the coated surface further includes applying an ion solution to the coated surface to cause ions in the solution to be adsorbed to the coated surface based upon the electrical charge of the coating and an electrical charge of the ions.
  • Example 12 may include the method of example 11, wherein applying an ion solution to the coated surface further includes dipping the coated surface into the ion solution.
  • Example 13 may include the method of example 11, further including applying a reducing agent to the coated surface to attach the ions to the coated surface.
  • Example 14 may include the method of example 13, wherein applying a reducing agent to the coated surface further includes dipping the coated surface into the reducing agent.
  • Example 15 may include the method of example 9, wherein applying a
  • polyelectrolyte solution to a surface of the material further includes dipping the surface of the material into the polyelectrolyte solution.
  • Example 16 may include the method of example 9, wherein applying a
  • polyelectrolyte solution to a surface of the material to create a coating on the surface of the material further includes applying a plurality of polyelectrolyte solutions respectively to the surface of the material to create a plurality of coatings on the surface of the material.
  • Example 17 may include the method of example 16, wherein each of the plurality of coatings has a positive charge or a negative charge.
  • Example 18 may include the method of any one of examples 9-17, wherein the polyelectrolyte solution includes poly acrylic acid, polystyrene sulfonate, or poly allylamine hydrochloride.
  • Example 19 may include the method of any one of examples 9-17, wherein the ion solution includes a palladium (Pd) ion solution.
  • Example 20 may include the method of any one of examples 9-17, wherein the substrate is a dielectric material, a polymer film, or solder resist.
  • Example 21 may be a computing device, comprising; a processor; a memory coupled with the processor; and wherein at least one of the processor or memory comprises an integrated circuit (IC), wherein the IC includes: a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus, wherein the metal layer is provided in response to a treatment of the surface with a polyelectrolyte solution having an electrical charge to provide adsorption of metal ions to the surface and subsequent electroless plating of the surface with a metal, wherein the adsorbed metal ions are to enhance electroless plating of the surface with the metal.
  • IC integrated circuit
  • Example 22 may include the computing device of example 21 , wherein the treatment of the surface with a polyelectrolyte further includes a plurality of treatments of the surface respectively with a plurality of polyelectrolyte solutions, and wherein each of the polyelectrolyte solutions have a positive charge or a negative charge.
  • Example 23 may include the computing device of example 21 , wherein the metal includes copper.
  • Example 24 may include the computing device of any one of examples 21 -23, wherein the polyelectrolyte solution includes poly acrylic acid, polystyrene sulfonate, or poly allylamine hydrochloride.
  • Example 25 may include the computing device of any one of examples 21 -23, wherein the metal ions include palladium (Pd) ions.
  • Example 26 may include the computing device of any one of examples 21 -23, wherein the substrate includes a dielectric material, a polymer film, or solder resist.
  • Example 27 may include the computing device of any one of examples 21 -23, wherein the adsorbtion of metal ions to the surface further includes adsorbtion of metal ions to the surface in response to exposure to a reducing agent.
  • Example 28 may include the computing device of any one of examples 21 -23, wherein the apparatus is an embedded multi-die interconnect bridge (EMIB).
  • Example 29 may be an apparatus, comprising: means for performing a polyelectrolyte solution treatment to a surface of a substrate to create a coating on the surface having an electrical charge; and applying a transition ion catalyst to the coated surface based at least upon the electrical charge of the coating and an electrical charge of ions in the ion catalyst.
  • EMIB embedded multi-die interconnect bridge
  • Example 30 may include the apparatus of example 29, further comprising means for conducting electroless plating of the surface with a metal, wherein the transition metal catalyst is to enhance electroless plating of the substrate surface.
  • Example 31 may include the apparatus of example 29, wherein means for applying an ion catalyst to the coated surface further includes means for applying an ion solution to the coated surface to cause ions in the solution to be adsorbed to the coated surface based upon the electrical charge of the coating and an electrical charge of the ions.
  • Example 32 may include the apparatus of example 31, wherein means for applying an ion solution to the coated surface further includes means for dipping the coated surface into the ion solution.
  • Example 33 may include the apparatus of example 31, further including means for applying a reducing agent to the coated surface to attach the ions to the coated surface.
  • Example 34 may include the apparatus of example 33, wherein means for applying a reducing agent to the coated surface further includes means for dipping the coated surface into the reducing agent.
  • Example 35 may include the apparatus of example 29, wherein means for applying a polyelectrolyte solution to a surface of the material further includes means for dipping the surface of the material into the polyelectrolyte solution.
  • Example 36 may include the apparatus of example 29, wherein means for applying a polyelectrolyte solution to a surface of the material to create a coating on the surface of the material further includes means for applying a plurality of polyelectrolyte solutions respectively to the surface of the material to create a plurality of coatings on the surface of the material.
  • Example 37 may include the apparatus of example 36, wherein each of the plurality of coatings has a positive charge or a negative charge.
  • Example 38 may include the apparatus of any one of examples 29-37, wherein the polyelectrolyte solution includes poly acrylic acid, polystyrene sulfonate, or poly allylamine hydrochloride.
  • Example 39 may include the apparatus of any one of examples 29-37, wherein the ion solution includes a palladium (Pd) ion solution.
  • Example 40 may include the apparatus of any one of examples 29-37, wherein the substrate is a dielectric material, a polymer film, or solder resist.

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  • General Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
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Abstract

Des modes de réalisation de la présente invention concernent un substrat ayant une surface qui comprend une couche métallique pour permettre un routage de signal dans l'appareil. La couche métallique peut être formée en réponse à un traitement de la surface avec une solution de polyélectrolyte ayant une charge électrique permettant une adsorption d'ions métalliques sur la surface. Ensuite, les ions métalliques adsorbés peuvent améliorer le dépôt autocatalytique du métal sur la surface. D'autres modes de réalisation peuvent être décrits et/ou revendiqués.
PCT/US2017/054299 2017-09-29 2017-09-29 Appareil avec un substrat formé par dépôt autocatalytique de métal en utilisant des polyélectrolytes pour adsorber des ions métalliques dans le substrat WO2019066900A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2017/054299 WO2019066900A1 (fr) 2017-09-29 2017-09-29 Appareil avec un substrat formé par dépôt autocatalytique de métal en utilisant des polyélectrolytes pour adsorber des ions métalliques dans le substrat

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2017/054299 WO2019066900A1 (fr) 2017-09-29 2017-09-29 Appareil avec un substrat formé par dépôt autocatalytique de métal en utilisant des polyélectrolytes pour adsorber des ions métalliques dans le substrat

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WO2019066900A1 true WO2019066900A1 (fr) 2019-04-04

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5443865A (en) * 1990-12-11 1995-08-22 International Business Machines Corporation Method for conditioning a substrate for subsequent electroless metal deposition
US20020084193A1 (en) * 2000-10-25 2002-07-04 Shipley Company, L.L.C. Seed layer
US20030034251A1 (en) * 2001-08-14 2003-02-20 Chikarmane Vinay B. Apparatus and method of surface treatment for electrolytic and electroless plating of metals in integrated circuit manufacturing
US20060134442A1 (en) * 2002-12-27 2006-06-22 Minoru Sugiyama Method for electroless plating
WO2015124331A1 (fr) * 2014-02-21 2015-08-27 Atotech Deutschland Gmbh Procédé de prétraitement pour placage electroless

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5443865A (en) * 1990-12-11 1995-08-22 International Business Machines Corporation Method for conditioning a substrate for subsequent electroless metal deposition
US20020084193A1 (en) * 2000-10-25 2002-07-04 Shipley Company, L.L.C. Seed layer
US20030034251A1 (en) * 2001-08-14 2003-02-20 Chikarmane Vinay B. Apparatus and method of surface treatment for electrolytic and electroless plating of metals in integrated circuit manufacturing
US20060134442A1 (en) * 2002-12-27 2006-06-22 Minoru Sugiyama Method for electroless plating
WO2015124331A1 (fr) * 2014-02-21 2015-08-27 Atotech Deutschland Gmbh Procédé de prétraitement pour placage electroless

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