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WO2018135705A1 - Procédé de production de boîtier de semi-conducteur - Google Patents

Procédé de production de boîtier de semi-conducteur Download PDF

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Publication number
WO2018135705A1
WO2018135705A1 PCT/KR2017/004824 KR2017004824W WO2018135705A1 WO 2018135705 A1 WO2018135705 A1 WO 2018135705A1 KR 2017004824 W KR2017004824 W KR 2017004824W WO 2018135705 A1 WO2018135705 A1 WO 2018135705A1
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WO
WIPO (PCT)
Prior art keywords
tray
wafers
metal layer
forming
insulating layer
Prior art date
Application number
PCT/KR2017/004824
Other languages
English (en)
Korean (ko)
Inventor
김남철
여용운
권용태
이영석
Original Assignee
주식회사 네패스
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020170053559A external-priority patent/KR101901989B1/ko
Application filed by 주식회사 네패스 filed Critical 주식회사 네패스
Publication of WO2018135705A1 publication Critical patent/WO2018135705A1/fr
Priority to US16/505,970 priority Critical patent/US10804146B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Definitions

  • the technical idea of the present invention relates to a method of manufacturing a semiconductor package, and more particularly, to a method of manufacturing a semiconductor package using a wafer level package technology.
  • a semiconductor package is manufactured by performing a semiconductor package process on semiconductor chips manufactured by performing various semiconductor processes on a wafer.
  • a wafer level package technology for performing a semiconductor package process at the wafer level and individualizing the wafer level semiconductor package subjected to the semiconductor package process into semiconductor chips has been proposed.
  • the wafer level package According to the wafer level package, a printed circuit board is unnecessary, so that the overall thickness of the semiconductor package can be made thin, and the semiconductor package can be manufactured with a low heat dissipation effect.
  • a method that can further reduce the cost of the semiconductor package process and improve the productivity of the semiconductor package process in using the wafer level package technology.
  • An object of the present invention is to provide a method for manufacturing a semiconductor package that can improve the productivity of the semiconductor package process.
  • the technical idea of the present invention is to prepare a wafer on which a semi-small element is formed, a first step of forming a first insulating layer exposing at least a portion of a pad of the semiconductor device on the wafer, A second step of forming a wiring layer connected to the pad exposed through the first insulating layer on the first insulating layer, and a second insulating layer exposing a part of the wiring layer on the first insulating layer and the wiring layer; And a third step of forming a semiconductor device, wherein at least one of the first to third steps provides a method of manufacturing a semiconductor package in a state of placing a plurality of wafers in a tray.
  • the technical idea of the present invention is to prepare a tray in which a plurality of cavities are formed, and to arrange a plurality of wafers in the plurality of cavities.
  • Forming a seed metal layer on the seed metal layer forming a mask pattern having a mask opening exposing a portion of the seed metal layer on the seed metal layer, separating the plurality of wafers from the tray;
  • the semiconductor package can be manufactured by using a wafer level package technology, so that a semiconductor package that can be miniaturized and excellent in heat dissipation efficiency can be manufactured.
  • At least a part of the semiconductor package process may be performed at the panel level by using a tray capable of arranging a plurality of wafers. It can reduce the cost and improve the productivity of semiconductor package process.
  • FIG. 1 is a flowchart illustrating a method of manufacturing a semiconductor package in accordance with some embodiments of the inventive concept.
  • FIG. 2A is a perspective view of a tray in accordance with some embodiments of the present invention.
  • FIG. 2B is a cross-sectional view of the tray taken along the line IIB-IIB ′ of FIG. 2A, illustrating a plurality of wafers arranged on the tray.
  • FIG 3 is a perspective view of a tray according to some embodiments of the inventive concept.
  • FIG. 4 is a cross-sectional view illustrating a plurality of wafers disposed in a tray according to some embodiments of the inventive concept.
  • FIG. 5 is a cross-sectional view illustrating a plurality of wafers disposed in a tray according to some embodiments of the inventive concept.
  • FIG. 6 is a flowchart illustrating a method of manufacturing a semiconductor package in accordance with some embodiments of the present invention.
  • FIG. 7A to 7K are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with some embodiments of the inventive concepts.
  • FIG. 8 is a flowchart illustrating a method of manufacturing a semiconductor package in accordance with some embodiments of the inventive concept.
  • FIGS. 9A through 9F are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with some embodiments of the inventive concepts, in a process sequence.
  • FIG. 10 is a flowchart illustrating a method of manufacturing a semiconductor package in accordance with some embodiments of the inventive concept.
  • FIGS. 11A through 11F are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with some embodiments of the inventive concepts, in a process sequence.
  • FIG. 12 is a flowchart illustrating a method of manufacturing a semiconductor package in accordance with some embodiments of the present invention.
  • a method of manufacturing a semiconductor package according to the present invention may include preparing a wafer on which a semi-small element is formed, and forming a first insulating layer exposing at least a portion of a pad of the semiconductor element on the wafer.
  • a third step wherein at least one of the first to third steps is performed while the plurality of wafers are disposed in a tray.
  • first and second may be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another.
  • first component may be referred to as the second component, and vice versa, the second component may be referred to as the first component.
  • FIG. 1 is a flowchart illustrating a method of manufacturing a semiconductor package in accordance with some embodiments of the inventive concept.
  • a method of manufacturing a semiconductor package includes preparing a plurality of wafers (S100), forming an interconnection structure on the plurality of wafers (S300), and a plurality of wafers. Cutting each of the four wafers in package units may be sequentially performed.
  • the semiconductor substrate may include, for example, silicon (Si).
  • the semiconductor substrate may include a semiconductor element such as germanium (Ge, germanium) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP).
  • the semiconductor substrate may have a silicon on insulator (SOI) structure.
  • the semiconductor substrate may include a buried oxide layer (BOX).
  • the semiconductor substrate may include a conductive region, for example, a well doped with impurities.
  • the semiconductor substrate may have various device isolation structures such as a shallow trench isolation (STI) structure.
  • STI shallow trench isolation
  • the semiconductor device may include various types of individual devices.
  • a plurality of individual devices may be used for various microelectronic devices, for example, metal-oxide-semiconductor field effect transistors (MOSFETs) such as complementary metal-insulator-semiconductor transistors, CMOS systems, and large scale integration. ), Image sensors such as CMOS imaging sensors (CIS), micro-electro-mechanical systems (MEMS), active devices, passive devices, and the like.
  • the plurality of individual devices may be electrically connected to the conductive region of the semiconductor substrate.
  • the semiconductor device may further include at least two of the plurality of individual devices or conductive wires or conductive plugs electrically connecting the plurality of individual devices with the conductive region of the semiconductor substrate.
  • the plurality of individual devices may be electrically separated from other neighboring individual devices by an insulating film.
  • the interconnection structure is simultaneously formed for the plurality of wafers arranged in the tray.
  • the interconnection structure may refer to a structure formed on the wafer to electrically connect the pad of the semiconductor element formed on the wafer and the external device.
  • forming the interconnection structure on the plurality of wafers may include placing the plurality of wafers in a tray between unit processes of the semiconductor package and / or separating the plurality of wafers from the tray. .
  • the placing of the plurality of wafers in the tray may include preparing a tray (for example, 100 of FIG. 2A) having a structure suitable for placing the plurality of wafers, and placing the plurality of wafers at a predetermined position of the tray. You can place them.
  • the tray may have a plurality of cavities that can accommodate the plurality of wafers to facilitate placement of the plurality of wafers. When a wafer is placed in the cavity of the tray, the top surface of the padded wafer may face upwards and the bottom surface opposite the top surface of the wafer may contact the surface of the tray.
  • the separating of the plurality of wafers from the tray may include removing a portion of the structure formed by forming an interconnection structure on the plurality of wafers, and then separating the plurality of wafers from the tray.
  • step S500 each of the plurality of wafers is cut in a package unit, and a sawing process is performed on a wafer-level semiconductor package including an interconnection structure, thereby forming a plurality of wafer-level semiconductor packages.
  • the semiconductor packages may be singulated into package units.
  • the semiconductor package can be manufactured by using a wafer level package technology, so that a semiconductor package that can be miniaturized and excellent in heat dissipation efficiency can be manufactured.
  • At least a portion of the unit processes of the semiconductor package process may be performed at a panel level by placing a plurality of wafers in a tray. Therefore, the semiconductor package process can be performed on a plurality of wafers at the same time, thereby simplifying the semiconductor package process and improving productivity.
  • FIG. 2A is a perspective view of a tray 100 in accordance with some embodiments of the present invention.
  • FIG. 2B is a cross-sectional view of the tray 100 taken along line IIB-IIB ′ of FIG. 2A, and illustrates a state in which a plurality of wafers 10 are disposed on the tray 100.
  • the tray 100 has a plate shape and may include a body 110 and a plurality of cavities 120.
  • the tray 100 may have a sufficient horizontal area so that the plurality of wafers 10 may be disposed at the same time.
  • the tray 100 may support the plurality of wafers 10 during the semiconductor package process of the plurality of wafers 10.
  • the outer edge of the tray 100 may have a rectangular shape as shown in FIG. 2A, but the shape of the outer edge of the tray 100 is not limited thereto.
  • the body 110 constitutes an overall appearance of the tray 100, and like the tray 100, may have a planar surface sufficient to simultaneously arrange a plurality of wafers 10.
  • the plurality of cavities 120 may provide a space in which the plurality of wafers 10 may be accommodated, respectively. That is, the cavity 120 may refer to a recessed area provided in the body 110, and may include a bottom surface facing the bottom surface of the wafer 10 and a sidewall facing the side of the wafer 10. Can be.
  • the plurality of cavities 120 may have a shape corresponding to the wafer 10.
  • the cavities 120 may have a circular shape.
  • 2A and 2B although the plurality of cavities 120 are shown to have substantially the same dimensions, the dimensions of the plurality of cavities 120, such as the horizontal area of each of the plurality of cavities 120 and / or Alternatively, the depths 120h may be different from each other.
  • the number of cavities 120 formed in one tray 100 may be two, three, or five or more.
  • the tray 100 may include a notch 130.
  • the notch 130 may be disposed in each of the plurality of cavities 120, and for example, may be disposed on the sidewall of the cavity 120.
  • the notch 130 may be provided to position the wafer 10 at a predetermined position of the tray 100. Through the notch 130, the wafer 10 may be aligned in a predetermined direction in the cavity 120. In some embodiments, notch 130 may contact the notch of wafer 10 to secure wafer 10 within cavity 120.
  • the tray 100 may include an align mark 140.
  • the alignment mark 140 may be disposed around each of the plurality of cavities 120 on the upper surface 111 of the body 110.
  • the alignment mark 140 may be provided to position the wafer 10 at a predetermined position of the tray 100.
  • semiconductor manufacturing equipment for performing a plurality of unit processes during the semiconductor package process may use the alignment mark 140 to recognize the position of the wafer 120 and / or the wafer 10 disposed in the cavity 120. Can be.
  • the wafer 10 has a cavity 120 such that the top surface 11 on which the pad 13 is formed faces upward and the bottom surface opposite to the top surface 11 faces the bottom surface of the cavity 120.
  • a cavity 120 such that the top surface 11 on which the pad 13 is formed faces upward and the bottom surface opposite to the top surface 11 faces the bottom surface of the cavity 120.
  • the horizontal width of the cavity 120 for example, the horizontal width across the diameter of the cavity 120, may be greater than the horizontal width of the wafer 10, such that the sidewalls of the cavity 120 and the edges of the wafer 10 are predetermined.
  • Distance 190 may be spaced apart.
  • the distance 190 between the sidewall of the cavity 120 and the edge of the wafer 10 may be an insulating layer (eg, a lamination method) on the surface of the plurality of wafers 10 and the tray 100.
  • an insulating layer eg, a lamination method
  • the space 120S between the sidewall of the cavity 120 and the edge of the wafer 10 may be appropriately adjusted so as not to be filled by the insulating layer.
  • the depth 120h of the cavity 120 may be substantially the same as the thickness 10h of the wafer 10.
  • the upper surface 111 of the body 110 may have the same level as the upper surface 11 of the wafer 10. That is, the upper surface 111 of the body 110 may be located on the same plane as the upper surface 11 of the wafer 10.
  • At least a part of the manufacturing process of the semiconductor package is made with the plurality of wafers 10 arranged on the tray 100, so that the tray 100 is formed of a material having chemical resistance and heat resistance. Can be done.
  • tray 100 may be comprised of a metallic material, such as iron, nickel, cobalt, titanium, or an alloy containing them.
  • tray 100 may be composed of a ceramic material, such as alumina or silicon carbide.
  • tray 100 may be comprised of carbon fiber.
  • the tray 100 may be composed of a prepreg, which is an insulator, for example, the tray 100 penetrates a thermosetting resin into a reinforcing fiber before being molded to B-stage (the semi-cured state of the resin). It may be composed of a cured material.
  • FIG. 3 is a perspective view of a tray 100a according to some embodiments of the inventive concept.
  • the tray 100a illustrated in FIG. 3 may have a configuration substantially the same as that of the tray 100 illustrated in FIGS. 2A and 2B except that the plurality of cavities 120a and 120b have different horizontal widths. have.
  • the same reference numerals as in Figs. 2A and 2B denote the same members, and detailed description thereof will be omitted or simplified here.
  • the tray 100a may include a first cavity 120a and a second cavity 120b having different horizontal widths.
  • the diameter of the first cavity 120a may be larger than the diameter of the second cavity 120b. Since the tray 100a includes a first cavity 120a and a second cavity 120b having different horizontal widths, wafers having different diameters may be simultaneously mounted on the tray 100a. Therefore, using the tray 100a, the semiconductor package process may be simultaneously performed on wafers having different diameters.
  • the tray 100a is illustrated as including cavities having two horizontal widths, but may also include cavities having three or more horizontal widths.
  • FIG. 4 is a cross-sectional view illustrating a plurality of wafers 10 disposed on a tray 100b according to some embodiments of the inventive concept.
  • the tray 100b shown in FIG. 4 may have substantially the same configuration as the tray 100 shown in FIGS. 2A and 2B except for the depth 120ha of the cavity 120a.
  • the same reference numerals as in Figs. 2A and 2B denote the same members, and detailed description thereof is omitted or simplified here.
  • the depth 120ha of the cavity 120a provided in the tray 100b may be smaller than the thickness 10h of the wafer 10.
  • the wafer 10 when the wafer 10 is disposed in the cavity 120a, at least a portion of the wafer 10 may protrude from the top surface 111a of the body 110a. That is, when the wafer 10 is disposed in the cavity 120a, the upper surface 111a of the body 110a may be located at a level lower than the upper surface 11 of the wafer 10.
  • the vertical distance between the top surface 111a of the body 110a from the bottom surface of the cavity 120a is the vertical distance between the top surface 11 of the wafer 10 accommodated in the cavity 120a from the bottom surface of the cavity 120a.
  • the tray 100b may include a notch portion (see 130 of FIG. 2A) disposed on the sidewall of the cavity 120a and / or an alignment mark disposed on the upper surface 111a of the body 110a (FIG. 2A). 140).
  • the insulating layer formed may be formed to have a step at a portion adjacent to the edge of the wafer 10. In addition, the insulating layer may be formed to cover a portion of the side surface of the wafer 10.
  • FIG. 5 is a cross-sectional view illustrating a plurality of wafers 10 disposed on a tray 100c according to some embodiments of the inventive concept.
  • the tray 100c illustrated in FIG. 5 may have a configuration substantially the same as that of the tray 100 illustrated in FIGS. 2A and 2B except that the cavity is not formed.
  • the same reference numerals as in Figs. 2A and 2B denote the same members, and detailed description thereof is omitted or simplified here.
  • the tray 100c may provide a flat upper surface 111b on which a plurality of wafers 10 may be disposed.
  • the plurality of wafers 10 may be located at predetermined positions on the upper surface 111b of the body 110b, respectively.
  • the tray 100c may include an alignment mark (see 140 of FIG. 2A) disposed on the top surface 111b of the body 110b.
  • an insulating layer formed along the surface of the tray 100c and the surface of the wafer 10 may be formed of the tray 100c.
  • the upper surface 111b may be covered and at least a portion of the upper surface 11 and the side surfaces of the wafer 10 may be covered.
  • the wafer 10 disposed in the tray 100c may be fixed during the semiconductor package process.
  • FIGS. 6 and 7A to 7K are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with some embodiments of the inventive concepts.
  • a method of manufacturing a semiconductor package using the tray 100 illustrated in FIGS. 2A and 2B will be described with reference to FIGS. 6 and 7A to 7K.
  • the plurality of wafers 10 are disposed in the tray 100 (S301). Each of the plurality of wafers 10 may be arranged to be accommodated in different cavities 120 provided in the tray 100.
  • the wafer 10 is disposed in the cavity 120 so that the top surface 11 of the wafer 10 on which the pads 13 are formed is exposed upward, and the bottom surface opposite to the top surface 11 has a bottom surface of the cavity 120. It may be disposed in the cavity 120 to face. In other words, the active surface of the wafer 10 may be exposed and the inactive surface of the wafer 10 may be in contact with the surface of the tray 100.
  • the wafer 10 may be disposed in the cavity 120 so as to be spaced apart from the sidewall of the cavity 120. As the side surface of the wafer 10 and the side wall of the cavity 120 are spaced apart from each other, a space 120S may be formed between the side surface of the wafer 10 and the side wall of the cavity 120.
  • the depth of the cavity 120 may be substantially the same as the thickness of the wafer 10, and thus the upper surface 11 and the body 110 of the wafer 10 disposed in the cavity 120.
  • the top surface 111 of) may have the same height level.
  • the present invention is not limited thereto, and when the wafer 10 is disposed in the cavity 120, the upper surface of the body 110 may have a height level different from that of the upper surface 11 of the wafer 10.
  • the upper surface of the body 110 may have a lower level than the upper surface 11 of the wafer 10.
  • the notch portion (see 130 of FIG. 2A) and / or alignment mark (of FIG. 2A) provided in the tray 100 to position the wafer 10 at a predetermined position within the cavity 120. 140).
  • a first insulating layer 211 is formed on the tray 100 and the plurality of wafers 10 (S310).
  • the first insulating layer 211 may be formed to have an opening 211H through which at least a portion of the pad 13 may be exposed.
  • the first insulating layer 211 may cover the upper surface 111 of the body 110 and the upper surface 11 of the plurality of wafers 10.
  • the first insulating layer 211 may function to fix the wafer 10 disposed in the cavity 120 during the subsequent process.
  • the first insulating layer 211 may cover the space 120S between the wafer 10 and the sidewall of the cavity 120.
  • the space 120S between the wafer 10 and the sidewall of the cavity 120 may be sealed by the first insulating layer 211.
  • the first insulating layer 211 may cover the space 120S between the sidewalls of the wafer 10 and the cavity 120 while the interconnection structure is formed, thereby preventing foreign matter from entering the space 120S. .
  • the first insulating layer 211 is formed to cover the top of the space 120S between the side of the wafer 10 and the sidewall of the cavity 120, wherein the side and the cavity of the wafer 10 are covered.
  • the material constituting the first insulating layer 211 may not be filled in the space 120S between the sidewalls of the 120. Since the material constituting the first insulating layer 211 is not filled in the space 120S between the side surface of the wafer 10 and the side wall of the cavity 120, the wafer 10 may be easily separated from the tray 100 in the future. Can be.
  • the first insulating layer 211 may be formed through a film process. More specifically, in order to form the first insulating layer 211, after the insulating film is attached to the upper surface 111 of the body 110 and the upper surface 11 of the plurality of wafers 10 by a laminating method. A portion of the insulating film may be removed to expose the pad of the wafer 10.
  • the insulating film may be a photosensitive film, and an exposure and development process may be performed to remove a portion of the photosensitive film.
  • the first insulating layer 211 may include a non-photosensitive material.
  • the non-photosensitive film is attached to the upper surface 111 of the body 110 and the upper surface 11 of the plurality of wafers 10, and then the wafer is processed with a laser cutting device. A portion of the non-photosensitive film can be removed so that the pad of (10) is exposed.
  • the first insulating layer 211 may be made of a polymer material such as, for example, polyimide.
  • the first insulating layer 211 may be formed by a spin-coating method.
  • the seed metal layer 221a is formed to cover the surface of the pad 13 exposed through the surface of the first insulating layer 211 and the opening 211H of the first insulating layer 211.
  • the seed metal layer 221a may be deposited by, for example, a sputtering method, but a method of forming the seed metal layer 221a is not limited thereto.
  • the seed metal layer 221a may include, for example, any one of Ti, Cu, Ni, Al, Pt, Au, Ag, W, Ta, Co, or a combination thereof.
  • a first mask pattern 290 having a first mask opening 290H is formed on the seed metal layer 221a (S330). A portion of the seed metal layer 221a may be exposed by the first mask opening 290H.
  • the first mask pattern 290 may be formed by, for example, forming an insulating film on the seed metal layer 221a and then performing a patterning process on the insulating film.
  • the first mask pattern 290 may be formed by a film process.
  • a photosensitive film is attached on the seed metal layer 221 a to cover the seed metal layer 221 a, and then a part of the seed metal layer 221 a is exposed through an exposure and development process.
  • the first mask opening 290H may be formed to be exposed.
  • the plurality of wafers 10 are separated from the tray 100 (S340). In this case, the material remaining between the sidewall and the wafer 10 accommodated in the cavity 120 may be removed.
  • a separation lane 250 may be formed.
  • the isolation lane 250 may vertically penetrate the first insulating layer 211, the seed metal layer 221a, and the first mask pattern 290, and may have edge portions of each of the plurality of wafers 10. Can be extended along.
  • the separation lane 250 may have a ring shape when viewed from the top. By the separation lane 250, the space 120S between the sidewall of the cavity 120 and the edge of the wafer 10 may be exposed upward. Further, by the separation lane 250, a portion of the edge region of the wafer 10 and / or a portion of the surface of the tray 100 may also be exposed.
  • the separation lane 250 may be formed through, for example, a laser drilling method.
  • a first metal layer 223 filling at least a portion of the first mask opening 290H is formed in each of the separated plurality of wafers 10 (S350).
  • the first metal layer 223 may be formed to cover the surface of the portion of the seed metal layer 211a exposed through the first mask opening 290H.
  • the first metal layer 223 can be formed, for example, by a plating method.
  • the first metal layer 223 may be made of copper.
  • the first metal layer 223 may be formed by a plating method using the seed metal layer 211a as a seed.
  • the first metal layer 223 may be formed by immersion plating, electroless plating, electroplating, or a combination thereof.
  • the plating process for forming the first metal layer 223 has a larger number of wafers 10 than the number of wafers 10 (hereinafter referred to as 'tray units') that can be accommodated in a single tray. Can be performed simultaneously.
  • the plating process may be performed by immersing a larger number of wafers 10 than the tray unit in the plating bath 500 in which the electrolyte is accommodated. Therefore, the plating process can be performed more efficiently than the case where the plating process is performed only by the tray unit.
  • An ashing or strip process may be used to remove the first mask pattern 290.
  • a chemical etching method may be used to remove a portion of the seed metal layer 211a of FIG. 7F under the first mask pattern 290.
  • the first metal layer 223 and the seed metal layer 221 may be integrally coupled to each other, and may constitute a distribution layer 220.
  • the plurality of wafers 10, which are the result of FIG. 7G, are disposed in the tray 100 (S370).
  • the plurality of wafers 10 are disposed in the tray 100 so that the first metal layer 223 is exposed upward, and each of the plurality of wafers 10 is disposed in a different cavity 120 provided in the tray 100. Can be accommodated.
  • the notch portion (see 130 of FIG. 2A) and / or alignment mark (of FIG. 2A) provided in the tray 100 to position the wafer 10 at a predetermined position within the cavity 120. 140).
  • the first mask pattern is different from the first insulating layer 211 (see 290 of FIG. 7E). There may be more left. Alternatively, the tray 100 in which the first insulating layer 211 is removed may be used.
  • a second insulating layer 213 is formed to cover the upper surface 111 of the tray 100 and the plurality of wafers 10.
  • the second insulating layer 213 may cover a portion of the first insulating layer 211 on the tray 100, a portion of the first insulating layer 211 on the plurality of wafers 10, and the first metal layer 223.
  • the second insulating layer 213 may include an opening that exposes a portion of the first metal layer 223.
  • the second insulating layer 213 may perform a function of fixing the plurality of wafers 10 to the tray 100 during a subsequent process.
  • the second insulating layer 213 may cover the space 120S between the sidewall of the cavity 120 and the edge of the wafer 10.
  • the second insulating layer 213 may seal the space 120S between the sidewall of the cavity 120 and the edge of the wafer 10.
  • the second insulating layer 213 may be formed by a film process similar to the first insulating layer 211 described with reference to FIG. 7B.
  • the second insulating layer 213 may include a photosensitive material or may include a non-photosensitive material.
  • a second metal layer 225 connected to a portion of the first metal layer 223 exposed through the second insulating layer 213 is formed (S380).
  • the first insulating layer 211, the wiring layer 220, the second insulating layer 213, and the second metal layer 225 may constitute the interconnection structure 200a.
  • the second metal layer 225 may be an under bump metal. In other embodiments, the second metal layer 225 may be omitted.
  • the external connection terminal 400 is formed on the second metal layer 225.
  • the external connection terminal 400 may be, for example, solder balls or solder bumps.
  • the external connection terminal 400 may be configured to electrically connect the semiconductor package and the external device.
  • the external connection terminal 400 may be electrically connected to the pad 13 of the wafer 10 through the seed metal layer 221, the first metal layer 223, and the second metal layer 225.
  • the external connection terminal 400 may be attached to the first metal layer 223 exposed by the second insulating layer 213.
  • the plurality of wafers 10 are separated from the tray 100 (S390).
  • a portion of the structure stacked on the tray 100 and / or the plurality of wafers 10 may be removed to form a separation lane 260. have.
  • the separation lane 260 may vertically penetrate the second insulating layer 213 and may be formed along an edge portion of each of the plurality of wafers 10. By the separation lane 260, the space 120S between the sidewall of the cavity 120 and the edge of the wafer 10 may be exposed upward.
  • the separation lanes 260 may separate the wafer-level semiconductor packages including the wafer 10 and the interconnection structure 200 on the wafer 10 from each other.
  • the separation lane 260 may be formed through, for example, a laser drilling method.
  • the semiconductor package 1 at the wafer level is singulated into semiconductor packages in a plurality of package units through a sawing process.
  • the wafer-level semiconductor package 1 is a semiconductor package of a plurality of package units. Can be individualized into
  • the remaining subsequent process may be performed separately for each of the plurality of wafers. That is, the remaining subsequent processes may be performed without placing the plurality of wafers in the tray.
  • a second insulating layer covering the wiring layer, a second metal layer connected to the wiring layer through the second insulating layer, and external connection terminals on the second metal layer are sequentially formed, thereby providing a plurality of wafers.
  • the semiconductor package process can be performed.
  • FIG. 8 is a flowchart illustrating a method of manufacturing a semiconductor package in accordance with some embodiments of the inventive concept.
  • part of the semiconductor package process may be performed on wafers in a tray unit, and another part may be performed on more wafers than a tray unit.
  • the semiconductor package process for the first group of wafers 10A in a tray unit and the second group of wafers 10B in a tray unit may be performed through S100 to S500.
  • processes performed by placing a wafer in a tray are performed by the wafers 10A and the second group of the first group.
  • the processes of the wafers 10B of the group and the processes of separating the wafers from the tray may be performed together with the wafers 10A of the first group and the wafers 10B of the second group.
  • the first group of wafers 10A and the second group of wafers 10B may be processed together.
  • step S350 and / or the step S360 are shown as processing two wafers in a tray unit, but the present invention is not limited thereto and may be performed for a larger number of wafers than two trays.
  • 9A through 9F are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with some embodiments of the inventive concepts, in a process sequence.
  • 9A to 9F a method of manufacturing a semiconductor package using the tray 100c illustrated in FIG. 5 will be described, and descriptions overlapping with those described with reference to FIGS. 7A to 7K will be omitted or simplified.
  • a plurality of wafers 10 are disposed on the tray 100c.
  • Each of the wafers 10 may have an upper surface 11 on which a pad 13 is formed, and a lower surface opposite to the upper surface 11 may face the surface of the tray 100c.
  • an alignment mark (see 140 of FIG. 2A) provided on the tray 100c may be used.
  • a first insulating layer 311 is formed to cover the surface of the tray 100c and the surface of the wafer 10 and have an opening 311H exposing the pad 13 of the wafer 10. . Since the upper surface 11 of the wafer 10 has a higher level than the surface of the tray 100c, the first insulating layer 311 may be formed to have a stepped shape. The first insulating layer 311 may fix the plurality of wafers 10 at a predetermined position on the tray 100c during a subsequent process.
  • the seed metal layer 3 may be disposed on the pad 13 of the wafer 10 exposed between the first insulating layer 311 and the opening 311H of the first insulating layer 311.
  • 321a is formed, and a second mask pattern 390 having a second mask opening 3900H is formed on the seed metal layer 321a.
  • the separation lane 350 may be removed by removing a portion of the structure stacked on the tray 100c and / or the plurality of wafers 10 to separate the plurality of wafers 10 from the tray 100c. ).
  • the separation lane 350 may extend along an edge portion of each of the plurality of wafers 10, and may vertically penetrate the first insulating layer 311 and the seed metal layer 321a.
  • the separation lane 350 When a portion of the structure stacked on the tray 100c and / or the plurality of wafers 10 is removed by the separation lane 350, the plurality of wafers 10 are separated from the tray 100c.
  • the first mask openings may be formed for each of the plurality of separated wafers 10 by substantially the same method as the method of forming the first metal layer 223 of FIG. 7F.
  • a first metal layer 323 is formed that fills at least a portion of 390H.
  • the second mask pattern 390 and portions of the seed metal layer 321a under the second mask pattern 390 are removed by the same method as described with reference to FIG. 7G.
  • the seed metal layer 321a and the first metal layer 323 may constitute the wiring layer 320.
  • the plurality of wafers 10 including the predetermined structure are placed in the tray 100c again, the tray 100c, the first insulating layer 311 on the plurality of wafers 10, and A second insulating layer 313 is formed to cover the wiring layer 320.
  • the plurality of wafers 10 may be fixed to the tray 100.
  • portions of the structure stacked on the tray 100c and / or the plurality of wafers 10 are removed along the edges of the plurality of wafers 10 to form a separation lane 360.
  • the separation lane 360 may vertically penetrate the second insulating layer 213.
  • the wafer-level semiconductor package may be separated from the tray 100c, and the separated wafer-level semiconductor package may be individualized into semiconductor packages in a plurality of package units through a sawing process.
  • FIGS. 10 is a flowchart illustrating a method of manufacturing a semiconductor package in accordance with some embodiments of the inventive concept.
  • 11A through 11F are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with some embodiments of the inventive concepts, in a process sequence.
  • a method of manufacturing a semiconductor package using the tray 100 illustrated in FIGS. 2A and 2B will be described with reference to FIGS. 10 and 11A through 11F, and described with reference to FIGS. 7A through 7K. Descriptions overlapping with those of the above are omitted or simplified.
  • a first insulating layer 212 is formed on each of the plurality of wafers 10 (S310a), and a plurality of wafers 10 are disposed on the tray 100 (S320a). ).
  • the first insulating layer 212 may be formed on the top surface 11 of the plurality of wafers 10 on which the pads 13 are provided, and the plurality of wafers 10 may be formed on the bottom surface of the cavity 120. It may be received in the cavity 120 to face the bottom surface of the.
  • the seed metal layer 221a electrically connected to the pad 13 of the plurality of wafers 10 is formed (S330a).
  • the seed metal layer 221a may cover the surface of the tray 100 and the surface of the first insulating layer 212, and may expose the pad 13 exposed through the opening 211H of the first insulating layer 212. Can be connected.
  • a first mask pattern 290 having a first mask opening 290H is formed on the seed metal layer 221a (S340a).
  • a photosensitive film is attached on the seed metal layer 221 a to cover the seed metal layer 221 a, and the seed metal layer 221 a through an exposure and development process.
  • the first mask opening 290H may be formed to expose a portion of the mask.
  • the first mask pattern 290 may serve to fix the plurality of wafers 10 to the tray 100.
  • a first metal layer 223 is formed on a portion of the seed metal layer 221a exposed through the first mask pattern 290 (S350a).
  • the first metal layer 223 may be formed by a plating method using the seed metal layer 211a as a seed. For example, in order to perform a plating process in which a plating jig is contacted with the seed metal layer 221a to apply a voltage to the seed metal layer 221a, the plating jig is seed metal layer 221a provided on each of the plurality of wafers 10. ) Can be contacted.
  • portions of the seed mask 290 and the seed metal layer 221a of FIG. 11D under the first mask pattern 290 and the first mask pattern 290 are removed from the resultant product of FIG. 11D (S360a).
  • the seed metal layer 221 and the first metal layer 223 may constitute a wiring layer 220.
  • a second insulating layer 213 is formed on the tray 100 and the plurality of wafers 10 (S370a).
  • the second insulating layer 213 may cover a portion of the seed metal layer 221 on the upper surface 111 of the tray 100, and may cover the first insulating layer 212 and the wiring layer 220 on the plurality of wafers 10. have.
  • the second insulating layer 213 may secure the plurality of wafers 10 to the tray 100 during subsequent processing.
  • a second metal layer 225 connected to a portion of the first metal layer 223 exposed through the second insulating layer 213 is formed (S380a).
  • the first insulating layer 212, the wiring layer 220, the second insulating layer 213, and the second metal layer 225 may constitute the interconnection structure 200a.
  • an external connection terminal may be formed on the second metal layer 325.
  • the plurality of wafers 10 are separated from the tray 100 (S390a). For example, a portion of the second insulating layer 213 may be removed to expose the edges of the plurality of wafers 10 to separate the plurality of wafers 10.
  • the plurality of wafers 10 separated from the tray 100 may be individualized into semiconductor packages of a plurality of package units through a sawing process.
  • the remaining subsequent processes may be performed separately for each of the plurality of wafers. That is, the remaining subsequent processes may be performed without placing the plurality of wafers in the tray. That is, in the resultant of FIG. 11E, a plurality of wafers are separated from the tray, and a second insulating layer covering the wiring layer for each of the plurality of wafers, a second metal layer connected to the wiring layer through the second insulating layer, and an outside on the second metal layer. By sequentially forming the connection terminals, the semiconductor package process for each of the plurality of wafers may be performed.
  • FIGS. 10 to 11F a method of manufacturing a semiconductor package using the tray 100 shown in FIGS. 2A and 2B has been described, but the semiconductor using the trays 100a, 100b and 100c described with reference to FIGS. 3 to 5 is described.
  • the method of manufacturing the package may be performed substantially the same as that described with reference to FIGS. 10-11F.
  • the manufacturing process of the semiconductor package may be performed in a state in which a plurality of wafers are arranged in a tray.
  • a method of manufacturing a semiconductor package according to some embodiments of the present invention will be described with reference to FIG. 12.
  • step S420 forming a second insulating layer on the wiring layer and the first insulating layer (S470), and forming a second metal layer connected to the portion of the wiring layer exposed through the second insulating layer (S480). It may include.
  • the forming of the wiring layer (S420) may include forming a seed metal layer on a pad of the wafer exposed through the first insulating layer and the first insulating layer (S430), and forming a first mask pattern on the seed metal layer. (S440), forming a first metal layer on the seed metal layer portion exposed through the first mask pattern (S450), and removing the seed metal layer portion below the first mask pattern and the first mask pattern (S460) It may include.
  • some of the steps S410 to S480 are performed in a state in which a plurality of wafers are placed in a tray, and in the other part, each of the plurality of wafers is separated from the tray. Can be performed separately. Accordingly, at least one of the steps before or after each of the steps S410 to S480 may be performed by placing a plurality of wafers in a tray or separating a plurality of wafers from a tray.
  • a plurality of unit processes of the semiconductor package process may be performed using a tray capable of supporting a plurality of wafers. That is, the semiconductor package process is performed by placing a plurality of wafers in a tray, so that a plurality of wafer-level semiconductor packages can be manufactured at the panel level. Therefore, according to the technical concept of the present invention, since the semiconductor package process for a plurality of wafers can be performed at the same time, productivity can be improved.
  • some of the plurality of unit processes of the semiconductor package process may process wafers using a tray, and in some other processes, wafers may be separated from the tray.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

La présente invention concerne un procédé de production d'un boîtier de semi-conducteur, le procédé selon le concept technique de la présente invention comprenant : une étape consistant à préparer une tranche ayant un élément semi-conducteur ; une première étape consistant à former, sur la tranche, une première couche d'isolation qui expose au moins une partie du plot de l'élément semi-conducteur ; une deuxième étape consistant à former, sur la première couche d'isolation, une couche de câblage connectée au plot exposé par la première couche d'isolation ; et une troisième étape consistant à former, au-dessus de la première couche d'isolation et de la couche de câblage, une seconde couche d'isolation exposant une partie de la couche de câblage, au moins une étape des première à troisième étapes étant réalisée avec la pluralité de tranches agencée sur un plateau.
PCT/KR2017/004824 2017-01-17 2017-05-10 Procédé de production de boîtier de semi-conducteur WO2018135705A1 (fr)

Priority Applications (1)

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US16/505,970 US10804146B2 (en) 2017-01-17 2019-07-09 Method for producing semiconductor package

Applications Claiming Priority (4)

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KR10-2017-0008190 2017-01-17
KR20170008190 2017-01-17
KR1020170053559A KR101901989B1 (ko) 2017-01-17 2017-04-26 반도체 패키지의 제조 방법
KR10-2017-0053559 2017-04-26

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PCT/KR2017/004829 Continuation WO2018135707A1 (fr) 2017-01-17 2017-05-10 Support plan pour produire un boîtier de semi-conducteur
PCT/KR2017/004825 Continuation WO2018135706A1 (fr) 2017-01-17 2017-05-10 Procédé de production d'un boîtier de semi-conducteur

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US16/505,970 Continuation US10804146B2 (en) 2017-01-17 2019-07-09 Method for producing semiconductor package

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020022600A (ko) * 2000-09-20 2002-03-27 마에다 시게루 기판도금장치 및 도금방법
KR20120138517A (ko) * 2011-06-15 2012-12-26 삼성전자주식회사 칩 고정 장치 및 이를 이용한 칩의 테스트 방법
JP2015504608A (ja) * 2011-11-22 2015-02-12 日本テキサス・インスツルメンツ株式会社 マイクロ表面実装デバイスパッケージング
KR20150065544A (ko) * 2013-12-05 2015-06-15 심기준 반도체 칩의 전기적 연결 구조 및 방법
KR20170003352A (ko) * 2015-06-30 2017-01-09 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 3ｄ 패키지 구조 및 그 형성 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020022600A (ko) * 2000-09-20 2002-03-27 마에다 시게루 기판도금장치 및 도금방법
KR20120138517A (ko) * 2011-06-15 2012-12-26 삼성전자주식회사 칩 고정 장치 및 이를 이용한 칩의 테스트 방법
JP2015504608A (ja) * 2011-11-22 2015-02-12 日本テキサス・インスツルメンツ株式会社 マイクロ表面実装デバイスパッケージング
KR20150065544A (ko) * 2013-12-05 2015-06-15 심기준 반도체 칩의 전기적 연결 구조 및 방법
KR20170003352A (ko) * 2015-06-30 2017-01-09 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 3ｄ 패키지 구조 및 그 형성 방법

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