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WO2018133879A1 - Serveur et procédé de traitement de données de celui-ci - Google Patents

Serveur et procédé de traitement de données de celui-ci Download PDF

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Publication number
WO2018133879A1
WO2018133879A1 PCT/CN2018/074553 CN2018074553W WO2018133879A1 WO 2018133879 A1 WO2018133879 A1 WO 2018133879A1 CN 2018074553 W CN2018074553 W CN 2018074553W WO 2018133879 A1 WO2018133879 A1 WO 2018133879A1
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WO
WIPO (PCT)
Prior art keywords
processor
heterogeneous
data
bus
hard disk
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PCT/CN2018/074553
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English (en)
Chinese (zh)
Inventor
姜凯
于治楼
王子彤
Original Assignee
济南浪潮高新科技投资发展有限公司
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Publication of WO2018133879A1 publication Critical patent/WO2018133879A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS

Definitions

  • the present invention relates to the field of computer technologies, and in particular, to a server and a method for processing data.
  • the invention provides a server and a method for processing the same, which can improve data processing capability.
  • the present invention provides a server, the server comprising: a processor, a first bus, at least one second bus, and at least one heterogeneous unit;
  • Each of the heterogeneous units is connected to the processor via one of the second buses; each of the heterogeneous units is connected to the first bus;
  • the processor configured to: when it is determined that the data received by the external input is non-transactional data, determine at least one target heterogeneous unit in the at least one heterogeneous unit, and send the non-transactional data to the Said at least one target heterogeneous unit;
  • Each of the heterogeneous units is configured to process the non-transactional data when receiving the non-transactional data sent by the processor.
  • the heterogeneous unit comprises: at least three FPGA chips and a third bus;
  • the at least three FPGA chips are all connected to the third bus;
  • Any one of the at least three FPGA chips is connected to the corresponding second bus.
  • the heterogeneous unit comprises: at least two FPGA chips;
  • Each of the FPGA chips is respectively connected to a corresponding second bus.
  • the heterogeneous unit comprises: at least three FPGA chips;
  • the at least three FPGA chips are sequentially connected;
  • the FPGA chip in the first place and the FPGA chip in the last position are respectively connected to the corresponding second bus.
  • any of the FPGA chips connected to the corresponding second bus is connected to at least one external storage hard disk.
  • the method further comprises: a solid state hard disk and a mechanical hard disk;
  • the processor is further configured to receive a processing result fed back by each of the heterogeneous units; and send the processing result to the solid state hard disk;
  • the solid state drive is respectively connected to the processor and the mechanical hard disk, and configured to receive the processing result sent by the processor, store the processing result, and transmit the stored processing result to the machine a hard disk; starting timing when receiving the processing result sent by the processor, and deleting the stored processing result when the accumulated duration reaches a preset length of time.
  • the mechanical hard disk is configured to receive the processing result of the solid state hard disk transmission and store the same.
  • Each of the heterogeneous units is further configured to send intermediate data generated in a process of processing the non-transactional data to the processor; send a call instruction to the processor, and receive the transmitted by the processor Intermediate data;
  • the processor is further configured to send the intermediate data to the memory; retrieve the intermediate data from the memory according to the calling instruction sent by the heterogeneous unit, and send the intermediate data Giving the heterogeneous unit;
  • the memory is configured to store the intermediate data sent by the processor.
  • the bus includes a peripheral component interconnect standard PCIE bus or a high speed serial port SRIO bus.
  • the solid state drive is a non-volatile memory standard NVMe solid state storage hard disk
  • the mechanical hard disk is a serial connection SAS expansion disk array.
  • the present invention provides a method for processing data by the server, the method comprising:
  • the receiving, by the each of the target heterogeneous units, the non-transactional data sent by the processor, after processing the non-transactional data further comprising:
  • the intermediate data stored in the memory is retrieved by the processor, and the intermediate data is sent to the target heterogeneous unit.
  • the present invention provides a server and method thereof for processing data, the server comprising: a processor, a first bus, at least one second bus, and at least one heterogeneous unit.
  • a processor determines that the data received by the external input is non-transactional data, determining at least one target in each of the heterogeneous units connected to the second bus respectively
  • the heterogeneous unit sends non-transactional data to at least one target heterogeneous unit, and each heterogeneous unit processes the non-transactional data when receiving the non-transactional data sent by the processor.
  • the heterogeneous unit connected thereto determines at least one target heterogeneous unit, so that the determined at least one target heterogeneous unit is for the received non-received unit. Transactional data is processed. Therefore, this solution can improve data processing capabilities.
  • FIG. 1 is a schematic structural diagram of a server according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural view of a heterogeneous unit according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a heterogeneous unit in which FPGA chips are connected in parallel according to an embodiment of the present invention
  • FIG. 4 is a schematic flow chart of a heterogeneous unit in which FPGA chips are connected in parallel according to an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of a heterogeneous unit in which FPGA chips are connected in series according to an embodiment of the present invention
  • FIG. 6 is a schematic flow chart of a heterogeneous unit in which FPGA chips are connected in series according to an embodiment of the present invention
  • FIG. 7 is a schematic structural diagram of a server including a solid state hard disk and a mechanical hard disk according to an embodiment of the present invention
  • FIG. 8 is a schematic structural diagram of a server including a memory according to an embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a server according to another embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a heterogeneous unit according to another embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of a heterogeneous unit in which FPGA chips are connected in parallel according to another embodiment of the present invention.
  • FIG. 12 is a schematic structural diagram of a heterogeneous unit in which FPGA chips are connected in series according to another embodiment of the present invention.
  • FIG. 13 is a flowchart of a method for processing data by a server according to an embodiment of the present invention.
  • an embodiment of the present invention provides a server, the server includes: a processor 101, a first bus 102, at least one second bus 103, and at least one heterogeneous unit 104;
  • Each of the heterogeneous units 104 is connected to the processor 101 via a second bus 103; each of the heterogeneous units 104 is connected to the first bus 102;
  • the processor 101 is configured to: when it is determined that the data received by the external input is non-transactional data, determine at least one target heterogeneous unit in the at least one heterogeneous unit 104, and send the non-transactional data To the at least one target heterogeneous unit;
  • Each of the heterogeneous units 104 is configured to process the non-transactional data when receiving the non-transactional data sent by the processor 101.
  • the server comprises: a processor, a first bus, at least one second bus, and at least one heterogeneous unit.
  • each of the heterogeneous units is connected to the first bus, and when the processor determines that the data received by the external input is non-transactional data, determining at least one target in each of the heterogeneous units connected to the second bus respectively
  • the heterogeneous unit sends non-transactional data to at least one target heterogeneous unit, and each heterogeneous unit processes the non-transactional data when receiving the non-transactional data sent by the processor.
  • the heterogeneous unit connected thereto determines at least one target heterogeneous unit, so that the determined at least one target heterogeneous unit is for the received non-received unit. Transactional data is processed. Therefore, embodiments of the present invention can improve data processing capabilities.
  • the bus includes: a peripheral component interconnect standard PCIE bus or a high speed serial port SRIO bus;
  • both the PCIE bus and the SRIO bus are high bandwidth low latency buses with fast transmission speed and low power consumption.
  • the choice of PCIE bus or SRIO bus is only a preferred way, and other forms of bus can be selected according to business requirements.
  • the first bus can select the SRIO bus, and the second bus can use the PCIE bus.
  • the processor when the number of the target heterogeneous units determined by the processor in the at least one heterogeneous unit is one, the processor sends the non-transactional data to the target heterogeneous unit, and the heterogeneous unit is receiving Non-transactional data is processed when it comes to non-transactional data.
  • the processor when the number of the target heterogeneous units determined by the processor in the at least one heterogeneous unit is at least two, the processor sends the non-transactional data to the at least two target heterogeneous units, at least two The heterogeneous unit processes the non-transactional data when it receives non-transactional data.
  • the processing of non-transactional data by at least two target heterogeneous units may exist in at least two cases: one is that each of the at least two target heterogeneous units sequentially processes non-transactional data, such as Two target heterogeneous units, the processor sends non-transactional data to the target heterogeneous unit 1, and the target heterogeneous unit 1 processes the non-transactional data first, and after the processing is completed, transmits the intermediate processing result to the target different The unit 2 and the target heterogeneous unit 2 perform the next processing on the intermediate processing result. After the target heterogeneous unit 2 is processed, the processing result is fed back to the processor.
  • each of the at least two target heterogeneous units simultaneously processes the non-transactional data, and there is an interaction process of the data during the processing. For example, if there is a target heterogeneous unit 1 and a target heterogeneous unit 2, the target heterogeneous unit 1 and the target heterogeneous unit 2 simultaneously process non-transactional data, and there is a data interaction process in the process, after the processing is completed, The processing result is fed back to the processor by any of the target heterogeneous unit 1 and the target heterogeneous unit 2.
  • one or more FPGA chips may be included in the heterogeneous unit, and the specific number may be determined according to service requirements.
  • the number of the FPGA chips included in each heterogeneous unit may be the same or different, and the connection manner between the respective FPGA chips included in each heterogeneous unit may be the same or different. Therefore, the connection manner between the respective FPGA chips included in the heterogeneous unit can be at least one of the following three methods:
  • Mode 2 parallel connection between individual FPGA chips in the heterogeneous unit
  • Mode 3 Connecting each FPGA chip in a heterogeneous unit in series.
  • the heterogeneous unit 104 includes: at least three FPGA chips 201 and a third bus 202;
  • the at least three FPGA chips 201 are all connected to the third bus 202;
  • Any one of the at least three FPGA chips 201 is connected to the corresponding second bus 103.
  • the types of the FPGA chip, the second bus, and the third bus can all be determined according to service requirements. For example, a Flash-based FPGA chip is selected, a PCIE bus is selected as the second bus, and the SRIO bus is selected as the third bus.
  • At least three FPGA chips are determined according to service requirements, and each FPGA chip is connected to the third bus.
  • the master FPGA chip is determined according to the service requirement in at least three FPGA chips, and the determined master FPGA chip is connected to the second bus. For example, determining that there are four FPGA chips of the FPGA chip 1, the FPGA chip 2, the FPGA chip 3, and the FPGA chip 4 in the heterogeneous unit, respectively, the FPGA chip 1, the FPGA chip 2, the FPGA chip 3, and the FPGA chip 4 are connected to the third bus.
  • the FPGA chip 1 is a main control FPGA chip
  • the FPGA chip 1 is connected to the second bus.
  • At least three FPGA chips included in the heterogeneous unit may be determined according to the number and computational difficulty of the non-transactional data. At least one FPGA chip is selected as the target FPGA chip.
  • the processor selects the FPGA chip 1 and the FPGA chip 2 as the target FPGA chip in the FPGA chip 1, the FPGA chip 2, the FPGA chip 3, and the FPGA chip 4, and the processor sends the received non-transactional data to the FPGA chip 1 And the FPGA chip 2, since the FPGA chip 1 and the FPGA chip 2 are both connected to the third bus, the non-transactional data is processed by the cooperation between the FPGA chip 1 and the FPGA chip 2. After the processing is completed, the processing result is fed back. Give the processor.
  • the cooperation processing data between the FPGA chip 1 and the FPGA chip 2 may exist in at least two cases: one is that the FPGA chip 1 first performs the non-transactional data. After the processing is completed, the intermediate processing result is transmitted to the FPGA chip 2, and the FPGA chip 2 performs the next processing on the intermediate processing result. After the processing of the FPGA chip 2 is completed, the processing result is fed back to the processor.
  • the other is that FPGA chip 1 and FPGA chip 2 simultaneously process non-transactional data, and there is data interaction process in the process. After the processing is completed, any FPGA chip in FPGA chip 1 and FPGA chip 2 will be processed. The processing result is fed back to the processor.
  • At least three FPGA chips and a third bus may be included in the heterogeneous unit, wherein at least three FPGA chips are connected to the third bus, and any one of the at least three FPGA chips is corresponding to the FPGA chip.
  • the second bus is connected.
  • the heterogeneous unit 104 may include: at least two FPGA chips 301;
  • Each of the FPGA chips 301 is connected to a corresponding second bus 103.
  • the types of the FPGA chip and the second bus can be determined according to service requirements. For example, a Flash-based FPGA chip is selected, and an SRIO bus is selected as the second bus.
  • each FPGA chip is connected to the second bus, thereby implementing a parallel state between the FPGA chips.
  • any FPGA chip can be selected as the main control FPGA chip, and the determined main control FPGA chip can control other FPGA chips through the second bus.
  • five FPGA chips of the FPGA chip 401, the FPGA chip 402, the FPGA chip 403, the FPGA chip 404, and the FPGA chip 405 are present in the heterogeneous unit, and five FPGA chips are respectively connected to the second bus 407.
  • the non-transactional data sent by the processor is received by the second bus, and the processing result is fed back to the processor through the second bus.
  • the main control FPGA chip 401 performs specific configuration on the FPGA chip 402, the FPGA chip 403, the FPGA chip 404, and the FPGA chip 405 through the lines 408, 409, and 410.
  • the types of specific transmission signals of lines 408, 409 and 410 can be determined according to business requirements. For example, when 408 is a clock line, the clocks in the respective FPGA chips can be unified through line 408.
  • the target heterogeneous unit may be determined according to the quantity and computational difficulty of the non-transactional data. Any one of the at least two FPGA chips included is selected as the target FPGA chip. For example, if the processor selects the FPGA chip 2 as the target FPGA chip in the FPGA chip 1, the FPGA chip 2, and the FPGA chip 3, the processor sends the received non-transactional data to the FPGA chip 2, and the FPGA chip 2 is non-transaction type. The data is processed, and after the processing is completed, the processing result is fed back to the processor. In addition, if the control of the FPGA chip is required when the FPGA chip 2 performs data processing, the master FPGA chip 1 controls the data processing of the FPGA chip 2 through the second bus.
  • At least two FPGA chips may be included in the heterogeneous unit, wherein each FPGA chip is respectively connected to a corresponding second bus. It can be seen from the above that there is a parallel relationship between the FPGA chips. When an FPGA chip processes non-transactional data, other FPGA chips other than the main control FPGA chip cannot interfere with it. Therefore, the independence of processing data is better. high.
  • the heterogeneous unit 104 may include: at least three FPGA chips 501;
  • the at least three FPGA chips 501 are sequentially connected;
  • the FPGA chip 501 in the first place and the FPGA chip 501 in the last position are respectively connected to the corresponding second bus 103.
  • the types of the FPGA chip and the second bus can be determined according to service requirements. For example, a Flash-based FPGA chip is selected, and an SRIO bus is selected as the second bus.
  • At least three FPGA chips are determined according to service requirements, and each FPGA chip is sequentially connected.
  • the FPGA chip in the first position and the FPGA chip in the last position are respectively corresponding to each other.
  • the second bus is connected.
  • the FPGA chip in the first position can be determined as the main control FPGA chip, and the main control FPGA chip can control each FPGA chip through the lines between the FPGA chips.
  • the main control FPGA chip can control the FPGA chip in the last position by using the line between the FPGA chips, and can also be controlled by the second bus.
  • the processor determines that the data input by the external input is non-transactional data
  • the non-transactional data is sent to the FPGA chip in the first place.
  • the intermediate result of the processing is sent to the next FPGA chip adjacent to it, and then the next FPGA chip performs corresponding processing, and the processing result is sent to the next FPGA chip adjacent thereto. In this way, after the processing of the FPGA chip in the last position is completed, the terminated processing result is sent to the processor.
  • the final processing result is sent to the processor: one is that the FPGA chip in the last bit directly sends the final processing result directly to the processor through the second bus; the other is at the end.
  • the bit FPGA chip sends the final processing result to the first-ranked master FPGA chip, and then the final FPGA chip sends the final processing result to the processor.
  • the processor 601 determines that it is received.
  • the non-transactional data is sent to the first-ranked FPGA chip 602 through the line 607, and the first FPGA chip 602 is processed to send the intermediate result of the processing to the next adjacent one.
  • the FPGA chip 603, and then the next FPGA chip 603 performs corresponding processing, and sends the processing result to the next FPGA chip 604 adjacent thereto, so that after the data processing of the FPGA chip 606 in the last position is completed, The final processing result is sent to the processor 601.
  • the FPGA chip 606 is a main control FPGA chip, and the FPGA chip 606 can specifically configure the FPGA chip 602, the FPGA chip 603, the FPGA chip 604, and the FPGA chip 605 through the lines 608, 609, and 610, wherein the line is configured.
  • the types of specific transmission signals of 608, 609 and 610 can be determined according to business requirements. For example, when 609 is a clock line, the clocks in the respective FPGA chips can be unified through the line 609.
  • the heterogeneous unit includes at least three FPGA chips connected in sequence, and the FPGA chip in the first position and the FPGA chip in the last position are respectively connected to the corresponding second bus.
  • the data is processed through each FPGA chip in turn, so that the data processing amount in each FPGA chip can be dispersed, thereby improving the data processing speed.
  • any of the FPGA chips connected to the corresponding second bus 103 are connected to at least one external storage hard disk.
  • the FPGA chip connected to the corresponding second bus can be used as the main control FPGA chip, because the main control FPGA chip can control other FPGA chips, and can obtain data processing results in each chip, so
  • the two bus-connected FPGA chips can be connected to at least one external storage hard disk to store the final data processing result or the data processing result of the intermediate process.
  • the number and type of storage hard disks can be determined according to business requirements. For example, two storage hard disks are selected, and all are solid state hard disks.
  • any FPGA chip connected to the corresponding second bus is connected to at least one external storage hard disk, so that the data processing result in the FPGA chip is timely stored in the storage hard disk, thereby reducing data processing result loss. The probability.
  • the server may further include a solid state hard disk 701 and a mechanical hard disk 702;
  • the processor 101 is further configured to receive a processing result fed back by each of the heterogeneous units 104; send the processing result to the solid state hard disk 701;
  • the SSDs 701 are respectively connected to the processor 101 and the mechanical hard disk 702, and are configured to receive the processing result sent by the processor 101, store the processing result, and transmit the stored processing result.
  • the mechanical hard disk 702 when the processor 101 receives the processing result, the timing is started, and when the accumulated duration reaches a preset duration, the stored processing result is deleted;
  • the mechanical hard disk 702 is configured to receive the processing result transmitted by the solid state hard disk 701 and store the result.
  • the number and model of the solid state hard disk and the mechanical hard disk can be determined according to service requirements. For example, one NVMe solid state storage hard disk is selected, and the selected mechanical hard disk is a SAS extended disk array.
  • Solid state drives have the advantage of fast write speed, but have the disadvantage of small storage space.
  • the mechanical hard disk has the advantage of large storage space, but has the disadvantage of slow writing speed. Therefore, the server of the present invention can include both a solid state hard disk and a mechanical hard disk, and a combination of a solid state hard disk and a mechanical hard disk is used to combine the storage frames to realize the advantages of the two types of hard disks.
  • the solid state hard disk is used as a cache disk based on the advantage that the solid state hard disk write speed is fast.
  • the processor receives the processing result of the heterogeneous unit feedback, the processing result is sent to the solid state hard disk, so that the processing result is quickly stored in the solid state hard disk. Due to the limited storage space of the fixed hard disk, the processing result of the storage is sent to the mechanical hard disk with a large storage space.
  • the storage capacity of the solid state hard disk is limited, and the processing result of the storage is written into the mechanical hard disk, the processing result of the storage itself is deleted, so as to prepare for the next storage of the new processing result.
  • the process of deleting the processing result stored by the SSD may be: when the SSD receives the processor to send the processing result, the timing starts, and when the accumulated duration reaches the preset duration, the stored processing result is deleted.
  • the set duration can be determined according to business requirements, such as 1 hour.
  • the server further includes a solid state hard disk and a mechanical hard disk, and constitutes a hybrid storage architecture with fast storage speed and large storage space.
  • the solid state drive 701 is a non-volatile memory standard NVMe solid state storage hard disk
  • the mechanical hard disk 702 is a serial connection SAS expansion disk array.
  • the solid state hard disk is a non-volatile memory standard NVMe solid state storage hard disk is only a preferred method, and other forms of solid state hard disks can be selected according to service requirements.
  • the mechanical hard disk is a serial connection SAS expansion disk array is only a preferred method, and other forms of mechanical hard disk can be selected according to business requirements.
  • the server may further include: a memory 801;
  • Each of the heterogeneous units 104 is further configured to send intermediate data generated in a process of processing the non-transactional data to the processor 101; send a call instruction to the processor 101, and receive the processor The intermediate data transmitted by 101;
  • the processor 101 is further configured to send the intermediate data to the memory 801; retrieve the intermediate data from the memory according to the calling instruction sent by the heterogeneous unit 104, and Intermediate data is sent to the heterogeneous unit 104;
  • the memory 801 is configured to store the intermediate data sent by the processor 101.
  • the number and form of the memory can be determined according to service requirements, for example, a memory in the form of synchronous dynamic random access memory is selected.
  • the intermediate data generated by each heterogeneous unit in the process of processing non-transactional data may be stored in each heterogeneous unit itself, and thus each heterogeneous unit may not have enough space for storage, so memory is required.
  • the intermediate data generated in the process of processing non-transactional data is stored.
  • the heterogeneous unit 1 is taken as an example.
  • the heterogeneous unit 1 When the heterogeneous unit 1 generates a large amount of intermediate data in the process of processing non-transactional data, the heterogeneous unit 1 sends the generated intermediate data to the processing.
  • the processor then sends the intermediate data to the memory.
  • the intermediate data is stored after the memory receives the intermediate data.
  • the calling instruction is sent to the processing data, wherein the calling instruction may include the identifier of the heterogeneous unit 1.
  • the processor calls the intermediate data of the heterogeneous unit 1 in the memory according to the identification information of the heterogeneous unit 1 in the calling instruction, and sends the called intermediate data to the heterogeneous unit 1 to enable the heterogeneous unit 1 to utilize the Intermediate data for data processing.
  • the server may further include a memory, and use the memory to store intermediate data generated by each heterogeneous unit in processing the non-transactional data to release the storage space in the heterogeneous unit, thereby improving the heterogeneous unit.
  • the speed at which data is processed may be performed.
  • the server includes:
  • the heterogeneous unit 902, the heterogeneous unit 903, and the heterogeneous unit 904 of the six heterogeneous units are respectively connected to the processor through the first PCIE bus; the heterogeneous unit 905 among the six heterogeneous units, The heterogeneous unit 906 and the heterogeneous unit 907 are respectively connected to the processor through the second PCIE bus; each heterogeneous unit is connected to the first SRIO bus; the first SRIO bus is connected to the second PCIE bus through the PCIE-SRIO converter. To achieve communication between the first SRIO bus and the second PCIE bus.
  • the SAS hard disk is connected to the processor through the SAS controller and the first PCIE bus; the NVMe solid state storage hard disk is connected to the processor through the first PCIE bus; the memory is connected to the processor.
  • each heterogeneous unit includes a set number of FPGA chips, wherein each FPGA chip may have: DDR (Double Data Rate) interface, SPI (serial peripheral interface) Serial peripheral interface), norflash interface, SMBus (System Management Bus) interface, PCIE interface, SRIO interface, JTAG (Joint Test) Action Group; Joint Test Workgroup Protocol) interface, mode mode interface.
  • DDR Double Data Rate
  • SPI Serial peripheral interface
  • norflash interface Serial peripheral interface
  • SMBus System Management Bus
  • PCIE interface PCIE interface
  • SRIO interface Joint Test Action Group
  • JTAG (Joint Test) Action Group Joint Test Workgroup Protocol) interface
  • the heterogeneous unit 902 and the heterogeneous unit 903 of the six heterogeneous units include an FPGA chip 9021, an FPGA chip 9022, an FPGA chip 9023, and a second SRIO bus 9024.
  • Each FPGA chip is connected to the second SRIO bus.
  • the FPGA chip 9021 of the three FPGA chips is connected as a master FPGA chip to the corresponding first PCIE bus.
  • the heterogeneous unit 904 of the six heterogeneous units includes an FPGA chip 9041, an FPGA chip 9042, and an FPGA chip 9043.
  • Each FPGA chip is in a parallel state, and each FPGA chip is respectively connected to a corresponding first PCIE bus.
  • the FPGA chip 9041 is connected as a main control FPGA chip to the corresponding first PCIE bus.
  • the heterogeneous unit 905, the heterogeneous unit 906, and the heterogeneous unit 907 of the six heterogeneous units include an FPGA chip 9051, an FPGA chip 9052, and an FPGA chip 9053.
  • Each FPGA chip is in a serial state, and the FPGA chip 9051, the FPGA chip 9052, and the FPGA chip 9053 are sequentially connected; the FPGA chip 9051 in the first position and the FPGA 9052 chip in the last position are respectively connected to the corresponding second PCIE bus.
  • the processor determines, when the data received by the external input is non-transactional data, determines at least one target heterogeneous unit among the six heterogeneous units, and transmits the non-transactional data to the at least one target heterogeneous unit.
  • the processor may be in the FPGA chip 9021 and the FPGA chip 9022 according to the number and computational difficulty of the non-transactional data. At least one FPGA chip is selected as the target FPGA chip in the FPGA chip 9023. For example, if the FPGA chip 9021 and the FPGA chip 9022 are selected as the target FPGA chip, the processor sends the received non-transactional data to the FPGA chip 9021 and the FPGA chip 9022. The non-transactional data is processed by the cooperation between the FPGA chip 9021 and the FPGA chip 9022, and after the processing is completed, the processing result is fed back to the processor.
  • the processor may select any one of the FPGA chip 9041, the FPGA chip 9042, and the FPGA chip 9043 as the target FPGA chip. For example, if the FPGA chip 9043 is selected as the target FPGA chip, the processor sends the received non-transactional data to the FPGA chip 9043, and the non-transactional data is processed by the FPGA chip 9043. After the processing is completed, the processing result is fed back. Give the processor.
  • the processor sends the non-transactional data to the FPGA chip 9051 in the first place, and the first FPGA After the processing of the chip 9051 is completed, the intermediate result of the processing is sent to the next FPGA chip 9052 adjacent thereto, and then the next FPGA chip 9052 performs corresponding processing, and the processing result is sent to the next FPGA chip adjacent thereto. 9053, in this way, until the data processing of the FPGA chip 9053 in the last position is completed, the terminated processing result is sent to the processor.
  • the processor When the processor receives the processing result fed back by the heterogeneous unit, such as the heterogeneous unit 902, the processing result is sent to the NVMe solid-state storage hard disk, and when the NVMe solid-state storage hard disk receives the processing result sent by the processor, the storage starts simultaneously, and The stored processing result is transmitted to the SAS hard disk; the SAS hard disk stores the processing result of the NVMe solid-state storage hard disk transmission; when the accumulated time of the NVMe solid-state storage hard disk reaches a preset time length, for example, 2 hours, the stored processing result is deleted.
  • a preset time length for example, 2 hours
  • the heterogeneous unit 901 is taken as an example.
  • the heterogeneous unit 901 When the heterogeneous unit 901 generates a large amount of intermediate data in the process of processing non-transactional data, the heterogeneous unit 901 sends the generated intermediate data to the processing.
  • the processor sends the intermediate data to the memory 916.
  • the intermediate data is stored after the memory receives the intermediate data.
  • the calling instruction is sent to the processing data, wherein the calling instruction includes the identifier of the heterogeneous unit 901.
  • Processing the data calling the intermediate data of the heterogeneous unit 901 in the memory according to the identification information in the calling instruction, and sending the called intermediate data to the heterogeneous unit 901, so that the heterogeneous unit 901 uses the intermediate data to perform data. deal with.
  • the server further includes: a network card 917, a BMC (Baseboard Management Controller) 918, a graphics card 919, a CPLD (Complex Programmable Logic Device) 920, and a USB controller. 921.
  • the USB controller may include at least one expansion port, so that the server can receive the data to be processed through the USB interface; the network card can be connected to the 40G optical port to enable the server to access the Internet, so that the data to be processed sent from the network channel can be received;
  • the BMC can perform configuration management, hardware management, and troubleshooting on the server.
  • an embodiment of the present invention provides a method for processing data by a server, where the method includes:
  • Step 1301 When the processor determines that the data received by the external input is non-transactional data, determine at least one target heterogeneous unit in the at least one heterogeneous unit, and send the non-transactional data to the Said at least one of said target heterogeneous units;
  • Step 1302 Receive, by using each of the target heterogeneous units, the non-transactional data sent by the processor, and process the non-transactional data.
  • the method includes: when the processor determines that the data received by the external input is non-transactional data, determines at least one target heterogeneous unit in at least one heterogeneous unit, and performs non-transaction Type data is sent to at least one target heterogeneous unit.
  • the non-transactional data is processed with each target heterogeneity.
  • the solution determines that at least one target heterogeneous unit is determined by the heterogeneous unit connected thereto when the processor determines that the non-transactional data is received, so that the determined at least one target heterogeneous unit is received.
  • Non-transactional data is processed.
  • embodiments of the present invention can increase data processing capabilities.
  • the receiving, by the target heterogeneous unit, the non-transactional data sent by the processor, after processing the non-transactional data further comprising:
  • the target heterogeneous unit sends intermediate data generated in the process of processing the non-transactional data to the processor
  • the intermediate data stored in the memory is retrieved by the processor, and the intermediate data is sent to the target heterogeneous unit.
  • the server comprises: a processor, a first bus, at least one second bus, and at least one heterogeneous unit. Wherein each of the heterogeneous units is connected to the first bus, and when the processor determines that the data received by the external input is non-transactional data, determining at least one target in each of the heterogeneous units connected to the second bus respectively.
  • the heterogeneous unit sends non-transactional data to at least one target heterogeneous unit, and each heterogeneous unit processes the non-transactional data when receiving non-transactional data sent by the processor.
  • the heterogeneous unit connected thereto determines at least one target heterogeneous unit, so that the determined at least one target heterogeneous unit is for the received non-received unit. Transactional data is processed. Therefore, embodiments of the present invention can improve data processing capabilities.
  • At least three FPGA chips and a third bus may be included in the heterogeneous unit, wherein at least three FPGA chips are connected to the third bus, and any one of the at least three FPGA chips is used.
  • the FPGA chip is connected to a corresponding second bus.
  • At least two FPGA chips may be included in the heterogeneous unit, wherein each FPGA chip is respectively connected to a corresponding second bus. It can be seen from the above that there is a parallel relationship between the FPGA chips. When an FPGA chip processes non-transactional data, other FPGA chips other than the main control FPGA chip cannot interfere with it. Therefore, the independence of processing data is better. high.
  • the heterogeneous unit includes at least three FPGA chips connected in sequence, and the FPGA chip in the first position and the FPGA chip in the last position are respectively connected to the corresponding second bus.
  • the data is processed through each FPGA chip in turn, so that the data processing amount in each FPGA chip can be dispersed, thereby improving the data processing speed.
  • any FPGA chip connected to the corresponding second bus is connected to at least one external storage hard disk, so that the data processing result in the FPGA chip is timely stored in the storage hard disk, thereby reducing The probability of data processing results being lost.
  • the server further includes a solid state hard disk and a mechanical hard disk, and constitutes a hybrid storage architecture with fast storage speed and large storage space.
  • the server may further include a memory, and use the memory to store intermediate data generated by each heterogeneous unit in processing non-transactional data to release the storage space in the heterogeneous unit, thereby Improve the speed at which heterogeneous units process data.
  • the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed.
  • the steps of the foregoing method embodiments are included; and the foregoing storage medium includes: various media that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

La présente invention concerne un serveur et un procédé de traitement de données de celui-ci. Le serveur comprend : un processeur, un premier bus, au moins un deuxième bus et au moins une unité hétérogène. Chacune des unités hétérogènes est connectée au premier bus. Lorsque le processeur détermine que des données reçues d'une entrée extérieure sont des données de non-transaction, le processeur sélectionne au moins une unité hétérogène cible parmi chacune des unités hétérogènes qui sont respectivement connectées à celui-ci par l'intermédiaire du deuxième bus et envoie les données de non-transaction à l'au moins une unité hétérogène cible. Lorsque chacune des unités hétérogènes reçoit les données de non-transaction envoyées par le processeur, chacune des unités hétérogènes traite les données de non-transaction. Comme décrit ci-dessus, la présente invention permet au processeur, lorsque le processeur détermine que des données de non-transaction sont reçues, de sélectionner au moins une unité hétérogène cible parmi les unités hétérogènes connectées à celui-ci, de sorte que l'au moins une unité hétérogène cible sélectionnée puisse traiter les données de non-transaction reçues. Ainsi, la présente invention peut améliorer la capacité de traitement de données.
PCT/CN2018/074553 2017-01-22 2018-01-30 Serveur et procédé de traitement de données de celui-ci WO2018133879A1 (fr)

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CN106708779A (zh) * 2017-01-22 2017-05-24 济南浪潮高新科技投资发展有限公司 一种服务器及其处理数据的方法
CN107450987A (zh) * 2017-07-28 2017-12-08 山东超越数控电子有限公司 一种高可用的异构服务器

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